Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.08 98.30 94.10 98.61 89.36 97.14 95.84 99.20


Total test records in report: 1081
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html

T838 /workspace/coverage/default/16.spi_device_intercept.4281599534 Jun 09 01:10:29 PM PDT 24 Jun 09 01:10:32 PM PDT 24 647686985 ps
T839 /workspace/coverage/default/45.spi_device_alert_test.4138842061 Jun 09 01:12:48 PM PDT 24 Jun 09 01:12:49 PM PDT 24 26434319 ps
T840 /workspace/coverage/default/28.spi_device_alert_test.1939044481 Jun 09 01:11:28 PM PDT 24 Jun 09 01:11:29 PM PDT 24 34323223 ps
T841 /workspace/coverage/default/19.spi_device_read_buffer_direct.755069389 Jun 09 01:10:46 PM PDT 24 Jun 09 01:10:51 PM PDT 24 157725951 ps
T842 /workspace/coverage/default/26.spi_device_tpm_all.3402015288 Jun 09 01:11:17 PM PDT 24 Jun 09 01:11:28 PM PDT 24 2155463869 ps
T843 /workspace/coverage/default/6.spi_device_upload.1216460496 Jun 09 01:09:23 PM PDT 24 Jun 09 01:09:30 PM PDT 24 5001616110 ps
T844 /workspace/coverage/default/5.spi_device_tpm_all.3343724045 Jun 09 01:09:18 PM PDT 24 Jun 09 01:09:45 PM PDT 24 2246876841 ps
T845 /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3632503238 Jun 09 01:08:45 PM PDT 24 Jun 09 01:08:54 PM PDT 24 1600398727 ps
T846 /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3887561242 Jun 09 01:09:22 PM PDT 24 Jun 09 01:09:31 PM PDT 24 7966538034 ps
T847 /workspace/coverage/default/9.spi_device_upload.3058463314 Jun 09 01:09:44 PM PDT 24 Jun 09 01:09:52 PM PDT 24 2002782244 ps
T848 /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2942860263 Jun 09 01:11:05 PM PDT 24 Jun 09 01:11:08 PM PDT 24 154642421 ps
T849 /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2280400082 Jun 09 01:11:45 PM PDT 24 Jun 09 01:11:48 PM PDT 24 7295136722 ps
T850 /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1731477160 Jun 09 01:10:24 PM PDT 24 Jun 09 01:10:31 PM PDT 24 666913311 ps
T851 /workspace/coverage/default/44.spi_device_intercept.4081311393 Jun 09 01:12:36 PM PDT 24 Jun 09 01:12:45 PM PDT 24 748121280 ps
T852 /workspace/coverage/default/44.spi_device_upload.1527679476 Jun 09 01:12:40 PM PDT 24 Jun 09 01:12:45 PM PDT 24 829701748 ps
T853 /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2260488241 Jun 09 01:11:15 PM PDT 24 Jun 09 01:11:30 PM PDT 24 24327865479 ps
T854 /workspace/coverage/default/7.spi_device_stress_all.4040704411 Jun 09 01:09:36 PM PDT 24 Jun 09 01:10:43 PM PDT 24 13947603253 ps
T855 /workspace/coverage/default/40.spi_device_flash_and_tpm.4035306274 Jun 09 01:12:26 PM PDT 24 Jun 09 01:14:06 PM PDT 24 13582104784 ps
T856 /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2147528753 Jun 09 01:12:20 PM PDT 24 Jun 09 01:12:30 PM PDT 24 11333647558 ps
T857 /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3947800539 Jun 09 01:10:45 PM PDT 24 Jun 09 01:10:48 PM PDT 24 295596923 ps
T858 /workspace/coverage/default/15.spi_device_upload.2892097420 Jun 09 01:10:19 PM PDT 24 Jun 09 01:10:22 PM PDT 24 680837299 ps
T859 /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1141945824 Jun 09 01:10:12 PM PDT 24 Jun 09 01:10:15 PM PDT 24 245742607 ps
T860 /workspace/coverage/default/4.spi_device_tpm_all.1345248454 Jun 09 01:09:11 PM PDT 24 Jun 09 01:09:17 PM PDT 24 830245770 ps
T861 /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1942524042 Jun 09 01:09:28 PM PDT 24 Jun 09 01:09:39 PM PDT 24 21886313462 ps
T862 /workspace/coverage/default/48.spi_device_pass_cmd_filtering.4233369842 Jun 09 01:12:53 PM PDT 24 Jun 09 01:12:59 PM PDT 24 970932006 ps
T863 /workspace/coverage/default/46.spi_device_alert_test.1260024032 Jun 09 01:12:48 PM PDT 24 Jun 09 01:12:49 PM PDT 24 24065804 ps
T864 /workspace/coverage/default/42.spi_device_flash_mode.3003724389 Jun 09 01:12:34 PM PDT 24 Jun 09 01:12:43 PM PDT 24 1556924091 ps
T865 /workspace/coverage/default/16.spi_device_csb_read.2905167463 Jun 09 01:10:21 PM PDT 24 Jun 09 01:10:22 PM PDT 24 31901483 ps
T866 /workspace/coverage/default/37.spi_device_csb_read.863587916 Jun 09 01:12:08 PM PDT 24 Jun 09 01:12:09 PM PDT 24 64079001 ps
T867 /workspace/coverage/default/19.spi_device_tpm_rw.1399613602 Jun 09 01:10:46 PM PDT 24 Jun 09 01:10:54 PM PDT 24 588053465 ps
T868 /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1567230817 Jun 09 01:12:21 PM PDT 24 Jun 09 01:12:49 PM PDT 24 12626998112 ps
T869 /workspace/coverage/default/19.spi_device_csb_read.3499142668 Jun 09 01:10:36 PM PDT 24 Jun 09 01:10:38 PM PDT 24 22261290 ps
T870 /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.552121765 Jun 09 01:11:44 PM PDT 24 Jun 09 01:11:56 PM PDT 24 7153523843 ps
T871 /workspace/coverage/default/17.spi_device_tpm_sts_read.3285248018 Jun 09 01:10:24 PM PDT 24 Jun 09 01:10:25 PM PDT 24 151871512 ps
T872 /workspace/coverage/default/46.spi_device_intercept.457685269 Jun 09 01:12:49 PM PDT 24 Jun 09 01:12:58 PM PDT 24 502619894 ps
T873 /workspace/coverage/default/39.spi_device_tpm_sts_read.2925765121 Jun 09 01:12:14 PM PDT 24 Jun 09 01:12:15 PM PDT 24 24658066 ps
T874 /workspace/coverage/default/24.spi_device_mailbox.796844225 Jun 09 01:11:03 PM PDT 24 Jun 09 01:12:16 PM PDT 24 24251129315 ps
T875 /workspace/coverage/default/2.spi_device_read_buffer_direct.828340618 Jun 09 01:09:04 PM PDT 24 Jun 09 01:09:10 PM PDT 24 923205789 ps
T876 /workspace/coverage/default/8.spi_device_pass_cmd_filtering.4017667998 Jun 09 01:09:33 PM PDT 24 Jun 09 01:10:03 PM PDT 24 35069044426 ps
T877 /workspace/coverage/default/26.spi_device_mailbox.1960132932 Jun 09 01:11:20 PM PDT 24 Jun 09 01:11:30 PM PDT 24 359216428 ps
T878 /workspace/coverage/default/45.spi_device_cfg_cmd.3172292805 Jun 09 01:12:43 PM PDT 24 Jun 09 01:12:46 PM PDT 24 51967097 ps
T879 /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3831625228 Jun 09 01:08:59 PM PDT 24 Jun 09 01:09:02 PM PDT 24 64297622 ps
T880 /workspace/coverage/default/32.spi_device_intercept.538521820 Jun 09 01:11:44 PM PDT 24 Jun 09 01:11:52 PM PDT 24 2755630485 ps
T881 /workspace/coverage/default/26.spi_device_tpm_rw.975328808 Jun 09 01:11:16 PM PDT 24 Jun 09 01:11:18 PM PDT 24 523631084 ps
T882 /workspace/coverage/default/42.spi_device_flash_all.2938291775 Jun 09 01:12:32 PM PDT 24 Jun 09 01:14:13 PM PDT 24 5077598424 ps
T883 /workspace/coverage/default/31.spi_device_tpm_all.42693338 Jun 09 01:11:45 PM PDT 24 Jun 09 01:12:14 PM PDT 24 12769455986 ps
T884 /workspace/coverage/default/44.spi_device_cfg_cmd.3432696763 Jun 09 01:12:42 PM PDT 24 Jun 09 01:12:53 PM PDT 24 4541127603 ps
T885 /workspace/coverage/default/9.spi_device_read_buffer_direct.2131872436 Jun 09 01:09:44 PM PDT 24 Jun 09 01:09:57 PM PDT 24 3002409610 ps
T886 /workspace/coverage/default/0.spi_device_upload.1647663410 Jun 09 01:08:36 PM PDT 24 Jun 09 01:08:39 PM PDT 24 269553661 ps
T309 /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1391149763 Jun 09 01:10:38 PM PDT 24 Jun 09 01:12:22 PM PDT 24 17449776713 ps
T887 /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3897152559 Jun 09 01:10:47 PM PDT 24 Jun 09 01:11:03 PM PDT 24 11145171071 ps
T888 /workspace/coverage/default/37.spi_device_flash_and_tpm.2850448735 Jun 09 01:12:07 PM PDT 24 Jun 09 01:13:04 PM PDT 24 2800184337 ps
T889 /workspace/coverage/default/33.spi_device_upload.965705118 Jun 09 01:11:50 PM PDT 24 Jun 09 01:12:13 PM PDT 24 6616063219 ps
T890 /workspace/coverage/default/18.spi_device_stress_all.1765660380 Jun 09 01:10:39 PM PDT 24 Jun 09 01:10:40 PM PDT 24 40836943 ps
T891 /workspace/coverage/default/39.spi_device_pass_cmd_filtering.714322197 Jun 09 01:12:18 PM PDT 24 Jun 09 01:12:35 PM PDT 24 3156364818 ps
T892 /workspace/coverage/default/40.spi_device_intercept.3987262506 Jun 09 01:12:24 PM PDT 24 Jun 09 01:12:33 PM PDT 24 1929524126 ps
T893 /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.4087134574 Jun 09 01:09:45 PM PDT 24 Jun 09 01:10:11 PM PDT 24 6382960453 ps
T312 /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1379802658 Jun 09 01:12:12 PM PDT 24 Jun 09 01:16:52 PM PDT 24 112701573984 ps
T323 /workspace/coverage/default/40.spi_device_flash_mode.2318217483 Jun 09 01:12:24 PM PDT 24 Jun 09 01:12:33 PM PDT 24 766854590 ps
T894 /workspace/coverage/default/48.spi_device_cfg_cmd.2507546486 Jun 09 01:12:55 PM PDT 24 Jun 09 01:12:58 PM PDT 24 132573853 ps
T123 /workspace/coverage/default/11.spi_device_flash_and_tpm.4112318295 Jun 09 01:09:56 PM PDT 24 Jun 09 01:11:23 PM PDT 24 11128637726 ps
T124 /workspace/coverage/default/28.spi_device_upload.2405136791 Jun 09 01:11:29 PM PDT 24 Jun 09 01:11:32 PM PDT 24 499989980 ps
T125 /workspace/coverage/default/4.spi_device_upload.2148842855 Jun 09 01:09:12 PM PDT 24 Jun 09 01:09:18 PM PDT 24 8381322848 ps
T126 /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.505925032 Jun 09 01:09:11 PM PDT 24 Jun 09 01:11:25 PM PDT 24 57760353641 ps
T127 /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1267594423 Jun 09 01:11:26 PM PDT 24 Jun 09 01:11:50 PM PDT 24 3669927246 ps
T128 /workspace/coverage/default/9.spi_device_cfg_cmd.47145513 Jun 09 01:09:46 PM PDT 24 Jun 09 01:09:49 PM PDT 24 157618810 ps
T129 /workspace/coverage/default/35.spi_device_alert_test.2797368191 Jun 09 01:12:00 PM PDT 24 Jun 09 01:12:01 PM PDT 24 16136432 ps
T130 /workspace/coverage/default/38.spi_device_flash_and_tpm.3633521 Jun 09 01:12:15 PM PDT 24 Jun 09 01:13:06 PM PDT 24 28859952137 ps
T131 /workspace/coverage/default/19.spi_device_intercept.978805307 Jun 09 01:10:41 PM PDT 24 Jun 09 01:10:48 PM PDT 24 428405113 ps
T132 /workspace/coverage/default/31.spi_device_cfg_cmd.657702939 Jun 09 01:11:38 PM PDT 24 Jun 09 01:11:41 PM PDT 24 84628165 ps
T895 /workspace/coverage/default/23.spi_device_csb_read.2107372228 Jun 09 01:10:57 PM PDT 24 Jun 09 01:10:59 PM PDT 24 43443870 ps
T896 /workspace/coverage/default/4.spi_device_flash_all.609842512 Jun 09 01:09:09 PM PDT 24 Jun 09 01:09:39 PM PDT 24 7853729936 ps
T897 /workspace/coverage/default/36.spi_device_tpm_all.4161039263 Jun 09 01:12:02 PM PDT 24 Jun 09 01:12:10 PM PDT 24 745803848 ps
T152 /workspace/coverage/default/39.spi_device_stress_all.1631218402 Jun 09 01:12:18 PM PDT 24 Jun 09 01:12:50 PM PDT 24 2172299273 ps
T898 /workspace/coverage/default/14.spi_device_alert_test.847847134 Jun 09 01:10:16 PM PDT 24 Jun 09 01:10:17 PM PDT 24 60560210 ps
T899 /workspace/coverage/default/8.spi_device_alert_test.3558785988 Jun 09 01:09:41 PM PDT 24 Jun 09 01:09:42 PM PDT 24 31989984 ps
T301 /workspace/coverage/default/12.spi_device_flash_and_tpm.3084548421 Jun 09 01:10:03 PM PDT 24 Jun 09 01:13:00 PM PDT 24 69415389954 ps
T900 /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2047822304 Jun 09 01:12:07 PM PDT 24 Jun 09 01:12:16 PM PDT 24 3306171445 ps
T901 /workspace/coverage/default/44.spi_device_tpm_sts_read.1040067359 Jun 09 01:12:36 PM PDT 24 Jun 09 01:12:37 PM PDT 24 616903882 ps
T902 /workspace/coverage/default/41.spi_device_intercept.2512706670 Jun 09 01:12:25 PM PDT 24 Jun 09 01:12:30 PM PDT 24 779819438 ps
T903 /workspace/coverage/default/44.spi_device_flash_all.148067080 Jun 09 01:12:41 PM PDT 24 Jun 09 01:13:58 PM PDT 24 21691601183 ps
T904 /workspace/coverage/default/42.spi_device_csb_read.2071444698 Jun 09 01:12:31 PM PDT 24 Jun 09 01:12:32 PM PDT 24 12445579 ps
T905 /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.4037486519 Jun 09 01:08:55 PM PDT 24 Jun 09 01:08:58 PM PDT 24 389676178 ps
T906 /workspace/coverage/default/6.spi_device_cfg_cmd.2850321855 Jun 09 01:09:22 PM PDT 24 Jun 09 01:09:39 PM PDT 24 1253445245 ps
T907 /workspace/coverage/default/21.spi_device_tpm_sts_read.3905091946 Jun 09 01:10:47 PM PDT 24 Jun 09 01:10:48 PM PDT 24 132331021 ps
T908 /workspace/coverage/default/1.spi_device_upload.269226866 Jun 09 01:08:50 PM PDT 24 Jun 09 01:09:12 PM PDT 24 6570440536 ps
T909 /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2008957387 Jun 09 01:11:25 PM PDT 24 Jun 09 01:11:30 PM PDT 24 2712757422 ps
T910 /workspace/coverage/default/31.spi_device_stress_all.1060498127 Jun 09 01:11:43 PM PDT 24 Jun 09 01:11:44 PM PDT 24 76001129 ps
T911 /workspace/coverage/default/28.spi_device_intercept.397680853 Jun 09 01:11:29 PM PDT 24 Jun 09 01:11:31 PM PDT 24 43409850 ps
T912 /workspace/coverage/default/14.spi_device_upload.1830734817 Jun 09 01:10:14 PM PDT 24 Jun 09 01:10:17 PM PDT 24 157580929 ps
T913 /workspace/coverage/default/29.spi_device_upload.2273218846 Jun 09 01:11:28 PM PDT 24 Jun 09 01:11:40 PM PDT 24 12333099886 ps
T914 /workspace/coverage/default/6.spi_device_pass_cmd_filtering.873969962 Jun 09 01:09:21 PM PDT 24 Jun 09 01:09:29 PM PDT 24 1253415544 ps
T915 /workspace/coverage/default/19.spi_device_flash_mode.2986802598 Jun 09 01:10:46 PM PDT 24 Jun 09 01:10:51 PM PDT 24 205088844 ps
T310 /workspace/coverage/default/2.spi_device_stress_all.1719695336 Jun 09 01:08:59 PM PDT 24 Jun 09 01:14:06 PM PDT 24 37069084638 ps
T916 /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3451300144 Jun 09 01:12:45 PM PDT 24 Jun 09 01:12:51 PM PDT 24 413706005 ps
T917 /workspace/coverage/default/27.spi_device_csb_read.1352475082 Jun 09 01:11:24 PM PDT 24 Jun 09 01:11:25 PM PDT 24 123234969 ps
T918 /workspace/coverage/default/45.spi_device_tpm_sts_read.296702866 Jun 09 01:12:43 PM PDT 24 Jun 09 01:12:44 PM PDT 24 159343811 ps
T919 /workspace/coverage/default/1.spi_device_mailbox.1137914972 Jun 09 01:08:42 PM PDT 24 Jun 09 01:08:52 PM PDT 24 804169855 ps
T920 /workspace/coverage/default/6.spi_device_tpm_sts_read.544689806 Jun 09 01:09:25 PM PDT 24 Jun 09 01:09:26 PM PDT 24 21215429 ps
T921 /workspace/coverage/default/19.spi_device_tpm_sts_read.539460792 Jun 09 01:10:40 PM PDT 24 Jun 09 01:10:42 PM PDT 24 31198573 ps
T922 /workspace/coverage/default/7.spi_device_tpm_all.3669532247 Jun 09 01:09:27 PM PDT 24 Jun 09 01:10:05 PM PDT 24 27806745607 ps
T302 /workspace/coverage/default/9.spi_device_flash_and_tpm.3139465656 Jun 09 01:09:45 PM PDT 24 Jun 09 01:11:01 PM PDT 24 10735866077 ps
T923 /workspace/coverage/default/2.spi_device_mailbox.1006782382 Jun 09 01:08:56 PM PDT 24 Jun 09 01:09:11 PM PDT 24 891471313 ps
T924 /workspace/coverage/default/1.spi_device_flash_all.3680587257 Jun 09 01:08:48 PM PDT 24 Jun 09 01:10:15 PM PDT 24 6325103647 ps
T925 /workspace/coverage/default/2.spi_device_intercept.1773169253 Jun 09 01:08:56 PM PDT 24 Jun 09 01:09:00 PM PDT 24 174059563 ps
T308 /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.4227004567 Jun 09 01:09:33 PM PDT 24 Jun 09 01:13:26 PM PDT 24 18591679175 ps
T926 /workspace/coverage/default/18.spi_device_upload.2183648882 Jun 09 01:10:39 PM PDT 24 Jun 09 01:10:42 PM PDT 24 37206003 ps
T927 /workspace/coverage/default/38.spi_device_mailbox.1235703761 Jun 09 01:12:12 PM PDT 24 Jun 09 01:12:15 PM PDT 24 443550491 ps
T928 /workspace/coverage/default/33.spi_device_stress_all.2764152196 Jun 09 01:11:50 PM PDT 24 Jun 09 01:15:19 PM PDT 24 49163962343 ps
T929 /workspace/coverage/default/32.spi_device_flash_mode.3274430993 Jun 09 01:11:45 PM PDT 24 Jun 09 01:11:58 PM PDT 24 222582931 ps
T930 /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3503490360 Jun 09 01:11:04 PM PDT 24 Jun 09 01:11:10 PM PDT 24 611214004 ps
T931 /workspace/coverage/default/23.spi_device_flash_all.2458414395 Jun 09 01:11:00 PM PDT 24 Jun 09 01:11:00 PM PDT 24 30461099 ps
T932 /workspace/coverage/default/26.spi_device_flash_mode.911056587 Jun 09 01:11:19 PM PDT 24 Jun 09 01:11:31 PM PDT 24 429146664 ps
T933 /workspace/coverage/default/37.spi_device_tpm_sts_read.2673157988 Jun 09 01:12:07 PM PDT 24 Jun 09 01:12:08 PM PDT 24 72858617 ps
T934 /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2230610893 Jun 09 01:10:59 PM PDT 24 Jun 09 01:12:27 PM PDT 24 87298609927 ps
T153 /workspace/coverage/default/8.spi_device_stress_all.3651966980 Jun 09 01:09:41 PM PDT 24 Jun 09 01:14:13 PM PDT 24 124241252971 ps
T935 /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1351415825 Jun 09 01:08:30 PM PDT 24 Jun 09 01:08:33 PM PDT 24 461278722 ps
T154 /workspace/coverage/default/9.spi_device_stress_all.459186074 Jun 09 01:09:46 PM PDT 24 Jun 09 01:10:59 PM PDT 24 35192800397 ps
T936 /workspace/coverage/default/38.spi_device_cfg_cmd.2575191558 Jun 09 01:12:12 PM PDT 24 Jun 09 01:12:14 PM PDT 24 34609625 ps
T45 /workspace/coverage/default/6.spi_device_stress_all.915510490 Jun 09 01:09:27 PM PDT 24 Jun 09 01:19:51 PM PDT 24 234686936638 ps
T46 /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.4115674282 Jun 09 01:12:56 PM PDT 24 Jun 09 01:14:30 PM PDT 24 12503322192 ps
T47 /workspace/coverage/default/34.spi_device_alert_test.3691877032 Jun 09 01:11:54 PM PDT 24 Jun 09 01:11:55 PM PDT 24 13955396 ps
T48 /workspace/coverage/default/21.spi_device_csb_read.3491573758 Jun 09 01:10:48 PM PDT 24 Jun 09 01:10:49 PM PDT 24 35090534 ps
T49 /workspace/coverage/default/49.spi_device_tpm_sts_read.3185477590 Jun 09 01:12:58 PM PDT 24 Jun 09 01:12:59 PM PDT 24 136290897 ps
T50 /workspace/coverage/default/33.spi_device_flash_mode.2099904945 Jun 09 01:11:49 PM PDT 24 Jun 09 01:11:59 PM PDT 24 2494173240 ps
T51 /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3324634917 Jun 09 01:10:44 PM PDT 24 Jun 09 01:10:46 PM PDT 24 424034806 ps
T52 /workspace/coverage/default/49.spi_device_read_buffer_direct.3054538923 Jun 09 01:13:03 PM PDT 24 Jun 09 01:13:12 PM PDT 24 728758896 ps
T53 /workspace/coverage/default/34.spi_device_mailbox.1499844696 Jun 09 01:11:51 PM PDT 24 Jun 09 01:12:06 PM PDT 24 2223953467 ps
T54 /workspace/coverage/default/20.spi_device_upload.1733020037 Jun 09 01:10:48 PM PDT 24 Jun 09 01:10:54 PM PDT 24 400974634 ps
T937 /workspace/coverage/default/17.spi_device_csb_read.3179208910 Jun 09 01:10:31 PM PDT 24 Jun 09 01:10:33 PM PDT 24 79198126 ps
T938 /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.4272587375 Jun 09 01:12:32 PM PDT 24 Jun 09 01:15:30 PM PDT 24 27172225694 ps
T939 /workspace/coverage/default/37.spi_device_intercept.1343620601 Jun 09 01:12:07 PM PDT 24 Jun 09 01:12:10 PM PDT 24 746085844 ps
T940 /workspace/coverage/default/4.spi_device_cfg_cmd.1536006280 Jun 09 01:09:09 PM PDT 24 Jun 09 01:09:18 PM PDT 24 2978644593 ps
T941 /workspace/coverage/default/16.spi_device_alert_test.1690485758 Jun 09 01:10:24 PM PDT 24 Jun 09 01:10:25 PM PDT 24 68561964 ps
T942 /workspace/coverage/default/43.spi_device_upload.2970463035 Jun 09 01:12:33 PM PDT 24 Jun 09 01:12:38 PM PDT 24 432269253 ps
T943 /workspace/coverage/default/2.spi_device_flash_all.2811000496 Jun 09 01:09:01 PM PDT 24 Jun 09 01:11:24 PM PDT 24 51862447367 ps
T944 /workspace/coverage/default/18.spi_device_flash_mode.2742463662 Jun 09 01:10:36 PM PDT 24 Jun 09 01:11:05 PM PDT 24 1373216368 ps
T945 /workspace/coverage/default/10.spi_device_read_buffer_direct.2430769596 Jun 09 01:09:51 PM PDT 24 Jun 09 01:10:05 PM PDT 24 2354621672 ps
T946 /workspace/coverage/default/26.spi_device_upload.1847529507 Jun 09 01:11:16 PM PDT 24 Jun 09 01:11:19 PM PDT 24 122852086 ps
T155 /workspace/coverage/default/10.spi_device_stress_all.3021924468 Jun 09 01:09:52 PM PDT 24 Jun 09 01:09:54 PM PDT 24 114974610 ps
T947 /workspace/coverage/default/46.spi_device_flash_and_tpm.136223225 Jun 09 01:12:48 PM PDT 24 Jun 09 01:16:14 PM PDT 24 100403231896 ps
T948 /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.82246076 Jun 09 01:09:10 PM PDT 24 Jun 09 01:09:16 PM PDT 24 8041421843 ps
T949 /workspace/coverage/default/0.spi_device_tpm_rw.3794634903 Jun 09 01:08:33 PM PDT 24 Jun 09 01:08:39 PM PDT 24 1166587638 ps
T950 /workspace/coverage/default/49.spi_device_tpm_rw.389351783 Jun 09 01:12:56 PM PDT 24 Jun 09 01:12:58 PM PDT 24 37950874 ps
T951 /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1244341502 Jun 09 01:12:24 PM PDT 24 Jun 09 01:12:30 PM PDT 24 6353483461 ps
T952 /workspace/coverage/default/17.spi_device_flash_mode.536200029 Jun 09 01:10:30 PM PDT 24 Jun 09 01:10:37 PM PDT 24 249041016 ps
T953 /workspace/coverage/default/41.spi_device_csb_read.2483769878 Jun 09 01:12:25 PM PDT 24 Jun 09 01:12:26 PM PDT 24 20517232 ps
T954 /workspace/coverage/default/2.spi_device_tpm_sts_read.1582932376 Jun 09 01:08:54 PM PDT 24 Jun 09 01:08:56 PM PDT 24 89248106 ps
T955 /workspace/coverage/default/36.spi_device_read_buffer_direct.593916209 Jun 09 01:12:02 PM PDT 24 Jun 09 01:12:06 PM PDT 24 320938433 ps
T956 /workspace/coverage/default/14.spi_device_flash_and_tpm.162245793 Jun 09 01:10:14 PM PDT 24 Jun 09 01:11:32 PM PDT 24 28665778505 ps
T957 /workspace/coverage/default/24.spi_device_tpm_rw.121426069 Jun 09 01:11:06 PM PDT 24 Jun 09 01:11:09 PM PDT 24 331676447 ps
T958 /workspace/coverage/default/33.spi_device_tpm_all.3195604145 Jun 09 01:11:44 PM PDT 24 Jun 09 01:12:13 PM PDT 24 3073727478 ps
T959 /workspace/coverage/default/10.spi_device_csb_read.2409067370 Jun 09 01:09:49 PM PDT 24 Jun 09 01:09:51 PM PDT 24 83671761 ps
T960 /workspace/coverage/default/46.spi_device_read_buffer_direct.716251946 Jun 09 01:12:45 PM PDT 24 Jun 09 01:12:49 PM PDT 24 134752375 ps
T961 /workspace/coverage/default/26.spi_device_intercept.3384332271 Jun 09 01:11:17 PM PDT 24 Jun 09 01:11:21 PM PDT 24 379926274 ps
T962 /workspace/coverage/default/0.spi_device_tpm_sts_read.424183045 Jun 09 01:08:31 PM PDT 24 Jun 09 01:08:32 PM PDT 24 16741819 ps
T133 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4004588892 Jun 09 12:27:04 PM PDT 24 Jun 09 12:27:06 PM PDT 24 23419690 ps
T963 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2153587842 Jun 09 12:27:08 PM PDT 24 Jun 09 12:27:10 PM PDT 24 15116999 ps
T964 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3476184220 Jun 09 12:27:07 PM PDT 24 Jun 09 12:27:13 PM PDT 24 11942841 ps
T58 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3435865735 Jun 09 12:26:57 PM PDT 24 Jun 09 12:27:00 PM PDT 24 144161180 ps
T965 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2819453121 Jun 09 12:27:03 PM PDT 24 Jun 09 12:27:05 PM PDT 24 24265332 ps
T112 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3127333035 Jun 09 12:27:13 PM PDT 24 Jun 09 12:27:16 PM PDT 24 142422606 ps
T113 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2505445654 Jun 09 12:27:02 PM PDT 24 Jun 09 12:27:16 PM PDT 24 1844137822 ps
T59 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.649518900 Jun 09 12:27:05 PM PDT 24 Jun 09 12:27:09 PM PDT 24 46341838 ps
T60 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1321809506 Jun 09 12:27:10 PM PDT 24 Jun 09 12:27:15 PM PDT 24 633205943 ps
T91 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1220231441 Jun 09 12:28:31 PM PDT 24 Jun 09 12:28:34 PM PDT 24 606004211 ps
T92 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.691313038 Jun 09 12:27:25 PM PDT 24 Jun 09 12:27:48 PM PDT 24 3305017375 ps
T966 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2024515729 Jun 09 12:27:03 PM PDT 24 Jun 09 12:27:05 PM PDT 24 20231862 ps
T103 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1042772302 Jun 09 12:27:38 PM PDT 24 Jun 09 12:27:43 PM PDT 24 171007278 ps
T967 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2609227688 Jun 09 12:27:08 PM PDT 24 Jun 09 12:27:11 PM PDT 24 14316375 ps
T109 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4088229358 Jun 09 12:27:09 PM PDT 24 Jun 09 12:27:12 PM PDT 24 44559609 ps
T968 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2462749265 Jun 09 12:27:05 PM PDT 24 Jun 09 12:27:07 PM PDT 24 31785406 ps
T969 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2663907881 Jun 09 12:27:00 PM PDT 24 Jun 09 12:27:01 PM PDT 24 13617433 ps
T970 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2127101822 Jun 09 12:28:32 PM PDT 24 Jun 09 12:28:34 PM PDT 24 25664971 ps
T971 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2951651445 Jun 09 12:28:07 PM PDT 24 Jun 09 12:28:09 PM PDT 24 25645697 ps
T972 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3022741093 Jun 09 12:27:38 PM PDT 24 Jun 09 12:27:40 PM PDT 24 16451607 ps
T973 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.358618825 Jun 09 12:27:00 PM PDT 24 Jun 09 12:27:01 PM PDT 24 26376141 ps
T134 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3299174861 Jun 09 12:26:54 PM PDT 24 Jun 09 12:26:57 PM PDT 24 119118379 ps
T104 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3977345197 Jun 09 12:27:05 PM PDT 24 Jun 09 12:27:10 PM PDT 24 380808565 ps
T135 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.561440733 Jun 09 12:27:08 PM PDT 24 Jun 09 12:27:13 PM PDT 24 76010296 ps
T110 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3052219222 Jun 09 12:27:07 PM PDT 24 Jun 09 12:27:13 PM PDT 24 141875107 ps
T974 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.6202098 Jun 09 12:27:07 PM PDT 24 Jun 09 12:27:10 PM PDT 24 23744848 ps
T975 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2552869618 Jun 09 12:26:59 PM PDT 24 Jun 09 12:27:00 PM PDT 24 27033732 ps
T111 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.286113728 Jun 09 12:27:13 PM PDT 24 Jun 09 12:27:16 PM PDT 24 90770221 ps
T114 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.544505289 Jun 09 12:27:04 PM PDT 24 Jun 09 12:27:09 PM PDT 24 195076156 ps
T976 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1702328166 Jun 09 12:27:05 PM PDT 24 Jun 09 12:27:08 PM PDT 24 17325124 ps
T115 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3702496447 Jun 09 12:27:08 PM PDT 24 Jun 09 12:27:12 PM PDT 24 64859993 ps
T116 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3456251553 Jun 09 12:27:05 PM PDT 24 Jun 09 12:27:08 PM PDT 24 31524500 ps
T117 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2682815490 Jun 09 12:27:07 PM PDT 24 Jun 09 12:27:12 PM PDT 24 123971572 ps
T142 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2719670798 Jun 09 12:27:05 PM PDT 24 Jun 09 12:27:11 PM PDT 24 386931136 ps
T118 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1251565553 Jun 09 12:28:30 PM PDT 24 Jun 09 12:28:45 PM PDT 24 1242353757 ps
T79 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.594553045 Jun 09 12:26:54 PM PDT 24 Jun 09 12:26:56 PM PDT 24 146199977 ps
T977 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.123901935 Jun 09 12:27:09 PM PDT 24 Jun 09 12:27:13 PM PDT 24 376841768 ps
T93 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4247035737 Jun 09 12:27:06 PM PDT 24 Jun 09 12:27:15 PM PDT 24 535477394 ps
T978 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.818629724 Jun 09 12:28:31 PM PDT 24 Jun 09 12:28:33 PM PDT 24 27063147 ps
T979 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.238459212 Jun 09 12:26:58 PM PDT 24 Jun 09 12:26:59 PM PDT 24 15031379 ps
T143 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3009048160 Jun 09 12:26:54 PM PDT 24 Jun 09 12:26:56 PM PDT 24 222670897 ps
T94 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3526095160 Jun 09 12:26:56 PM PDT 24 Jun 09 12:27:09 PM PDT 24 2380810266 ps
T119 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1136997445 Jun 09 12:27:05 PM PDT 24 Jun 09 12:27:08 PM PDT 24 132351217 ps
T980 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1472010920 Jun 09 12:27:37 PM PDT 24 Jun 09 12:27:38 PM PDT 24 11861103 ps
T95 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3832846586 Jun 09 12:27:07 PM PDT 24 Jun 09 12:27:14 PM PDT 24 180026704 ps
T981 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1430600229 Jun 09 12:27:29 PM PDT 24 Jun 09 12:27:31 PM PDT 24 53815462 ps
T97 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3873815514 Jun 09 12:27:08 PM PDT 24 Jun 09 12:27:12 PM PDT 24 55971804 ps
T120 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.157461359 Jun 09 12:27:02 PM PDT 24 Jun 09 12:27:30 PM PDT 24 1867108398 ps
T982 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3925075517 Jun 09 12:27:03 PM PDT 24 Jun 09 12:27:05 PM PDT 24 14962644 ps
T122 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.629793834 Jun 09 12:27:04 PM PDT 24 Jun 09 12:27:07 PM PDT 24 29320663 ps
T983 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.175961794 Jun 09 12:27:24 PM PDT 24 Jun 09 12:27:25 PM PDT 24 26484116 ps
T984 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1622273024 Jun 09 12:27:07 PM PDT 24 Jun 09 12:27:10 PM PDT 24 20941994 ps
T98 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.80371458 Jun 09 12:27:17 PM PDT 24 Jun 09 12:27:22 PM PDT 24 1938282998 ps
T144 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3134386002 Jun 09 12:27:06 PM PDT 24 Jun 09 12:27:16 PM PDT 24 350907497 ps
T985 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.238540366 Jun 09 12:27:36 PM PDT 24 Jun 09 12:27:37 PM PDT 24 15828962 ps
T986 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.687916509 Jun 09 12:27:07 PM PDT 24 Jun 09 12:27:11 PM PDT 24 132906000 ps
T987 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.913127915 Jun 09 12:26:57 PM PDT 24 Jun 09 12:26:59 PM PDT 24 49648400 ps
T80 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3580624156 Jun 09 12:27:20 PM PDT 24 Jun 09 12:27:22 PM PDT 24 50173672 ps
T988 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2859073395 Jun 09 12:27:06 PM PDT 24 Jun 09 12:27:11 PM PDT 24 212415430 ps
T121 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2058784256 Jun 09 12:27:00 PM PDT 24 Jun 09 12:27:02 PM PDT 24 88646120 ps
T989 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3565009192 Jun 09 12:27:04 PM PDT 24 Jun 09 12:27:05 PM PDT 24 25356792 ps
T990 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3253706587 Jun 09 12:27:03 PM PDT 24 Jun 09 12:27:29 PM PDT 24 1240907064 ps
T991 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3629755860 Jun 09 12:27:02 PM PDT 24 Jun 09 12:27:05 PM PDT 24 70064050 ps
T992 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3881105911 Jun 09 12:27:05 PM PDT 24 Jun 09 12:27:09 PM PDT 24 156390693 ps
T993 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3825574701 Jun 09 12:26:57 PM PDT 24 Jun 09 12:26:58 PM PDT 24 23028082 ps
T994 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4244767734 Jun 09 12:27:04 PM PDT 24 Jun 09 12:27:07 PM PDT 24 266682773 ps
T81 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3711112745 Jun 09 12:27:03 PM PDT 24 Jun 09 12:27:05 PM PDT 24 51928857 ps
T995 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.11670472 Jun 09 12:27:06 PM PDT 24 Jun 09 12:27:10 PM PDT 24 24834255 ps
T996 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2013000741 Jun 09 12:27:04 PM PDT 24 Jun 09 12:27:13 PM PDT 24 36853039 ps
T997 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.140496139 Jun 09 12:27:02 PM PDT 24 Jun 09 12:27:06 PM PDT 24 40739718 ps
T998 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2702911742 Jun 09 12:28:26 PM PDT 24 Jun 09 12:28:27 PM PDT 24 46949426 ps
T999 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3643528597 Jun 09 12:27:07 PM PDT 24 Jun 09 12:27:10 PM PDT 24 15725863 ps
T1000 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3858124611 Jun 09 12:27:06 PM PDT 24 Jun 09 12:27:09 PM PDT 24 56016428 ps
T1001 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3433969236 Jun 09 12:27:01 PM PDT 24 Jun 09 12:27:04 PM PDT 24 65021482 ps
T1002 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.274788158 Jun 09 12:28:32 PM PDT 24 Jun 09 12:28:34 PM PDT 24 11652690 ps
T1003 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.357084557 Jun 09 12:28:28 PM PDT 24 Jun 09 12:28:29 PM PDT 24 14422496 ps
T145 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3522610052 Jun 09 12:27:05 PM PDT 24 Jun 09 12:27:22 PM PDT 24 700775928 ps
T1004 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3081162888 Jun 09 12:27:09 PM PDT 24 Jun 09 12:27:12 PM PDT 24 46510396 ps
T146 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.973838049 Jun 09 12:27:01 PM PDT 24 Jun 09 12:27:04 PM PDT 24 83765358 ps
T1005 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1029404500 Jun 09 12:27:30 PM PDT 24 Jun 09 12:27:34 PM PDT 24 2031908081 ps
T1006 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.357349303 Jun 09 12:27:02 PM PDT 24 Jun 09 12:27:05 PM PDT 24 483849395 ps
T1007 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3368784376 Jun 09 12:27:05 PM PDT 24 Jun 09 12:27:08 PM PDT 24 23463350 ps
T1008 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3468778030 Jun 09 12:27:25 PM PDT 24 Jun 09 12:27:26 PM PDT 24 78638319 ps
T1009 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1942880762 Jun 09 12:27:04 PM PDT 24 Jun 09 12:27:07 PM PDT 24 15943042 ps
T1010 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4213761544 Jun 09 12:26:55 PM PDT 24 Jun 09 12:26:59 PM PDT 24 284715418 ps
T105 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2726473778 Jun 09 12:27:05 PM PDT 24 Jun 09 12:27:09 PM PDT 24 156630339 ps
T106 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3296550912 Jun 09 12:27:04 PM PDT 24 Jun 09 12:27:07 PM PDT 24 91116613 ps
T1011 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.740479862 Jun 09 12:27:38 PM PDT 24 Jun 09 12:27:40 PM PDT 24 60225817 ps
T1012 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2051470561 Jun 09 12:27:07 PM PDT 24 Jun 09 12:27:10 PM PDT 24 14647386 ps
T1013 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1574107856 Jun 09 12:27:08 PM PDT 24 Jun 09 12:27:11 PM PDT 24 15218820 ps
T1014 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3665204656 Jun 09 12:26:52 PM PDT 24 Jun 09 12:26:53 PM PDT 24 20427494 ps
T102 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4084284095 Jun 09 12:27:22 PM PDT 24 Jun 09 12:27:32 PM PDT 24 248390791 ps
T1015 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4114658772 Jun 09 12:27:00 PM PDT 24 Jun 09 12:27:02 PM PDT 24 247182081 ps
T1016 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2220748846 Jun 09 12:26:58 PM PDT 24 Jun 09 12:27:38 PM PDT 24 5412197178 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%