Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.08 98.30 94.10 98.61 89.36 97.14 95.84 99.20


Total test records in report: 1081
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T100 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4287929054 Jun 09 12:27:08 PM PDT 24 Jun 09 12:27:12 PM PDT 24 237432228 ps
T176 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2263223450 Jun 09 12:27:08 PM PDT 24 Jun 09 12:27:29 PM PDT 24 2481597180 ps
T1017 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.47379288 Jun 09 12:27:07 PM PDT 24 Jun 09 12:27:13 PM PDT 24 2445272568 ps
T1018 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4192099468 Jun 09 12:27:07 PM PDT 24 Jun 09 12:27:12 PM PDT 24 562177211 ps
T1019 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.727493635 Jun 09 12:27:00 PM PDT 24 Jun 09 12:27:02 PM PDT 24 60658651 ps
T180 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1005845352 Jun 09 12:27:05 PM PDT 24 Jun 09 12:27:24 PM PDT 24 291058680 ps
T1020 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1425848881 Jun 09 12:26:58 PM PDT 24 Jun 09 12:27:22 PM PDT 24 4346449096 ps
T101 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2272380182 Jun 09 12:27:04 PM PDT 24 Jun 09 12:27:12 PM PDT 24 1266238930 ps
T1021 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3569160723 Jun 09 12:27:03 PM PDT 24 Jun 09 12:27:05 PM PDT 24 239759974 ps
T181 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3128375644 Jun 09 12:27:00 PM PDT 24 Jun 09 12:27:17 PM PDT 24 1200189247 ps
T1022 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3154794671 Jun 09 12:27:05 PM PDT 24 Jun 09 12:27:08 PM PDT 24 58840823 ps
T1023 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2757944951 Jun 09 12:27:07 PM PDT 24 Jun 09 12:27:10 PM PDT 24 18846723 ps
T1024 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.967639080 Jun 09 12:27:07 PM PDT 24 Jun 09 12:27:11 PM PDT 24 25448879 ps
T1025 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3343531518 Jun 09 12:27:00 PM PDT 24 Jun 09 12:27:02 PM PDT 24 20776366 ps
T182 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.507703826 Jun 09 12:27:00 PM PDT 24 Jun 09 12:27:15 PM PDT 24 634825417 ps
T99 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1104030085 Jun 09 12:27:06 PM PDT 24 Jun 09 12:27:13 PM PDT 24 64583344 ps
T107 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3056306622 Jun 09 12:26:55 PM PDT 24 Jun 09 12:26:58 PM PDT 24 62121864 ps
T108 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3792661068 Jun 09 12:27:08 PM PDT 24 Jun 09 12:27:12 PM PDT 24 35607161 ps
T1026 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.361208135 Jun 09 12:26:58 PM PDT 24 Jun 09 12:27:01 PM PDT 24 306155102 ps
T1027 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3905055092 Jun 09 12:27:09 PM PDT 24 Jun 09 12:27:15 PM PDT 24 38686102 ps
T1028 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.264157872 Jun 09 12:26:58 PM PDT 24 Jun 09 12:27:03 PM PDT 24 2032834594 ps
T1029 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1022506402 Jun 09 12:28:32 PM PDT 24 Jun 09 12:28:34 PM PDT 24 24088260 ps
T1030 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2560238371 Jun 09 12:27:04 PM PDT 24 Jun 09 12:27:10 PM PDT 24 120116158 ps
T1031 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3042120484 Jun 09 12:27:06 PM PDT 24 Jun 09 12:27:10 PM PDT 24 296130802 ps
T1032 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.911414438 Jun 09 12:27:06 PM PDT 24 Jun 09 12:27:11 PM PDT 24 141379263 ps
T1033 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.203657285 Jun 09 12:27:08 PM PDT 24 Jun 09 12:27:30 PM PDT 24 930888074 ps
T1034 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1610355556 Jun 09 12:27:09 PM PDT 24 Jun 09 12:27:11 PM PDT 24 11484631 ps
T1035 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.597423014 Jun 09 12:27:02 PM PDT 24 Jun 09 12:27:27 PM PDT 24 13003692260 ps
T1036 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1114593325 Jun 09 12:27:06 PM PDT 24 Jun 09 12:27:09 PM PDT 24 13558813 ps
T1037 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1758468252 Jun 09 12:27:08 PM PDT 24 Jun 09 12:27:11 PM PDT 24 42750900 ps
T1038 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3624250326 Jun 09 12:27:06 PM PDT 24 Jun 09 12:27:09 PM PDT 24 42592251 ps
T183 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3725615830 Jun 09 12:27:07 PM PDT 24 Jun 09 12:27:29 PM PDT 24 1490743869 ps
T1039 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3245850591 Jun 09 12:27:03 PM PDT 24 Jun 09 12:27:05 PM PDT 24 16052567 ps
T1040 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.918844010 Jun 09 12:27:06 PM PDT 24 Jun 09 12:27:09 PM PDT 24 36167290 ps
T1041 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.342976989 Jun 09 12:27:06 PM PDT 24 Jun 09 12:27:10 PM PDT 24 181889953 ps
T1042 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3046496401 Jun 09 12:27:02 PM PDT 24 Jun 09 12:27:04 PM PDT 24 44535091 ps
T177 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2214129992 Jun 09 12:27:02 PM PDT 24 Jun 09 12:27:10 PM PDT 24 416624846 ps
T1043 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.882590921 Jun 09 12:27:24 PM PDT 24 Jun 09 12:27:26 PM PDT 24 36002503 ps
T1044 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3471929002 Jun 09 12:27:04 PM PDT 24 Jun 09 12:27:06 PM PDT 24 16651899 ps
T1045 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1996847392 Jun 09 12:27:12 PM PDT 24 Jun 09 12:27:16 PM PDT 24 68273232 ps
T178 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.494202887 Jun 09 12:27:04 PM PDT 24 Jun 09 12:27:25 PM PDT 24 320264998 ps
T1046 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3288285730 Jun 09 12:27:06 PM PDT 24 Jun 09 12:27:12 PM PDT 24 1876566353 ps
T184 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1813631282 Jun 09 12:27:09 PM PDT 24 Jun 09 12:27:32 PM PDT 24 2588532571 ps
T1047 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1374709851 Jun 09 12:27:02 PM PDT 24 Jun 09 12:27:11 PM PDT 24 338289101 ps
T1048 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3669166663 Jun 09 12:27:06 PM PDT 24 Jun 09 12:27:11 PM PDT 24 42031895 ps
T1049 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4038736664 Jun 09 12:27:02 PM PDT 24 Jun 09 12:27:05 PM PDT 24 84590125 ps
T1050 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3371717773 Jun 09 12:27:09 PM PDT 24 Jun 09 12:27:25 PM PDT 24 407484671 ps
T1051 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1647103067 Jun 09 12:27:04 PM PDT 24 Jun 09 12:27:06 PM PDT 24 12454693 ps
T1052 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1427214317 Jun 09 12:26:52 PM PDT 24 Jun 09 12:26:57 PM PDT 24 137938693 ps
T1053 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3915591644 Jun 09 12:27:04 PM PDT 24 Jun 09 12:27:06 PM PDT 24 18267654 ps
T1054 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.751611245 Jun 09 12:27:04 PM PDT 24 Jun 09 12:27:25 PM PDT 24 1733831310 ps
T1055 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1337842136 Jun 09 12:28:27 PM PDT 24 Jun 09 12:28:28 PM PDT 24 16716238 ps
T1056 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1202983010 Jun 09 12:27:00 PM PDT 24 Jun 09 12:27:10 PM PDT 24 120076928 ps
T1057 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.162161781 Jun 09 12:27:37 PM PDT 24 Jun 09 12:27:42 PM PDT 24 353188215 ps
T1058 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1319455284 Jun 09 12:27:34 PM PDT 24 Jun 09 12:27:58 PM PDT 24 3609371249 ps
T1059 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1209045894 Jun 09 12:26:56 PM PDT 24 Jun 09 12:26:59 PM PDT 24 107298048 ps
T1060 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2886166486 Jun 09 12:27:06 PM PDT 24 Jun 09 12:27:10 PM PDT 24 95690416 ps
T1061 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.225276082 Jun 09 12:26:59 PM PDT 24 Jun 09 12:27:19 PM PDT 24 615732930 ps
T1062 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2597087197 Jun 09 12:27:08 PM PDT 24 Jun 09 12:27:11 PM PDT 24 36484484 ps
T1063 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3853863276 Jun 09 12:26:56 PM PDT 24 Jun 09 12:27:09 PM PDT 24 3342120327 ps
T1064 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1671145393 Jun 09 12:27:03 PM PDT 24 Jun 09 12:27:06 PM PDT 24 59118549 ps
T1065 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.717071421 Jun 09 12:27:05 PM PDT 24 Jun 09 12:27:09 PM PDT 24 259225094 ps
T1066 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.181776441 Jun 09 12:27:08 PM PDT 24 Jun 09 12:27:11 PM PDT 24 100856798 ps
T1067 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2786198045 Jun 09 12:27:03 PM PDT 24 Jun 09 12:27:05 PM PDT 24 21474013 ps
T1068 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.531091973 Jun 09 12:27:06 PM PDT 24 Jun 09 12:27:09 PM PDT 24 11878817 ps
T1069 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2953468041 Jun 09 12:28:46 PM PDT 24 Jun 09 12:28:50 PM PDT 24 1049316836 ps
T1070 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2196197263 Jun 09 12:28:20 PM PDT 24 Jun 09 12:28:21 PM PDT 24 15263314 ps
T185 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2801754316 Jun 09 12:27:04 PM PDT 24 Jun 09 12:27:21 PM PDT 24 590831290 ps
T1071 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.266172064 Jun 09 12:27:12 PM PDT 24 Jun 09 12:27:13 PM PDT 24 11082175 ps
T1072 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.466184918 Jun 09 12:26:53 PM PDT 24 Jun 09 12:26:55 PM PDT 24 40734485 ps
T1073 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3519631189 Jun 09 12:28:30 PM PDT 24 Jun 09 12:28:32 PM PDT 24 17241315 ps
T1074 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2657632269 Jun 09 12:27:08 PM PDT 24 Jun 09 12:27:11 PM PDT 24 25104096 ps
T1075 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1477141365 Jun 09 12:27:00 PM PDT 24 Jun 09 12:27:02 PM PDT 24 138626472 ps
T1076 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1615770703 Jun 09 12:27:35 PM PDT 24 Jun 09 12:27:40 PM PDT 24 184723004 ps
T1077 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1501083426 Jun 09 12:27:07 PM PDT 24 Jun 09 12:27:12 PM PDT 24 115414040 ps
T175 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3626685179 Jun 09 12:27:05 PM PDT 24 Jun 09 12:27:09 PM PDT 24 365966054 ps
T1078 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.516521298 Jun 09 12:26:59 PM PDT 24 Jun 09 12:27:13 PM PDT 24 3371870114 ps
T179 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.363895146 Jun 09 12:27:38 PM PDT 24 Jun 09 12:28:01 PM PDT 24 880139136 ps
T1079 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2528357027 Jun 09 12:27:03 PM PDT 24 Jun 09 12:27:06 PM PDT 24 110658684 ps
T1080 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1836484383 Jun 09 12:27:07 PM PDT 24 Jun 09 12:27:11 PM PDT 24 111478863 ps
T1081 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.502480121 Jun 09 12:27:06 PM PDT 24 Jun 09 12:27:10 PM PDT 24 35843009 ps

Test location /workspace/coverage/default/33.spi_device_flash_all.1224401586
Short name T8
Test name
Test status
Simulation time 76562297158 ps
CPU time 130.93 seconds
Started Jun 09 01:11:50 PM PDT 24
Finished Jun 09 01:14:01 PM PDT 24
Peak memory 233616 kb
Host smart-65ecf81d-70c4-47e7-b595-15780da6590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224401586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1224401586
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.46115451
Short name T18
Test name
Test status
Simulation time 420134007377 ps
CPU time 945.79 seconds
Started Jun 09 01:10:09 PM PDT 24
Finished Jun 09 01:25:56 PM PDT 24
Peak memory 267812 kb
Host smart-6fb49795-eaf2-48b0-9c1a-250ec4e7769b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46115451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress
_all.46115451
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1189582213
Short name T31
Test name
Test status
Simulation time 68517523782 ps
CPU time 351.92 seconds
Started Jun 09 01:12:01 PM PDT 24
Finished Jun 09 01:17:53 PM PDT 24
Peak memory 265848 kb
Host smart-dc4f85d9-dfac-422c-8167-095414ead670
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189582213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1189582213
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1042772302
Short name T103
Test name
Test status
Simulation time 171007278 ps
CPU time 3.84 seconds
Started Jun 09 12:27:38 PM PDT 24
Finished Jun 09 12:27:43 PM PDT 24
Peak memory 218072 kb
Host smart-5cdcdfc7-713a-4d5b-8422-075f84d88ee5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042772302 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1042772302
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.291358988
Short name T195
Test name
Test status
Simulation time 11337915259 ps
CPU time 151.5 seconds
Started Jun 09 01:12:25 PM PDT 24
Finished Jun 09 01:14:57 PM PDT 24
Peak memory 266652 kb
Host smart-94df74c6-65a4-48e1-ba21-13ef0a268a04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291358988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.291358988
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1866051321
Short name T186
Test name
Test status
Simulation time 5295156775 ps
CPU time 99.4 seconds
Started Jun 09 01:10:53 PM PDT 24
Finished Jun 09 01:12:33 PM PDT 24
Peak memory 262628 kb
Host smart-f05d30d8-6d81-4c36-8dcb-82e4891fd789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866051321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1866051321
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1919655844
Short name T62
Test name
Test status
Simulation time 16497164 ps
CPU time 0.71 seconds
Started Jun 09 01:08:31 PM PDT 24
Finished Jun 09 01:08:32 PM PDT 24
Peak memory 216968 kb
Host smart-f061a196-93dc-4fb8-8f99-8e312eb038b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919655844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1919655844
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.587128040
Short name T191
Test name
Test status
Simulation time 42341751915 ps
CPU time 386.31 seconds
Started Jun 09 01:11:44 PM PDT 24
Finished Jun 09 01:18:11 PM PDT 24
Peak memory 258296 kb
Host smart-9631d31e-ee1f-464d-85c4-fd01d1af8468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587128040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.587128040
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3864766336
Short name T57
Test name
Test status
Simulation time 58198659 ps
CPU time 1.07 seconds
Started Jun 09 01:08:58 PM PDT 24
Finished Jun 09 01:09:00 PM PDT 24
Peak memory 236048 kb
Host smart-c9a3c387-b236-4636-a441-b64a86e55ae8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864766336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3864766336
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.227916277
Short name T166
Test name
Test status
Simulation time 24842767326 ps
CPU time 293.83 seconds
Started Jun 09 01:11:20 PM PDT 24
Finished Jun 09 01:16:14 PM PDT 24
Peak memory 253164 kb
Host smart-bec61d3f-3f73-414a-9ce5-f8e23d354600
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227916277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.227916277
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3911580182
Short name T168
Test name
Test status
Simulation time 12851291810 ps
CPU time 86.96 seconds
Started Jun 09 01:10:57 PM PDT 24
Finished Jun 09 01:12:25 PM PDT 24
Peak memory 266496 kb
Host smart-dde3ef8b-e590-48c3-b7e6-bcd5d5c59df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911580182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3911580182
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1526809825
Short name T209
Test name
Test status
Simulation time 32176418038 ps
CPU time 349.26 seconds
Started Jun 09 01:11:42 PM PDT 24
Finished Jun 09 01:17:32 PM PDT 24
Peak memory 257852 kb
Host smart-1f16ac0f-e832-493f-9040-54e75e78cb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526809825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1526809825
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1975601867
Short name T14
Test name
Test status
Simulation time 152487266 ps
CPU time 3.21 seconds
Started Jun 09 01:10:27 PM PDT 24
Finished Jun 09 01:10:30 PM PDT 24
Peak memory 219756 kb
Host smart-36da1b54-fe35-4f3e-bb25-3ecccf171b64
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1975601867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1975601867
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2648823560
Short name T25
Test name
Test status
Simulation time 285989591429 ps
CPU time 696.84 seconds
Started Jun 09 01:10:59 PM PDT 24
Finished Jun 09 01:22:36 PM PDT 24
Peak memory 262700 kb
Host smart-1364ead2-a592-4eea-8996-497dd6c7b3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648823560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2648823560
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1785232313
Short name T215
Test name
Test status
Simulation time 399398953249 ps
CPU time 887.45 seconds
Started Jun 09 01:09:57 PM PDT 24
Finished Jun 09 01:24:45 PM PDT 24
Peak memory 253564 kb
Host smart-ad7b37f8-c976-4a3a-883a-842dec9ef44a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785232313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1785232313
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3128375644
Short name T181
Test name
Test status
Simulation time 1200189247 ps
CPU time 16.82 seconds
Started Jun 09 12:27:00 PM PDT 24
Finished Jun 09 12:27:17 PM PDT 24
Peak memory 215384 kb
Host smart-d36a649e-5b1a-4ff7-ac46-1230d0e8603c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128375644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3128375644
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3127333035
Short name T112
Test name
Test status
Simulation time 142422606 ps
CPU time 2.47 seconds
Started Jun 09 12:27:13 PM PDT 24
Finished Jun 09 12:27:16 PM PDT 24
Peak memory 215168 kb
Host smart-b63a2376-87ad-4337-9d69-ad852269ff2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127333035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3127333035
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3832846586
Short name T95
Test name
Test status
Simulation time 180026704 ps
CPU time 4.42 seconds
Started Jun 09 12:27:07 PM PDT 24
Finished Jun 09 12:27:14 PM PDT 24
Peak memory 215324 kb
Host smart-86b3d963-75bf-4de0-a68b-0912976d857c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832846586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
832846586
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.4123107577
Short name T202
Test name
Test status
Simulation time 489466080448 ps
CPU time 286.73 seconds
Started Jun 09 01:09:50 PM PDT 24
Finished Jun 09 01:14:38 PM PDT 24
Peak memory 256132 kb
Host smart-86af330e-f2ef-4c86-bc24-197d3e8995f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123107577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.4123107577
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1708572426
Short name T23
Test name
Test status
Simulation time 110276217754 ps
CPU time 281.92 seconds
Started Jun 09 01:08:43 PM PDT 24
Finished Jun 09 01:13:26 PM PDT 24
Peak memory 257100 kb
Host smart-2fbc06f4-eb6b-4de4-b573-9b1a06b0a870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708572426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1708572426
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.563884966
Short name T283
Test name
Test status
Simulation time 40791297607 ps
CPU time 124.07 seconds
Started Jun 09 01:10:06 PM PDT 24
Finished Jun 09 01:12:11 PM PDT 24
Peak memory 250108 kb
Host smart-ac02fce7-9a6f-4f68-970f-c832bbbb66f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563884966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.563884966
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1451723386
Short name T212
Test name
Test status
Simulation time 5069831322 ps
CPU time 104.33 seconds
Started Jun 09 01:10:47 PM PDT 24
Finished Jun 09 01:12:32 PM PDT 24
Peak memory 264568 kb
Host smart-fd7fbefa-8825-4c86-88ac-13b7aa24fb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451723386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1451723386
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.4038213357
Short name T30
Test name
Test status
Simulation time 530375291492 ps
CPU time 384.32 seconds
Started Jun 09 01:08:42 PM PDT 24
Finished Jun 09 01:15:07 PM PDT 24
Peak memory 252796 kb
Host smart-35127f59-3c6f-4336-a70e-c7a9c6d89ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038213357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.4038213357
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.505614328
Short name T189
Test name
Test status
Simulation time 57386387957 ps
CPU time 289.83 seconds
Started Jun 09 01:12:35 PM PDT 24
Finished Jun 09 01:17:25 PM PDT 24
Peak memory 255928 kb
Host smart-ae5306a8-3b86-4462-b9e2-35e23e54ed88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505614328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.505614328
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.649556105
Short name T15
Test name
Test status
Simulation time 37894334941 ps
CPU time 319.28 seconds
Started Jun 09 01:12:00 PM PDT 24
Finished Jun 09 01:17:20 PM PDT 24
Peak memory 250132 kb
Host smart-548ff94b-24ff-4b6a-bd39-9f6b8cccc475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649556105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.649556105
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.125630160
Short name T356
Test name
Test status
Simulation time 28662576 ps
CPU time 0.69 seconds
Started Jun 09 01:10:40 PM PDT 24
Finished Jun 09 01:10:41 PM PDT 24
Peak memory 206224 kb
Host smart-c6166406-ac8d-4a1d-9ce0-a5d12261eb74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125630160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.125630160
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3871568426
Short name T32
Test name
Test status
Simulation time 109130521961 ps
CPU time 279.1 seconds
Started Jun 09 01:10:43 PM PDT 24
Finished Jun 09 01:15:22 PM PDT 24
Peak memory 267664 kb
Host smart-301bbfec-4b47-44f1-bfa3-c1b4130d6857
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871568426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3871568426
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2198631978
Short name T77
Test name
Test status
Simulation time 7108827376 ps
CPU time 125.23 seconds
Started Jun 09 01:10:54 PM PDT 24
Finished Jun 09 01:13:00 PM PDT 24
Peak memory 256976 kb
Host smart-8633af6d-a8a2-4cbf-8716-e4cd1f5f1f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198631978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2198631978
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.4127980978
Short name T40
Test name
Test status
Simulation time 119172806902 ps
CPU time 190.66 seconds
Started Jun 09 01:10:57 PM PDT 24
Finished Jun 09 01:14:08 PM PDT 24
Peak memory 255920 kb
Host smart-6b410550-5eb0-491e-b7d3-e2f5509e862a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127980978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.4127980978
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.915510490
Short name T45
Test name
Test status
Simulation time 234686936638 ps
CPU time 622.52 seconds
Started Jun 09 01:09:27 PM PDT 24
Finished Jun 09 01:19:51 PM PDT 24
Peak memory 268548 kb
Host smart-abc7512a-327d-4fd5-b763-d48589efa9e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915510490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.915510490
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.494202887
Short name T178
Test name
Test status
Simulation time 320264998 ps
CPU time 19.12 seconds
Started Jun 09 12:27:04 PM PDT 24
Finished Jun 09 12:27:25 PM PDT 24
Peak memory 215204 kb
Host smart-adf2ba0b-0527-4421-b211-bc8f603e31af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494202887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.494202887
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3598268513
Short name T369
Test name
Test status
Simulation time 739911566 ps
CPU time 6.35 seconds
Started Jun 09 01:10:41 PM PDT 24
Finished Jun 09 01:10:47 PM PDT 24
Peak memory 217056 kb
Host smart-9233c8b0-df27-4d73-9c1f-379e4e027c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598268513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3598268513
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3114599528
Short name T320
Test name
Test status
Simulation time 280932825 ps
CPU time 4.34 seconds
Started Jun 09 01:11:30 PM PDT 24
Finished Jun 09 01:11:35 PM PDT 24
Peak memory 225356 kb
Host smart-0d02e3cc-4490-49b3-989a-a3fbe2f320f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114599528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3114599528
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1557578091
Short name T240
Test name
Test status
Simulation time 254395360028 ps
CPU time 450.6 seconds
Started Jun 09 01:10:30 PM PDT 24
Finished Jun 09 01:18:01 PM PDT 24
Peak memory 271032 kb
Host smart-9a1de30a-2e6c-40ef-a469-59f0c52efa1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557578091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1557578091
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3572888069
Short name T24
Test name
Test status
Simulation time 27640343453 ps
CPU time 88.3 seconds
Started Jun 09 01:09:35 PM PDT 24
Finished Jun 09 01:11:04 PM PDT 24
Peak memory 250156 kb
Host smart-13a5274d-767e-46c7-9890-a919fdc0af6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572888069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3572888069
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.4227004567
Short name T308
Test name
Test status
Simulation time 18591679175 ps
CPU time 232.98 seconds
Started Jun 09 01:09:33 PM PDT 24
Finished Jun 09 01:13:26 PM PDT 24
Peak memory 269732 kb
Host smart-4252ed20-dfe2-4354-8c6e-017e4e3d98a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227004567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.4227004567
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3905055092
Short name T1027
Test name
Test status
Simulation time 38686102 ps
CPU time 2.19 seconds
Started Jun 09 12:27:09 PM PDT 24
Finished Jun 09 12:27:15 PM PDT 24
Peak memory 215388 kb
Host smart-5714503b-3b54-49e9-b645-a94e47c527c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905055092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3905055092
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2278538330
Short name T7
Test name
Test status
Simulation time 5278722724 ps
CPU time 23.69 seconds
Started Jun 09 01:10:14 PM PDT 24
Finished Jun 09 01:10:38 PM PDT 24
Peak memory 241856 kb
Host smart-3e2e43ee-837e-44e3-b2da-2e219e6e2a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278538330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2278538330
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.656789577
Short name T718
Test name
Test status
Simulation time 11576311950 ps
CPU time 102.92 seconds
Started Jun 09 01:08:54 PM PDT 24
Finished Jun 09 01:10:38 PM PDT 24
Peak memory 258328 kb
Host smart-e3999350-d92a-40d2-9884-f2e79e8a0e67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656789577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.656789577
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2391212400
Short name T196
Test name
Test status
Simulation time 77259449554 ps
CPU time 160.72 seconds
Started Jun 09 01:10:21 PM PDT 24
Finished Jun 09 01:13:02 PM PDT 24
Peak memory 257336 kb
Host smart-d2af33c0-f5db-4d1d-965d-995f07292b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391212400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2391212400
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.62515131
Short name T190
Test name
Test status
Simulation time 38593171884 ps
CPU time 163.66 seconds
Started Jun 09 01:10:47 PM PDT 24
Finished Jun 09 01:13:31 PM PDT 24
Peak memory 253328 kb
Host smart-c5112095-1146-454f-95d9-92423aa32333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62515131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.62515131
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1369924859
Short name T299
Test name
Test status
Simulation time 188108530891 ps
CPU time 372.03 seconds
Started Jun 09 01:09:06 PM PDT 24
Finished Jun 09 01:15:19 PM PDT 24
Peak memory 250976 kb
Host smart-63a65d93-2086-4ac8-b53b-b1c853a0e4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369924859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1369924859
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2318217483
Short name T323
Test name
Test status
Simulation time 766854590 ps
CPU time 8.44 seconds
Started Jun 09 01:12:24 PM PDT 24
Finished Jun 09 01:12:33 PM PDT 24
Peak memory 241500 kb
Host smart-5db4d9c2-b3ac-4ef6-bbdc-e394add81dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318217483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2318217483
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1431260261
Short name T307
Test name
Test status
Simulation time 20688636550 ps
CPU time 74.68 seconds
Started Jun 09 01:12:41 PM PDT 24
Finished Jun 09 01:13:56 PM PDT 24
Peak memory 241392 kb
Host smart-ae6afb08-4e55-472d-8d29-b519b1dd74b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431260261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1431260261
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.828733099
Short name T89
Test name
Test status
Simulation time 404880669 ps
CPU time 2.37 seconds
Started Jun 09 01:09:52 PM PDT 24
Finished Jun 09 01:09:55 PM PDT 24
Peak memory 233460 kb
Host smart-ba5937c0-833e-45a1-9d10-25336fe35251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828733099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.828733099
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3526095160
Short name T94
Test name
Test status
Simulation time 2380810266 ps
CPU time 12.04 seconds
Started Jun 09 12:26:56 PM PDT 24
Finished Jun 09 12:27:09 PM PDT 24
Peak memory 215256 kb
Host smart-9a103d8c-42b1-4425-8c21-4150af8a0c39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526095160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3526095160
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1895438839
Short name T448
Test name
Test status
Simulation time 716029918 ps
CPU time 3.65 seconds
Started Jun 09 01:08:36 PM PDT 24
Finished Jun 09 01:08:40 PM PDT 24
Peak memory 218428 kb
Host smart-9f20febd-64e3-467e-92e5-e89e380f787a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895438839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1895438839
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3473554693
Short name T619
Test name
Test status
Simulation time 176533309 ps
CPU time 5.14 seconds
Started Jun 09 01:08:48 PM PDT 24
Finished Jun 09 01:08:53 PM PDT 24
Peak memory 233540 kb
Host smart-673f3cf4-eae4-4e33-b34e-a16158250ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473554693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3473554693
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2679525476
Short name T222
Test name
Test status
Simulation time 22463538408 ps
CPU time 146 seconds
Started Jun 09 01:09:57 PM PDT 24
Finished Jun 09 01:12:24 PM PDT 24
Peak memory 256836 kb
Host smart-220bfe98-5150-43b3-818d-def5d1e1ee95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679525476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2679525476
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.4112318295
Short name T123
Test name
Test status
Simulation time 11128637726 ps
CPU time 86.59 seconds
Started Jun 09 01:09:56 PM PDT 24
Finished Jun 09 01:11:23 PM PDT 24
Peak memory 266496 kb
Host smart-3e375291-b5a2-4ddb-ab53-9ef2c9a25dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112318295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.4112318295
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3084548421
Short name T301
Test name
Test status
Simulation time 69415389954 ps
CPU time 176.34 seconds
Started Jun 09 01:10:03 PM PDT 24
Finished Jun 09 01:13:00 PM PDT 24
Peak memory 254580 kb
Host smart-840d8164-6382-40b7-a6c5-dc105da94cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084548421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3084548421
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1614980724
Short name T151
Test name
Test status
Simulation time 5071958242 ps
CPU time 107.97 seconds
Started Jun 09 01:11:07 PM PDT 24
Finished Jun 09 01:12:55 PM PDT 24
Peak memory 257308 kb
Host smart-46ff7848-3b30-4d8d-b3c4-9938fe801282
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614980724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1614980724
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1619107582
Short name T279
Test name
Test status
Simulation time 58074667917 ps
CPU time 222.26 seconds
Started Jun 09 01:11:17 PM PDT 24
Finished Jun 09 01:15:00 PM PDT 24
Peak memory 251072 kb
Host smart-8ec3292e-48fd-4a40-aaa3-e4e758c576f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619107582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1619107582
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1678012593
Short name T327
Test name
Test status
Simulation time 292856956 ps
CPU time 8.06 seconds
Started Jun 09 01:11:39 PM PDT 24
Finished Jun 09 01:11:47 PM PDT 24
Peak memory 233548 kb
Host smart-84f63ce9-ee3e-4e27-9a6d-d1fcdfdb4870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678012593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1678012593
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1379802658
Short name T312
Test name
Test status
Simulation time 112701573984 ps
CPU time 280.51 seconds
Started Jun 09 01:12:12 PM PDT 24
Finished Jun 09 01:16:52 PM PDT 24
Peak memory 257700 kb
Host smart-ce5a3237-da5c-483d-882e-853715a087c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379802658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1379802658
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.4109672793
Short name T288
Test name
Test status
Simulation time 200012030909 ps
CPU time 361.81 seconds
Started Jun 09 01:12:34 PM PDT 24
Finished Jun 09 01:18:37 PM PDT 24
Peak memory 256044 kb
Host smart-ae04313e-1b30-478d-8f15-0bb33d882ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109672793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.4109672793
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1479327020
Short name T364
Test name
Test status
Simulation time 1740092638 ps
CPU time 3.91 seconds
Started Jun 09 01:10:18 PM PDT 24
Finished Jun 09 01:10:23 PM PDT 24
Peak memory 233540 kb
Host smart-b9655bcd-9fe3-4b02-aefe-b9d1719856c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479327020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1479327020
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.594553045
Short name T79
Test name
Test status
Simulation time 146199977 ps
CPU time 1.42 seconds
Started Jun 09 12:26:54 PM PDT 24
Finished Jun 09 12:26:56 PM PDT 24
Peak memory 206912 kb
Host smart-fe61ce94-52fb-496e-8769-fe6d2c003599
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594553045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.594553045
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3056306622
Short name T107
Test name
Test status
Simulation time 62121864 ps
CPU time 1.72 seconds
Started Jun 09 12:26:55 PM PDT 24
Finished Jun 09 12:26:58 PM PDT 24
Peak memory 215444 kb
Host smart-812c712c-8399-4e51-95d7-0459eb529d78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056306622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3056306622
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.597423014
Short name T1035
Test name
Test status
Simulation time 13003692260 ps
CPU time 24.18 seconds
Started Jun 09 12:27:02 PM PDT 24
Finished Jun 09 12:27:27 PM PDT 24
Peak memory 216232 kb
Host smart-e2f95d9a-1000-498a-8d24-0927462572ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597423014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.597423014
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.157461359
Short name T120
Test name
Test status
Simulation time 1867108398 ps
CPU time 27.48 seconds
Started Jun 09 12:27:02 PM PDT 24
Finished Jun 09 12:27:30 PM PDT 24
Peak memory 207232 kb
Host smart-25f99344-d21d-4150-b972-4c59fb62941f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157461359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.157461359
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3825574701
Short name T993
Test name
Test status
Simulation time 23028082 ps
CPU time 0.97 seconds
Started Jun 09 12:26:57 PM PDT 24
Finished Jun 09 12:26:58 PM PDT 24
Peak memory 206832 kb
Host smart-948dae44-bed6-400a-a637-2576103db8a3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825574701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3825574701
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3052219222
Short name T110
Test name
Test status
Simulation time 141875107 ps
CPU time 3.5 seconds
Started Jun 09 12:27:07 PM PDT 24
Finished Jun 09 12:27:13 PM PDT 24
Peak memory 217652 kb
Host smart-90ff3e1a-4e25-4a6f-b026-7c506af4905f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052219222 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3052219222
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2058784256
Short name T121
Test name
Test status
Simulation time 88646120 ps
CPU time 1.77 seconds
Started Jun 09 12:27:00 PM PDT 24
Finished Jun 09 12:27:02 PM PDT 24
Peak memory 215084 kb
Host smart-557f59e4-bd0e-4cb5-9e2a-0ca228011b3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058784256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
058784256
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.357084557
Short name T1003
Test name
Test status
Simulation time 14422496 ps
CPU time 0.79 seconds
Started Jun 09 12:28:28 PM PDT 24
Finished Jun 09 12:28:29 PM PDT 24
Peak memory 203644 kb
Host smart-f893ae96-9e8a-43ce-8a20-52d19d21d521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357084557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.357084557
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3629755860
Short name T991
Test name
Test status
Simulation time 70064050 ps
CPU time 2.05 seconds
Started Jun 09 12:27:02 PM PDT 24
Finished Jun 09 12:27:05 PM PDT 24
Peak memory 215252 kb
Host smart-a9595df9-8307-476a-972c-6d80dd0d6dd2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629755860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3629755860
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3665204656
Short name T1014
Test name
Test status
Simulation time 20427494 ps
CPU time 0.67 seconds
Started Jun 09 12:26:52 PM PDT 24
Finished Jun 09 12:26:53 PM PDT 24
Peak memory 203992 kb
Host smart-07d149e3-4b85-47c2-8e3d-a4116dfd2d79
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665204656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3665204656
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1209045894
Short name T1059
Test name
Test status
Simulation time 107298048 ps
CPU time 2.75 seconds
Started Jun 09 12:26:56 PM PDT 24
Finished Jun 09 12:26:59 PM PDT 24
Peak memory 215208 kb
Host smart-11383ae7-f305-49db-9510-6f7680bc5c3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209045894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1209045894
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3873815514
Short name T97
Test name
Test status
Simulation time 55971804 ps
CPU time 1.92 seconds
Started Jun 09 12:27:08 PM PDT 24
Finished Jun 09 12:27:12 PM PDT 24
Peak memory 215360 kb
Host smart-4e4ac794-f186-4e9a-8a41-82a9c80e2460
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873815514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
873815514
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2263223450
Short name T176
Test name
Test status
Simulation time 2481597180 ps
CPU time 14.83 seconds
Started Jun 09 12:27:08 PM PDT 24
Finished Jun 09 12:27:29 PM PDT 24
Peak memory 215912 kb
Host smart-5ddb9910-35b8-4191-b0fd-00ef59f562c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263223450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2263223450
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1251565553
Short name T118
Test name
Test status
Simulation time 1242353757 ps
CPU time 13.04 seconds
Started Jun 09 12:28:30 PM PDT 24
Finished Jun 09 12:28:45 PM PDT 24
Peak memory 215364 kb
Host smart-ddceb771-fcb9-48f0-aa4f-7f8d4e546408
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251565553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1251565553
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2505445654
Short name T113
Test name
Test status
Simulation time 1844137822 ps
CPU time 13.12 seconds
Started Jun 09 12:27:02 PM PDT 24
Finished Jun 09 12:27:16 PM PDT 24
Peak memory 215120 kb
Host smart-63760062-94b1-4eb8-821d-07abaaa44c8a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505445654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2505445654
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.140496139
Short name T997
Test name
Test status
Simulation time 40739718 ps
CPU time 2.6 seconds
Started Jun 09 12:27:02 PM PDT 24
Finished Jun 09 12:27:06 PM PDT 24
Peak memory 216652 kb
Host smart-39539692-e3ce-44ad-a58f-5293c79f31e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140496139 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.140496139
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.544505289
Short name T114
Test name
Test status
Simulation time 195076156 ps
CPU time 2.89 seconds
Started Jun 09 12:27:04 PM PDT 24
Finished Jun 09 12:27:09 PM PDT 24
Peak memory 215172 kb
Host smart-506bc121-d259-4fe3-a336-ce9664bdc3c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544505289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.544505289
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1337842136
Short name T1055
Test name
Test status
Simulation time 16716238 ps
CPU time 0.75 seconds
Started Jun 09 12:28:27 PM PDT 24
Finished Jun 09 12:28:28 PM PDT 24
Peak memory 203948 kb
Host smart-7c2fd5ef-86be-4d6b-ad6d-d51d68fbaa48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337842136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
337842136
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1136997445
Short name T119
Test name
Test status
Simulation time 132351217 ps
CPU time 1.13 seconds
Started Jun 09 12:27:05 PM PDT 24
Finished Jun 09 12:27:08 PM PDT 24
Peak memory 215192 kb
Host smart-1d52eb53-d9bc-4833-b1d7-6e7fbf5cb1ef
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136997445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1136997445
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2196197263
Short name T1070
Test name
Test status
Simulation time 15263314 ps
CPU time 0.66 seconds
Started Jun 09 12:28:20 PM PDT 24
Finished Jun 09 12:28:21 PM PDT 24
Peak memory 203564 kb
Host smart-d8a50bcb-76ef-46b1-a150-789d916d9ca6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196197263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2196197263
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2953468041
Short name T1069
Test name
Test status
Simulation time 1049316836 ps
CPU time 3.34 seconds
Started Jun 09 12:28:46 PM PDT 24
Finished Jun 09 12:28:50 PM PDT 24
Peak memory 215116 kb
Host smart-b7321258-4159-419a-93ba-c5c1bfe28e7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953468041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2953468041
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1427214317
Short name T1052
Test name
Test status
Simulation time 137938693 ps
CPU time 4.63 seconds
Started Jun 09 12:26:52 PM PDT 24
Finished Jun 09 12:26:57 PM PDT 24
Peak memory 215324 kb
Host smart-b283c3a1-091e-4ea5-9311-73b87c9e449c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427214317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
427214317
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2214129992
Short name T177
Test name
Test status
Simulation time 416624846 ps
CPU time 6.41 seconds
Started Jun 09 12:27:02 PM PDT 24
Finished Jun 09 12:27:10 PM PDT 24
Peak memory 215436 kb
Host smart-c16a47f9-0f3a-49ee-b7b1-9f70f18a9131
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214129992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2214129992
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3669166663
Short name T1048
Test name
Test status
Simulation time 42031895 ps
CPU time 2.67 seconds
Started Jun 09 12:27:06 PM PDT 24
Finished Jun 09 12:27:11 PM PDT 24
Peak memory 217028 kb
Host smart-7e1a3784-e729-4808-ad58-d3647e5dbfea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669166663 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3669166663
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3471929002
Short name T1044
Test name
Test status
Simulation time 16651899 ps
CPU time 0.73 seconds
Started Jun 09 12:27:04 PM PDT 24
Finished Jun 09 12:27:06 PM PDT 24
Peak memory 203700 kb
Host smart-33c383f2-9511-490d-8b84-1cf735a23c42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471929002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3471929002
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4213761544
Short name T1010
Test name
Test status
Simulation time 284715418 ps
CPU time 2.77 seconds
Started Jun 09 12:26:55 PM PDT 24
Finished Jun 09 12:26:59 PM PDT 24
Peak memory 215196 kb
Host smart-e267a1f7-3801-4278-aabc-9deb671f29b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213761544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.4213761544
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4084284095
Short name T102
Test name
Test status
Simulation time 248390791 ps
CPU time 3.72 seconds
Started Jun 09 12:27:22 PM PDT 24
Finished Jun 09 12:27:32 PM PDT 24
Peak memory 215492 kb
Host smart-c07404aa-170f-4dce-a678-13cf73c4401f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084284095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
4084284095
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.516521298
Short name T1078
Test name
Test status
Simulation time 3371870114 ps
CPU time 13.31 seconds
Started Jun 09 12:26:59 PM PDT 24
Finished Jun 09 12:27:13 PM PDT 24
Peak memory 215344 kb
Host smart-53fcd812-f1ed-4502-9cc7-f7ac08afe793
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516521298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.516521298
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3569160723
Short name T1021
Test name
Test status
Simulation time 239759974 ps
CPU time 1.68 seconds
Started Jun 09 12:27:03 PM PDT 24
Finished Jun 09 12:27:05 PM PDT 24
Peak memory 216284 kb
Host smart-239c5424-188b-4413-9140-eef2d6fb2aad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569160723 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3569160723
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2682815490
Short name T117
Test name
Test status
Simulation time 123971572 ps
CPU time 2.32 seconds
Started Jun 09 12:27:07 PM PDT 24
Finished Jun 09 12:27:12 PM PDT 24
Peak memory 215100 kb
Host smart-2f8eb50d-91f5-43e3-96e7-4760020fdd5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682815490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2682815490
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3643528597
Short name T999
Test name
Test status
Simulation time 15725863 ps
CPU time 0.79 seconds
Started Jun 09 12:27:07 PM PDT 24
Finished Jun 09 12:27:10 PM PDT 24
Peak memory 203684 kb
Host smart-d041d759-825f-4223-a231-6a4b5d16fe29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643528597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3643528597
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.264157872
Short name T1028
Test name
Test status
Simulation time 2032834594 ps
CPU time 4.09 seconds
Started Jun 09 12:26:58 PM PDT 24
Finished Jun 09 12:27:03 PM PDT 24
Peak memory 215220 kb
Host smart-e52db576-cdb4-443d-9501-3be7b09a7768
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264157872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.264157872
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4247035737
Short name T93
Test name
Test status
Simulation time 535477394 ps
CPU time 7.17 seconds
Started Jun 09 12:27:06 PM PDT 24
Finished Jun 09 12:27:15 PM PDT 24
Peak memory 215388 kb
Host smart-8ebe8977-6271-4bdd-bf33-60974a8c472e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247035737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.4247035737
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3009048160
Short name T143
Test name
Test status
Simulation time 222670897 ps
CPU time 1.91 seconds
Started Jun 09 12:26:54 PM PDT 24
Finished Jun 09 12:26:56 PM PDT 24
Peak memory 216348 kb
Host smart-ddaacf5f-48ab-468d-ac56-8167df36cdd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009048160 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3009048160
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3042120484
Short name T1031
Test name
Test status
Simulation time 296130802 ps
CPU time 2.49 seconds
Started Jun 09 12:27:06 PM PDT 24
Finished Jun 09 12:27:10 PM PDT 24
Peak memory 215132 kb
Host smart-86a8e758-253e-4155-b186-1bd70750bfec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042120484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3042120484
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3624250326
Short name T1038
Test name
Test status
Simulation time 42592251 ps
CPU time 0.68 seconds
Started Jun 09 12:27:06 PM PDT 24
Finished Jun 09 12:27:09 PM PDT 24
Peak memory 203692 kb
Host smart-82ff6b1d-ba20-4191-98fd-d2301192e73f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624250326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3624250326
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1202983010
Short name T1056
Test name
Test status
Simulation time 120076928 ps
CPU time 3.78 seconds
Started Jun 09 12:27:00 PM PDT 24
Finished Jun 09 12:27:10 PM PDT 24
Peak memory 215260 kb
Host smart-fcba13e5-cf91-4752-8688-1ea7eb0b8c01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202983010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1202983010
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4287929054
Short name T100
Test name
Test status
Simulation time 237432228 ps
CPU time 1.93 seconds
Started Jun 09 12:27:08 PM PDT 24
Finished Jun 09 12:27:12 PM PDT 24
Peak memory 215388 kb
Host smart-a02aaf22-4ef6-457a-920e-16c331ce2221
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287929054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
4287929054
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3522610052
Short name T145
Test name
Test status
Simulation time 700775928 ps
CPU time 15.62 seconds
Started Jun 09 12:27:05 PM PDT 24
Finished Jun 09 12:27:22 PM PDT 24
Peak memory 215240 kb
Host smart-00e2d465-44a4-4358-9621-dfd6810ba82a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522610052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3522610052
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.286113728
Short name T111
Test name
Test status
Simulation time 90770221 ps
CPU time 2.58 seconds
Started Jun 09 12:27:13 PM PDT 24
Finished Jun 09 12:27:16 PM PDT 24
Peak memory 216300 kb
Host smart-5442ea70-d7db-4246-b4e8-9ff7ad7247bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286113728 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.286113728
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.967639080
Short name T1024
Test name
Test status
Simulation time 25448879 ps
CPU time 1.21 seconds
Started Jun 09 12:27:07 PM PDT 24
Finished Jun 09 12:27:11 PM PDT 24
Peak memory 215176 kb
Host smart-ba70bab0-2866-4c58-8551-dc4d9ca3177f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967639080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.967639080
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1758468252
Short name T1037
Test name
Test status
Simulation time 42750900 ps
CPU time 0.73 seconds
Started Jun 09 12:27:08 PM PDT 24
Finished Jun 09 12:27:11 PM PDT 24
Peak memory 203728 kb
Host smart-90eec61f-d5d1-41c3-9da9-35b8f7d70811
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758468252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1758468252
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3858124611
Short name T1000
Test name
Test status
Simulation time 56016428 ps
CPU time 1.74 seconds
Started Jun 09 12:27:06 PM PDT 24
Finished Jun 09 12:27:09 PM PDT 24
Peak memory 215200 kb
Host smart-884627e6-15d4-4227-8818-50adc0a74a03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858124611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3858124611
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3296550912
Short name T106
Test name
Test status
Simulation time 91116613 ps
CPU time 1.46 seconds
Started Jun 09 12:27:04 PM PDT 24
Finished Jun 09 12:27:07 PM PDT 24
Peak memory 215300 kb
Host smart-1825afaa-55b4-4e6c-9714-99e6e77012f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296550912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3296550912
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1374709851
Short name T1047
Test name
Test status
Simulation time 338289101 ps
CPU time 7.49 seconds
Started Jun 09 12:27:02 PM PDT 24
Finished Jun 09 12:27:11 PM PDT 24
Peak memory 215880 kb
Host smart-033a7786-75a3-471e-aca4-cc2b7d6ada6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374709851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1374709851
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.717071421
Short name T1065
Test name
Test status
Simulation time 259225094 ps
CPU time 1.96 seconds
Started Jun 09 12:27:05 PM PDT 24
Finished Jun 09 12:27:09 PM PDT 24
Peak memory 216276 kb
Host smart-6066db47-47df-415e-9ef1-f5e667f24658
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717071421 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.717071421
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.181776441
Short name T1066
Test name
Test status
Simulation time 100856798 ps
CPU time 1.4 seconds
Started Jun 09 12:27:08 PM PDT 24
Finished Jun 09 12:27:11 PM PDT 24
Peak memory 207108 kb
Host smart-3de58d2f-a804-43f8-aad7-88ba3b901c7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181776441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.181776441
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1114593325
Short name T1036
Test name
Test status
Simulation time 13558813 ps
CPU time 0.68 seconds
Started Jun 09 12:27:06 PM PDT 24
Finished Jun 09 12:27:09 PM PDT 24
Peak memory 203696 kb
Host smart-243aaa66-0e02-4103-862e-3b6d5af1ce37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114593325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1114593325
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.973838049
Short name T146
Test name
Test status
Simulation time 83765358 ps
CPU time 1.97 seconds
Started Jun 09 12:27:01 PM PDT 24
Finished Jun 09 12:27:04 PM PDT 24
Peak memory 206960 kb
Host smart-ddab9e40-7459-44c3-a533-8557cc9102d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973838049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.973838049
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1615770703
Short name T1076
Test name
Test status
Simulation time 184723004 ps
CPU time 4.35 seconds
Started Jun 09 12:27:35 PM PDT 24
Finished Jun 09 12:27:40 PM PDT 24
Peak memory 215388 kb
Host smart-9ccccb1f-30d9-4cb3-a47d-dc338210f39e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615770703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1615770703
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.363895146
Short name T179
Test name
Test status
Simulation time 880139136 ps
CPU time 21.96 seconds
Started Jun 09 12:27:38 PM PDT 24
Finished Jun 09 12:28:01 PM PDT 24
Peak memory 215188 kb
Host smart-0b3cae4a-68cd-4cf6-8f03-2ab652497a66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363895146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.363895146
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.123901935
Short name T977
Test name
Test status
Simulation time 376841768 ps
CPU time 2.39 seconds
Started Jun 09 12:27:09 PM PDT 24
Finished Jun 09 12:27:13 PM PDT 24
Peak memory 218036 kb
Host smart-707853c0-c53f-444d-af32-7c5900a0b477
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123901935 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.123901935
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4004588892
Short name T133
Test name
Test status
Simulation time 23419690 ps
CPU time 1.29 seconds
Started Jun 09 12:27:04 PM PDT 24
Finished Jun 09 12:27:06 PM PDT 24
Peak memory 206920 kb
Host smart-deeb298a-b127-4002-ac57-a7d41bb1eb94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004588892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
4004588892
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1647103067
Short name T1051
Test name
Test status
Simulation time 12454693 ps
CPU time 0.74 seconds
Started Jun 09 12:27:04 PM PDT 24
Finished Jun 09 12:27:06 PM PDT 24
Peak memory 203672 kb
Host smart-812ab0b6-1147-4001-a921-8b72ac492497
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647103067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1647103067
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2859073395
Short name T988
Test name
Test status
Simulation time 212415430 ps
CPU time 2.87 seconds
Started Jun 09 12:27:06 PM PDT 24
Finished Jun 09 12:27:11 PM PDT 24
Peak memory 215156 kb
Host smart-594faa15-542f-4f68-b760-770bd00fee2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859073395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2859073395
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3626685179
Short name T175
Test name
Test status
Simulation time 365966054 ps
CPU time 2.16 seconds
Started Jun 09 12:27:05 PM PDT 24
Finished Jun 09 12:27:09 PM PDT 24
Peak memory 215308 kb
Host smart-19eea66f-5af2-4630-957e-30e00c23e1e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626685179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3626685179
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1836484383
Short name T1080
Test name
Test status
Simulation time 111478863 ps
CPU time 1.61 seconds
Started Jun 09 12:27:07 PM PDT 24
Finished Jun 09 12:27:11 PM PDT 24
Peak memory 215272 kb
Host smart-598318ae-b955-4df8-97cb-550fb23046ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836484383 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1836484383
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4114658772
Short name T1015
Test name
Test status
Simulation time 247182081 ps
CPU time 1.89 seconds
Started Jun 09 12:27:00 PM PDT 24
Finished Jun 09 12:27:02 PM PDT 24
Peak memory 215180 kb
Host smart-9d084f73-fbe0-475e-aa33-061143a1d29d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114658772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
4114658772
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1574107856
Short name T1013
Test name
Test status
Simulation time 15218820 ps
CPU time 0.74 seconds
Started Jun 09 12:27:08 PM PDT 24
Finished Jun 09 12:27:11 PM PDT 24
Peak memory 203632 kb
Host smart-4da4757b-18ad-47ca-9da5-5afbe5c844c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574107856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1574107856
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1996847392
Short name T1045
Test name
Test status
Simulation time 68273232 ps
CPU time 3.5 seconds
Started Jun 09 12:27:12 PM PDT 24
Finished Jun 09 12:27:16 PM PDT 24
Peak memory 207360 kb
Host smart-e0bdb339-9a09-41bc-8f5a-c59cf5c7ce5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996847392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1996847392
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.507703826
Short name T182
Test name
Test status
Simulation time 634825417 ps
CPU time 13.82 seconds
Started Jun 09 12:27:00 PM PDT 24
Finished Jun 09 12:27:15 PM PDT 24
Peak memory 215196 kb
Host smart-151d5008-12a4-4a65-ad00-b11cd9f0c670
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507703826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.507703826
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4088229358
Short name T109
Test name
Test status
Simulation time 44559609 ps
CPU time 1.59 seconds
Started Jun 09 12:27:09 PM PDT 24
Finished Jun 09 12:27:12 PM PDT 24
Peak memory 215216 kb
Host smart-afa2ff0c-ddbd-4be3-a8e3-13c21c1fbec7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088229358 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.4088229358
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3456251553
Short name T116
Test name
Test status
Simulation time 31524500 ps
CPU time 1.91 seconds
Started Jun 09 12:27:05 PM PDT 24
Finished Jun 09 12:27:08 PM PDT 24
Peak memory 215192 kb
Host smart-829292a6-a538-4e83-8cee-561f2e4c7f4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456251553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3456251553
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.358618825
Short name T973
Test name
Test status
Simulation time 26376141 ps
CPU time 0.73 seconds
Started Jun 09 12:27:00 PM PDT 24
Finished Jun 09 12:27:01 PM PDT 24
Peak memory 203684 kb
Host smart-430c2175-030c-4bdf-ae7e-a116c54c9da9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358618825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.358618825
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1671145393
Short name T1064
Test name
Test status
Simulation time 59118549 ps
CPU time 1.86 seconds
Started Jun 09 12:27:03 PM PDT 24
Finished Jun 09 12:27:06 PM PDT 24
Peak memory 215264 kb
Host smart-f05ef54a-7ebe-41e6-966c-91084c444904
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671145393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1671145393
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1220231441
Short name T91
Test name
Test status
Simulation time 606004211 ps
CPU time 2.33 seconds
Started Jun 09 12:28:31 PM PDT 24
Finished Jun 09 12:28:34 PM PDT 24
Peak memory 215052 kb
Host smart-de5d54e0-04a4-474d-b0d9-d905e4f08c2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220231441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1220231441
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3134386002
Short name T144
Test name
Test status
Simulation time 350907497 ps
CPU time 7.39 seconds
Started Jun 09 12:27:06 PM PDT 24
Finished Jun 09 12:27:16 PM PDT 24
Peak memory 216208 kb
Host smart-c1fd8f45-c7d2-454b-bb3a-3733cefe30f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134386002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3134386002
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.361208135
Short name T1026
Test name
Test status
Simulation time 306155102 ps
CPU time 2.55 seconds
Started Jun 09 12:26:58 PM PDT 24
Finished Jun 09 12:27:01 PM PDT 24
Peak memory 216836 kb
Host smart-6d8da7a9-49a2-4466-8518-e4ce5b376bd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361208135 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.361208135
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.687916509
Short name T986
Test name
Test status
Simulation time 132906000 ps
CPU time 2.01 seconds
Started Jun 09 12:27:07 PM PDT 24
Finished Jun 09 12:27:11 PM PDT 24
Peak memory 206892 kb
Host smart-c2325d60-530d-4644-9519-af87fafc7d77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687916509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.687916509
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2013000741
Short name T996
Test name
Test status
Simulation time 36853039 ps
CPU time 0.75 seconds
Started Jun 09 12:27:04 PM PDT 24
Finished Jun 09 12:27:13 PM PDT 24
Peak memory 203688 kb
Host smart-0e745edc-c6cb-48ce-8cca-e5dee07c688c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013000741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2013000741
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2719670798
Short name T142
Test name
Test status
Simulation time 386931136 ps
CPU time 3.99 seconds
Started Jun 09 12:27:05 PM PDT 24
Finished Jun 09 12:27:11 PM PDT 24
Peak memory 215168 kb
Host smart-e062d465-78c9-44af-9f29-3dda9ec5eda2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719670798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2719670798
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1501083426
Short name T1077
Test name
Test status
Simulation time 115414040 ps
CPU time 3.23 seconds
Started Jun 09 12:27:07 PM PDT 24
Finished Jun 09 12:27:12 PM PDT 24
Peak memory 215448 kb
Host smart-d528d99c-3acf-45b7-80aa-dd2db3358678
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501083426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1501083426
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.691313038
Short name T92
Test name
Test status
Simulation time 3305017375 ps
CPU time 22.85 seconds
Started Jun 09 12:27:25 PM PDT 24
Finished Jun 09 12:27:48 PM PDT 24
Peak memory 215496 kb
Host smart-70f729e1-feac-4a68-b524-970db1048b06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691313038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.691313038
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2886166486
Short name T1060
Test name
Test status
Simulation time 95690416 ps
CPU time 1.74 seconds
Started Jun 09 12:27:06 PM PDT 24
Finished Jun 09 12:27:10 PM PDT 24
Peak memory 215304 kb
Host smart-7d25aa92-241c-4064-af32-b55f391f7fa7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886166486 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2886166486
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3702496447
Short name T115
Test name
Test status
Simulation time 64859993 ps
CPU time 1.92 seconds
Started Jun 09 12:27:08 PM PDT 24
Finished Jun 09 12:27:12 PM PDT 24
Peak memory 206924 kb
Host smart-4fe0422d-665d-467d-9ccf-453b0ce2c230
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702496447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3702496447
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2597087197
Short name T1062
Test name
Test status
Simulation time 36484484 ps
CPU time 0.74 seconds
Started Jun 09 12:27:08 PM PDT 24
Finished Jun 09 12:27:11 PM PDT 24
Peak memory 203640 kb
Host smart-863d5893-6a80-40c5-9e0d-3fc66e42398a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597087197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2597087197
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.561440733
Short name T135
Test name
Test status
Simulation time 76010296 ps
CPU time 2.58 seconds
Started Jun 09 12:27:08 PM PDT 24
Finished Jun 09 12:27:13 PM PDT 24
Peak memory 215192 kb
Host smart-23fe23b5-7636-489a-8d15-bedded588c6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561440733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.561440733
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.649518900
Short name T59
Test name
Test status
Simulation time 46341838 ps
CPU time 1.6 seconds
Started Jun 09 12:27:05 PM PDT 24
Finished Jun 09 12:27:09 PM PDT 24
Peak memory 215312 kb
Host smart-4e10ea1e-ddfb-4eb5-b923-b2b2107c68bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649518900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.649518900
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1319455284
Short name T1058
Test name
Test status
Simulation time 3609371249 ps
CPU time 23.87 seconds
Started Jun 09 12:27:34 PM PDT 24
Finished Jun 09 12:27:58 PM PDT 24
Peak memory 215128 kb
Host smart-5a9b9570-b6f9-4f98-8494-a65cfd50312a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319455284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1319455284
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2220748846
Short name T1016
Test name
Test status
Simulation time 5412197178 ps
CPU time 39.56 seconds
Started Jun 09 12:26:58 PM PDT 24
Finished Jun 09 12:27:38 PM PDT 24
Peak memory 206988 kb
Host smart-d808abf8-d8a7-4c85-b782-904d65b19e2e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220748846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2220748846
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3368784376
Short name T1007
Test name
Test status
Simulation time 23463350 ps
CPU time 1.29 seconds
Started Jun 09 12:27:05 PM PDT 24
Finished Jun 09 12:27:08 PM PDT 24
Peak memory 206944 kb
Host smart-1a7e4bdf-77f8-4071-a98f-21024ea04616
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368784376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3368784376
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3288285730
Short name T1046
Test name
Test status
Simulation time 1876566353 ps
CPU time 3.47 seconds
Started Jun 09 12:27:06 PM PDT 24
Finished Jun 09 12:27:12 PM PDT 24
Peak memory 216984 kb
Host smart-ce24ccdf-c88c-4c34-a01b-32ec8bde714a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288285730 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3288285730
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4038736664
Short name T1049
Test name
Test status
Simulation time 84590125 ps
CPU time 2.04 seconds
Started Jun 09 12:27:02 PM PDT 24
Finished Jun 09 12:27:05 PM PDT 24
Peak memory 206900 kb
Host smart-228d263f-f5dc-4b87-a233-d1c6e117eed5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038736664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.4
038736664
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3468778030
Short name T1008
Test name
Test status
Simulation time 78638319 ps
CPU time 0.75 seconds
Started Jun 09 12:27:25 PM PDT 24
Finished Jun 09 12:27:26 PM PDT 24
Peak memory 204004 kb
Host smart-f6ad211b-926e-481f-af58-9d760e29cef2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468778030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
468778030
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2528357027
Short name T1079
Test name
Test status
Simulation time 110658684 ps
CPU time 1.79 seconds
Started Jun 09 12:27:03 PM PDT 24
Finished Jun 09 12:27:06 PM PDT 24
Peak memory 215244 kb
Host smart-46f6b056-8b5f-4f59-bdea-c5afcc27bc00
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528357027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2528357027
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3343531518
Short name T1025
Test name
Test status
Simulation time 20776366 ps
CPU time 0.65 seconds
Started Jun 09 12:27:00 PM PDT 24
Finished Jun 09 12:27:02 PM PDT 24
Peak memory 203940 kb
Host smart-a78c49b1-3f7a-4021-9e68-c3f99ae002e6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343531518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3343531518
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.47379288
Short name T1017
Test name
Test status
Simulation time 2445272568 ps
CPU time 3.36 seconds
Started Jun 09 12:27:07 PM PDT 24
Finished Jun 09 12:27:13 PM PDT 24
Peak memory 215292 kb
Host smart-ffca4d46-a85a-4cd9-bf6a-d11854389509
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47379288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_same_csr_outstanding.47379288
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3792661068
Short name T108
Test name
Test status
Simulation time 35607161 ps
CPU time 1.9 seconds
Started Jun 09 12:27:08 PM PDT 24
Finished Jun 09 12:27:12 PM PDT 24
Peak memory 215288 kb
Host smart-f2651682-292c-4f30-a98c-6f714034f310
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792661068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
792661068
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1472010920
Short name T980
Test name
Test status
Simulation time 11861103 ps
CPU time 0.69 seconds
Started Jun 09 12:27:37 PM PDT 24
Finished Jun 09 12:27:38 PM PDT 24
Peak memory 203704 kb
Host smart-5883cf95-6644-4207-8db5-46b5bdf5f311
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472010920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1472010920
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1622273024
Short name T984
Test name
Test status
Simulation time 20941994 ps
CPU time 0.71 seconds
Started Jun 09 12:27:07 PM PDT 24
Finished Jun 09 12:27:10 PM PDT 24
Peak memory 203672 kb
Host smart-b6ae1d47-1f9c-4d67-9cb4-c73e3028d950
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622273024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1622273024
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3915591644
Short name T1053
Test name
Test status
Simulation time 18267654 ps
CPU time 0.75 seconds
Started Jun 09 12:27:04 PM PDT 24
Finished Jun 09 12:27:06 PM PDT 24
Peak memory 203688 kb
Host smart-ae22f65e-8e33-4048-ac74-23fdbfb281a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915591644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3915591644
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3245850591
Short name T1039
Test name
Test status
Simulation time 16052567 ps
CPU time 0.7 seconds
Started Jun 09 12:27:03 PM PDT 24
Finished Jun 09 12:27:05 PM PDT 24
Peak memory 203688 kb
Host smart-f50f762d-2905-4922-aa9b-d8f81b0d28aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245850591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3245850591
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2609227688
Short name T967
Test name
Test status
Simulation time 14316375 ps
CPU time 0.73 seconds
Started Jun 09 12:27:08 PM PDT 24
Finished Jun 09 12:27:11 PM PDT 24
Peak memory 203964 kb
Host smart-ea48364d-e2bc-48c1-af60-862ffb50d6fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609227688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2609227688
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.238459212
Short name T979
Test name
Test status
Simulation time 15031379 ps
CPU time 0.74 seconds
Started Jun 09 12:26:58 PM PDT 24
Finished Jun 09 12:26:59 PM PDT 24
Peak memory 203648 kb
Host smart-3b4d7b4a-e12a-4ce4-9fd8-b9a07cc2bac0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238459212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.238459212
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2657632269
Short name T1074
Test name
Test status
Simulation time 25104096 ps
CPU time 0.69 seconds
Started Jun 09 12:27:08 PM PDT 24
Finished Jun 09 12:27:11 PM PDT 24
Peak memory 203660 kb
Host smart-4f2dc82d-5f31-452c-8b60-4e6ba1a31c50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657632269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2657632269
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.238540366
Short name T985
Test name
Test status
Simulation time 15828962 ps
CPU time 0.73 seconds
Started Jun 09 12:27:36 PM PDT 24
Finished Jun 09 12:27:37 PM PDT 24
Peak memory 203704 kb
Host smart-8169ca38-f772-42df-ad55-ff9d276e6a59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238540366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.238540366
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.6202098
Short name T974
Test name
Test status
Simulation time 23744848 ps
CPU time 0.69 seconds
Started Jun 09 12:27:07 PM PDT 24
Finished Jun 09 12:27:10 PM PDT 24
Peak memory 203996 kb
Host smart-2060069f-ab66-43b1-84b8-8bd5a1438ca7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6202098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.6202098
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3519631189
Short name T1073
Test name
Test status
Simulation time 17241315 ps
CPU time 0.76 seconds
Started Jun 09 12:28:30 PM PDT 24
Finished Jun 09 12:28:32 PM PDT 24
Peak memory 202792 kb
Host smart-a4de7452-22f3-4279-a8e2-e563096e708a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519631189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3519631189
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3371717773
Short name T1050
Test name
Test status
Simulation time 407484671 ps
CPU time 14.55 seconds
Started Jun 09 12:27:09 PM PDT 24
Finished Jun 09 12:27:25 PM PDT 24
Peak memory 215144 kb
Host smart-a69db897-3c46-4c4e-a0e2-7da380c8a7d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371717773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3371717773
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3853863276
Short name T1063
Test name
Test status
Simulation time 3342120327 ps
CPU time 13.17 seconds
Started Jun 09 12:26:56 PM PDT 24
Finished Jun 09 12:27:09 PM PDT 24
Peak memory 206952 kb
Host smart-c53b8488-e2a5-40ea-a77e-8ab2ab3f3e4b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853863276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3853863276
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3580624156
Short name T80
Test name
Test status
Simulation time 50173672 ps
CPU time 1.45 seconds
Started Jun 09 12:27:20 PM PDT 24
Finished Jun 09 12:27:22 PM PDT 24
Peak memory 206956 kb
Host smart-523f7b0a-f0f1-425e-a3b1-ed1c15695592
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580624156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3580624156
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3435865735
Short name T58
Test name
Test status
Simulation time 144161180 ps
CPU time 2.63 seconds
Started Jun 09 12:26:57 PM PDT 24
Finished Jun 09 12:27:00 PM PDT 24
Peak memory 216572 kb
Host smart-28e67484-0b70-48d8-a804-9da2e30823d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435865735 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3435865735
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3299174861
Short name T134
Test name
Test status
Simulation time 119118379 ps
CPU time 1.27 seconds
Started Jun 09 12:26:54 PM PDT 24
Finished Jun 09 12:26:57 PM PDT 24
Peak memory 215168 kb
Host smart-10659aa7-688d-40d6-b304-eed2b609a8d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299174861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
299174861
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1942880762
Short name T1009
Test name
Test status
Simulation time 15943042 ps
CPU time 0.75 seconds
Started Jun 09 12:27:04 PM PDT 24
Finished Jun 09 12:27:07 PM PDT 24
Peak memory 203996 kb
Host smart-33dd744c-9087-4fce-b7d0-c1621fb96fb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942880762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
942880762
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3081162888
Short name T1004
Test name
Test status
Simulation time 46510396 ps
CPU time 1.78 seconds
Started Jun 09 12:27:09 PM PDT 24
Finished Jun 09 12:27:12 PM PDT 24
Peak memory 215220 kb
Host smart-0b78502d-3d6e-4b7c-83ff-c78053b6a22f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081162888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3081162888
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2663907881
Short name T969
Test name
Test status
Simulation time 13617433 ps
CPU time 0.65 seconds
Started Jun 09 12:27:00 PM PDT 24
Finished Jun 09 12:27:01 PM PDT 24
Peak memory 203936 kb
Host smart-06437d48-a21b-4e17-94ff-0bcb94c9451e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663907881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2663907881
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4192099468
Short name T1018
Test name
Test status
Simulation time 562177211 ps
CPU time 3.05 seconds
Started Jun 09 12:27:07 PM PDT 24
Finished Jun 09 12:27:12 PM PDT 24
Peak memory 215220 kb
Host smart-88cbba2c-854d-4fb8-8971-eb4b1f23a8d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192099468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.4192099468
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.80371458
Short name T98
Test name
Test status
Simulation time 1938282998 ps
CPU time 5.03 seconds
Started Jun 09 12:27:17 PM PDT 24
Finished Jun 09 12:27:22 PM PDT 24
Peak memory 215348 kb
Host smart-92558c5c-b00b-4ffe-97ba-9530e74e5c97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80371458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.80371458
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2801754316
Short name T185
Test name
Test status
Simulation time 590831290 ps
CPU time 15.12 seconds
Started Jun 09 12:27:04 PM PDT 24
Finished Jun 09 12:27:21 PM PDT 24
Peak memory 215180 kb
Host smart-cbef5c76-432f-407f-b8ab-ba385d65f236
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801754316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2801754316
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2051470561
Short name T1012
Test name
Test status
Simulation time 14647386 ps
CPU time 0.74 seconds
Started Jun 09 12:27:07 PM PDT 24
Finished Jun 09 12:27:10 PM PDT 24
Peak memory 203652 kb
Host smart-79c2fb88-9b31-4dbd-bcc9-604b74a09c7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051470561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2051470561
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.882590921
Short name T1043
Test name
Test status
Simulation time 36002503 ps
CPU time 0.7 seconds
Started Jun 09 12:27:24 PM PDT 24
Finished Jun 09 12:27:26 PM PDT 24
Peak memory 203696 kb
Host smart-55762b99-857e-4af5-ac07-13894038ac83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882590921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.882590921
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3925075517
Short name T982
Test name
Test status
Simulation time 14962644 ps
CPU time 0.72 seconds
Started Jun 09 12:27:03 PM PDT 24
Finished Jun 09 12:27:05 PM PDT 24
Peak memory 203992 kb
Host smart-638fe0fa-dac6-4f4b-92f2-d7dbdb248676
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925075517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3925075517
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.818629724
Short name T978
Test name
Test status
Simulation time 27063147 ps
CPU time 0.73 seconds
Started Jun 09 12:28:31 PM PDT 24
Finished Jun 09 12:28:33 PM PDT 24
Peak memory 203428 kb
Host smart-436326d8-e7b4-4386-89b0-0b4ff7b0bb44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818629724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.818629724
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2552869618
Short name T975
Test name
Test status
Simulation time 27033732 ps
CPU time 0.72 seconds
Started Jun 09 12:26:59 PM PDT 24
Finished Jun 09 12:27:00 PM PDT 24
Peak memory 203984 kb
Host smart-e46a7e7c-b139-413c-ad07-bbddb6e60d56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552869618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2552869618
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3565009192
Short name T989
Test name
Test status
Simulation time 25356792 ps
CPU time 0.75 seconds
Started Jun 09 12:27:04 PM PDT 24
Finished Jun 09 12:27:05 PM PDT 24
Peak memory 203680 kb
Host smart-f526986f-aa40-4c8e-b2a8-55cb02312f4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565009192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3565009192
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3476184220
Short name T964
Test name
Test status
Simulation time 11942841 ps
CPU time 0.71 seconds
Started Jun 09 12:27:07 PM PDT 24
Finished Jun 09 12:27:13 PM PDT 24
Peak memory 203656 kb
Host smart-9c7d0b2d-91e7-4c2d-aa22-af287f5dc351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476184220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3476184220
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.175961794
Short name T983
Test name
Test status
Simulation time 26484116 ps
CPU time 0.75 seconds
Started Jun 09 12:27:24 PM PDT 24
Finished Jun 09 12:27:25 PM PDT 24
Peak memory 203652 kb
Host smart-6cfb2060-b806-4fda-9fdc-4cde935b4c4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175961794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.175961794
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2127101822
Short name T970
Test name
Test status
Simulation time 25664971 ps
CPU time 0.72 seconds
Started Jun 09 12:28:32 PM PDT 24
Finished Jun 09 12:28:34 PM PDT 24
Peak memory 203648 kb
Host smart-e2590aa8-d0f4-4c94-9a9a-f0b118306af8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127101822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2127101822
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2462749265
Short name T968
Test name
Test status
Simulation time 31785406 ps
CPU time 0.68 seconds
Started Jun 09 12:27:05 PM PDT 24
Finished Jun 09 12:27:07 PM PDT 24
Peak memory 203996 kb
Host smart-ec30d946-d2b9-4852-964d-2038eb61463d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462749265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2462749265
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1425848881
Short name T1020
Test name
Test status
Simulation time 4346449096 ps
CPU time 23.56 seconds
Started Jun 09 12:26:58 PM PDT 24
Finished Jun 09 12:27:22 PM PDT 24
Peak memory 206996 kb
Host smart-8d07506b-f1dc-49da-8089-cc09fe8c9464
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425848881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1425848881
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3253706587
Short name T990
Test name
Test status
Simulation time 1240907064 ps
CPU time 24.17 seconds
Started Jun 09 12:27:03 PM PDT 24
Finished Jun 09 12:27:29 PM PDT 24
Peak memory 206912 kb
Host smart-7062d450-165f-46c8-a831-2f52edc7d11d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253706587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3253706587
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3711112745
Short name T81
Test name
Test status
Simulation time 51928857 ps
CPU time 1.42 seconds
Started Jun 09 12:27:03 PM PDT 24
Finished Jun 09 12:27:05 PM PDT 24
Peak memory 216220 kb
Host smart-6d7cf099-431a-41c2-a337-1733d51b228d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711112745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3711112745
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3977345197
Short name T104
Test name
Test status
Simulation time 380808565 ps
CPU time 3.43 seconds
Started Jun 09 12:27:05 PM PDT 24
Finished Jun 09 12:27:10 PM PDT 24
Peak memory 217992 kb
Host smart-e8dc546a-f28e-4df6-b691-e06b0d9bb8a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977345197 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3977345197
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.740479862
Short name T1011
Test name
Test status
Simulation time 60225817 ps
CPU time 1.96 seconds
Started Jun 09 12:27:38 PM PDT 24
Finished Jun 09 12:27:40 PM PDT 24
Peak memory 206880 kb
Host smart-1c6883e8-17c5-4c79-94a8-1103afff430c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740479862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.740479862
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2153587842
Short name T963
Test name
Test status
Simulation time 15116999 ps
CPU time 0.68 seconds
Started Jun 09 12:27:08 PM PDT 24
Finished Jun 09 12:27:10 PM PDT 24
Peak memory 204020 kb
Host smart-54ebf852-1026-4925-b824-4d3237c79381
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153587842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
153587842
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.629793834
Short name T122
Test name
Test status
Simulation time 29320663 ps
CPU time 1.96 seconds
Started Jun 09 12:27:04 PM PDT 24
Finished Jun 09 12:27:07 PM PDT 24
Peak memory 215248 kb
Host smart-18234ac9-9540-4372-9a89-f3a8c2b6ae99
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629793834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.629793834
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1610355556
Short name T1034
Test name
Test status
Simulation time 11484631 ps
CPU time 0.67 seconds
Started Jun 09 12:27:09 PM PDT 24
Finished Jun 09 12:27:11 PM PDT 24
Peak memory 203940 kb
Host smart-f925e4f7-8dd6-4e1b-9954-f348192df4f6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610355556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1610355556
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2560238371
Short name T1030
Test name
Test status
Simulation time 120116158 ps
CPU time 3.84 seconds
Started Jun 09 12:27:04 PM PDT 24
Finished Jun 09 12:27:10 PM PDT 24
Peak memory 215188 kb
Host smart-a0fa3709-578b-4f60-868e-9a5c6171046e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560238371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2560238371
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1477141365
Short name T1075
Test name
Test status
Simulation time 138626472 ps
CPU time 1.69 seconds
Started Jun 09 12:27:00 PM PDT 24
Finished Jun 09 12:27:02 PM PDT 24
Peak memory 215428 kb
Host smart-fef314bb-fe46-43ff-87be-04debd6ae6a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477141365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
477141365
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1005845352
Short name T180
Test name
Test status
Simulation time 291058680 ps
CPU time 17.65 seconds
Started Jun 09 12:27:05 PM PDT 24
Finished Jun 09 12:27:24 PM PDT 24
Peak memory 215204 kb
Host smart-f3af4ca3-1e22-47ed-9c0e-ed78c32db39f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005845352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1005845352
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3022741093
Short name T972
Test name
Test status
Simulation time 16451607 ps
CPU time 0.73 seconds
Started Jun 09 12:27:38 PM PDT 24
Finished Jun 09 12:27:40 PM PDT 24
Peak memory 204076 kb
Host smart-8595e314-da12-4a95-a37c-18c5a08772a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022741093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3022741093
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2819453121
Short name T965
Test name
Test status
Simulation time 24265332 ps
CPU time 0.71 seconds
Started Jun 09 12:27:03 PM PDT 24
Finished Jun 09 12:27:05 PM PDT 24
Peak memory 203988 kb
Host smart-0a97a2a9-6199-449b-a323-f0c8e70932a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819453121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2819453121
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.266172064
Short name T1071
Test name
Test status
Simulation time 11082175 ps
CPU time 0.76 seconds
Started Jun 09 12:27:12 PM PDT 24
Finished Jun 09 12:27:13 PM PDT 24
Peak memory 203728 kb
Host smart-f2cb6faf-32e8-48da-9d52-b0f8318c66e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266172064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.266172064
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.502480121
Short name T1081
Test name
Test status
Simulation time 35843009 ps
CPU time 0.78 seconds
Started Jun 09 12:27:06 PM PDT 24
Finished Jun 09 12:27:10 PM PDT 24
Peak memory 203684 kb
Host smart-a9785c82-478a-4575-a129-975285db516c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502480121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.502480121
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2702911742
Short name T998
Test name
Test status
Simulation time 46949426 ps
CPU time 0.67 seconds
Started Jun 09 12:28:26 PM PDT 24
Finished Jun 09 12:28:27 PM PDT 24
Peak memory 203592 kb
Host smart-f7dba0cf-4cf7-4ef3-830c-acb159439ddf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702911742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2702911742
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2786198045
Short name T1067
Test name
Test status
Simulation time 21474013 ps
CPU time 0.73 seconds
Started Jun 09 12:27:03 PM PDT 24
Finished Jun 09 12:27:05 PM PDT 24
Peak memory 203996 kb
Host smart-d63364a0-345d-410d-954b-e0b1c562d33a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786198045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2786198045
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1022506402
Short name T1029
Test name
Test status
Simulation time 24088260 ps
CPU time 0.71 seconds
Started Jun 09 12:28:32 PM PDT 24
Finished Jun 09 12:28:34 PM PDT 24
Peak memory 203600 kb
Host smart-0144a321-3b29-46f6-9bfb-164ae63f49d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022506402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1022506402
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2951651445
Short name T971
Test name
Test status
Simulation time 25645697 ps
CPU time 0.77 seconds
Started Jun 09 12:28:07 PM PDT 24
Finished Jun 09 12:28:09 PM PDT 24
Peak memory 203216 kb
Host smart-9c1bf864-0c5c-4daf-8433-60dc192a6591
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951651445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2951651445
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.274788158
Short name T1002
Test name
Test status
Simulation time 11652690 ps
CPU time 0.67 seconds
Started Jun 09 12:28:32 PM PDT 24
Finished Jun 09 12:28:34 PM PDT 24
Peak memory 203948 kb
Host smart-611ebb16-24b4-4d2e-829e-3b2d186f42e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274788158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.274788158
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.531091973
Short name T1068
Test name
Test status
Simulation time 11878817 ps
CPU time 0.72 seconds
Started Jun 09 12:27:06 PM PDT 24
Finished Jun 09 12:27:09 PM PDT 24
Peak memory 204000 kb
Host smart-1d9dfacc-8e01-4d97-9dfd-69f7ee10144c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531091973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.531091973
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1321809506
Short name T60
Test name
Test status
Simulation time 633205943 ps
CPU time 3.49 seconds
Started Jun 09 12:27:10 PM PDT 24
Finished Jun 09 12:27:15 PM PDT 24
Peak memory 217284 kb
Host smart-93dea88c-6ce7-4a8d-9ed9-c1fbb60cdf29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321809506 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1321809506
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3046496401
Short name T1042
Test name
Test status
Simulation time 44535091 ps
CPU time 1.25 seconds
Started Jun 09 12:27:02 PM PDT 24
Finished Jun 09 12:27:04 PM PDT 24
Peak memory 215164 kb
Host smart-691e6fd2-d6a0-4ba0-ac3c-abb2fbd3bd04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046496401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
046496401
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2757944951
Short name T1023
Test name
Test status
Simulation time 18846723 ps
CPU time 0.73 seconds
Started Jun 09 12:27:07 PM PDT 24
Finished Jun 09 12:27:10 PM PDT 24
Peak memory 203700 kb
Host smart-6ee629d6-022f-4ead-b816-731e7b95172c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757944951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
757944951
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.911414438
Short name T1032
Test name
Test status
Simulation time 141379263 ps
CPU time 3.05 seconds
Started Jun 09 12:27:06 PM PDT 24
Finished Jun 09 12:27:11 PM PDT 24
Peak memory 215164 kb
Host smart-11290035-7154-4d8c-b188-218fc79f595f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911414438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.911414438
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2272380182
Short name T101
Test name
Test status
Simulation time 1266238930 ps
CPU time 5.32 seconds
Started Jun 09 12:27:04 PM PDT 24
Finished Jun 09 12:27:12 PM PDT 24
Peak memory 215460 kb
Host smart-4a70e143-a539-4ab3-b0d0-2ca999da06cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272380182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
272380182
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.203657285
Short name T1033
Test name
Test status
Simulation time 930888074 ps
CPU time 19.86 seconds
Started Jun 09 12:27:08 PM PDT 24
Finished Jun 09 12:27:30 PM PDT 24
Peak memory 217928 kb
Host smart-531ed02a-e8e9-4407-a75a-8c3f9c3eea9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203657285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.203657285
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1029404500
Short name T1005
Test name
Test status
Simulation time 2031908081 ps
CPU time 3.72 seconds
Started Jun 09 12:27:30 PM PDT 24
Finished Jun 09 12:27:34 PM PDT 24
Peak memory 217836 kb
Host smart-35c9194d-d197-4634-8b6e-66b75512bd6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029404500 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1029404500
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.357349303
Short name T1006
Test name
Test status
Simulation time 483849395 ps
CPU time 2.29 seconds
Started Jun 09 12:27:02 PM PDT 24
Finished Jun 09 12:27:05 PM PDT 24
Peak memory 215192 kb
Host smart-8d0fb4a9-fec6-48b4-ae01-0f8e5949e0b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357349303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.357349303
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2024515729
Short name T966
Test name
Test status
Simulation time 20231862 ps
CPU time 0.7 seconds
Started Jun 09 12:27:03 PM PDT 24
Finished Jun 09 12:27:05 PM PDT 24
Peak memory 203992 kb
Host smart-143908e0-554b-438d-bf51-aecc7d000164
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024515729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
024515729
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4244767734
Short name T994
Test name
Test status
Simulation time 266682773 ps
CPU time 1.73 seconds
Started Jun 09 12:27:04 PM PDT 24
Finished Jun 09 12:27:07 PM PDT 24
Peak memory 215272 kb
Host smart-97dee6d2-4efe-4ba6-8d23-81ebf6c2de58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244767734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.4244767734
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1104030085
Short name T99
Test name
Test status
Simulation time 64583344 ps
CPU time 3.97 seconds
Started Jun 09 12:27:06 PM PDT 24
Finished Jun 09 12:27:13 PM PDT 24
Peak memory 215368 kb
Host smart-6ca2253e-f264-4883-b797-18f173eb0241
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104030085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
104030085
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3725615830
Short name T183
Test name
Test status
Simulation time 1490743869 ps
CPU time 19.04 seconds
Started Jun 09 12:27:07 PM PDT 24
Finished Jun 09 12:27:29 PM PDT 24
Peak memory 223352 kb
Host smart-9f06545f-55cc-4304-857d-1c6c705e8446
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725615830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3725615830
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.11670472
Short name T995
Test name
Test status
Simulation time 24834255 ps
CPU time 1.54 seconds
Started Jun 09 12:27:06 PM PDT 24
Finished Jun 09 12:27:10 PM PDT 24
Peak memory 215376 kb
Host smart-19e8fbe3-0b09-45ee-8072-e66e60b1166c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11670472 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.11670472
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3433969236
Short name T1001
Test name
Test status
Simulation time 65021482 ps
CPU time 2.01 seconds
Started Jun 09 12:27:01 PM PDT 24
Finished Jun 09 12:27:04 PM PDT 24
Peak memory 215096 kb
Host smart-70b68e5d-eb56-4c96-8e9c-d64215bfb22c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433969236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
433969236
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.913127915
Short name T987
Test name
Test status
Simulation time 49648400 ps
CPU time 0.71 seconds
Started Jun 09 12:26:57 PM PDT 24
Finished Jun 09 12:26:59 PM PDT 24
Peak memory 203700 kb
Host smart-91a7d0e0-2972-477d-97c0-07a540de8295
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913127915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.913127915
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.727493635
Short name T1019
Test name
Test status
Simulation time 60658651 ps
CPU time 1.77 seconds
Started Jun 09 12:27:00 PM PDT 24
Finished Jun 09 12:27:02 PM PDT 24
Peak memory 206988 kb
Host smart-a7caee8f-1d90-44a7-86e6-93778686bae8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727493635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.727493635
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2726473778
Short name T105
Test name
Test status
Simulation time 156630339 ps
CPU time 2.17 seconds
Started Jun 09 12:27:05 PM PDT 24
Finished Jun 09 12:27:09 PM PDT 24
Peak memory 215312 kb
Host smart-0f8bd720-8c86-4fcd-b42f-92c04896e6b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726473778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
726473778
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.751611245
Short name T1054
Test name
Test status
Simulation time 1733831310 ps
CPU time 20.11 seconds
Started Jun 09 12:27:04 PM PDT 24
Finished Jun 09 12:27:25 PM PDT 24
Peak memory 216440 kb
Host smart-9af0f6a1-9f26-451d-b793-404186c3c0b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751611245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.751611245
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1430600229
Short name T981
Test name
Test status
Simulation time 53815462 ps
CPU time 1.7 seconds
Started Jun 09 12:27:29 PM PDT 24
Finished Jun 09 12:27:31 PM PDT 24
Peak memory 215268 kb
Host smart-388db1f6-db53-4921-9ada-b5c1429082ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430600229 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1430600229
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.342976989
Short name T1041
Test name
Test status
Simulation time 181889953 ps
CPU time 1.31 seconds
Started Jun 09 12:27:06 PM PDT 24
Finished Jun 09 12:27:10 PM PDT 24
Peak memory 215156 kb
Host smart-94be4328-a835-4a70-9ef1-c717a9df2fb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342976989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.342976989
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1702328166
Short name T976
Test name
Test status
Simulation time 17325124 ps
CPU time 0.71 seconds
Started Jun 09 12:27:05 PM PDT 24
Finished Jun 09 12:27:08 PM PDT 24
Peak memory 203976 kb
Host smart-cce317b6-953e-4d93-aac2-15fb3506792a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702328166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
702328166
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3154794671
Short name T1022
Test name
Test status
Simulation time 58840823 ps
CPU time 1.73 seconds
Started Jun 09 12:27:05 PM PDT 24
Finished Jun 09 12:27:08 PM PDT 24
Peak memory 215232 kb
Host smart-77e76605-ba51-4f4d-b822-ea2b15d17bc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154794671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3154794671
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1813631282
Short name T184
Test name
Test status
Simulation time 2588532571 ps
CPU time 21.5 seconds
Started Jun 09 12:27:09 PM PDT 24
Finished Jun 09 12:27:32 PM PDT 24
Peak memory 223492 kb
Host smart-d01a84da-74be-4086-896f-6e1fb725fcc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813631282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1813631282
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.466184918
Short name T1072
Test name
Test status
Simulation time 40734485 ps
CPU time 1.32 seconds
Started Jun 09 12:26:53 PM PDT 24
Finished Jun 09 12:26:55 PM PDT 24
Peak memory 215524 kb
Host smart-fc472ab8-f1ce-4d91-b436-f2a460477c72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466184918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.466184918
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.918844010
Short name T1040
Test name
Test status
Simulation time 36167290 ps
CPU time 0.68 seconds
Started Jun 09 12:27:06 PM PDT 24
Finished Jun 09 12:27:09 PM PDT 24
Peak memory 203700 kb
Host smart-e2194ebb-4a6a-4cce-86ed-41a7faed6cf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918844010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.918844010
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3881105911
Short name T992
Test name
Test status
Simulation time 156390693 ps
CPU time 1.71 seconds
Started Jun 09 12:27:05 PM PDT 24
Finished Jun 09 12:27:09 PM PDT 24
Peak memory 206996 kb
Host smart-293ba7be-dfed-427f-bded-9351a803016a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881105911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3881105911
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.162161781
Short name T1057
Test name
Test status
Simulation time 353188215 ps
CPU time 4.36 seconds
Started Jun 09 12:27:37 PM PDT 24
Finished Jun 09 12:27:42 PM PDT 24
Peak memory 215376 kb
Host smart-c7c3415d-cf4e-4429-8f9a-0c4fea81a674
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162161781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.162161781
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.225276082
Short name T1061
Test name
Test status
Simulation time 615732930 ps
CPU time 19.7 seconds
Started Jun 09 12:26:59 PM PDT 24
Finished Jun 09 12:27:19 PM PDT 24
Peak memory 215184 kb
Host smart-e9e99881-d8a2-4a4c-83e7-81d2cee84f62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225276082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.225276082
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1239519036
Short name T717
Test name
Test status
Simulation time 27869319 ps
CPU time 0.75 seconds
Started Jun 09 01:08:40 PM PDT 24
Finished Jun 09 01:08:41 PM PDT 24
Peak memory 206208 kb
Host smart-37cbcb11-0587-48c0-be16-64bcd09a1b41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239519036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
239519036
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1597863967
Short name T290
Test name
Test status
Simulation time 3134341538 ps
CPU time 8.53 seconds
Started Jun 09 01:08:41 PM PDT 24
Finished Jun 09 01:08:50 PM PDT 24
Peak memory 233604 kb
Host smart-ef4ff973-1a59-4728-aa36-ba30345d51cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597863967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1597863967
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1035198420
Short name T793
Test name
Test status
Simulation time 35467799 ps
CPU time 0.78 seconds
Started Jun 09 01:08:32 PM PDT 24
Finished Jun 09 01:08:33 PM PDT 24
Peak memory 207396 kb
Host smart-0485f44c-4bf8-48c4-ac27-b351fe261470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035198420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1035198420
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.383656714
Short name T733
Test name
Test status
Simulation time 14366287405 ps
CPU time 49.08 seconds
Started Jun 09 01:08:36 PM PDT 24
Finished Jun 09 01:09:26 PM PDT 24
Peak memory 251580 kb
Host smart-ad78ca07-75dc-4783-8198-cdc986610aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383656714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.383656714
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1423322985
Short name T471
Test name
Test status
Simulation time 258341542 ps
CPU time 2.38 seconds
Started Jun 09 01:08:41 PM PDT 24
Finished Jun 09 01:08:44 PM PDT 24
Peak memory 233452 kb
Host smart-8a36146e-a926-4aa0-a208-a6f20f0d5ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423322985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1423322985
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3497345155
Short name T70
Test name
Test status
Simulation time 306545880 ps
CPU time 5.03 seconds
Started Jun 09 01:08:43 PM PDT 24
Finished Jun 09 01:08:48 PM PDT 24
Peak memory 233536 kb
Host smart-8fc7269d-7cc8-4e22-ba28-eb630de861b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497345155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3497345155
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2033837626
Short name T575
Test name
Test status
Simulation time 1230534485 ps
CPU time 4.71 seconds
Started Jun 09 01:08:46 PM PDT 24
Finished Jun 09 01:08:51 PM PDT 24
Peak memory 221136 kb
Host smart-15cbf22d-f77b-4859-bd07-580b9eba13f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033837626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2033837626
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.119768330
Short name T457
Test name
Test status
Simulation time 293237931 ps
CPU time 3.58 seconds
Started Jun 09 01:08:38 PM PDT 24
Finished Jun 09 01:08:42 PM PDT 24
Peak memory 233448 kb
Host smart-73a7db8a-6514-439c-a823-15eb65dda0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119768330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
119768330
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1351415825
Short name T935
Test name
Test status
Simulation time 461278722 ps
CPU time 2.24 seconds
Started Jun 09 01:08:30 PM PDT 24
Finished Jun 09 01:08:33 PM PDT 24
Peak memory 224188 kb
Host smart-b0dfd0cb-7681-4d76-b491-ae30f60c914a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351415825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1351415825
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.972869557
Short name T799
Test name
Test status
Simulation time 223227469 ps
CPU time 3.97 seconds
Started Jun 09 01:08:41 PM PDT 24
Finished Jun 09 01:08:45 PM PDT 24
Peak memory 223804 kb
Host smart-a033572c-3ddb-474c-802d-70f556cd0456
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=972869557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.972869557
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2472932029
Short name T746
Test name
Test status
Simulation time 17681191751 ps
CPU time 24.28 seconds
Started Jun 09 01:08:31 PM PDT 24
Finished Jun 09 01:08:56 PM PDT 24
Peak memory 217280 kb
Host smart-10bb6b49-baea-4939-bbd2-b177f16e5a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472932029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2472932029
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2149580744
Short name T424
Test name
Test status
Simulation time 8981494430 ps
CPU time 4.15 seconds
Started Jun 09 01:08:33 PM PDT 24
Finished Jun 09 01:08:37 PM PDT 24
Peak memory 217224 kb
Host smart-92e91500-6c41-4749-92f6-2d6e0ab3a3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149580744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2149580744
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3794634903
Short name T949
Test name
Test status
Simulation time 1166587638 ps
CPU time 4.99 seconds
Started Jun 09 01:08:33 PM PDT 24
Finished Jun 09 01:08:39 PM PDT 24
Peak memory 217100 kb
Host smart-429e5fba-637e-4ae4-8cf5-9f52aed6d7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794634903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3794634903
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.424183045
Short name T962
Test name
Test status
Simulation time 16741819 ps
CPU time 0.7 seconds
Started Jun 09 01:08:31 PM PDT 24
Finished Jun 09 01:08:32 PM PDT 24
Peak memory 206684 kb
Host smart-e58fb979-8a9e-4f88-81d2-dffedf6c74e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424183045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.424183045
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1647663410
Short name T886
Test name
Test status
Simulation time 269553661 ps
CPU time 2.68 seconds
Started Jun 09 01:08:36 PM PDT 24
Finished Jun 09 01:08:39 PM PDT 24
Peak memory 241692 kb
Host smart-e3633407-db7d-41e3-9092-33cdc5b762db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647663410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1647663410
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1506210251
Short name T559
Test name
Test status
Simulation time 44550873 ps
CPU time 0.73 seconds
Started Jun 09 01:08:55 PM PDT 24
Finished Jun 09 01:08:56 PM PDT 24
Peak memory 206280 kb
Host smart-74d6ee4b-34a3-4598-a64e-93f1a9a2838f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506210251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
506210251
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.363728611
Short name T678
Test name
Test status
Simulation time 161107090 ps
CPU time 4.12 seconds
Started Jun 09 01:08:43 PM PDT 24
Finished Jun 09 01:08:47 PM PDT 24
Peak memory 233508 kb
Host smart-08fbcd9a-e808-4ab6-8194-2c2fafeea879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363728611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.363728611
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1963340166
Short name T609
Test name
Test status
Simulation time 19046090 ps
CPU time 0.78 seconds
Started Jun 09 01:08:41 PM PDT 24
Finished Jun 09 01:08:42 PM PDT 24
Peak memory 207412 kb
Host smart-d0c71abb-6b32-4d20-98b2-63c7d0d8a15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963340166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1963340166
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3680587257
Short name T924
Test name
Test status
Simulation time 6325103647 ps
CPU time 87.16 seconds
Started Jun 09 01:08:48 PM PDT 24
Finished Jun 09 01:10:15 PM PDT 24
Peak memory 252644 kb
Host smart-eead9e4d-724e-4aea-97ec-412c83600650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680587257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3680587257
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3058872738
Short name T796
Test name
Test status
Simulation time 36902239267 ps
CPU time 87.21 seconds
Started Jun 09 01:08:47 PM PDT 24
Finished Jun 09 01:10:14 PM PDT 24
Peak memory 250112 kb
Host smart-20102cd1-e4f7-4ed2-9c72-daabb039fd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058872738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3058872738
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.555765121
Short name T765
Test name
Test status
Simulation time 5372371028 ps
CPU time 28.99 seconds
Started Jun 09 01:08:51 PM PDT 24
Finished Jun 09 01:09:20 PM PDT 24
Peak memory 225360 kb
Host smart-37af60e1-c3a3-41b0-b7e6-99918476add9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555765121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
555765121
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2096880370
Short name T835
Test name
Test status
Simulation time 1480430681 ps
CPU time 7.42 seconds
Started Jun 09 01:08:40 PM PDT 24
Finished Jun 09 01:08:48 PM PDT 24
Peak memory 225228 kb
Host smart-566502a0-000e-40b7-b001-92b3cca846db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096880370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2096880370
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1137914972
Short name T919
Test name
Test status
Simulation time 804169855 ps
CPU time 9.83 seconds
Started Jun 09 01:08:42 PM PDT 24
Finished Jun 09 01:08:52 PM PDT 24
Peak memory 225360 kb
Host smart-4c8b52b8-81dd-4627-b156-8a3c6ac1047e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137914972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1137914972
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1078905310
Short name T637
Test name
Test status
Simulation time 7478906088 ps
CPU time 19.54 seconds
Started Jun 09 01:08:42 PM PDT 24
Finished Jun 09 01:09:02 PM PDT 24
Peak memory 225404 kb
Host smart-8f402b00-484d-468c-a95f-b02f563d82cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078905310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1078905310
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3632503238
Short name T845
Test name
Test status
Simulation time 1600398727 ps
CPU time 8.28 seconds
Started Jun 09 01:08:45 PM PDT 24
Finished Jun 09 01:08:54 PM PDT 24
Peak memory 225292 kb
Host smart-842d5357-0aef-45bc-b790-0e0b9171dcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632503238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3632503238
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1649988441
Short name T792
Test name
Test status
Simulation time 4084946626 ps
CPU time 7.98 seconds
Started Jun 09 01:08:47 PM PDT 24
Finished Jun 09 01:08:55 PM PDT 24
Peak memory 219748 kb
Host smart-2a955ce3-6e3d-4f1d-81b4-4d412fd99ef0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1649988441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1649988441
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1653451980
Short name T66
Test name
Test status
Simulation time 123243959 ps
CPU time 1.19 seconds
Started Jun 09 01:08:54 PM PDT 24
Finished Jun 09 01:08:56 PM PDT 24
Peak memory 236364 kb
Host smart-eaaa88b2-b203-458c-967f-8691af91e993
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653451980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1653451980
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3350100790
Short name T663
Test name
Test status
Simulation time 2317970447 ps
CPU time 23.29 seconds
Started Jun 09 01:08:41 PM PDT 24
Finished Jun 09 01:09:04 PM PDT 24
Peak memory 219304 kb
Host smart-f6a5479e-99dd-4254-9a03-3dd97c7b45be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350100790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3350100790
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.4282888439
Short name T586
Test name
Test status
Simulation time 1067738194 ps
CPU time 7.2 seconds
Started Jun 09 01:08:45 PM PDT 24
Finished Jun 09 01:08:53 PM PDT 24
Peak memory 217100 kb
Host smart-90057edc-6b18-4082-8e1d-f0d159fcd893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282888439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.4282888439
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1871266024
Short name T469
Test name
Test status
Simulation time 251654592 ps
CPU time 1.67 seconds
Started Jun 09 01:08:45 PM PDT 24
Finished Jun 09 01:08:47 PM PDT 24
Peak memory 217116 kb
Host smart-ce647c62-0963-41c5-9a36-8fcc8fc9fdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871266024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1871266024
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2645588295
Short name T391
Test name
Test status
Simulation time 95754033 ps
CPU time 0.88 seconds
Started Jun 09 01:08:41 PM PDT 24
Finished Jun 09 01:08:43 PM PDT 24
Peak memory 206696 kb
Host smart-d1937cf7-2743-4f5b-a90a-a4edbe46fa81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645588295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2645588295
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.269226866
Short name T908
Test name
Test status
Simulation time 6570440536 ps
CPU time 21.48 seconds
Started Jun 09 01:08:50 PM PDT 24
Finished Jun 09 01:09:12 PM PDT 24
Peak memory 249692 kb
Host smart-6bb7456d-4216-4c4c-9ca2-b08f48c84115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269226866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.269226866
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1757398821
Short name T738
Test name
Test status
Simulation time 40757917 ps
CPU time 0.69 seconds
Started Jun 09 01:09:51 PM PDT 24
Finished Jun 09 01:09:52 PM PDT 24
Peak memory 205680 kb
Host smart-cb868b60-dfc0-41a9-a193-a1e7679e6d27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757398821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1757398821
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2409067370
Short name T959
Test name
Test status
Simulation time 83671761 ps
CPU time 0.8 seconds
Started Jun 09 01:09:49 PM PDT 24
Finished Jun 09 01:09:51 PM PDT 24
Peak memory 207424 kb
Host smart-0927d390-99d8-40bf-8a66-ba7e566a6fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409067370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2409067370
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.897167298
Short name T684
Test name
Test status
Simulation time 29036323786 ps
CPU time 229.6 seconds
Started Jun 09 01:09:49 PM PDT 24
Finished Jun 09 01:13:39 PM PDT 24
Peak memory 250292 kb
Host smart-dcabcc6c-cb24-4034-9a2f-c9919e9dab40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897167298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.897167298
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1634438691
Short name T306
Test name
Test status
Simulation time 67796747823 ps
CPU time 342.97 seconds
Started Jun 09 01:09:52 PM PDT 24
Finished Jun 09 01:15:36 PM PDT 24
Peak memory 254668 kb
Host smart-86ffc3fd-d488-4641-bbb8-4d4f88641834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634438691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1634438691
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3095370985
Short name T623
Test name
Test status
Simulation time 941193589 ps
CPU time 3.65 seconds
Started Jun 09 01:09:51 PM PDT 24
Finished Jun 09 01:09:55 PM PDT 24
Peak memory 225348 kb
Host smart-7ca8b399-cc07-45f6-9f33-85cebb228fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095370985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3095370985
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2442971874
Short name T811
Test name
Test status
Simulation time 1728891817 ps
CPU time 16.75 seconds
Started Jun 09 01:09:53 PM PDT 24
Finished Jun 09 01:10:10 PM PDT 24
Peak memory 233552 kb
Host smart-bfcad82c-cbc2-48cf-ba0a-ab07c2d0d9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442971874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2442971874
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.438069883
Short name T449
Test name
Test status
Simulation time 1673675145 ps
CPU time 9.06 seconds
Started Jun 09 01:09:50 PM PDT 24
Finished Jun 09 01:09:59 PM PDT 24
Peak memory 225256 kb
Host smart-ae13bb5c-b779-47b9-a78a-f6cfb636eae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438069883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.438069883
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2363932508
Short name T428
Test name
Test status
Simulation time 290681929 ps
CPU time 4.86 seconds
Started Jun 09 01:09:49 PM PDT 24
Finished Jun 09 01:09:54 PM PDT 24
Peak memory 233556 kb
Host smart-a516fbe5-dba5-407c-ac1c-a9a7d8a9796d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363932508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2363932508
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1048767006
Short name T217
Test name
Test status
Simulation time 8663837721 ps
CPU time 18.39 seconds
Started Jun 09 01:09:46 PM PDT 24
Finished Jun 09 01:10:05 PM PDT 24
Peak memory 229076 kb
Host smart-b4111875-f161-4c78-a271-e152e19ca142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048767006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1048767006
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2430769596
Short name T945
Test name
Test status
Simulation time 2354621672 ps
CPU time 13.76 seconds
Started Jun 09 01:09:51 PM PDT 24
Finished Jun 09 01:10:05 PM PDT 24
Peak memory 224268 kb
Host smart-510c6bed-2526-4f1b-a2fd-15859800be90
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2430769596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2430769596
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3021924468
Short name T155
Test name
Test status
Simulation time 114974610 ps
CPU time 1.02 seconds
Started Jun 09 01:09:52 PM PDT 24
Finished Jun 09 01:09:54 PM PDT 24
Peak memory 208460 kb
Host smart-d3a03040-4c51-4a13-a4a3-bde827748dc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021924468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3021924468
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1041377543
Short name T539
Test name
Test status
Simulation time 425266843 ps
CPU time 2.45 seconds
Started Jun 09 01:09:47 PM PDT 24
Finished Jun 09 01:09:49 PM PDT 24
Peak memory 217168 kb
Host smart-648e362f-68b0-411c-9b22-144fb5820bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041377543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1041377543
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.4248370736
Short name T375
Test name
Test status
Simulation time 13898930164 ps
CPU time 12.97 seconds
Started Jun 09 01:09:46 PM PDT 24
Finished Jun 09 01:09:59 PM PDT 24
Peak memory 217264 kb
Host smart-6d61bdee-5b06-4d23-b4ca-e378619827bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248370736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.4248370736
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.935444346
Short name T768
Test name
Test status
Simulation time 125754561 ps
CPU time 2.2 seconds
Started Jun 09 01:09:47 PM PDT 24
Finished Jun 09 01:09:50 PM PDT 24
Peak memory 217080 kb
Host smart-3c3e8a8c-0eea-4a47-aeaa-e80675d394a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935444346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.935444346
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.4273683238
Short name T807
Test name
Test status
Simulation time 34304501 ps
CPU time 0.87 seconds
Started Jun 09 01:09:45 PM PDT 24
Finished Jun 09 01:09:46 PM PDT 24
Peak memory 206676 kb
Host smart-59fefe69-1d64-4004-8bf4-1ffa4e523114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273683238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.4273683238
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2447708647
Short name T230
Test name
Test status
Simulation time 9011040380 ps
CPU time 7 seconds
Started Jun 09 01:09:52 PM PDT 24
Finished Jun 09 01:10:00 PM PDT 24
Peak memory 225460 kb
Host smart-6db88750-ef76-4469-8f50-d412e4901a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447708647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2447708647
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1283494741
Short name T433
Test name
Test status
Simulation time 33256307 ps
CPU time 0.8 seconds
Started Jun 09 01:09:57 PM PDT 24
Finished Jun 09 01:09:58 PM PDT 24
Peak memory 205684 kb
Host smart-fc6477ae-70e7-4b14-a202-50a9f6053619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283494741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1283494741
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.798248423
Short name T606
Test name
Test status
Simulation time 159907149 ps
CPU time 4.07 seconds
Started Jun 09 01:09:57 PM PDT 24
Finished Jun 09 01:10:01 PM PDT 24
Peak memory 233564 kb
Host smart-3f59a29a-b5c5-4fb6-99bd-5f15b7290272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798248423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.798248423
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2457697265
Short name T531
Test name
Test status
Simulation time 134070056 ps
CPU time 0.85 seconds
Started Jun 09 01:09:52 PM PDT 24
Finished Jun 09 01:09:54 PM PDT 24
Peak memory 207696 kb
Host smart-c6e1f678-b0e4-4a0e-ac98-5540fa3664f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457697265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2457697265
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.4294138777
Short name T17
Test name
Test status
Simulation time 7041042430 ps
CPU time 45.59 seconds
Started Jun 09 01:09:57 PM PDT 24
Finished Jun 09 01:10:43 PM PDT 24
Peak memory 236184 kb
Host smart-2b4c0fd1-7fe8-44b4-8e0f-b307e8b8e8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294138777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.4294138777
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2194160366
Short name T68
Test name
Test status
Simulation time 2409807316 ps
CPU time 8.23 seconds
Started Jun 09 01:09:55 PM PDT 24
Finished Jun 09 01:10:04 PM PDT 24
Peak memory 225464 kb
Host smart-70f70d3a-b56d-48d5-949a-04ae0ec2fb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194160366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2194160366
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2913932906
Short name T419
Test name
Test status
Simulation time 3932773995 ps
CPU time 10.27 seconds
Started Jun 09 01:10:00 PM PDT 24
Finished Jun 09 01:10:11 PM PDT 24
Peak memory 225492 kb
Host smart-d6a5eb07-4838-46cb-9dc5-fa6784561e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913932906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2913932906
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3949870354
Short name T218
Test name
Test status
Simulation time 5142452605 ps
CPU time 18.61 seconds
Started Jun 09 01:09:56 PM PDT 24
Finished Jun 09 01:10:15 PM PDT 24
Peak memory 225448 kb
Host smart-4e0667e7-a2f3-4301-9598-de1f48b14787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949870354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3949870354
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.4118094006
Short name T479
Test name
Test status
Simulation time 1066917387 ps
CPU time 5.28 seconds
Started Jun 09 01:09:57 PM PDT 24
Finished Jun 09 01:10:02 PM PDT 24
Peak memory 225284 kb
Host smart-de4f6409-a031-4406-aa39-d4fde6d49af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118094006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.4118094006
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1081863756
Short name T251
Test name
Test status
Simulation time 3303979342 ps
CPU time 10.87 seconds
Started Jun 09 01:09:59 PM PDT 24
Finished Jun 09 01:10:10 PM PDT 24
Peak memory 225472 kb
Host smart-8a44c6fe-f8b3-4f58-9ab5-83ea1da549d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081863756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1081863756
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1572381213
Short name T67
Test name
Test status
Simulation time 1507600306 ps
CPU time 8.73 seconds
Started Jun 09 01:09:57 PM PDT 24
Finished Jun 09 01:10:06 PM PDT 24
Peak memory 223784 kb
Host smart-682e78f0-73c6-4bad-bc4b-91f8b552a268
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1572381213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1572381213
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.395110731
Short name T572
Test name
Test status
Simulation time 1302763728 ps
CPU time 12.5 seconds
Started Jun 09 01:09:49 PM PDT 24
Finished Jun 09 01:10:02 PM PDT 24
Peak memory 220056 kb
Host smart-7d748512-c23d-4526-a96b-9bad7a9a9702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395110731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.395110731
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.339069064
Short name T429
Test name
Test status
Simulation time 4709106695 ps
CPU time 7.61 seconds
Started Jun 09 01:09:52 PM PDT 24
Finished Jun 09 01:10:00 PM PDT 24
Peak memory 217260 kb
Host smart-d4f99c77-f518-4775-b9d0-5a6c083b68a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339069064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.339069064
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1139228815
Short name T382
Test name
Test status
Simulation time 11114958 ps
CPU time 0.7 seconds
Started Jun 09 01:09:56 PM PDT 24
Finished Jun 09 01:09:57 PM PDT 24
Peak memory 206364 kb
Host smart-7dab649d-82d7-4aaf-aae3-4c7a4f254dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139228815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1139228815
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1725045033
Short name T377
Test name
Test status
Simulation time 158073948 ps
CPU time 0.81 seconds
Started Jun 09 01:09:51 PM PDT 24
Finished Jun 09 01:09:52 PM PDT 24
Peak memory 206704 kb
Host smart-29a75996-ac1c-44a1-87a6-9fe672359a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725045033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1725045033
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1584940622
Short name T5
Test name
Test status
Simulation time 449711178 ps
CPU time 8.26 seconds
Started Jun 09 01:09:58 PM PDT 24
Finished Jun 09 01:10:06 PM PDT 24
Peak memory 249864 kb
Host smart-f023d7c4-29c7-43ce-a69f-a80bed8416e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584940622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1584940622
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2410730928
Short name T395
Test name
Test status
Simulation time 31006266 ps
CPU time 0.7 seconds
Started Jun 09 01:10:04 PM PDT 24
Finished Jun 09 01:10:05 PM PDT 24
Peak memory 206240 kb
Host smart-6639e716-db6b-4cfd-b231-5cd7965edc7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410730928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2410730928
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1642464967
Short name T27
Test name
Test status
Simulation time 115228027 ps
CPU time 2.32 seconds
Started Jun 09 01:10:05 PM PDT 24
Finished Jun 09 01:10:08 PM PDT 24
Peak memory 233560 kb
Host smart-207d5291-cb54-418f-89e9-7f0d73b96269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642464967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1642464967
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2897465249
Short name T351
Test name
Test status
Simulation time 219937655 ps
CPU time 0.8 seconds
Started Jun 09 01:09:56 PM PDT 24
Finished Jun 09 01:09:58 PM PDT 24
Peak memory 207412 kb
Host smart-d45ee701-634c-4b95-9439-f1ffafc8a642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897465249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2897465249
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1736021818
Short name T760
Test name
Test status
Simulation time 2344535026 ps
CPU time 23.63 seconds
Started Jun 09 01:10:03 PM PDT 24
Finished Jun 09 01:10:27 PM PDT 24
Peak memory 239356 kb
Host smart-23fccb90-2619-4b81-b585-a6d29f5cf14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736021818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1736021818
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.238040944
Short name T573
Test name
Test status
Simulation time 146037995 ps
CPU time 5.83 seconds
Started Jun 09 01:10:04 PM PDT 24
Finished Jun 09 01:10:10 PM PDT 24
Peak memory 233540 kb
Host smart-3e96c98e-a0ec-42c1-8bc3-d53fae1d3da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238040944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.238040944
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.871858588
Short name T204
Test name
Test status
Simulation time 199280485 ps
CPU time 2.77 seconds
Started Jun 09 01:10:04 PM PDT 24
Finished Jun 09 01:10:07 PM PDT 24
Peak memory 228992 kb
Host smart-2c0c8553-3e3d-474a-b375-de8f8bb9a2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871858588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.871858588
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2350488373
Short name T205
Test name
Test status
Simulation time 46272387330 ps
CPU time 65.29 seconds
Started Jun 09 01:10:06 PM PDT 24
Finished Jun 09 01:11:12 PM PDT 24
Peak memory 241864 kb
Host smart-782cc651-72ed-47b0-a2ce-606d3ba08c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350488373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2350488373
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3752847209
Short name T284
Test name
Test status
Simulation time 1794147931 ps
CPU time 6.84 seconds
Started Jun 09 01:10:04 PM PDT 24
Finished Jun 09 01:10:11 PM PDT 24
Peak memory 241656 kb
Host smart-aa086514-b197-4c9e-8bfc-bddd864737d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752847209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3752847209
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3301198541
Short name T648
Test name
Test status
Simulation time 14838050502 ps
CPU time 10.41 seconds
Started Jun 09 01:10:03 PM PDT 24
Finished Jun 09 01:10:14 PM PDT 24
Peak memory 241268 kb
Host smart-87c137d7-0e99-4a5e-aeb9-a8a654be286c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301198541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3301198541
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.53707087
Short name T594
Test name
Test status
Simulation time 1816992395 ps
CPU time 12.89 seconds
Started Jun 09 01:10:02 PM PDT 24
Finished Jun 09 01:10:15 PM PDT 24
Peak memory 221208 kb
Host smart-bd7697e8-ef27-4ea2-8bd2-740c32a1b3de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=53707087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direc
t.53707087
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1934863593
Short name T421
Test name
Test status
Simulation time 41102611 ps
CPU time 1.09 seconds
Started Jun 09 01:10:02 PM PDT 24
Finished Jun 09 01:10:03 PM PDT 24
Peak memory 207724 kb
Host smart-0f3de922-8a18-43a6-b747-3a1327ee35dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934863593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1934863593
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.4049192713
Short name T372
Test name
Test status
Simulation time 388282000 ps
CPU time 5.47 seconds
Started Jun 09 01:10:09 PM PDT 24
Finished Jun 09 01:10:15 PM PDT 24
Peak memory 217116 kb
Host smart-e0ff0b93-9579-4543-bc6b-e534a6294357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049192713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.4049192713
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.976959926
Short name T384
Test name
Test status
Simulation time 723940995 ps
CPU time 2.22 seconds
Started Jun 09 01:09:56 PM PDT 24
Finished Jun 09 01:09:59 PM PDT 24
Peak memory 217084 kb
Host smart-e163ec1a-a84d-44b5-9ab6-bb53c70c431e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976959926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.976959926
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2816639189
Short name T617
Test name
Test status
Simulation time 49937855 ps
CPU time 1.21 seconds
Started Jun 09 01:10:03 PM PDT 24
Finished Jun 09 01:10:04 PM PDT 24
Peak memory 208720 kb
Host smart-11fb2f13-62c4-4846-84eb-b88ba2db37dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816639189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2816639189
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1113996881
Short name T477
Test name
Test status
Simulation time 62493753 ps
CPU time 0.79 seconds
Started Jun 09 01:10:06 PM PDT 24
Finished Jun 09 01:10:07 PM PDT 24
Peak memory 206676 kb
Host smart-964c4674-0aa3-4ba5-ac56-62ba12bed0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113996881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1113996881
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.341369517
Short name T293
Test name
Test status
Simulation time 1982543072 ps
CPU time 7.9 seconds
Started Jun 09 01:10:03 PM PDT 24
Finished Jun 09 01:10:11 PM PDT 24
Peak memory 233552 kb
Host smart-2ebb1ce8-2545-41f6-96be-a50be14516df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341369517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.341369517
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3349487546
Short name T782
Test name
Test status
Simulation time 19766271 ps
CPU time 0.71 seconds
Started Jun 09 01:10:10 PM PDT 24
Finished Jun 09 01:10:11 PM PDT 24
Peak memory 206252 kb
Host smart-24d8d877-c58c-4988-963f-9edbc9081958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349487546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3349487546
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.855428107
Short name T502
Test name
Test status
Simulation time 432742003 ps
CPU time 3.52 seconds
Started Jun 09 01:10:09 PM PDT 24
Finished Jun 09 01:10:13 PM PDT 24
Peak memory 233500 kb
Host smart-47c1063f-0d34-4398-a36f-3e10334e2378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855428107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.855428107
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3684051385
Short name T482
Test name
Test status
Simulation time 55992954 ps
CPU time 0.77 seconds
Started Jun 09 01:10:08 PM PDT 24
Finished Jun 09 01:10:09 PM PDT 24
Peak memory 206668 kb
Host smart-3841b89b-79e9-4265-bec0-f4db4949aa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684051385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3684051385
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.193032836
Short name T167
Test name
Test status
Simulation time 43186258284 ps
CPU time 62.27 seconds
Started Jun 09 01:10:12 PM PDT 24
Finished Jun 09 01:11:15 PM PDT 24
Peak memory 251164 kb
Host smart-2b374c96-729d-4cc5-bb39-65e82012cfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193032836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.193032836
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.232945893
Short name T228
Test name
Test status
Simulation time 9528516229 ps
CPU time 55.31 seconds
Started Jun 09 01:10:07 PM PDT 24
Finished Jun 09 01:11:03 PM PDT 24
Peak memory 250052 kb
Host smart-27e07a6a-e576-4e3f-ab67-e7b92f14f5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232945893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.232945893
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2438471307
Short name T630
Test name
Test status
Simulation time 12385060648 ps
CPU time 80.69 seconds
Started Jun 09 01:10:07 PM PDT 24
Finished Jun 09 01:11:28 PM PDT 24
Peak memory 256572 kb
Host smart-3a4b9bdd-820c-4a3b-a06c-4a16ce4288af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438471307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2438471307
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.660267379
Short name T69
Test name
Test status
Simulation time 316300125 ps
CPU time 4.74 seconds
Started Jun 09 01:10:09 PM PDT 24
Finished Jun 09 01:10:15 PM PDT 24
Peak memory 237696 kb
Host smart-ea6904b5-8f8b-4552-8a14-d7b40b3c1893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660267379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.660267379
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3871006298
Short name T291
Test name
Test status
Simulation time 3877765266 ps
CPU time 10.5 seconds
Started Jun 09 01:10:09 PM PDT 24
Finished Jun 09 01:10:20 PM PDT 24
Peak memory 233664 kb
Host smart-ff0205ca-36e4-4829-8756-8fd65f803315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871006298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3871006298
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1944038728
Short name T509
Test name
Test status
Simulation time 487984984 ps
CPU time 7.24 seconds
Started Jun 09 01:10:10 PM PDT 24
Finished Jun 09 01:10:18 PM PDT 24
Peak memory 233500 kb
Host smart-27978127-3140-44b6-8485-64bf1bd5d16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944038728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1944038728
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3413450799
Short name T72
Test name
Test status
Simulation time 420213084 ps
CPU time 5.46 seconds
Started Jun 09 01:10:10 PM PDT 24
Finished Jun 09 01:10:16 PM PDT 24
Peak memory 229772 kb
Host smart-217b1c87-6542-4a5f-b040-821109e1081b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413450799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3413450799
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1795525493
Short name T214
Test name
Test status
Simulation time 3173019198 ps
CPU time 6.25 seconds
Started Jun 09 01:10:08 PM PDT 24
Finished Jun 09 01:10:15 PM PDT 24
Peak memory 241492 kb
Host smart-f7a328bd-89de-4211-908b-b81d3f0cccdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795525493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1795525493
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1093927471
Short name T466
Test name
Test status
Simulation time 625602232 ps
CPU time 5.66 seconds
Started Jun 09 01:10:09 PM PDT 24
Finished Jun 09 01:10:14 PM PDT 24
Peak memory 221308 kb
Host smart-941aaaa3-8af1-43b0-81a4-654c536d1aa0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1093927471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1093927471
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2877053967
Short name T3
Test name
Test status
Simulation time 9362419312 ps
CPU time 14.07 seconds
Started Jun 09 01:10:09 PM PDT 24
Finished Jun 09 01:10:23 PM PDT 24
Peak memory 217208 kb
Host smart-accdc5c3-8119-42ad-9950-0758f98f725d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877053967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2877053967
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3161567214
Short name T824
Test name
Test status
Simulation time 6360528481 ps
CPU time 20.01 seconds
Started Jun 09 01:10:12 PM PDT 24
Finished Jun 09 01:10:32 PM PDT 24
Peak memory 217296 kb
Host smart-6fe77b48-16df-4fa6-afa4-0bbf15fc6ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161567214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3161567214
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3777016799
Short name T16
Test name
Test status
Simulation time 84800442 ps
CPU time 1.61 seconds
Started Jun 09 01:10:08 PM PDT 24
Finished Jun 09 01:10:10 PM PDT 24
Peak memory 217148 kb
Host smart-bf762125-4a85-4d32-9900-6dcfcce3cda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777016799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3777016799
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.759748350
Short name T603
Test name
Test status
Simulation time 147677265 ps
CPU time 0.95 seconds
Started Jun 09 01:10:10 PM PDT 24
Finished Jun 09 01:10:12 PM PDT 24
Peak memory 206688 kb
Host smart-7a4d9244-a039-48fd-9408-f497b6f39cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759748350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.759748350
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1708833193
Short name T527
Test name
Test status
Simulation time 2115275682 ps
CPU time 4.66 seconds
Started Jun 09 01:10:11 PM PDT 24
Finished Jun 09 01:10:16 PM PDT 24
Peak memory 225348 kb
Host smart-3cd0c7fb-80e4-4b29-89d5-8e93b44f1407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708833193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1708833193
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.847847134
Short name T898
Test name
Test status
Simulation time 60560210 ps
CPU time 0.7 seconds
Started Jun 09 01:10:16 PM PDT 24
Finished Jun 09 01:10:17 PM PDT 24
Peak memory 206276 kb
Host smart-4e2c87d3-c708-4aaa-b90e-e1bfdb227b0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847847134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.847847134
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3479478901
Short name T476
Test name
Test status
Simulation time 50836325 ps
CPU time 2.55 seconds
Started Jun 09 01:10:15 PM PDT 24
Finished Jun 09 01:10:18 PM PDT 24
Peak memory 233532 kb
Host smart-17ace390-5406-4778-bd31-0ede149d05c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479478901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3479478901
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.45257241
Short name T163
Test name
Test status
Simulation time 20202808 ps
CPU time 0.77 seconds
Started Jun 09 01:10:13 PM PDT 24
Finished Jun 09 01:10:15 PM PDT 24
Peak memory 207396 kb
Host smart-34002865-e93e-4b94-8979-204b39bfbf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45257241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.45257241
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1981953025
Short name T237
Test name
Test status
Simulation time 78188550742 ps
CPU time 274.71 seconds
Started Jun 09 01:10:16 PM PDT 24
Finished Jun 09 01:14:51 PM PDT 24
Peak memory 254228 kb
Host smart-608111fa-1c77-477a-9b70-d27933be24c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981953025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1981953025
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.162245793
Short name T956
Test name
Test status
Simulation time 28665778505 ps
CPU time 76.91 seconds
Started Jun 09 01:10:14 PM PDT 24
Finished Jun 09 01:11:32 PM PDT 24
Peak memory 251588 kb
Host smart-a61255b5-2112-4e2f-833f-98683707a642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162245793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.162245793
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.205091673
Short name T784
Test name
Test status
Simulation time 5821912724 ps
CPU time 43.12 seconds
Started Jun 09 01:10:14 PM PDT 24
Finished Jun 09 01:10:57 PM PDT 24
Peak memory 252148 kb
Host smart-e71badb8-740e-4d6a-97bf-c5b4bba06362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205091673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.205091673
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1297996540
Short name T636
Test name
Test status
Simulation time 880187848 ps
CPU time 4.78 seconds
Started Jun 09 01:10:13 PM PDT 24
Finished Jun 09 01:10:19 PM PDT 24
Peak memory 233544 kb
Host smart-0d268879-dbcb-4b4b-9c03-9ee54381c7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297996540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1297996540
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1091666569
Short name T285
Test name
Test status
Simulation time 8074750912 ps
CPU time 43.4 seconds
Started Jun 09 01:10:13 PM PDT 24
Finished Jun 09 01:10:57 PM PDT 24
Peak memory 230088 kb
Host smart-56d15dfa-e96e-4f91-80a4-ec68b8818ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091666569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1091666569
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1141945824
Short name T859
Test name
Test status
Simulation time 245742607 ps
CPU time 2.75 seconds
Started Jun 09 01:10:12 PM PDT 24
Finished Jun 09 01:10:15 PM PDT 24
Peak memory 225300 kb
Host smart-3abd4f62-64d6-4a0c-9728-e36cdf8bc154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141945824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1141945824
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3195704705
Short name T703
Test name
Test status
Simulation time 6607813326 ps
CPU time 22.17 seconds
Started Jun 09 01:10:09 PM PDT 24
Finished Jun 09 01:10:31 PM PDT 24
Peak memory 233664 kb
Host smart-496b7deb-9881-4602-815e-fbd72fe4c3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195704705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3195704705
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1573610006
Short name T416
Test name
Test status
Simulation time 1796426360 ps
CPU time 13.05 seconds
Started Jun 09 01:10:11 PM PDT 24
Finished Jun 09 01:10:24 PM PDT 24
Peak memory 221056 kb
Host smart-7ca527a9-e62b-4e50-9c68-1e9d91ae4df8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1573610006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1573610006
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1841507989
Short name T165
Test name
Test status
Simulation time 3722347164 ps
CPU time 17.6 seconds
Started Jun 09 01:10:17 PM PDT 24
Finished Jun 09 01:10:35 PM PDT 24
Peak memory 251000 kb
Host smart-c8ff2f4e-d6a6-465c-ac72-647af268ecbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841507989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1841507989
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.393926927
Short name T38
Test name
Test status
Simulation time 2756120378 ps
CPU time 26.01 seconds
Started Jun 09 01:10:10 PM PDT 24
Finished Jun 09 01:10:37 PM PDT 24
Peak memory 217376 kb
Host smart-20e68494-4ab8-4b48-b97b-945913d63b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393926927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.393926927
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2130805811
Short name T561
Test name
Test status
Simulation time 2831775118 ps
CPU time 3.95 seconds
Started Jun 09 01:10:09 PM PDT 24
Finished Jun 09 01:10:13 PM PDT 24
Peak memory 217276 kb
Host smart-bad921cf-6a49-473d-b5e1-b64f1d6a102e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130805811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2130805811
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3159738383
Short name T598
Test name
Test status
Simulation time 33166368 ps
CPU time 1.12 seconds
Started Jun 09 01:10:12 PM PDT 24
Finished Jun 09 01:10:13 PM PDT 24
Peak memory 216928 kb
Host smart-8241fea6-415b-4a38-8b12-a8c320b474bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159738383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3159738383
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.472512993
Short name T837
Test name
Test status
Simulation time 91157248 ps
CPU time 0.79 seconds
Started Jun 09 01:10:09 PM PDT 24
Finished Jun 09 01:10:10 PM PDT 24
Peak memory 206624 kb
Host smart-f3fbf537-b7c7-43ff-9be7-043309aa7d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472512993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.472512993
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1830734817
Short name T912
Test name
Test status
Simulation time 157580929 ps
CPU time 2.97 seconds
Started Jun 09 01:10:14 PM PDT 24
Finished Jun 09 01:10:17 PM PDT 24
Peak memory 233536 kb
Host smart-10244374-0e7f-4b62-a765-234add39e0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830734817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1830734817
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.394171875
Short name T461
Test name
Test status
Simulation time 10843630 ps
CPU time 0.69 seconds
Started Jun 09 01:10:22 PM PDT 24
Finished Jun 09 01:10:23 PM PDT 24
Peak memory 205708 kb
Host smart-298e6ab2-3504-4cd3-ab54-ed38371a9bba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394171875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.394171875
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.4144032539
Short name T712
Test name
Test status
Simulation time 120840095 ps
CPU time 4.17 seconds
Started Jun 09 01:10:21 PM PDT 24
Finished Jun 09 01:10:25 PM PDT 24
Peak memory 225236 kb
Host smart-6a8af5d3-9dc2-4254-895e-777807b6592e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144032539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.4144032539
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1775855700
Short name T826
Test name
Test status
Simulation time 14107525 ps
CPU time 0.81 seconds
Started Jun 09 01:10:17 PM PDT 24
Finished Jun 09 01:10:18 PM PDT 24
Peak memory 207396 kb
Host smart-1c712d75-e62d-4650-85f0-1bf27f7110ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775855700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1775855700
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2954698512
Short name T565
Test name
Test status
Simulation time 86187466268 ps
CPU time 156.55 seconds
Started Jun 09 01:10:21 PM PDT 24
Finished Jun 09 01:12:58 PM PDT 24
Peak memory 254728 kb
Host smart-c1fd15d0-ff8a-4d84-8325-8bd24d66bf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954698512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2954698512
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3300290034
Short name T459
Test name
Test status
Simulation time 17196509300 ps
CPU time 84.41 seconds
Started Jun 09 01:10:20 PM PDT 24
Finished Jun 09 01:11:44 PM PDT 24
Peak memory 251140 kb
Host smart-2aba85e1-4273-400b-9a57-8750e73a4e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300290034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3300290034
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.4158768735
Short name T413
Test name
Test status
Simulation time 1432955782 ps
CPU time 23.85 seconds
Started Jun 09 01:10:21 PM PDT 24
Finished Jun 09 01:10:45 PM PDT 24
Peak memory 233548 kb
Host smart-78638a7b-d370-4ce5-908e-78385b32570c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158768735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.4158768735
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1662767984
Short name T529
Test name
Test status
Simulation time 6480938613 ps
CPU time 13.52 seconds
Started Jun 09 01:10:21 PM PDT 24
Finished Jun 09 01:10:35 PM PDT 24
Peak memory 233872 kb
Host smart-6b8ccf47-fa2d-4dc2-89d8-9769584bcf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662767984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1662767984
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2749014228
Short name T266
Test name
Test status
Simulation time 25773510827 ps
CPU time 47.92 seconds
Started Jun 09 01:10:18 PM PDT 24
Finished Jun 09 01:11:06 PM PDT 24
Peak memory 241748 kb
Host smart-ba0fd010-2b45-49ca-ade1-df6ee3fa6e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749014228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2749014228
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3701817028
Short name T250
Test name
Test status
Simulation time 10727757865 ps
CPU time 8.76 seconds
Started Jun 09 01:10:20 PM PDT 24
Finished Jun 09 01:10:29 PM PDT 24
Peak memory 233672 kb
Host smart-c264f2fa-8624-4ee9-95ff-50e8c5335104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701817028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3701817028
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.380362911
Short name T141
Test name
Test status
Simulation time 831127660 ps
CPU time 6.15 seconds
Started Jun 09 01:10:23 PM PDT 24
Finished Jun 09 01:10:29 PM PDT 24
Peak memory 219492 kb
Host smart-604c096d-8bef-42e4-812f-7e60a529b6aa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=380362911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.380362911
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1478629698
Short name T148
Test name
Test status
Simulation time 39710862687 ps
CPU time 359.51 seconds
Started Jun 09 01:10:18 PM PDT 24
Finished Jun 09 01:16:17 PM PDT 24
Peak memory 253608 kb
Host smart-e1640930-c841-45b9-8373-11ba7b40ae3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478629698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1478629698
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.96160505
Short name T755
Test name
Test status
Simulation time 11982945935 ps
CPU time 34.2 seconds
Started Jun 09 01:10:12 PM PDT 24
Finished Jun 09 01:10:47 PM PDT 24
Peak memory 217260 kb
Host smart-025aa305-c355-46ef-9790-986f3a8a7d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96160505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.96160505
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.4018516322
Short name T431
Test name
Test status
Simulation time 1154116993 ps
CPU time 6.87 seconds
Started Jun 09 01:10:13 PM PDT 24
Finished Jun 09 01:10:20 PM PDT 24
Peak memory 217176 kb
Host smart-c9fcb710-d9aa-465c-8cd6-99f11fb61339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018516322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.4018516322
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.273200194
Short name T749
Test name
Test status
Simulation time 197603658 ps
CPU time 2.57 seconds
Started Jun 09 01:10:21 PM PDT 24
Finished Jun 09 01:10:23 PM PDT 24
Peak memory 217184 kb
Host smart-ca99c936-0cc8-450d-add6-c1240ab7b849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273200194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.273200194
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3545427377
Short name T783
Test name
Test status
Simulation time 34144751 ps
CPU time 0.78 seconds
Started Jun 09 01:10:23 PM PDT 24
Finished Jun 09 01:10:24 PM PDT 24
Peak memory 206684 kb
Host smart-b1737e62-4a89-49ee-90aa-9d5601bb61e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545427377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3545427377
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2892097420
Short name T858
Test name
Test status
Simulation time 680837299 ps
CPU time 2.7 seconds
Started Jun 09 01:10:19 PM PDT 24
Finished Jun 09 01:10:22 PM PDT 24
Peak memory 225324 kb
Host smart-53f67367-8003-4e35-b312-265dc53f4b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892097420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2892097420
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1690485758
Short name T941
Test name
Test status
Simulation time 68561964 ps
CPU time 0.71 seconds
Started Jun 09 01:10:24 PM PDT 24
Finished Jun 09 01:10:25 PM PDT 24
Peak memory 206404 kb
Host smart-aeece1e7-cfd7-45f4-a868-3cd733efe0a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690485758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1690485758
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.4280768843
Short name T260
Test name
Test status
Simulation time 507558621 ps
CPU time 2.75 seconds
Started Jun 09 01:10:28 PM PDT 24
Finished Jun 09 01:10:31 PM PDT 24
Peak memory 225344 kb
Host smart-f7e7e14c-3ad6-44dd-9f99-46e8017af3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280768843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4280768843
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2905167463
Short name T865
Test name
Test status
Simulation time 31901483 ps
CPU time 0.77 seconds
Started Jun 09 01:10:21 PM PDT 24
Finished Jun 09 01:10:22 PM PDT 24
Peak memory 207700 kb
Host smart-4d899122-2ade-47a8-9aa3-26cf4df519da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905167463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2905167463
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3941074496
Short name T300
Test name
Test status
Simulation time 39351564983 ps
CPU time 78.74 seconds
Started Jun 09 01:10:29 PM PDT 24
Finished Jun 09 01:11:48 PM PDT 24
Peak memory 251576 kb
Host smart-fa7a0cd1-ea5d-43e6-aa9d-dec0cb49e62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941074496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3941074496
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.4020735144
Short name T22
Test name
Test status
Simulation time 405114608833 ps
CPU time 413.44 seconds
Started Jun 09 01:10:28 PM PDT 24
Finished Jun 09 01:17:22 PM PDT 24
Peak memory 258292 kb
Host smart-4c38c242-b34b-4755-a28b-6d3f98d87c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020735144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.4020735144
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.975386185
Short name T578
Test name
Test status
Simulation time 52111825625 ps
CPU time 120.42 seconds
Started Jun 09 01:10:27 PM PDT 24
Finished Jun 09 01:12:27 PM PDT 24
Peak memory 241344 kb
Host smart-df102524-5789-47fa-a79e-66319832c8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975386185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.975386185
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1889753351
Short name T621
Test name
Test status
Simulation time 1425417310 ps
CPU time 12.1 seconds
Started Jun 09 01:10:26 PM PDT 24
Finished Jun 09 01:10:38 PM PDT 24
Peak memory 225292 kb
Host smart-f8dc0d9f-5685-4348-a358-9aaafe55b953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889753351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1889753351
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.4281599534
Short name T838
Test name
Test status
Simulation time 647686985 ps
CPU time 3.06 seconds
Started Jun 09 01:10:29 PM PDT 24
Finished Jun 09 01:10:32 PM PDT 24
Peak memory 225344 kb
Host smart-927b6820-89b6-46ae-8072-2ff2797d0369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281599534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.4281599534
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1533532318
Short name T467
Test name
Test status
Simulation time 3627347421 ps
CPU time 10.46 seconds
Started Jun 09 01:10:26 PM PDT 24
Finished Jun 09 01:10:37 PM PDT 24
Peak memory 241852 kb
Host smart-48fce83d-48a8-42ed-a0ec-44ca10e3801f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533532318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1533532318
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1731477160
Short name T850
Test name
Test status
Simulation time 666913311 ps
CPU time 6.81 seconds
Started Jun 09 01:10:24 PM PDT 24
Finished Jun 09 01:10:31 PM PDT 24
Peak memory 225308 kb
Host smart-642d1e95-6b82-4ac9-9e1b-46fc274e9f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731477160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1731477160
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3634279696
Short name T692
Test name
Test status
Simulation time 1011501488 ps
CPU time 4.59 seconds
Started Jun 09 01:10:31 PM PDT 24
Finished Jun 09 01:10:36 PM PDT 24
Peak memory 233524 kb
Host smart-0a470229-a274-4fb0-8f8f-2637326ac8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634279696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3634279696
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3190492981
Short name T197
Test name
Test status
Simulation time 24738626440 ps
CPU time 143.02 seconds
Started Jun 09 01:10:28 PM PDT 24
Finished Jun 09 01:12:52 PM PDT 24
Peak memory 255456 kb
Host smart-24ef869f-1f1f-4cd6-9625-0a6bafdb1eb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190492981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3190492981
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1125272375
Short name T653
Test name
Test status
Simulation time 7056698376 ps
CPU time 46 seconds
Started Jun 09 01:10:23 PM PDT 24
Finished Jun 09 01:11:09 PM PDT 24
Peak memory 217268 kb
Host smart-87c90b3e-0669-46bf-935c-9d231d81f5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125272375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1125272375
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2618902164
Short name T751
Test name
Test status
Simulation time 4644157635 ps
CPU time 8.49 seconds
Started Jun 09 01:10:31 PM PDT 24
Finished Jun 09 01:10:40 PM PDT 24
Peak memory 217224 kb
Host smart-d02f0908-27f3-4340-ac2e-55aa297eb0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618902164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2618902164
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3618331650
Short name T673
Test name
Test status
Simulation time 216949266 ps
CPU time 6.57 seconds
Started Jun 09 01:10:29 PM PDT 24
Finished Jun 09 01:10:36 PM PDT 24
Peak memory 217156 kb
Host smart-8cd1669d-bc85-4424-87eb-0dedd51ed36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618331650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3618331650
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1423602314
Short name T355
Test name
Test status
Simulation time 48815050 ps
CPU time 0.85 seconds
Started Jun 09 01:10:27 PM PDT 24
Finished Jun 09 01:10:28 PM PDT 24
Peak memory 206688 kb
Host smart-c35376e9-bd80-4cde-9447-cbc27a120d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423602314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1423602314
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3347143218
Short name T803
Test name
Test status
Simulation time 30668540873 ps
CPU time 20.06 seconds
Started Jun 09 01:10:25 PM PDT 24
Finished Jun 09 01:10:46 PM PDT 24
Peak memory 225468 kb
Host smart-508f5dd7-540c-4cee-affd-76e19dd0a78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347143218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3347143218
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3366942990
Short name T545
Test name
Test status
Simulation time 23797702 ps
CPU time 0.76 seconds
Started Jun 09 01:10:31 PM PDT 24
Finished Jun 09 01:10:32 PM PDT 24
Peak memory 206252 kb
Host smart-585b03df-1061-4465-bd51-63f9f5cfd85b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366942990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3366942990
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.568005343
Short name T536
Test name
Test status
Simulation time 115707096 ps
CPU time 3.8 seconds
Started Jun 09 01:10:34 PM PDT 24
Finished Jun 09 01:10:38 PM PDT 24
Peak memory 233544 kb
Host smart-1b01cc7e-87d8-4a60-8e7a-4b2a4bf53b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568005343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.568005343
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3179208910
Short name T937
Test name
Test status
Simulation time 79198126 ps
CPU time 0.77 seconds
Started Jun 09 01:10:31 PM PDT 24
Finished Jun 09 01:10:33 PM PDT 24
Peak memory 207704 kb
Host smart-614323bb-3a28-4841-8a8b-3dfb1446cefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179208910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3179208910
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2081890529
Short name T752
Test name
Test status
Simulation time 1580907053 ps
CPU time 33.92 seconds
Started Jun 09 01:10:30 PM PDT 24
Finished Jun 09 01:11:04 PM PDT 24
Peak memory 249936 kb
Host smart-a79d7547-ead7-4922-8784-05a3f9e264b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081890529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2081890529
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3523638652
Short name T304
Test name
Test status
Simulation time 41776524386 ps
CPU time 115.43 seconds
Started Jun 09 01:10:31 PM PDT 24
Finished Jun 09 01:12:27 PM PDT 24
Peak memory 250104 kb
Host smart-dff20691-5f5b-433f-8d22-a27b23223f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523638652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3523638652
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1861746275
Short name T558
Test name
Test status
Simulation time 9939870414 ps
CPU time 39.6 seconds
Started Jun 09 01:10:32 PM PDT 24
Finished Jun 09 01:11:12 PM PDT 24
Peak memory 250104 kb
Host smart-b2c193f9-231b-40e3-a7cf-4cd7218fbc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861746275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1861746275
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.536200029
Short name T952
Test name
Test status
Simulation time 249041016 ps
CPU time 6.47 seconds
Started Jun 09 01:10:30 PM PDT 24
Finished Jun 09 01:10:37 PM PDT 24
Peak memory 233556 kb
Host smart-1f79abab-31c5-402a-b9c3-ddddd03a69ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536200029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.536200029
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3770716162
Short name T208
Test name
Test status
Simulation time 762451409 ps
CPU time 4.39 seconds
Started Jun 09 01:10:31 PM PDT 24
Finished Jun 09 01:10:36 PM PDT 24
Peak memory 220432 kb
Host smart-7e771a50-ad06-409f-bb83-8c601e629f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770716162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3770716162
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2308182465
Short name T497
Test name
Test status
Simulation time 1023072980 ps
CPU time 8.29 seconds
Started Jun 09 01:10:32 PM PDT 24
Finished Jun 09 01:10:41 PM PDT 24
Peak memory 237648 kb
Host smart-0fcab68c-ddf2-415d-b53b-afcddcfe8df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308182465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2308182465
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3084714436
Short name T669
Test name
Test status
Simulation time 1331861953 ps
CPU time 7.61 seconds
Started Jun 09 01:10:23 PM PDT 24
Finished Jun 09 01:10:30 PM PDT 24
Peak memory 233704 kb
Host smart-92da56d6-f5d0-4ee4-b8c3-505076b7753a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084714436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3084714436
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2768830674
Short name T12
Test name
Test status
Simulation time 8185109647 ps
CPU time 7.89 seconds
Started Jun 09 01:10:27 PM PDT 24
Finished Jun 09 01:10:35 PM PDT 24
Peak memory 233668 kb
Host smart-911b1265-53b3-429a-ad5e-33ae30e55872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768830674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2768830674
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2625582970
Short name T381
Test name
Test status
Simulation time 2009801323 ps
CPU time 15.31 seconds
Started Jun 09 01:10:31 PM PDT 24
Finished Jun 09 01:10:46 PM PDT 24
Peak memory 221296 kb
Host smart-65bc6629-e946-427a-9345-0a325984e2be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2625582970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2625582970
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1182291975
Short name T453
Test name
Test status
Simulation time 66578492331 ps
CPU time 31.32 seconds
Started Jun 09 01:10:28 PM PDT 24
Finished Jun 09 01:10:59 PM PDT 24
Peak memory 221552 kb
Host smart-724039e2-f75b-4aaf-98b6-d01348426279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182291975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1182291975
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.479463983
Short name T554
Test name
Test status
Simulation time 5539782296 ps
CPU time 16.16 seconds
Started Jun 09 01:10:31 PM PDT 24
Finished Jun 09 01:10:48 PM PDT 24
Peak memory 217272 kb
Host smart-8ed2c3b4-2b38-4e00-9580-ed0667508ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479463983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.479463983
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2860293115
Short name T422
Test name
Test status
Simulation time 399272465 ps
CPU time 2.01 seconds
Started Jun 09 01:10:28 PM PDT 24
Finished Jun 09 01:10:30 PM PDT 24
Peak memory 217096 kb
Host smart-a94efeca-75f2-49c0-9429-046ea06f7b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860293115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2860293115
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3285248018
Short name T871
Test name
Test status
Simulation time 151871512 ps
CPU time 0.85 seconds
Started Jun 09 01:10:24 PM PDT 24
Finished Jun 09 01:10:25 PM PDT 24
Peak memory 206708 kb
Host smart-2fb48c75-a127-41f5-b6a7-fd72a08212c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285248018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3285248018
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2826582179
Short name T602
Test name
Test status
Simulation time 3208505912 ps
CPU time 5.13 seconds
Started Jun 09 01:10:32 PM PDT 24
Finished Jun 09 01:10:37 PM PDT 24
Peak memory 225404 kb
Host smart-50900b17-e3f0-4e0d-a231-fa77ec493cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826582179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2826582179
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1008399514
Short name T753
Test name
Test status
Simulation time 36799101 ps
CPU time 2.79 seconds
Started Jun 09 01:10:38 PM PDT 24
Finished Jun 09 01:10:41 PM PDT 24
Peak memory 233564 kb
Host smart-63b3139b-e545-47ed-87b4-2b127fe96a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008399514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1008399514
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.4061126860
Short name T724
Test name
Test status
Simulation time 18822932 ps
CPU time 0.82 seconds
Started Jun 09 01:10:31 PM PDT 24
Finished Jun 09 01:10:32 PM PDT 24
Peak memory 207380 kb
Host smart-858eb207-8b88-4fe6-a9c4-d73ea06abc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061126860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.4061126860
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1941577226
Short name T550
Test name
Test status
Simulation time 2267107574 ps
CPU time 6.98 seconds
Started Jun 09 01:10:39 PM PDT 24
Finished Jun 09 01:10:46 PM PDT 24
Peak memory 236380 kb
Host smart-f6f48981-03bf-4273-8fb0-6a420e7c03e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941577226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1941577226
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3617056246
Short name T234
Test name
Test status
Simulation time 7640687220 ps
CPU time 49.07 seconds
Started Jun 09 01:10:38 PM PDT 24
Finished Jun 09 01:11:27 PM PDT 24
Peak memory 254572 kb
Host smart-85acc7b5-9ffa-409c-8a89-0683b6959265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617056246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3617056246
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1391149763
Short name T309
Test name
Test status
Simulation time 17449776713 ps
CPU time 103.22 seconds
Started Jun 09 01:10:38 PM PDT 24
Finished Jun 09 01:12:22 PM PDT 24
Peak memory 269700 kb
Host smart-a9de4cad-2320-4d5b-8990-44df7f91c73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391149763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1391149763
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2742463662
Short name T944
Test name
Test status
Simulation time 1373216368 ps
CPU time 28.01 seconds
Started Jun 09 01:10:36 PM PDT 24
Finished Jun 09 01:11:05 PM PDT 24
Peak memory 234560 kb
Host smart-f6ffd44e-829b-442c-89fd-76de24889778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742463662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2742463662
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2543014234
Short name T444
Test name
Test status
Simulation time 14402549421 ps
CPU time 18.05 seconds
Started Jun 09 01:10:37 PM PDT 24
Finished Jun 09 01:10:56 PM PDT 24
Peak memory 225468 kb
Host smart-645936ca-897b-41aa-89c8-3671611f5d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543014234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2543014234
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2560953840
Short name T576
Test name
Test status
Simulation time 6989377406 ps
CPU time 67.13 seconds
Started Jun 09 01:10:36 PM PDT 24
Finished Jun 09 01:11:43 PM PDT 24
Peak memory 233596 kb
Host smart-19b4eb7d-2ef2-4d39-a8f4-e6fb89cdf60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560953840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2560953840
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1909389692
Short name T827
Test name
Test status
Simulation time 421589304 ps
CPU time 4.17 seconds
Started Jun 09 01:10:40 PM PDT 24
Finished Jun 09 01:10:44 PM PDT 24
Peak memory 233504 kb
Host smart-1c5dd7a8-6126-4684-9f8d-59f97d15b241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909389692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1909389692
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1062312654
Short name T463
Test name
Test status
Simulation time 1188742937 ps
CPU time 4.12 seconds
Started Jun 09 01:10:38 PM PDT 24
Finished Jun 09 01:10:43 PM PDT 24
Peak memory 233484 kb
Host smart-08860c97-d212-4ded-8c36-b901eadf41e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062312654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1062312654
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.942791738
Short name T450
Test name
Test status
Simulation time 288294872 ps
CPU time 3.83 seconds
Started Jun 09 01:10:36 PM PDT 24
Finished Jun 09 01:10:40 PM PDT 24
Peak memory 223868 kb
Host smart-a7821116-7151-49ee-9cbf-0c4f22f23c0d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=942791738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.942791738
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1765660380
Short name T890
Test name
Test status
Simulation time 40836943 ps
CPU time 0.99 seconds
Started Jun 09 01:10:39 PM PDT 24
Finished Jun 09 01:10:40 PM PDT 24
Peak memory 207508 kb
Host smart-df982f17-6181-47b6-b748-a1738e2fa0e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765660380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1765660380
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1285468330
Short name T781
Test name
Test status
Simulation time 4645863022 ps
CPU time 9.3 seconds
Started Jun 09 01:10:37 PM PDT 24
Finished Jun 09 01:10:46 PM PDT 24
Peak memory 217232 kb
Host smart-bea7b3bc-a37b-4702-bb30-033bf2b61168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285468330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1285468330
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2925875598
Short name T725
Test name
Test status
Simulation time 4463293329 ps
CPU time 11.69 seconds
Started Jun 09 01:10:37 PM PDT 24
Finished Jun 09 01:10:49 PM PDT 24
Peak memory 217184 kb
Host smart-e087c62d-28e4-44a0-8a1c-fd5b6a586972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925875598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2925875598
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1929995569
Short name T563
Test name
Test status
Simulation time 106520059 ps
CPU time 1.06 seconds
Started Jun 09 01:10:38 PM PDT 24
Finished Jun 09 01:10:39 PM PDT 24
Peak memory 208084 kb
Host smart-b44c1944-2ca9-46f1-9149-f551d218109e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929995569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1929995569
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2934309674
Short name T704
Test name
Test status
Simulation time 237960769 ps
CPU time 0.87 seconds
Started Jun 09 01:10:38 PM PDT 24
Finished Jun 09 01:10:39 PM PDT 24
Peak memory 206696 kb
Host smart-d3ce85ae-997e-444c-ae01-2c686f5946ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934309674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2934309674
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2183648882
Short name T926
Test name
Test status
Simulation time 37206003 ps
CPU time 2.4 seconds
Started Jun 09 01:10:39 PM PDT 24
Finished Jun 09 01:10:42 PM PDT 24
Peak memory 235044 kb
Host smart-d7279802-8b7d-4f8d-ac43-65684fecebed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183648882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2183648882
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1218985524
Short name T393
Test name
Test status
Simulation time 12766807 ps
CPU time 0.75 seconds
Started Jun 09 01:10:42 PM PDT 24
Finished Jun 09 01:10:43 PM PDT 24
Peak memory 206244 kb
Host smart-2c3d5f0c-f045-4d7a-9658-e2c980eb0f27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218985524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1218985524
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1593566440
Short name T836
Test name
Test status
Simulation time 90597811 ps
CPU time 3.13 seconds
Started Jun 09 01:10:43 PM PDT 24
Finished Jun 09 01:10:46 PM PDT 24
Peak memory 225352 kb
Host smart-cec79009-7258-4285-8aa3-117c37c2a23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593566440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1593566440
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3499142668
Short name T869
Test name
Test status
Simulation time 22261290 ps
CPU time 0.81 seconds
Started Jun 09 01:10:36 PM PDT 24
Finished Jun 09 01:10:38 PM PDT 24
Peak memory 207420 kb
Host smart-85c6d687-d9cf-4087-94c6-9bb849a0d491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499142668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3499142668
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2241996
Short name T629
Test name
Test status
Simulation time 153911913664 ps
CPU time 298.2 seconds
Started Jun 09 01:10:45 PM PDT 24
Finished Jun 09 01:15:43 PM PDT 24
Peak memory 254980 kb
Host smart-4bbce747-043d-407d-92c2-1b5b4d6651a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2241996
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3970418737
Short name T659
Test name
Test status
Simulation time 112341444740 ps
CPU time 258.12 seconds
Started Jun 09 01:10:46 PM PDT 24
Finished Jun 09 01:15:04 PM PDT 24
Peak memory 257308 kb
Host smart-605cfead-cc01-4525-8fcd-7231c49b0ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970418737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3970418737
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2986802598
Short name T915
Test name
Test status
Simulation time 205088844 ps
CPU time 3.98 seconds
Started Jun 09 01:10:46 PM PDT 24
Finished Jun 09 01:10:51 PM PDT 24
Peak memory 233548 kb
Host smart-5666dbfe-4350-4c61-8c4b-b72f7f3c3041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986802598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2986802598
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.978805307
Short name T131
Test name
Test status
Simulation time 428405113 ps
CPU time 6.74 seconds
Started Jun 09 01:10:41 PM PDT 24
Finished Jun 09 01:10:48 PM PDT 24
Peak memory 225304 kb
Host smart-bdc15ff1-626a-4034-a9ce-963c9aa1911c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978805307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.978805307
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3571784136
Short name T414
Test name
Test status
Simulation time 72153929487 ps
CPU time 67.9 seconds
Started Jun 09 01:10:46 PM PDT 24
Finished Jun 09 01:11:54 PM PDT 24
Peak memory 233836 kb
Host smart-cccecdad-733f-4481-8ead-44591cca8bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571784136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3571784136
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3407116909
Short name T199
Test name
Test status
Simulation time 6134928089 ps
CPU time 18.23 seconds
Started Jun 09 01:10:45 PM PDT 24
Finished Jun 09 01:11:04 PM PDT 24
Peak memory 233664 kb
Host smart-b35b5939-d54a-4f16-b63f-6cccd17d067f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407116909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3407116909
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2848283955
Short name T436
Test name
Test status
Simulation time 11299655823 ps
CPU time 23.18 seconds
Started Jun 09 01:10:43 PM PDT 24
Finished Jun 09 01:11:07 PM PDT 24
Peak memory 237868 kb
Host smart-e7f5c197-c072-47ae-83a5-dae7171ceb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848283955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2848283955
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.755069389
Short name T841
Test name
Test status
Simulation time 157725951 ps
CPU time 4.39 seconds
Started Jun 09 01:10:46 PM PDT 24
Finished Jun 09 01:10:51 PM PDT 24
Peak memory 223804 kb
Host smart-2528351d-2a2d-447f-b2ab-f5855cfedf34
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=755069389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.755069389
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.566923170
Short name T342
Test name
Test status
Simulation time 8138627465 ps
CPU time 30.94 seconds
Started Jun 09 01:10:41 PM PDT 24
Finished Jun 09 01:11:13 PM PDT 24
Peak memory 217240 kb
Host smart-e3c38906-dd1c-4cb2-be0d-1cf60b7bddfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566923170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.566923170
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1399613602
Short name T867
Test name
Test status
Simulation time 588053465 ps
CPU time 7.69 seconds
Started Jun 09 01:10:46 PM PDT 24
Finished Jun 09 01:10:54 PM PDT 24
Peak memory 217340 kb
Host smart-d50dc166-fdde-45d8-a36f-3d4384d55e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399613602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1399613602
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.539460792
Short name T921
Test name
Test status
Simulation time 31198573 ps
CPU time 0.8 seconds
Started Jun 09 01:10:40 PM PDT 24
Finished Jun 09 01:10:42 PM PDT 24
Peak memory 206668 kb
Host smart-9d8bc87d-6dae-4f73-942f-fb736d90fa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539460792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.539460792
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3289733503
Short name T268
Test name
Test status
Simulation time 531515887 ps
CPU time 4.61 seconds
Started Jun 09 01:10:46 PM PDT 24
Finished Jun 09 01:10:51 PM PDT 24
Peak memory 233552 kb
Host smart-035265cc-b77f-43f3-82f8-a43db3ff437c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289733503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3289733503
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2949832323
Short name T398
Test name
Test status
Simulation time 49986841 ps
CPU time 0.71 seconds
Started Jun 09 01:08:59 PM PDT 24
Finished Jun 09 01:09:00 PM PDT 24
Peak memory 206260 kb
Host smart-73cf1511-a088-41d2-a59b-795bac774185
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949832323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
949832323
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2098689052
Short name T188
Test name
Test status
Simulation time 617663887 ps
CPU time 2.46 seconds
Started Jun 09 01:08:57 PM PDT 24
Finished Jun 09 01:09:00 PM PDT 24
Peak memory 225356 kb
Host smart-2e6f7347-b9cc-4835-ac8c-595a27a0f322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098689052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2098689052
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3323336516
Short name T642
Test name
Test status
Simulation time 17240975 ps
CPU time 0.77 seconds
Started Jun 09 01:08:54 PM PDT 24
Finished Jun 09 01:08:55 PM PDT 24
Peak memory 207744 kb
Host smart-55c821a1-be08-4e77-bd9a-8bf86fb5acc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323336516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3323336516
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2811000496
Short name T943
Test name
Test status
Simulation time 51862447367 ps
CPU time 142.39 seconds
Started Jun 09 01:09:01 PM PDT 24
Finished Jun 09 01:11:24 PM PDT 24
Peak memory 258212 kb
Host smart-a733ea0a-f7aa-4fcc-933c-f84d50868b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811000496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2811000496
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.920019458
Short name T219
Test name
Test status
Simulation time 2375735000 ps
CPU time 31.25 seconds
Started Jun 09 01:09:04 PM PDT 24
Finished Jun 09 01:09:36 PM PDT 24
Peak memory 241816 kb
Host smart-594e3af3-c8dc-4437-8a54-096fd84d9053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920019458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.920019458
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1840747803
Short name T334
Test name
Test status
Simulation time 11993276249 ps
CPU time 69.71 seconds
Started Jun 09 01:09:01 PM PDT 24
Finished Jun 09 01:10:11 PM PDT 24
Peak memory 254532 kb
Host smart-fc3f7698-e8a6-45ab-8525-52f12f4084de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840747803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1840747803
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2530050300
Short name T319
Test name
Test status
Simulation time 8206242435 ps
CPU time 28.68 seconds
Started Jun 09 01:08:57 PM PDT 24
Finished Jun 09 01:09:26 PM PDT 24
Peak memory 233916 kb
Host smart-d47c292c-205f-4ae3-b8a9-43d94eecf985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530050300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2530050300
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1773169253
Short name T925
Test name
Test status
Simulation time 174059563 ps
CPU time 3.88 seconds
Started Jun 09 01:08:56 PM PDT 24
Finished Jun 09 01:09:00 PM PDT 24
Peak memory 233524 kb
Host smart-0abc0862-776d-4181-9b65-cebd066273ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773169253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1773169253
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1006782382
Short name T923
Test name
Test status
Simulation time 891471313 ps
CPU time 14.93 seconds
Started Jun 09 01:08:56 PM PDT 24
Finished Jun 09 01:09:11 PM PDT 24
Peak memory 233492 kb
Host smart-dd3cf902-d816-4bcc-8a05-e9c66d4b5449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006782382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1006782382
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.943151962
Short name T317
Test name
Test status
Simulation time 2180454497 ps
CPU time 8.38 seconds
Started Jun 09 01:08:56 PM PDT 24
Finished Jun 09 01:09:05 PM PDT 24
Peak memory 228264 kb
Host smart-ad8c26a2-d41b-4738-a1a6-153eaa47ef3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943151962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
943151962
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3889543732
Short name T592
Test name
Test status
Simulation time 111455759 ps
CPU time 2.63 seconds
Started Jun 09 01:08:54 PM PDT 24
Finished Jun 09 01:08:57 PM PDT 24
Peak memory 225292 kb
Host smart-5710c81d-b002-4d63-8adb-bbf79ecb5a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889543732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3889543732
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.828340618
Short name T875
Test name
Test status
Simulation time 923205789 ps
CPU time 5.46 seconds
Started Jun 09 01:09:04 PM PDT 24
Finished Jun 09 01:09:10 PM PDT 24
Peak memory 221328 kb
Host smart-0eeac62d-a363-4d77-ba8c-3f81246e7607
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=828340618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.828340618
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2369911157
Short name T65
Test name
Test status
Simulation time 325256953 ps
CPU time 1.07 seconds
Started Jun 09 01:08:59 PM PDT 24
Finished Jun 09 01:09:01 PM PDT 24
Peak memory 236332 kb
Host smart-f239df20-fcf6-4fd9-8093-92f1a0f819ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369911157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2369911157
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1719695336
Short name T310
Test name
Test status
Simulation time 37069084638 ps
CPU time 305.97 seconds
Started Jun 09 01:08:59 PM PDT 24
Finished Jun 09 01:14:06 PM PDT 24
Peak memory 272148 kb
Host smart-1a65ed0e-fb04-4bbc-91bd-5676154c02da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719695336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1719695336
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.4022781428
Short name T338
Test name
Test status
Simulation time 2930799011 ps
CPU time 26.98 seconds
Started Jun 09 01:08:55 PM PDT 24
Finished Jun 09 01:09:23 PM PDT 24
Peak memory 217148 kb
Host smart-ca44bd79-3d50-4f53-9658-38dc77f5de6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022781428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.4022781428
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.4037486519
Short name T905
Test name
Test status
Simulation time 389676178 ps
CPU time 2.77 seconds
Started Jun 09 01:08:55 PM PDT 24
Finished Jun 09 01:08:58 PM PDT 24
Peak memory 217188 kb
Host smart-80fde89b-2f8f-415b-95c5-a303c176fe3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037486519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.4037486519
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2377228172
Short name T547
Test name
Test status
Simulation time 56434727 ps
CPU time 0.99 seconds
Started Jun 09 01:08:57 PM PDT 24
Finished Jun 09 01:08:58 PM PDT 24
Peak memory 207792 kb
Host smart-03dd6fb9-8982-4cf1-a009-b725c0877854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377228172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2377228172
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1582932376
Short name T954
Test name
Test status
Simulation time 89248106 ps
CPU time 0.87 seconds
Started Jun 09 01:08:54 PM PDT 24
Finished Jun 09 01:08:56 PM PDT 24
Peak memory 206708 kb
Host smart-200a5c69-589f-4c3d-962e-7e8cc6a7f95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582932376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1582932376
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.255393560
Short name T748
Test name
Test status
Simulation time 579906928 ps
CPU time 3.12 seconds
Started Jun 09 01:08:56 PM PDT 24
Finished Jun 09 01:09:00 PM PDT 24
Peak memory 233772 kb
Host smart-80a7af4e-103c-4460-8ec3-8c46c2877ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255393560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.255393560
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1844182741
Short name T772
Test name
Test status
Simulation time 36791973 ps
CPU time 0.7 seconds
Started Jun 09 01:10:46 PM PDT 24
Finished Jun 09 01:10:47 PM PDT 24
Peak memory 205672 kb
Host smart-d29284d5-91f8-4a97-b3ae-539a59e2cba5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844182741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1844182741
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2665830909
Short name T747
Test name
Test status
Simulation time 108418228 ps
CPU time 3.6 seconds
Started Jun 09 01:10:48 PM PDT 24
Finished Jun 09 01:10:52 PM PDT 24
Peak memory 233564 kb
Host smart-7063d14e-3525-4102-a13a-e325344977e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665830909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2665830909
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.4090638023
Short name T681
Test name
Test status
Simulation time 111106897 ps
CPU time 0.78 seconds
Started Jun 09 01:10:44 PM PDT 24
Finished Jun 09 01:10:45 PM PDT 24
Peak memory 206364 kb
Host smart-72f93ab4-8d39-4b20-b9b1-dbf2988a8b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090638023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.4090638023
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.267866947
Short name T541
Test name
Test status
Simulation time 1564114379 ps
CPU time 25.55 seconds
Started Jun 09 01:10:45 PM PDT 24
Finished Jun 09 01:11:11 PM PDT 24
Peak memory 236276 kb
Host smart-e200e6f3-8937-4b0e-9b7f-d3c3dc9fe343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267866947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.267866947
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.4029085116
Short name T430
Test name
Test status
Simulation time 13880909140 ps
CPU time 94 seconds
Started Jun 09 01:10:50 PM PDT 24
Finished Jun 09 01:12:24 PM PDT 24
Peak memory 253504 kb
Host smart-51a99948-59fd-4127-8040-de77f936916b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029085116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.4029085116
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1543055015
Short name T137
Test name
Test status
Simulation time 4930861507 ps
CPU time 12.91 seconds
Started Jun 09 01:10:47 PM PDT 24
Finished Jun 09 01:11:00 PM PDT 24
Peak memory 241856 kb
Host smart-7d0b3fc1-5d84-4152-9a1d-3430a4086631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543055015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1543055015
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1225807019
Short name T831
Test name
Test status
Simulation time 1129465853 ps
CPU time 11.72 seconds
Started Jun 09 01:10:46 PM PDT 24
Finished Jun 09 01:10:58 PM PDT 24
Peak memory 233552 kb
Host smart-432774a4-d956-487c-bdba-fafb4d5faec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225807019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1225807019
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3574836608
Short name T249
Test name
Test status
Simulation time 440661378 ps
CPU time 5.48 seconds
Started Jun 09 01:10:48 PM PDT 24
Finished Jun 09 01:10:54 PM PDT 24
Peak memory 225304 kb
Host smart-47822564-a897-4412-ad56-acfffa31498a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574836608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3574836608
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1229474794
Short name T711
Test name
Test status
Simulation time 475879472 ps
CPU time 2.06 seconds
Started Jun 09 01:10:47 PM PDT 24
Finished Jun 09 01:10:49 PM PDT 24
Peak memory 223792 kb
Host smart-e8db6b51-2289-4d9c-8d46-7147d59350f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229474794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1229474794
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1561107498
Short name T474
Test name
Test status
Simulation time 27644202773 ps
CPU time 22.07 seconds
Started Jun 09 01:10:47 PM PDT 24
Finished Jun 09 01:11:09 PM PDT 24
Peak memory 250296 kb
Host smart-c47e56a0-e04a-4c41-85d9-7779f53c761f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561107498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1561107498
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1323318815
Short name T691
Test name
Test status
Simulation time 734309631 ps
CPU time 5.25 seconds
Started Jun 09 01:10:46 PM PDT 24
Finished Jun 09 01:10:51 PM PDT 24
Peak memory 223384 kb
Host smart-591fc1f7-093c-417d-b639-df23268365ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1323318815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1323318815
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1819302274
Short name T658
Test name
Test status
Simulation time 46328533 ps
CPU time 0.93 seconds
Started Jun 09 01:10:46 PM PDT 24
Finished Jun 09 01:10:47 PM PDT 24
Peak memory 206776 kb
Host smart-cd2fda5c-4455-4125-93f9-4cb30420bd06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819302274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1819302274
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2112527285
Short name T700
Test name
Test status
Simulation time 8377050539 ps
CPU time 27.35 seconds
Started Jun 09 01:10:41 PM PDT 24
Finished Jun 09 01:11:09 PM PDT 24
Peak memory 217312 kb
Host smart-13d144a7-b7b7-4b39-a028-aa6c89f63a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112527285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2112527285
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3324634917
Short name T51
Test name
Test status
Simulation time 424034806 ps
CPU time 2.4 seconds
Started Jun 09 01:10:44 PM PDT 24
Finished Jun 09 01:10:46 PM PDT 24
Peak memory 217136 kb
Host smart-636ed50f-9dce-4b76-8b7c-62241d44c4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324634917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3324634917
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2271352218
Short name T441
Test name
Test status
Simulation time 114812014 ps
CPU time 2.22 seconds
Started Jun 09 01:10:48 PM PDT 24
Finished Jun 09 01:10:50 PM PDT 24
Peak memory 217096 kb
Host smart-d862f728-6687-4913-a231-41522758bc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271352218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2271352218
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2923687589
Short name T804
Test name
Test status
Simulation time 331654307 ps
CPU time 0.84 seconds
Started Jun 09 01:10:47 PM PDT 24
Finished Jun 09 01:10:48 PM PDT 24
Peak memory 206676 kb
Host smart-4dec6808-57fe-47c0-83e6-9f9deab9ed00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923687589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2923687589
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1733020037
Short name T54
Test name
Test status
Simulation time 400974634 ps
CPU time 6.37 seconds
Started Jun 09 01:10:48 PM PDT 24
Finished Jun 09 01:10:54 PM PDT 24
Peak memory 233488 kb
Host smart-fa35363e-8ea3-4dd0-a982-e4b26c0d9cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733020037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1733020037
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3552988255
Short name T639
Test name
Test status
Simulation time 50000883 ps
CPU time 0.72 seconds
Started Jun 09 01:10:54 PM PDT 24
Finished Jun 09 01:10:55 PM PDT 24
Peak memory 206260 kb
Host smart-764e7015-384e-4bbe-917b-6f4cffefe9ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552988255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3552988255
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1193415609
Short name T90
Test name
Test status
Simulation time 1411223003 ps
CPU time 8.76 seconds
Started Jun 09 01:10:54 PM PDT 24
Finished Jun 09 01:11:03 PM PDT 24
Peak memory 233584 kb
Host smart-d8964491-750c-4bd4-9ba1-8f883f785738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193415609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1193415609
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3491573758
Short name T48
Test name
Test status
Simulation time 35090534 ps
CPU time 0.78 seconds
Started Jun 09 01:10:48 PM PDT 24
Finished Jun 09 01:10:49 PM PDT 24
Peak memory 207708 kb
Host smart-bbe5444e-f454-425c-895c-a30e12ca8d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491573758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3491573758
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1037135382
Short name T282
Test name
Test status
Simulation time 26154297257 ps
CPU time 88.36 seconds
Started Jun 09 01:10:58 PM PDT 24
Finished Jun 09 01:12:26 PM PDT 24
Peak memory 238384 kb
Host smart-c359ea7d-0c2b-4dad-820d-9a06c2a6e141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037135382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1037135382
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3895358501
Short name T329
Test name
Test status
Simulation time 213406734 ps
CPU time 7.35 seconds
Started Jun 09 01:10:55 PM PDT 24
Finished Jun 09 01:11:03 PM PDT 24
Peak memory 225296 kb
Host smart-f75909f6-a4b6-45ce-a21b-bc8966430b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895358501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3895358501
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.225611630
Short name T687
Test name
Test status
Simulation time 697823252 ps
CPU time 3.83 seconds
Started Jun 09 01:10:56 PM PDT 24
Finished Jun 09 01:11:00 PM PDT 24
Peak memory 233548 kb
Host smart-be6cbe4e-5733-402c-8a40-517bf8d99b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225611630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.225611630
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.4149784383
Short name T625
Test name
Test status
Simulation time 62746035503 ps
CPU time 40.93 seconds
Started Jun 09 01:10:54 PM PDT 24
Finished Jun 09 01:11:35 PM PDT 24
Peak memory 229072 kb
Host smart-044b407b-595d-4eed-8f74-56e746eb75fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149784383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.4149784383
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3947800539
Short name T857
Test name
Test status
Simulation time 295596923 ps
CPU time 2.32 seconds
Started Jun 09 01:10:45 PM PDT 24
Finished Jun 09 01:10:48 PM PDT 24
Peak memory 225344 kb
Host smart-e86ace48-b935-43d2-a09a-591c8d69b2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947800539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3947800539
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1601433401
Short name T373
Test name
Test status
Simulation time 82647979 ps
CPU time 2.25 seconds
Started Jun 09 01:10:50 PM PDT 24
Finished Jun 09 01:10:52 PM PDT 24
Peak memory 233376 kb
Host smart-54958705-1e18-4695-b502-beb1081ed988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601433401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1601433401
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2670673080
Short name T641
Test name
Test status
Simulation time 825006412 ps
CPU time 3.82 seconds
Started Jun 09 01:10:54 PM PDT 24
Finished Jun 09 01:10:58 PM PDT 24
Peak memory 220076 kb
Host smart-6a4c047c-e07e-4bd2-8f7b-f0c32fd4b73a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2670673080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2670673080
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3487161332
Short name T336
Test name
Test status
Simulation time 6654866409 ps
CPU time 73.01 seconds
Started Jun 09 01:10:55 PM PDT 24
Finished Jun 09 01:12:08 PM PDT 24
Peak memory 241928 kb
Host smart-94828761-2fdb-403c-8391-980e64f0435f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487161332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3487161332
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.4050247034
Short name T339
Test name
Test status
Simulation time 4427980752 ps
CPU time 24.81 seconds
Started Jun 09 01:10:48 PM PDT 24
Finished Jun 09 01:11:13 PM PDT 24
Peak memory 217560 kb
Host smart-2b7f8218-f290-4f5a-a89f-4911e9d51f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050247034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.4050247034
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3897152559
Short name T887
Test name
Test status
Simulation time 11145171071 ps
CPU time 15.79 seconds
Started Jun 09 01:10:47 PM PDT 24
Finished Jun 09 01:11:03 PM PDT 24
Peak memory 217228 kb
Host smart-ced408e7-05c7-4efa-b806-33f06252c9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897152559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3897152559
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.856856490
Short name T464
Test name
Test status
Simulation time 273088854 ps
CPU time 3.68 seconds
Started Jun 09 01:10:49 PM PDT 24
Finished Jun 09 01:10:52 PM PDT 24
Peak memory 217196 kb
Host smart-f468153f-85cf-42f6-b070-adeb8104bef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856856490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.856856490
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3905091946
Short name T907
Test name
Test status
Simulation time 132331021 ps
CPU time 0.71 seconds
Started Jun 09 01:10:47 PM PDT 24
Finished Jun 09 01:10:48 PM PDT 24
Peak memory 206680 kb
Host smart-e912ac2b-f28b-4c4e-86a3-348487c1e804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905091946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3905091946
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3415749237
Short name T192
Test name
Test status
Simulation time 3558184900 ps
CPU time 13.56 seconds
Started Jun 09 01:10:55 PM PDT 24
Finished Jun 09 01:11:09 PM PDT 24
Peak memory 225396 kb
Host smart-067a6684-eadb-4111-a25e-67d2616d7bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415749237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3415749237
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.863814628
Short name T472
Test name
Test status
Simulation time 12873094 ps
CPU time 0.71 seconds
Started Jun 09 01:10:57 PM PDT 24
Finished Jun 09 01:10:58 PM PDT 24
Peak memory 205680 kb
Host smart-5d4cad1a-dbe4-4d4a-861e-eb5e43e2e353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863814628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.863814628
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3144357330
Short name T577
Test name
Test status
Simulation time 1735937036 ps
CPU time 9.78 seconds
Started Jun 09 01:10:57 PM PDT 24
Finished Jun 09 01:11:07 PM PDT 24
Peak memory 233560 kb
Host smart-564beda1-50ed-4c87-9764-1a5186eb57cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144357330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3144357330
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2280460453
Short name T401
Test name
Test status
Simulation time 12117853 ps
CPU time 0.75 seconds
Started Jun 09 01:10:56 PM PDT 24
Finished Jun 09 01:10:57 PM PDT 24
Peak memory 206376 kb
Host smart-bef03d19-629e-4af7-9ca4-0070ec42e7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280460453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2280460453
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2230610893
Short name T934
Test name
Test status
Simulation time 87298609927 ps
CPU time 87.38 seconds
Started Jun 09 01:10:59 PM PDT 24
Finished Jun 09 01:12:27 PM PDT 24
Peak memory 250116 kb
Host smart-b5810f48-3822-40d1-9466-bcf60964ca97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230610893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2230610893
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1967312677
Short name T513
Test name
Test status
Simulation time 226074756 ps
CPU time 7.31 seconds
Started Jun 09 01:10:57 PM PDT 24
Finished Jun 09 01:11:05 PM PDT 24
Peak memory 249456 kb
Host smart-86b93d9c-5103-404b-ab00-bf034b38706b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967312677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1967312677
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3355706570
Short name T258
Test name
Test status
Simulation time 8517664871 ps
CPU time 20.97 seconds
Started Jun 09 01:10:54 PM PDT 24
Finished Jun 09 01:11:16 PM PDT 24
Peak memory 233664 kb
Host smart-f6f3df1d-4033-46a4-be12-9aa6f276cda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355706570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3355706570
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.4008831055
Short name T483
Test name
Test status
Simulation time 712502804 ps
CPU time 15.88 seconds
Started Jun 09 01:10:54 PM PDT 24
Finished Jun 09 01:11:10 PM PDT 24
Peak memory 249508 kb
Host smart-accb51e6-3c64-4115-acea-9735006646e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008831055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.4008831055
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2465546250
Short name T403
Test name
Test status
Simulation time 2266237571 ps
CPU time 9.1 seconds
Started Jun 09 01:10:57 PM PDT 24
Finished Jun 09 01:11:06 PM PDT 24
Peak memory 225472 kb
Host smart-f64c21b9-5038-486d-9dde-c03a19b4a6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465546250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2465546250
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3918818288
Short name T235
Test name
Test status
Simulation time 8461210522 ps
CPU time 7.31 seconds
Started Jun 09 01:10:56 PM PDT 24
Finished Jun 09 01:11:04 PM PDT 24
Peak memory 225368 kb
Host smart-4a7f37a4-1e8a-44dc-ba03-30a574b83f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918818288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3918818288
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.243885444
Short name T638
Test name
Test status
Simulation time 367460788 ps
CPU time 4.33 seconds
Started Jun 09 01:10:57 PM PDT 24
Finished Jun 09 01:11:02 PM PDT 24
Peak memory 221460 kb
Host smart-e79e48a1-de0f-4571-9ae5-fb40bf8ca605
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=243885444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.243885444
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3110225361
Short name T294
Test name
Test status
Simulation time 29746755477 ps
CPU time 155.54 seconds
Started Jun 09 01:11:05 PM PDT 24
Finished Jun 09 01:13:40 PM PDT 24
Peak memory 251604 kb
Host smart-3ab23bd3-662f-4e95-953a-bbac23f41d6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110225361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3110225361
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.88741151
Short name T501
Test name
Test status
Simulation time 6892626492 ps
CPU time 39.84 seconds
Started Jun 09 01:10:55 PM PDT 24
Finished Jun 09 01:11:36 PM PDT 24
Peak memory 217344 kb
Host smart-a5e6dbe7-6ae3-4110-a6ff-acec44ed4e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88741151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.88741151
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1706382807
Short name T379
Test name
Test status
Simulation time 68921588 ps
CPU time 1.03 seconds
Started Jun 09 01:10:56 PM PDT 24
Finished Jun 09 01:10:57 PM PDT 24
Peak memory 208724 kb
Host smart-a9a5ae09-0d40-4132-971d-486079f191ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706382807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1706382807
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1776479323
Short name T521
Test name
Test status
Simulation time 1627736937 ps
CPU time 13.33 seconds
Started Jun 09 01:10:55 PM PDT 24
Finished Jun 09 01:11:09 PM PDT 24
Peak memory 217108 kb
Host smart-fe2e4d8b-3e74-43d5-bf59-e9626e11335b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776479323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1776479323
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.728950679
Short name T583
Test name
Test status
Simulation time 201258854 ps
CPU time 0.76 seconds
Started Jun 09 01:10:52 PM PDT 24
Finished Jun 09 01:10:53 PM PDT 24
Peak memory 206668 kb
Host smart-e70963c3-6249-4de4-875a-8a5fd98f45c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728950679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.728950679
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2189020673
Short name T537
Test name
Test status
Simulation time 152447218 ps
CPU time 2.13 seconds
Started Jun 09 01:10:56 PM PDT 24
Finished Jun 09 01:10:58 PM PDT 24
Peak memory 224296 kb
Host smart-ceccd9ba-6f85-4dbd-9742-9f4d31e0a0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189020673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2189020673
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1541303646
Short name T726
Test name
Test status
Simulation time 21594895 ps
CPU time 0.73 seconds
Started Jun 09 01:11:06 PM PDT 24
Finished Jun 09 01:11:07 PM PDT 24
Peak memory 205700 kb
Host smart-f4a92290-d37f-4e2f-ac34-929523ff4a8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541303646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1541303646
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2908364322
Short name T287
Test name
Test status
Simulation time 198468533 ps
CPU time 3.51 seconds
Started Jun 09 01:11:00 PM PDT 24
Finished Jun 09 01:11:04 PM PDT 24
Peak memory 225276 kb
Host smart-54ba391a-c357-4a40-846e-dc8dede851af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908364322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2908364322
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2107372228
Short name T895
Test name
Test status
Simulation time 43443870 ps
CPU time 0.77 seconds
Started Jun 09 01:10:57 PM PDT 24
Finished Jun 09 01:10:59 PM PDT 24
Peak memory 207348 kb
Host smart-2a7f4779-83b4-4a05-b50d-f860ea256cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107372228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2107372228
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2458414395
Short name T931
Test name
Test status
Simulation time 30461099 ps
CPU time 0.73 seconds
Started Jun 09 01:11:00 PM PDT 24
Finished Jun 09 01:11:00 PM PDT 24
Peak memory 216660 kb
Host smart-c1c6177f-e2e2-47ba-9ebf-39fb15839f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458414395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2458414395
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3407022905
Short name T194
Test name
Test status
Simulation time 28666346875 ps
CPU time 232.03 seconds
Started Jun 09 01:11:00 PM PDT 24
Finished Jun 09 01:14:52 PM PDT 24
Peak memory 256456 kb
Host smart-9709a1f4-3e7e-4dd6-b0c4-761473a27bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407022905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3407022905
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1127964260
Short name T328
Test name
Test status
Simulation time 2153709582 ps
CPU time 13.87 seconds
Started Jun 09 01:10:57 PM PDT 24
Finished Jun 09 01:11:11 PM PDT 24
Peak memory 233664 kb
Host smart-653b3a18-9479-4e31-8bfc-f11494ec2a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127964260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1127964260
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1526931267
Short name T221
Test name
Test status
Simulation time 234278132 ps
CPU time 5.56 seconds
Started Jun 09 01:10:57 PM PDT 24
Finished Jun 09 01:11:03 PM PDT 24
Peak memory 221052 kb
Host smart-3e4cfcf0-4433-444c-be82-10ab0f2754c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526931267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1526931267
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3842472675
Short name T359
Test name
Test status
Simulation time 2125364353 ps
CPU time 4.92 seconds
Started Jun 09 01:10:58 PM PDT 24
Finished Jun 09 01:11:03 PM PDT 24
Peak memory 233692 kb
Host smart-3d78d104-1d91-467a-ad5a-7a35b9d9d995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842472675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3842472675
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.126671229
Short name T567
Test name
Test status
Simulation time 293002850 ps
CPU time 2.39 seconds
Started Jun 09 01:10:58 PM PDT 24
Finished Jun 09 01:11:01 PM PDT 24
Peak memory 223836 kb
Host smart-a0c75807-d64c-47d8-a384-6c7b9c58dfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126671229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.126671229
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3024240900
Short name T432
Test name
Test status
Simulation time 7950994578 ps
CPU time 11.57 seconds
Started Jun 09 01:10:58 PM PDT 24
Finished Jun 09 01:11:10 PM PDT 24
Peak memory 233820 kb
Host smart-c201cd64-20c3-4ac2-aa13-2b5f3d067a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024240900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3024240900
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.84323391
Short name T750
Test name
Test status
Simulation time 90838006 ps
CPU time 4.01 seconds
Started Jun 09 01:11:05 PM PDT 24
Finished Jun 09 01:11:09 PM PDT 24
Peak memory 223748 kb
Host smart-3604f663-c8a3-4e88-b3da-e57c06e91658
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=84323391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direc
t.84323391
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.160133567
Short name T331
Test name
Test status
Simulation time 10693844789 ps
CPU time 19.37 seconds
Started Jun 09 01:10:58 PM PDT 24
Finished Jun 09 01:11:18 PM PDT 24
Peak memory 217252 kb
Host smart-44b37bc4-4ebd-4601-9a3a-e4ead63e1303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160133567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.160133567
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3801827755
Short name T612
Test name
Test status
Simulation time 1482982913 ps
CPU time 8.23 seconds
Started Jun 09 01:10:57 PM PDT 24
Finished Jun 09 01:11:06 PM PDT 24
Peak memory 217072 kb
Host smart-4dde02b6-7eca-4b9c-b9bb-1a0de1bba02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801827755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3801827755
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2599087620
Short name T553
Test name
Test status
Simulation time 69827490 ps
CPU time 1.22 seconds
Started Jun 09 01:11:01 PM PDT 24
Finished Jun 09 01:11:02 PM PDT 24
Peak memory 208708 kb
Host smart-a49716fb-52dc-494b-b929-41ff5f05680e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599087620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2599087620
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.820148953
Short name T626
Test name
Test status
Simulation time 61836711 ps
CPU time 0.78 seconds
Started Jun 09 01:11:05 PM PDT 24
Finished Jun 09 01:11:06 PM PDT 24
Peak memory 206676 kb
Host smart-2f8ab125-4543-4322-8699-347842d3c919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820148953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.820148953
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1509609079
Short name T525
Test name
Test status
Simulation time 1006349144 ps
CPU time 5.99 seconds
Started Jun 09 01:10:57 PM PDT 24
Finished Jun 09 01:11:04 PM PDT 24
Peak memory 241848 kb
Host smart-388d7701-4b2d-48ad-afb1-7606276a32aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509609079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1509609079
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3397642345
Short name T465
Test name
Test status
Simulation time 15324293 ps
CPU time 0.73 seconds
Started Jun 09 01:11:10 PM PDT 24
Finished Jun 09 01:11:11 PM PDT 24
Peak memory 205676 kb
Host smart-46206e3c-7c25-4c25-9d11-22a4fb2d9ebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397642345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3397642345
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3634459762
Short name T540
Test name
Test status
Simulation time 206760418 ps
CPU time 5.34 seconds
Started Jun 09 01:11:12 PM PDT 24
Finished Jun 09 01:11:17 PM PDT 24
Peak memory 225304 kb
Host smart-6401dad6-9187-4132-a6fd-863a8d891dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634459762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3634459762
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1796633836
Short name T352
Test name
Test status
Simulation time 19090436 ps
CPU time 0.82 seconds
Started Jun 09 01:11:05 PM PDT 24
Finished Jun 09 01:11:06 PM PDT 24
Peak memory 207388 kb
Host smart-27399cd9-f372-45af-9c3d-4794006596fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796633836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1796633836
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2133669068
Short name T582
Test name
Test status
Simulation time 2337636233 ps
CPU time 17.11 seconds
Started Jun 09 01:11:09 PM PDT 24
Finished Jun 09 01:11:26 PM PDT 24
Peak memory 233660 kb
Host smart-4c6a3ae6-4896-4394-88bc-ee6ec4af65d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133669068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2133669068
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2227045833
Short name T276
Test name
Test status
Simulation time 20545053236 ps
CPU time 94.17 seconds
Started Jun 09 01:11:10 PM PDT 24
Finished Jun 09 01:12:45 PM PDT 24
Peak memory 249180 kb
Host smart-30cb1f6b-c606-481b-b27d-3c52eb3157d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227045833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2227045833
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1850204154
Short name T574
Test name
Test status
Simulation time 164750099260 ps
CPU time 438.68 seconds
Started Jun 09 01:11:10 PM PDT 24
Finished Jun 09 01:18:30 PM PDT 24
Peak memory 257292 kb
Host smart-c317f0ec-2960-4672-82cd-64232ef2ab8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850204154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1850204154
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.998216779
Short name T71
Test name
Test status
Simulation time 6051069629 ps
CPU time 21.14 seconds
Started Jun 09 01:11:08 PM PDT 24
Finished Jun 09 01:11:30 PM PDT 24
Peak memory 241312 kb
Host smart-4e56421b-e40c-42e1-a88c-0569e5610538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998216779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.998216779
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3615105298
Short name T271
Test name
Test status
Simulation time 683940199 ps
CPU time 4.89 seconds
Started Jun 09 01:11:03 PM PDT 24
Finished Jun 09 01:11:08 PM PDT 24
Peak memory 233540 kb
Host smart-fb04b5bd-4f3b-4f67-85a7-45da89376a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615105298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3615105298
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.796844225
Short name T874
Test name
Test status
Simulation time 24251129315 ps
CPU time 73.48 seconds
Started Jun 09 01:11:03 PM PDT 24
Finished Jun 09 01:12:16 PM PDT 24
Peak memory 241824 kb
Host smart-9d61cae8-1291-4683-80d6-e47bface326c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796844225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.796844225
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2942860263
Short name T848
Test name
Test status
Simulation time 154642421 ps
CPU time 2.95 seconds
Started Jun 09 01:11:05 PM PDT 24
Finished Jun 09 01:11:08 PM PDT 24
Peak memory 233572 kb
Host smart-50cd0eca-d140-46d9-831a-8bfddabaddd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942860263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2942860263
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2001604890
Short name T833
Test name
Test status
Simulation time 1331789595 ps
CPU time 5.68 seconds
Started Jun 09 01:11:05 PM PDT 24
Finished Jun 09 01:11:11 PM PDT 24
Peak memory 225268 kb
Host smart-73d60433-2467-43c1-a084-b591372518c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001604890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2001604890
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2619216764
Short name T528
Test name
Test status
Simulation time 6866849762 ps
CPU time 14.64 seconds
Started Jun 09 01:11:10 PM PDT 24
Finished Jun 09 01:11:25 PM PDT 24
Peak memory 223852 kb
Host smart-68ad53ea-dc27-43cb-a0e2-529c6136174b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2619216764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2619216764
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1080096751
Short name T532
Test name
Test status
Simulation time 45356193 ps
CPU time 0.9 seconds
Started Jun 09 01:11:09 PM PDT 24
Finished Jun 09 01:11:10 PM PDT 24
Peak memory 207732 kb
Host smart-559e17fc-a602-4f20-a234-5b03ca30f6d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080096751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1080096751
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1608882609
Short name T535
Test name
Test status
Simulation time 2454307295 ps
CPU time 5.02 seconds
Started Jun 09 01:11:03 PM PDT 24
Finished Jun 09 01:11:08 PM PDT 24
Peak memory 220080 kb
Host smart-05c787a9-ac4c-4834-b17d-1f101f4a642e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608882609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1608882609
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3503490360
Short name T930
Test name
Test status
Simulation time 611214004 ps
CPU time 5.46 seconds
Started Jun 09 01:11:04 PM PDT 24
Finished Jun 09 01:11:10 PM PDT 24
Peak memory 217152 kb
Host smart-ecbce592-b31f-4afd-a222-25b4a6675d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503490360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3503490360
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.121426069
Short name T957
Test name
Test status
Simulation time 331676447 ps
CPU time 2.24 seconds
Started Jun 09 01:11:06 PM PDT 24
Finished Jun 09 01:11:09 PM PDT 24
Peak memory 217164 kb
Host smart-1c74a417-9eb6-44a6-be9b-220171e0175e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121426069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.121426069
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.294890320
Short name T376
Test name
Test status
Simulation time 79708768 ps
CPU time 0.82 seconds
Started Jun 09 01:11:05 PM PDT 24
Finished Jun 09 01:11:06 PM PDT 24
Peak memory 206680 kb
Host smart-79d1950b-d083-4f8d-95d7-e6b9bdeb59c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294890320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.294890320
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.982148111
Short name T407
Test name
Test status
Simulation time 1600682538 ps
CPU time 3.98 seconds
Started Jun 09 01:11:05 PM PDT 24
Finished Jun 09 01:11:09 PM PDT 24
Peak memory 233476 kb
Host smart-ae19c747-48e3-4e13-a544-14e92fd7512e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982148111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.982148111
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.295289357
Short name T480
Test name
Test status
Simulation time 16054342 ps
CPU time 0.75 seconds
Started Jun 09 01:11:18 PM PDT 24
Finished Jun 09 01:11:19 PM PDT 24
Peak memory 206256 kb
Host smart-e936a2be-6ae3-4b2f-983c-4ae9beb4b358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295289357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.295289357
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1114912825
Short name T599
Test name
Test status
Simulation time 396721335 ps
CPU time 2.27 seconds
Started Jun 09 01:11:09 PM PDT 24
Finished Jun 09 01:11:12 PM PDT 24
Peak memory 225384 kb
Host smart-3f77ec8b-158b-43a4-9b2a-66b363fdedad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114912825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1114912825
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1089539370
Short name T508
Test name
Test status
Simulation time 17897487 ps
CPU time 0.8 seconds
Started Jun 09 01:11:09 PM PDT 24
Finished Jun 09 01:11:10 PM PDT 24
Peak memory 206660 kb
Host smart-ec3d304a-8381-4839-9784-2aa41d79bb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089539370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1089539370
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1271545081
Short name T29
Test name
Test status
Simulation time 32014434158 ps
CPU time 117.61 seconds
Started Jun 09 01:11:18 PM PDT 24
Finished Jun 09 01:13:16 PM PDT 24
Peak memory 250048 kb
Host smart-dec4f699-ffdf-42a2-96e7-1fe92f5210cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271545081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1271545081
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3858569270
Short name T633
Test name
Test status
Simulation time 3249161077 ps
CPU time 14.25 seconds
Started Jun 09 01:11:17 PM PDT 24
Finished Jun 09 01:11:31 PM PDT 24
Peak memory 218428 kb
Host smart-8413a549-6cce-48f4-a183-ba15513a91a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858569270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3858569270
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.157217440
Short name T314
Test name
Test status
Simulation time 17211840069 ps
CPU time 37.78 seconds
Started Jun 09 01:11:15 PM PDT 24
Finished Jun 09 01:11:53 PM PDT 24
Peak memory 250104 kb
Host smart-d031fa2a-d83a-4132-9b6b-9e240890d1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157217440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.157217440
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3430813
Short name T330
Test name
Test status
Simulation time 347888502 ps
CPU time 9.22 seconds
Started Jun 09 01:11:11 PM PDT 24
Finished Jun 09 01:11:20 PM PDT 24
Peak memory 225368 kb
Host smart-2f85f99f-3054-4524-a9f3-2c7d16637f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3430813
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.83433906
Short name T680
Test name
Test status
Simulation time 224668225 ps
CPU time 3.24 seconds
Started Jun 09 01:11:09 PM PDT 24
Finished Jun 09 01:11:13 PM PDT 24
Peak memory 225328 kb
Host smart-63026c3a-02d3-4d3d-ae49-7bbc97b750c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83433906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.83433906
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3543734366
Short name T160
Test name
Test status
Simulation time 341105807 ps
CPU time 7.56 seconds
Started Jun 09 01:11:10 PM PDT 24
Finished Jun 09 01:11:18 PM PDT 24
Peak memory 230796 kb
Host smart-ab1ed500-12d6-4cf9-9e5f-f4c1e3013bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543734366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3543734366
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.4156021572
Short name T396
Test name
Test status
Simulation time 102138181 ps
CPU time 2.1 seconds
Started Jun 09 01:11:09 PM PDT 24
Finished Jun 09 01:11:11 PM PDT 24
Peak memory 223992 kb
Host smart-a5e2f494-ae9f-4512-98f1-2ef1f95c0c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156021572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.4156021572
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.858479460
Short name T263
Test name
Test status
Simulation time 5752038940 ps
CPU time 8.04 seconds
Started Jun 09 01:11:09 PM PDT 24
Finished Jun 09 01:11:17 PM PDT 24
Peak memory 241672 kb
Host smart-9eb7d173-d2dc-4755-8ccc-6c57562caa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858479460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.858479460
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3522335864
Short name T757
Test name
Test status
Simulation time 212381370 ps
CPU time 5.46 seconds
Started Jun 09 01:11:16 PM PDT 24
Finished Jun 09 01:11:22 PM PDT 24
Peak memory 221048 kb
Host smart-a3b3f6fa-2eb3-4403-b194-7418eb7109c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3522335864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3522335864
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.524124311
Short name T61
Test name
Test status
Simulation time 19917683261 ps
CPU time 38.2 seconds
Started Jun 09 01:11:17 PM PDT 24
Finished Jun 09 01:11:55 PM PDT 24
Peak memory 235172 kb
Host smart-6e3891ee-9fd9-44b1-9535-de705c4d2cb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524124311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.524124311
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.90941002
Short name T332
Test name
Test status
Simulation time 4149314200 ps
CPU time 26.98 seconds
Started Jun 09 01:11:08 PM PDT 24
Finished Jun 09 01:11:35 PM PDT 24
Peak memory 217344 kb
Host smart-5702bab7-b131-4165-9bb3-2ac13ddb53d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90941002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.90941002
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3642563044
Short name T533
Test name
Test status
Simulation time 908841987 ps
CPU time 6.27 seconds
Started Jun 09 01:11:10 PM PDT 24
Finished Jun 09 01:11:17 PM PDT 24
Peak memory 217156 kb
Host smart-da032853-2514-487f-afa6-be876c0fd430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642563044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3642563044
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3677451174
Short name T386
Test name
Test status
Simulation time 161474746 ps
CPU time 0.84 seconds
Started Jun 09 01:11:09 PM PDT 24
Finished Jun 09 01:11:10 PM PDT 24
Peak memory 207388 kb
Host smart-5a584ced-a99e-444c-9595-d50b70431ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677451174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3677451174
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.764536571
Short name T656
Test name
Test status
Simulation time 33207588 ps
CPU time 0.73 seconds
Started Jun 09 01:11:10 PM PDT 24
Finished Jun 09 01:11:11 PM PDT 24
Peak memory 206884 kb
Host smart-1118bb2d-d5b0-4c0e-937c-9417fe94ec0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764536571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.764536571
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.308589197
Short name T256
Test name
Test status
Simulation time 2015306576 ps
CPU time 3.31 seconds
Started Jun 09 01:11:09 PM PDT 24
Finished Jun 09 01:11:12 PM PDT 24
Peak memory 225284 kb
Host smart-afe60ce9-2963-49eb-89bd-bd90fa5bab19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308589197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.308589197
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3194400004
Short name T405
Test name
Test status
Simulation time 43287942 ps
CPU time 0.71 seconds
Started Jun 09 01:11:25 PM PDT 24
Finished Jun 09 01:11:26 PM PDT 24
Peak memory 205664 kb
Host smart-2f88b604-11f6-4e65-a37a-5a71856e3ca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194400004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3194400004
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3772984211
Short name T516
Test name
Test status
Simulation time 2734502532 ps
CPU time 6.62 seconds
Started Jun 09 01:11:16 PM PDT 24
Finished Jun 09 01:11:23 PM PDT 24
Peak memory 233684 kb
Host smart-90616f0a-006d-43e3-b1dd-67c1fea92e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772984211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3772984211
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3134728017
Short name T161
Test name
Test status
Simulation time 13074621 ps
CPU time 0.76 seconds
Started Jun 09 01:11:20 PM PDT 24
Finished Jun 09 01:11:21 PM PDT 24
Peak memory 207368 kb
Host smart-64463a0c-ff74-4b3f-a4e9-bb47eaef0f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134728017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3134728017
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.4273749975
Short name T693
Test name
Test status
Simulation time 7275445760 ps
CPU time 50.21 seconds
Started Jun 09 01:11:17 PM PDT 24
Finished Jun 09 01:12:07 PM PDT 24
Peak memory 236596 kb
Host smart-560d211a-f52f-446c-a47a-8af3f6484817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273749975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.4273749975
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.145474962
Short name T499
Test name
Test status
Simulation time 1477558823 ps
CPU time 20.28 seconds
Started Jun 09 01:11:17 PM PDT 24
Finished Jun 09 01:11:38 PM PDT 24
Peak memory 225368 kb
Host smart-977ba35d-e66c-4725-9df8-7eca233fd2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145474962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.145474962
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.911056587
Short name T932
Test name
Test status
Simulation time 429146664 ps
CPU time 11.45 seconds
Started Jun 09 01:11:19 PM PDT 24
Finished Jun 09 01:11:31 PM PDT 24
Peak memory 225328 kb
Host smart-44c9d9b2-6572-47ba-998c-1783fdc63e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911056587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.911056587
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3384332271
Short name T961
Test name
Test status
Simulation time 379926274 ps
CPU time 4.02 seconds
Started Jun 09 01:11:17 PM PDT 24
Finished Jun 09 01:11:21 PM PDT 24
Peak memory 225276 kb
Host smart-8f358c85-7f7c-4424-bd65-87c0998867f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384332271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3384332271
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1960132932
Short name T877
Test name
Test status
Simulation time 359216428 ps
CPU time 9.7 seconds
Started Jun 09 01:11:20 PM PDT 24
Finished Jun 09 01:11:30 PM PDT 24
Peak memory 233440 kb
Host smart-8b39bfb5-722f-4031-ad91-d08222e4a499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960132932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1960132932
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2361745771
Short name T761
Test name
Test status
Simulation time 1240273749 ps
CPU time 2.74 seconds
Started Jun 09 01:11:16 PM PDT 24
Finished Jun 09 01:11:19 PM PDT 24
Peak memory 225356 kb
Host smart-e056b8f8-e49d-4002-b398-c73c3aaef453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361745771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2361745771
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2260488241
Short name T853
Test name
Test status
Simulation time 24327865479 ps
CPU time 14.36 seconds
Started Jun 09 01:11:15 PM PDT 24
Finished Jun 09 01:11:30 PM PDT 24
Peak memory 233668 kb
Host smart-92f1f5ea-88ba-403d-b30e-e71b598010c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260488241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2260488241
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.4111263641
Short name T707
Test name
Test status
Simulation time 134412960 ps
CPU time 3.32 seconds
Started Jun 09 01:11:17 PM PDT 24
Finished Jun 09 01:11:20 PM PDT 24
Peak memory 219980 kb
Host smart-13a4e8f1-f1ce-474d-a9ad-2c33db76aa29
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4111263641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.4111263641
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3402015288
Short name T842
Test name
Test status
Simulation time 2155463869 ps
CPU time 11.33 seconds
Started Jun 09 01:11:17 PM PDT 24
Finished Jun 09 01:11:28 PM PDT 24
Peak memory 220668 kb
Host smart-d63cf283-4e18-431f-84e3-a9412fa37052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402015288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3402015288
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1345527172
Short name T349
Test name
Test status
Simulation time 13676424845 ps
CPU time 11.63 seconds
Started Jun 09 01:11:16 PM PDT 24
Finished Jun 09 01:11:28 PM PDT 24
Peak memory 217260 kb
Host smart-5fef72d4-4b40-48e1-9cf1-633deb1f9c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345527172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1345527172
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.975328808
Short name T881
Test name
Test status
Simulation time 523631084 ps
CPU time 1.05 seconds
Started Jun 09 01:11:16 PM PDT 24
Finished Jun 09 01:11:18 PM PDT 24
Peak memory 208176 kb
Host smart-06ff336c-177a-4806-8955-48187ff440c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975328808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.975328808
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3850887087
Short name T622
Test name
Test status
Simulation time 24126294 ps
CPU time 0.74 seconds
Started Jun 09 01:11:16 PM PDT 24
Finished Jun 09 01:11:17 PM PDT 24
Peak memory 206712 kb
Host smart-6dab4e72-887b-4edc-8853-2f80d684f793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850887087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3850887087
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1847529507
Short name T946
Test name
Test status
Simulation time 122852086 ps
CPU time 2.35 seconds
Started Jun 09 01:11:16 PM PDT 24
Finished Jun 09 01:11:19 PM PDT 24
Peak memory 223684 kb
Host smart-cf3cc441-f4c4-440d-934d-d0f5f6e8d680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847529507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1847529507
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1643601012
Short name T778
Test name
Test status
Simulation time 43860711 ps
CPU time 0.74 seconds
Started Jun 09 01:11:24 PM PDT 24
Finished Jun 09 01:11:25 PM PDT 24
Peak memory 206248 kb
Host smart-618a0bc5-dec7-46e9-9c28-f6f9b18992c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643601012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1643601012
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1756529511
Short name T800
Test name
Test status
Simulation time 1404468553 ps
CPU time 12.78 seconds
Started Jun 09 01:11:24 PM PDT 24
Finished Jun 09 01:11:37 PM PDT 24
Peak memory 225364 kb
Host smart-7b887940-efa3-42f2-b541-7ce2f10f64cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756529511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1756529511
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1352475082
Short name T917
Test name
Test status
Simulation time 123234969 ps
CPU time 0.82 seconds
Started Jun 09 01:11:24 PM PDT 24
Finished Jun 09 01:11:25 PM PDT 24
Peak memory 207700 kb
Host smart-77ba85db-43c6-4c6f-bb9c-2cc408561286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352475082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1352475082
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.4216768312
Short name T548
Test name
Test status
Simulation time 6732250724 ps
CPU time 58.9 seconds
Started Jun 09 01:11:24 PM PDT 24
Finished Jun 09 01:12:23 PM PDT 24
Peak memory 252636 kb
Host smart-34e7cedb-6af6-4845-bb86-720fb733e490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216768312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.4216768312
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1113957214
Short name T546
Test name
Test status
Simulation time 7268858405 ps
CPU time 24.68 seconds
Started Jun 09 01:11:24 PM PDT 24
Finished Jun 09 01:11:49 PM PDT 24
Peak memory 218432 kb
Host smart-6cfdf419-b9d6-43db-a69c-2be0e71b71ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113957214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1113957214
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.36588383
Short name T675
Test name
Test status
Simulation time 3880256782 ps
CPU time 79.14 seconds
Started Jun 09 01:11:24 PM PDT 24
Finished Jun 09 01:12:44 PM PDT 24
Peak memory 250056 kb
Host smart-b574480a-6e7c-4ae7-afd6-a1a7c7cdb271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36588383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.36588383
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2332239420
Short name T439
Test name
Test status
Simulation time 1697011032 ps
CPU time 27.08 seconds
Started Jun 09 01:11:24 PM PDT 24
Finished Jun 09 01:11:51 PM PDT 24
Peak memory 241708 kb
Host smart-124dbbca-8f16-4104-b252-ca9f845a58ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332239420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2332239420
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.469278235
Short name T394
Test name
Test status
Simulation time 2824539913 ps
CPU time 10.83 seconds
Started Jun 09 01:11:23 PM PDT 24
Finished Jun 09 01:11:34 PM PDT 24
Peak memory 225412 kb
Host smart-e66715ca-9323-47b2-b1bc-c1233903740d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469278235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.469278235
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2957022003
Short name T272
Test name
Test status
Simulation time 138193764 ps
CPU time 3.81 seconds
Started Jun 09 01:11:22 PM PDT 24
Finished Jun 09 01:11:27 PM PDT 24
Peak memory 233524 kb
Host smart-683bfbeb-8505-4ca0-9dfb-a9c9cc6a1aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957022003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2957022003
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1993352287
Short name T157
Test name
Test status
Simulation time 2106594636 ps
CPU time 10.67 seconds
Started Jun 09 01:11:22 PM PDT 24
Finished Jun 09 01:11:33 PM PDT 24
Peak memory 241252 kb
Host smart-4dd6473e-449d-4a2e-b967-4610d8e2627b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993352287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1993352287
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2836716838
Short name T223
Test name
Test status
Simulation time 11724477112 ps
CPU time 31.46 seconds
Started Jun 09 01:11:22 PM PDT 24
Finished Jun 09 01:11:54 PM PDT 24
Peak memory 241820 kb
Host smart-02cc84d7-1e85-4286-8d5b-7f2d7d264470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836716838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2836716838
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.508339913
Short name T511
Test name
Test status
Simulation time 376731287 ps
CPU time 3.92 seconds
Started Jun 09 01:11:22 PM PDT 24
Finished Jun 09 01:11:27 PM PDT 24
Peak memory 219704 kb
Host smart-dea5cae2-8181-4257-b901-9c7a7e56499f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=508339913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.508339913
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3326956356
Short name T150
Test name
Test status
Simulation time 51595534545 ps
CPU time 478.25 seconds
Started Jun 09 01:11:25 PM PDT 24
Finished Jun 09 01:19:23 PM PDT 24
Peak memory 250476 kb
Host smart-4e93ab76-451b-4413-af4a-35e7c9177970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326956356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3326956356
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.4143096677
Short name T345
Test name
Test status
Simulation time 16090740140 ps
CPU time 27.1 seconds
Started Jun 09 01:11:25 PM PDT 24
Finished Jun 09 01:11:52 PM PDT 24
Peak memory 217264 kb
Host smart-8504f4c9-44d9-4856-ab19-5b2c2f35ef53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143096677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.4143096677
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.751352616
Short name T435
Test name
Test status
Simulation time 454761149 ps
CPU time 3.13 seconds
Started Jun 09 01:11:24 PM PDT 24
Finished Jun 09 01:11:28 PM PDT 24
Peak memory 217068 kb
Host smart-8bf0e9e4-42dd-4855-a247-bc6bf9dae301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751352616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.751352616
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.532905173
Short name T635
Test name
Test status
Simulation time 16240167 ps
CPU time 0.77 seconds
Started Jun 09 01:11:25 PM PDT 24
Finished Jun 09 01:11:26 PM PDT 24
Peak memory 206704 kb
Host smart-f4586390-7675-4d16-997d-f74e13f26b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532905173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.532905173
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.4175703776
Short name T360
Test name
Test status
Simulation time 25724238 ps
CPU time 0.72 seconds
Started Jun 09 01:11:22 PM PDT 24
Finished Jun 09 01:11:23 PM PDT 24
Peak memory 206892 kb
Host smart-bfba6bef-e013-4040-8a35-33553ca4ec43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175703776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.4175703776
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1362806971
Short name T462
Test name
Test status
Simulation time 20482990681 ps
CPU time 17.16 seconds
Started Jun 09 01:11:24 PM PDT 24
Finished Jun 09 01:11:42 PM PDT 24
Peak memory 233668 kb
Host smart-4b8774d2-1b14-4ea2-afaa-437a2f51e683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362806971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1362806971
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1939044481
Short name T840
Test name
Test status
Simulation time 34323223 ps
CPU time 0.67 seconds
Started Jun 09 01:11:28 PM PDT 24
Finished Jun 09 01:11:29 PM PDT 24
Peak memory 206192 kb
Host smart-5a7b4d2b-17e5-41a4-9d2f-10deb063127c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939044481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1939044481
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.810482108
Short name T786
Test name
Test status
Simulation time 184107435 ps
CPU time 2.91 seconds
Started Jun 09 01:11:30 PM PDT 24
Finished Jun 09 01:11:34 PM PDT 24
Peak memory 233548 kb
Host smart-e62f0c3f-eecd-411a-ac33-dee70e34dd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810482108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.810482108
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3684799326
Short name T488
Test name
Test status
Simulation time 24346218 ps
CPU time 0.8 seconds
Started Jun 09 01:11:25 PM PDT 24
Finished Jun 09 01:11:26 PM PDT 24
Peak memory 207396 kb
Host smart-e4b127d3-7390-476a-bdf8-3e464774561f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684799326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3684799326
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2569872764
Short name T710
Test name
Test status
Simulation time 6973883574 ps
CPU time 23.28 seconds
Started Jun 09 01:11:31 PM PDT 24
Finished Jun 09 01:11:55 PM PDT 24
Peak memory 241260 kb
Host smart-8a4f96fd-aa27-48e3-846d-ceeab152d34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569872764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2569872764
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2028337550
Short name T286
Test name
Test status
Simulation time 19779777591 ps
CPU time 76.33 seconds
Started Jun 09 01:11:31 PM PDT 24
Finished Jun 09 01:12:48 PM PDT 24
Peak memory 237780 kb
Host smart-a15f28f1-49cb-431a-a14e-83e587555067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028337550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2028337550
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1267594423
Short name T127
Test name
Test status
Simulation time 3669927246 ps
CPU time 23.73 seconds
Started Jun 09 01:11:26 PM PDT 24
Finished Jun 09 01:11:50 PM PDT 24
Peak memory 225468 kb
Host smart-5a150885-64fc-4912-a42e-b58e2d2f30d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267594423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1267594423
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_intercept.397680853
Short name T911
Test name
Test status
Simulation time 43409850 ps
CPU time 2.39 seconds
Started Jun 09 01:11:29 PM PDT 24
Finished Jun 09 01:11:31 PM PDT 24
Peak memory 233540 kb
Host smart-e4cb181f-42d4-48a4-ad41-71d9e0a13a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397680853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.397680853
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.997778360
Short name T87
Test name
Test status
Simulation time 2409531626 ps
CPU time 25.16 seconds
Started Jun 09 01:11:29 PM PDT 24
Finished Jun 09 01:11:54 PM PDT 24
Peak memory 225404 kb
Host smart-31572474-cf5d-4ca2-a9e0-b07937054d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997778360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.997778360
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.4010381520
Short name T10
Test name
Test status
Simulation time 19383409679 ps
CPU time 24.28 seconds
Started Jun 09 01:11:30 PM PDT 24
Finished Jun 09 01:11:54 PM PDT 24
Peak memory 225484 kb
Host smart-a950482e-e1be-4a65-89ee-2b5e8a5b55cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010381520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.4010381520
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2752625200
Short name T505
Test name
Test status
Simulation time 838915352 ps
CPU time 7.2 seconds
Started Jun 09 01:11:30 PM PDT 24
Finished Jun 09 01:11:38 PM PDT 24
Peak memory 233700 kb
Host smart-2201d3b6-2be7-44c4-8315-f97dc8be0810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752625200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2752625200
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.237600748
Short name T743
Test name
Test status
Simulation time 1083410017 ps
CPU time 7.96 seconds
Started Jun 09 01:11:29 PM PDT 24
Finished Jun 09 01:11:37 PM PDT 24
Peak memory 220152 kb
Host smart-683bb879-aa7a-4e72-8e9e-ca90670ee711
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=237600748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.237600748
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1319965636
Short name T608
Test name
Test status
Simulation time 7355542565 ps
CPU time 114.52 seconds
Started Jun 09 01:11:27 PM PDT 24
Finished Jun 09 01:13:22 PM PDT 24
Peak memory 254360 kb
Host smart-646b4abd-1b5e-4350-8a1f-e1442c56e83f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319965636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1319965636
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1731908775
Short name T341
Test name
Test status
Simulation time 840022270 ps
CPU time 2.99 seconds
Started Jun 09 01:11:24 PM PDT 24
Finished Jun 09 01:11:27 PM PDT 24
Peak memory 219428 kb
Host smart-6173360a-f17a-4338-84af-40c2094fc12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731908775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1731908775
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2008957387
Short name T909
Test name
Test status
Simulation time 2712757422 ps
CPU time 4.5 seconds
Started Jun 09 01:11:25 PM PDT 24
Finished Jun 09 01:11:30 PM PDT 24
Peak memory 217264 kb
Host smart-b8e2f6d4-89a5-4252-a877-e57794764e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008957387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2008957387
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3764734503
Short name T425
Test name
Test status
Simulation time 106093673 ps
CPU time 1.62 seconds
Started Jun 09 01:11:24 PM PDT 24
Finished Jun 09 01:11:26 PM PDT 24
Peak memory 216984 kb
Host smart-c746a841-b021-4502-b64a-46de46d18831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764734503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3764734503
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1032752821
Short name T358
Test name
Test status
Simulation time 57530829 ps
CPU time 0.92 seconds
Started Jun 09 01:11:22 PM PDT 24
Finished Jun 09 01:11:24 PM PDT 24
Peak memory 206676 kb
Host smart-45d4e9d5-27d8-44e0-88f0-8072f054e7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032752821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1032752821
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2405136791
Short name T124
Test name
Test status
Simulation time 499989980 ps
CPU time 2.56 seconds
Started Jun 09 01:11:29 PM PDT 24
Finished Jun 09 01:11:32 PM PDT 24
Peak memory 224596 kb
Host smart-7166262c-7e4f-4904-94be-e7fea38f44ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405136791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2405136791
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.711658687
Short name T400
Test name
Test status
Simulation time 108529362 ps
CPU time 0.69 seconds
Started Jun 09 01:11:34 PM PDT 24
Finished Jun 09 01:11:35 PM PDT 24
Peak memory 205704 kb
Host smart-c06d5f5d-cf5f-4270-a1c8-f5748b2790db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711658687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.711658687
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2023245501
Short name T253
Test name
Test status
Simulation time 322054494 ps
CPU time 4.04 seconds
Started Jun 09 01:11:35 PM PDT 24
Finished Jun 09 01:11:40 PM PDT 24
Peak memory 225300 kb
Host smart-792ddce5-092b-41a1-bd00-e415d8866a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023245501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2023245501
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1717856049
Short name T674
Test name
Test status
Simulation time 67212055 ps
CPU time 0.84 seconds
Started Jun 09 01:11:29 PM PDT 24
Finished Jun 09 01:11:30 PM PDT 24
Peak memory 207392 kb
Host smart-a1455906-9447-4a92-8f0c-1cff24a3c73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717856049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1717856049
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2665674132
Short name T731
Test name
Test status
Simulation time 22447612907 ps
CPU time 75.96 seconds
Started Jun 09 01:11:33 PM PDT 24
Finished Jun 09 01:12:50 PM PDT 24
Peak memory 254220 kb
Host smart-4ff69303-8b3e-49a8-b16b-bad07a86a723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665674132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2665674132
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3223569593
Short name T226
Test name
Test status
Simulation time 7491617271 ps
CPU time 81.72 seconds
Started Jun 09 01:11:34 PM PDT 24
Finished Jun 09 01:12:56 PM PDT 24
Peak memory 252332 kb
Host smart-d3f28831-28a0-4df7-84d1-e7b8c11d4817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223569593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3223569593
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3844396015
Short name T795
Test name
Test status
Simulation time 10711504113 ps
CPU time 53.08 seconds
Started Jun 09 01:11:34 PM PDT 24
Finished Jun 09 01:12:28 PM PDT 24
Peak memory 235348 kb
Host smart-1062f67b-1835-4fcd-860d-9f60a744fa8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844396015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3844396015
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1855086107
Short name T265
Test name
Test status
Simulation time 8756071158 ps
CPU time 22.22 seconds
Started Jun 09 01:11:26 PM PDT 24
Finished Jun 09 01:11:49 PM PDT 24
Peak memory 233604 kb
Host smart-bfe6f439-958e-4443-b0c2-4481bcd9683c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855086107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1855086107
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3754622682
Short name T708
Test name
Test status
Simulation time 4006573631 ps
CPU time 36.88 seconds
Started Jun 09 01:11:29 PM PDT 24
Finished Jun 09 01:12:06 PM PDT 24
Peak memory 225408 kb
Host smart-d55477d0-1a79-43e4-90cf-d5158cb87b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754622682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3754622682
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2896110363
Short name T33
Test name
Test status
Simulation time 3781563192 ps
CPU time 8.83 seconds
Started Jun 09 01:11:30 PM PDT 24
Finished Jun 09 01:11:39 PM PDT 24
Peak memory 225384 kb
Host smart-f7c1eb0a-9d2e-41b5-86e1-fff189d52f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896110363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2896110363
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1842347561
Short name T643
Test name
Test status
Simulation time 35761076 ps
CPU time 2.41 seconds
Started Jun 09 01:11:29 PM PDT 24
Finished Jun 09 01:11:31 PM PDT 24
Peak memory 233328 kb
Host smart-d8873b0f-4594-47e4-8a37-ad0cca095a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842347561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1842347561
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3185296527
Short name T791
Test name
Test status
Simulation time 296529204 ps
CPU time 4.4 seconds
Started Jun 09 01:11:35 PM PDT 24
Finished Jun 09 01:11:39 PM PDT 24
Peak memory 221012 kb
Host smart-52a3e6d4-1874-49f0-b1de-f51293362759
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3185296527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3185296527
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.4110973593
Short name T727
Test name
Test status
Simulation time 9833758670 ps
CPU time 70.27 seconds
Started Jun 09 01:11:34 PM PDT 24
Finished Jun 09 01:12:45 PM PDT 24
Peak memory 225528 kb
Host smart-a7ad7b54-8e11-490d-a339-b62f79cab8c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110973593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.4110973593
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3749123107
Short name T43
Test name
Test status
Simulation time 33708272613 ps
CPU time 47.68 seconds
Started Jun 09 01:11:29 PM PDT 24
Finished Jun 09 01:12:17 PM PDT 24
Peak memory 217232 kb
Host smart-4751c4f5-130b-42c4-98d3-0901e534f3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749123107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3749123107
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2146062622
Short name T455
Test name
Test status
Simulation time 33291604 ps
CPU time 0.75 seconds
Started Jun 09 01:11:29 PM PDT 24
Finished Jun 09 01:11:30 PM PDT 24
Peak memory 206516 kb
Host smart-96ec2a52-b9e3-4c28-bc40-4ce588805c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146062622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2146062622
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2635939444
Short name T494
Test name
Test status
Simulation time 120322854 ps
CPU time 2.41 seconds
Started Jun 09 01:11:26 PM PDT 24
Finished Jun 09 01:11:29 PM PDT 24
Peak memory 217116 kb
Host smart-08d615b7-d21b-4222-9ea6-2b39bfea71eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635939444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2635939444
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.540937953
Short name T368
Test name
Test status
Simulation time 264449355 ps
CPU time 0.88 seconds
Started Jun 09 01:11:29 PM PDT 24
Finished Jun 09 01:11:30 PM PDT 24
Peak memory 206944 kb
Host smart-d952b7f8-63f6-4ec0-b910-33fc32b453c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540937953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.540937953
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2273218846
Short name T913
Test name
Test status
Simulation time 12333099886 ps
CPU time 11.31 seconds
Started Jun 09 01:11:28 PM PDT 24
Finished Jun 09 01:11:40 PM PDT 24
Peak memory 225408 kb
Host smart-0c018b95-06e3-4d13-8481-bf22c81859e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273218846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2273218846
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3724006971
Short name T485
Test name
Test status
Simulation time 33187736 ps
CPU time 0.66 seconds
Started Jun 09 01:09:11 PM PDT 24
Finished Jun 09 01:09:12 PM PDT 24
Peak memory 205700 kb
Host smart-aaf2741d-af28-4a17-b41f-f54526cdc6f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724006971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
724006971
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1347566046
Short name T683
Test name
Test status
Simulation time 198388060 ps
CPU time 3.27 seconds
Started Jun 09 01:09:05 PM PDT 24
Finished Jun 09 01:09:08 PM PDT 24
Peak memory 233544 kb
Host smart-bf774a49-9a53-4ef3-bb52-db104f68c74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347566046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1347566046
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1588075949
Short name T4
Test name
Test status
Simulation time 22491637 ps
CPU time 0.8 seconds
Started Jun 09 01:09:01 PM PDT 24
Finished Jun 09 01:09:02 PM PDT 24
Peak memory 207392 kb
Host smart-75598074-1b22-41dc-ada9-740632224efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588075949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1588075949
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3969733803
Short name T478
Test name
Test status
Simulation time 306541871691 ps
CPU time 142.9 seconds
Started Jun 09 01:09:02 PM PDT 24
Finished Jun 09 01:11:25 PM PDT 24
Peak memory 254316 kb
Host smart-056db8b4-79ea-458c-a1b2-83908da5a98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969733803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3969733803
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.4250773093
Short name T232
Test name
Test status
Simulation time 2458254916 ps
CPU time 60.22 seconds
Started Jun 09 01:09:06 PM PDT 24
Finished Jun 09 01:10:06 PM PDT 24
Peak memory 255176 kb
Host smart-811e6997-d0de-446f-aaf1-f095f70d9b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250773093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.4250773093
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1041708465
Short name T140
Test name
Test status
Simulation time 745302634 ps
CPU time 7.27 seconds
Started Jun 09 01:09:03 PM PDT 24
Finished Jun 09 01:09:11 PM PDT 24
Peak memory 225348 kb
Host smart-61f52a8a-eccc-405f-b950-01b861b98193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041708465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1041708465
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3530945038
Short name T236
Test name
Test status
Simulation time 667118679 ps
CPU time 4.06 seconds
Started Jun 09 01:09:06 PM PDT 24
Finished Jun 09 01:09:11 PM PDT 24
Peak memory 225276 kb
Host smart-3547caba-3865-4c58-b0d0-3a6a0cc0d048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530945038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3530945038
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3886601328
Short name T88
Test name
Test status
Simulation time 9728563483 ps
CPU time 103.49 seconds
Started Jun 09 01:09:05 PM PDT 24
Finished Jun 09 01:10:48 PM PDT 24
Peak memory 236412 kb
Host smart-f5d382fb-f09c-40a2-ac66-3797b1898f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886601328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3886601328
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3831625228
Short name T879
Test name
Test status
Simulation time 64297622 ps
CPU time 3.13 seconds
Started Jun 09 01:08:59 PM PDT 24
Finished Jun 09 01:09:02 PM PDT 24
Peak memory 233548 kb
Host smart-ff0758e7-ff49-4b1c-8837-942963573c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831625228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3831625228
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1518039998
Short name T671
Test name
Test status
Simulation time 394757285 ps
CPU time 3.17 seconds
Started Jun 09 01:08:58 PM PDT 24
Finished Jun 09 01:09:02 PM PDT 24
Peak memory 225260 kb
Host smart-c50a48a8-2fb2-4075-ae74-c567b00ef687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518039998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1518039998
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.856800405
Short name T371
Test name
Test status
Simulation time 143748683 ps
CPU time 4.34 seconds
Started Jun 09 01:09:06 PM PDT 24
Finished Jun 09 01:09:10 PM PDT 24
Peak memory 223316 kb
Host smart-803732d4-6f76-4230-925c-5b899f621f06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=856800405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.856800405
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.4007969225
Short name T63
Test name
Test status
Simulation time 629866153 ps
CPU time 1.2 seconds
Started Jun 09 01:09:03 PM PDT 24
Finished Jun 09 01:09:05 PM PDT 24
Peak memory 235832 kb
Host smart-7aeff8c4-33d4-4369-82c2-97035719313f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007969225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.4007969225
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.4195654291
Short name T147
Test name
Test status
Simulation time 21705906737 ps
CPU time 107.31 seconds
Started Jun 09 01:09:05 PM PDT 24
Finished Jun 09 01:10:53 PM PDT 24
Peak memory 257556 kb
Host smart-99b3c7f0-b5e0-430f-98c5-95b25976aed0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195654291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.4195654291
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.458787090
Short name T335
Test name
Test status
Simulation time 2877734519 ps
CPU time 22.48 seconds
Started Jun 09 01:08:57 PM PDT 24
Finished Jun 09 01:09:20 PM PDT 24
Peak memory 217316 kb
Host smart-c5949de7-77b7-4d38-9149-d4e617406676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458787090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.458787090
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2189671604
Short name T780
Test name
Test status
Simulation time 11310273167 ps
CPU time 5.44 seconds
Started Jun 09 01:09:00 PM PDT 24
Finished Jun 09 01:09:06 PM PDT 24
Peak memory 217220 kb
Host smart-2e8970b0-41b1-448f-beea-0cfd610a2488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189671604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2189671604
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3103267523
Short name T822
Test name
Test status
Simulation time 86289220 ps
CPU time 1.46 seconds
Started Jun 09 01:09:04 PM PDT 24
Finished Jun 09 01:09:06 PM PDT 24
Peak memory 217108 kb
Host smart-abbe55ab-85ea-4560-9396-8233063fff9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103267523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3103267523
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3622677184
Short name T385
Test name
Test status
Simulation time 145699320 ps
CPU time 0.75 seconds
Started Jun 09 01:08:59 PM PDT 24
Finished Jun 09 01:09:00 PM PDT 24
Peak memory 206680 kb
Host smart-47df082a-1392-424b-8a3b-75fbc8a57cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622677184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3622677184
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1611583370
Short name T274
Test name
Test status
Simulation time 199848681 ps
CPU time 2.22 seconds
Started Jun 09 01:09:03 PM PDT 24
Finished Jun 09 01:09:06 PM PDT 24
Peak memory 225224 kb
Host smart-1864c15c-0f9a-464d-b962-16e4aa7e0ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611583370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1611583370
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1013072924
Short name T389
Test name
Test status
Simulation time 17244250 ps
CPU time 0.72 seconds
Started Jun 09 01:11:42 PM PDT 24
Finished Jun 09 01:11:43 PM PDT 24
Peak memory 206588 kb
Host smart-3607d273-6ccc-4d99-82a7-2bbe643d8baa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013072924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1013072924
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.327837862
Short name T694
Test name
Test status
Simulation time 33912435 ps
CPU time 2.13 seconds
Started Jun 09 01:11:36 PM PDT 24
Finished Jun 09 01:11:39 PM PDT 24
Peak memory 225344 kb
Host smart-b4e575c5-d89c-427d-a7cd-e8b8a2b3009a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327837862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.327837862
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.589898106
Short name T418
Test name
Test status
Simulation time 31442905 ps
CPU time 0.79 seconds
Started Jun 09 01:11:35 PM PDT 24
Finished Jun 09 01:11:36 PM PDT 24
Peak memory 207640 kb
Host smart-e875dc71-8e15-43dd-a69e-ece30c17754b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589898106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.589898106
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.92354386
Short name T245
Test name
Test status
Simulation time 5975107409 ps
CPU time 66.1 seconds
Started Jun 09 01:11:37 PM PDT 24
Finished Jun 09 01:12:44 PM PDT 24
Peak memory 257984 kb
Host smart-cead3a7f-4da3-4686-a524-c958f068cf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92354386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.92354386
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2120655629
Short name T383
Test name
Test status
Simulation time 30039646 ps
CPU time 0.82 seconds
Started Jun 09 01:11:38 PM PDT 24
Finished Jun 09 01:11:40 PM PDT 24
Peak memory 218020 kb
Host smart-0aa2c10d-374b-4c82-b0d9-74111b84216b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120655629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2120655629
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.590785200
Short name T402
Test name
Test status
Simulation time 18507922961 ps
CPU time 39.24 seconds
Started Jun 09 01:11:42 PM PDT 24
Finished Jun 09 01:12:22 PM PDT 24
Peak memory 225508 kb
Host smart-72cdb132-8f92-4146-b2bc-2924f4830a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590785200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.590785200
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.137641923
Short name T564
Test name
Test status
Simulation time 1511516676 ps
CPU time 11.96 seconds
Started Jun 09 01:11:35 PM PDT 24
Finished Jun 09 01:11:47 PM PDT 24
Peak memory 241756 kb
Host smart-5625d005-e0c9-40a7-abc3-ca9105b96f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137641923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.137641923
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.388819726
Short name T207
Test name
Test status
Simulation time 470393989 ps
CPU time 6.47 seconds
Started Jun 09 01:11:35 PM PDT 24
Finished Jun 09 01:11:42 PM PDT 24
Peak memory 220764 kb
Host smart-7a1e0807-9720-4438-b8ae-2d46aa34a9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388819726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.388819726
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.629631007
Short name T231
Test name
Test status
Simulation time 40313818844 ps
CPU time 108.11 seconds
Started Jun 09 01:11:34 PM PDT 24
Finished Jun 09 01:13:22 PM PDT 24
Peak memory 241568 kb
Host smart-f867f643-6f3a-4b61-9ff9-eee282cd42a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629631007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.629631007
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2824969780
Short name T660
Test name
Test status
Simulation time 765928306 ps
CPU time 2.81 seconds
Started Jun 09 01:11:38 PM PDT 24
Finished Jun 09 01:11:41 PM PDT 24
Peak memory 225344 kb
Host smart-5b62003c-a191-4d03-b771-4cdf97dacbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824969780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2824969780
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1631726471
Short name T590
Test name
Test status
Simulation time 31698517241 ps
CPU time 15.37 seconds
Started Jun 09 01:11:33 PM PDT 24
Finished Jun 09 01:11:49 PM PDT 24
Peak memory 228860 kb
Host smart-fa8ee881-f9af-4b01-85d0-21d88a5ca81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631726471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1631726471
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3662553935
Short name T741
Test name
Test status
Simulation time 331438042 ps
CPU time 5.91 seconds
Started Jun 09 01:11:39 PM PDT 24
Finished Jun 09 01:11:45 PM PDT 24
Peak memory 219512 kb
Host smart-a51bfc35-6aef-4a20-9ac4-745d4a0f23e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3662553935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3662553935
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2822581497
Short name T551
Test name
Test status
Simulation time 349036852 ps
CPU time 1.1 seconds
Started Jun 09 01:11:42 PM PDT 24
Finished Jun 09 01:11:44 PM PDT 24
Peak memory 207920 kb
Host smart-d1185095-429a-4084-ac8f-a9e55589dc9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822581497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2822581497
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1590251571
Short name T740
Test name
Test status
Simulation time 8256046764 ps
CPU time 25.73 seconds
Started Jun 09 01:11:34 PM PDT 24
Finished Jun 09 01:12:00 PM PDT 24
Peak memory 217636 kb
Host smart-f51451c3-042d-4200-8685-7546c803bbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590251571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1590251571
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2458911369
Short name T84
Test name
Test status
Simulation time 474259335 ps
CPU time 1.48 seconds
Started Jun 09 01:11:37 PM PDT 24
Finished Jun 09 01:11:39 PM PDT 24
Peak memory 208680 kb
Host smart-2ad41fa0-681a-420c-bd97-b88a6b5cf34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458911369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2458911369
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3559926284
Short name T814
Test name
Test status
Simulation time 87059817 ps
CPU time 1.05 seconds
Started Jun 09 01:11:33 PM PDT 24
Finished Jun 09 01:11:34 PM PDT 24
Peak memory 208752 kb
Host smart-da2b9422-fc3c-4be2-8ddd-3491362e4f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559926284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3559926284
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2505937302
Short name T701
Test name
Test status
Simulation time 87290136 ps
CPU time 0.75 seconds
Started Jun 09 01:11:33 PM PDT 24
Finished Jun 09 01:11:34 PM PDT 24
Peak memory 206684 kb
Host smart-4ebd473c-5a0e-40cb-9ee9-82daff11bffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505937302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2505937302
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2941332068
Short name T229
Test name
Test status
Simulation time 14928599587 ps
CPU time 16.42 seconds
Started Jun 09 01:11:37 PM PDT 24
Finished Jun 09 01:11:54 PM PDT 24
Peak memory 229548 kb
Host smart-3338316d-39fd-406f-9652-6e8ee3130fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941332068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2941332068
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2325089370
Short name T473
Test name
Test status
Simulation time 37459612 ps
CPU time 0.68 seconds
Started Jun 09 01:11:40 PM PDT 24
Finished Jun 09 01:11:42 PM PDT 24
Peak memory 205684 kb
Host smart-a4d4a11f-399b-4185-b03f-abab3244d7be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325089370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2325089370
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.657702939
Short name T132
Test name
Test status
Simulation time 84628165 ps
CPU time 3.05 seconds
Started Jun 09 01:11:38 PM PDT 24
Finished Jun 09 01:11:41 PM PDT 24
Peak memory 233516 kb
Host smart-89db5f6c-093b-45dc-97c2-2d5e480d5042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657702939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.657702939
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2672027581
Short name T705
Test name
Test status
Simulation time 58127159 ps
CPU time 0.76 seconds
Started Jun 09 01:11:42 PM PDT 24
Finished Jun 09 01:11:44 PM PDT 24
Peak memory 207368 kb
Host smart-20f7b65c-9e72-4324-91d0-0199802ad608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672027581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2672027581
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2559995945
Short name T498
Test name
Test status
Simulation time 49728749093 ps
CPU time 87.24 seconds
Started Jun 09 01:11:38 PM PDT 24
Finished Jun 09 01:13:25 PM PDT 24
Peak memory 256960 kb
Host smart-5f656dd7-4321-4a0d-9e3e-d27505a19f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559995945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2559995945
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1665772872
Short name T604
Test name
Test status
Simulation time 10016000217 ps
CPU time 107.14 seconds
Started Jun 09 01:11:41 PM PDT 24
Finished Jun 09 01:13:28 PM PDT 24
Peak memory 250108 kb
Host smart-eb00ee5b-fc59-4c4c-88f3-df940ec5b21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665772872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1665772872
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3190212901
Short name T34
Test name
Test status
Simulation time 323070137 ps
CPU time 6.89 seconds
Started Jun 09 01:11:39 PM PDT 24
Finished Jun 09 01:11:46 PM PDT 24
Peak memory 241728 kb
Host smart-154c83ad-b756-4f51-9d8e-e50734416bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190212901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3190212901
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2280880039
Short name T224
Test name
Test status
Simulation time 1874038677 ps
CPU time 17.67 seconds
Started Jun 09 01:11:39 PM PDT 24
Finished Jun 09 01:11:57 PM PDT 24
Peak memory 225288 kb
Host smart-a156f919-8c8c-4c0d-92f3-8f3f4a19c517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280880039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2280880039
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.141461695
Short name T37
Test name
Test status
Simulation time 2722976660 ps
CPU time 26.88 seconds
Started Jun 09 01:11:45 PM PDT 24
Finished Jun 09 01:12:12 PM PDT 24
Peak memory 233672 kb
Host smart-90107b4e-9e91-4179-92ec-a007339bd74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141461695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.141461695
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1111073526
Short name T169
Test name
Test status
Simulation time 473275902 ps
CPU time 4.64 seconds
Started Jun 09 01:11:42 PM PDT 24
Finished Jun 09 01:11:47 PM PDT 24
Peak memory 233520 kb
Host smart-07b8197d-cc7e-4459-b655-c7c0c9b0180d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111073526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1111073526
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.220205090
Short name T709
Test name
Test status
Simulation time 1378580638 ps
CPU time 8.7 seconds
Started Jun 09 01:11:38 PM PDT 24
Finished Jun 09 01:11:47 PM PDT 24
Peak memory 233564 kb
Host smart-34ffde50-0eb0-49e9-9c27-7e584eba7216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220205090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.220205090
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3507989519
Short name T809
Test name
Test status
Simulation time 166533341 ps
CPU time 4.8 seconds
Started Jun 09 01:11:45 PM PDT 24
Finished Jun 09 01:11:50 PM PDT 24
Peak memory 223448 kb
Host smart-cb45e268-36ee-464b-92bb-d629a26cdcfa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3507989519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3507989519
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1060498127
Short name T910
Test name
Test status
Simulation time 76001129 ps
CPU time 1.26 seconds
Started Jun 09 01:11:43 PM PDT 24
Finished Jun 09 01:11:44 PM PDT 24
Peak memory 208624 kb
Host smart-b414b01a-68ef-4a08-ac38-d628c15af6e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060498127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1060498127
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.42693338
Short name T883
Test name
Test status
Simulation time 12769455986 ps
CPU time 28.84 seconds
Started Jun 09 01:11:45 PM PDT 24
Finished Jun 09 01:12:14 PM PDT 24
Peak memory 217076 kb
Host smart-6567bf41-4242-4add-8a09-ee0f83ec6990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42693338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.42693338
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2280400082
Short name T849
Test name
Test status
Simulation time 7295136722 ps
CPU time 3.41 seconds
Started Jun 09 01:11:45 PM PDT 24
Finished Jun 09 01:11:48 PM PDT 24
Peak memory 216864 kb
Host smart-7017f537-9b17-4f83-a50a-5d90053fb9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280400082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2280400082
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1391977697
Short name T632
Test name
Test status
Simulation time 318498713 ps
CPU time 1.44 seconds
Started Jun 09 01:11:41 PM PDT 24
Finished Jun 09 01:11:43 PM PDT 24
Peak memory 217096 kb
Host smart-5b7bf6e9-a892-4bd3-96ba-2266c313a000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391977697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1391977697
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.671910794
Short name T739
Test name
Test status
Simulation time 115776417 ps
CPU time 0.84 seconds
Started Jun 09 01:11:37 PM PDT 24
Finished Jun 09 01:11:39 PM PDT 24
Peak memory 206676 kb
Host smart-9d5aa4e3-659f-4ab0-8a44-7f71fa8c0934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671910794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.671910794
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1524825251
Short name T767
Test name
Test status
Simulation time 2908337911 ps
CPU time 8.22 seconds
Started Jun 09 01:11:39 PM PDT 24
Finished Jun 09 01:11:47 PM PDT 24
Peak memory 233632 kb
Host smart-7f1d8e00-f41b-4072-8cbd-69bd0185ae12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524825251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1524825251
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.752464497
Short name T593
Test name
Test status
Simulation time 12908759 ps
CPU time 0.71 seconds
Started Jun 09 01:11:43 PM PDT 24
Finished Jun 09 01:11:44 PM PDT 24
Peak memory 205704 kb
Host smart-40270fa4-a5c0-4269-9a59-41742ddbf432
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752464497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.752464497
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1972528567
Short name T699
Test name
Test status
Simulation time 289024403 ps
CPU time 6.33 seconds
Started Jun 09 01:11:49 PM PDT 24
Finished Jun 09 01:11:55 PM PDT 24
Peak memory 233500 kb
Host smart-5786dda7-3fbc-4a19-bd0e-4eed915d6139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972528567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1972528567
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3631072467
Short name T672
Test name
Test status
Simulation time 32618652 ps
CPU time 0.78 seconds
Started Jun 09 01:11:43 PM PDT 24
Finished Jun 09 01:11:45 PM PDT 24
Peak memory 206316 kb
Host smart-8a7cd209-7abe-4eea-afa7-2ee26cea773c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631072467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3631072467
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2917027095
Short name T526
Test name
Test status
Simulation time 1209474250 ps
CPU time 12.84 seconds
Started Jun 09 01:11:44 PM PDT 24
Finished Jun 09 01:11:57 PM PDT 24
Peak memory 239452 kb
Host smart-5f00ea28-0327-4b21-8e31-9bc20d3ad71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917027095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2917027095
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2306801274
Short name T220
Test name
Test status
Simulation time 300396067839 ps
CPU time 162.44 seconds
Started Jun 09 01:11:42 PM PDT 24
Finished Jun 09 01:14:25 PM PDT 24
Peak memory 250532 kb
Host smart-5f8634d9-4c8a-46a3-8603-7e7000fc52fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306801274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2306801274
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3274430993
Short name T929
Test name
Test status
Simulation time 222582931 ps
CPU time 12.19 seconds
Started Jun 09 01:11:45 PM PDT 24
Finished Jun 09 01:11:58 PM PDT 24
Peak memory 233716 kb
Host smart-d38c6f81-cfcf-498c-8535-45fe1a58264a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274430993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3274430993
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.538521820
Short name T880
Test name
Test status
Simulation time 2755630485 ps
CPU time 7.36 seconds
Started Jun 09 01:11:44 PM PDT 24
Finished Jun 09 01:11:52 PM PDT 24
Peak memory 225420 kb
Host smart-8f1ea22b-2326-4126-8ad2-54de4a8294d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538521820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.538521820
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.456448260
Short name T779
Test name
Test status
Simulation time 847019104 ps
CPU time 11.12 seconds
Started Jun 09 01:11:42 PM PDT 24
Finished Jun 09 01:11:54 PM PDT 24
Peak memory 241640 kb
Host smart-e09b680d-e7d9-4943-a3cb-864070e8d230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456448260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.456448260
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.552121765
Short name T870
Test name
Test status
Simulation time 7153523843 ps
CPU time 12.17 seconds
Started Jun 09 01:11:44 PM PDT 24
Finished Jun 09 01:11:56 PM PDT 24
Peak memory 225360 kb
Host smart-372a5b1a-2f9c-4abe-946e-fad55d51257c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552121765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.552121765
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3202241228
Short name T802
Test name
Test status
Simulation time 3455744913 ps
CPU time 12.65 seconds
Started Jun 09 01:11:43 PM PDT 24
Finished Jun 09 01:11:56 PM PDT 24
Peak memory 233692 kb
Host smart-b0901bde-850d-41d9-aa9b-78627e7a2ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202241228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3202241228
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.777409394
Short name T136
Test name
Test status
Simulation time 1788013483 ps
CPU time 8.34 seconds
Started Jun 09 01:11:45 PM PDT 24
Finished Jun 09 01:11:54 PM PDT 24
Peak memory 223912 kb
Host smart-ea9f7077-5632-402d-b355-42f3f56980d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=777409394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.777409394
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3418138558
Short name T404
Test name
Test status
Simulation time 10153708253 ps
CPU time 53.51 seconds
Started Jun 09 01:11:46 PM PDT 24
Finished Jun 09 01:12:40 PM PDT 24
Peak memory 234812 kb
Host smart-73311456-e276-441b-96ec-fb4f8b899043
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418138558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3418138558
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2678002560
Short name T333
Test name
Test status
Simulation time 380142350 ps
CPU time 4.87 seconds
Started Jun 09 01:11:45 PM PDT 24
Finished Jun 09 01:11:51 PM PDT 24
Peak memory 217192 kb
Host smart-c2068a8f-ccf8-4e87-8245-efd4ee427e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678002560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2678002560
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.184829618
Short name T415
Test name
Test status
Simulation time 13969591 ps
CPU time 0.72 seconds
Started Jun 09 01:11:43 PM PDT 24
Finished Jun 09 01:11:44 PM PDT 24
Peak memory 206468 kb
Host smart-9271b07e-f5ce-4e0e-9627-81d513c921f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184829618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.184829618
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.4082524905
Short name T510
Test name
Test status
Simulation time 304777977 ps
CPU time 1.43 seconds
Started Jun 09 01:11:48 PM PDT 24
Finished Jun 09 01:11:50 PM PDT 24
Peak memory 217036 kb
Host smart-abb575b6-fa97-442e-8f0d-af49d73c98d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082524905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.4082524905
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3532267100
Short name T427
Test name
Test status
Simulation time 48645686 ps
CPU time 0.73 seconds
Started Jun 09 01:11:45 PM PDT 24
Finished Jun 09 01:11:46 PM PDT 24
Peak memory 206680 kb
Host smart-cb6bf4f6-91d7-46fe-bc74-8b9930c5fce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532267100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3532267100
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2332423576
Short name T296
Test name
Test status
Simulation time 78465854 ps
CPU time 2.86 seconds
Started Jun 09 01:11:43 PM PDT 24
Finished Jun 09 01:11:46 PM PDT 24
Peak memory 237436 kb
Host smart-bfcbedc8-0710-449e-9082-2fdabb7b77e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332423576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2332423576
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.980986640
Short name T696
Test name
Test status
Simulation time 29028139 ps
CPU time 0.71 seconds
Started Jun 09 01:11:48 PM PDT 24
Finished Jun 09 01:11:49 PM PDT 24
Peak memory 205680 kb
Host smart-ffb4c419-c88b-4d6b-a92d-98b2375f1845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980986640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.980986640
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2778992374
Short name T248
Test name
Test status
Simulation time 186949447 ps
CPU time 3.82 seconds
Started Jun 09 01:11:49 PM PDT 24
Finished Jun 09 01:11:53 PM PDT 24
Peak memory 233500 kb
Host smart-583fb441-880f-4e0b-86c0-d39e6fc475ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778992374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2778992374
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.4205085053
Short name T442
Test name
Test status
Simulation time 39405231 ps
CPU time 0.78 seconds
Started Jun 09 01:11:45 PM PDT 24
Finished Jun 09 01:11:46 PM PDT 24
Peak memory 207868 kb
Host smart-6f3f9ea5-67a1-424a-a29a-4f5c589f5310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205085053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.4205085053
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3160416744
Short name T721
Test name
Test status
Simulation time 17186353138 ps
CPU time 158.62 seconds
Started Jun 09 01:11:48 PM PDT 24
Finished Jun 09 01:14:27 PM PDT 24
Peak memory 250112 kb
Host smart-e11700bf-565f-4625-935a-e2c4ba503151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160416744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3160416744
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.365356720
Short name T668
Test name
Test status
Simulation time 4759310706 ps
CPU time 54.05 seconds
Started Jun 09 01:11:51 PM PDT 24
Finished Jun 09 01:12:46 PM PDT 24
Peak memory 240720 kb
Host smart-1da5647a-17e0-4579-8e51-3f7990b7097a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365356720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.365356720
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2099904945
Short name T50
Test name
Test status
Simulation time 2494173240 ps
CPU time 9.7 seconds
Started Jun 09 01:11:49 PM PDT 24
Finished Jun 09 01:11:59 PM PDT 24
Peak memory 250036 kb
Host smart-e6ea8572-34a1-4b39-94a0-5f9f6b1354d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099904945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2099904945
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1346147122
Short name T555
Test name
Test status
Simulation time 906683268 ps
CPU time 6.29 seconds
Started Jun 09 01:11:44 PM PDT 24
Finished Jun 09 01:11:51 PM PDT 24
Peak memory 233536 kb
Host smart-c2d7d5c3-0f5e-4ba7-909d-37d4aed0e605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346147122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1346147122
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3995292858
Short name T504
Test name
Test status
Simulation time 475630281 ps
CPU time 12.39 seconds
Started Jun 09 01:11:46 PM PDT 24
Finished Jun 09 01:11:58 PM PDT 24
Peak memory 233492 kb
Host smart-840644fc-8e66-4303-abac-549b7b46260a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995292858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3995292858
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2790203753
Short name T534
Test name
Test status
Simulation time 372428608 ps
CPU time 2.21 seconds
Started Jun 09 01:11:44 PM PDT 24
Finished Jun 09 01:11:47 PM PDT 24
Peak memory 223872 kb
Host smart-3ba8fe2d-9e35-4be8-80c3-08d8af6bf4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790203753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2790203753
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2204366971
Short name T162
Test name
Test status
Simulation time 568109018 ps
CPU time 3.65 seconds
Started Jun 09 01:11:46 PM PDT 24
Finished Jun 09 01:11:50 PM PDT 24
Peak memory 225264 kb
Host smart-e152521c-dba4-4ba1-8962-48de71b77869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204366971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2204366971
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3691146822
Short name T730
Test name
Test status
Simulation time 1476680376 ps
CPU time 6.25 seconds
Started Jun 09 01:11:52 PM PDT 24
Finished Jun 09 01:11:58 PM PDT 24
Peak memory 220928 kb
Host smart-47e80fef-0e0f-40ca-b953-50533292aa77
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3691146822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3691146822
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2764152196
Short name T928
Test name
Test status
Simulation time 49163962343 ps
CPU time 208.81 seconds
Started Jun 09 01:11:50 PM PDT 24
Finished Jun 09 01:15:19 PM PDT 24
Peak memory 266508 kb
Host smart-d014cce3-7dbc-46e1-b79a-87862835c725
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764152196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2764152196
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3195604145
Short name T958
Test name
Test status
Simulation time 3073727478 ps
CPU time 28.17 seconds
Started Jun 09 01:11:44 PM PDT 24
Finished Jun 09 01:12:13 PM PDT 24
Peak memory 221300 kb
Host smart-b305e24e-d991-4a2e-b24f-fe189ade7331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195604145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3195604145
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.694990254
Short name T420
Test name
Test status
Simulation time 769662699 ps
CPU time 5.52 seconds
Started Jun 09 01:11:45 PM PDT 24
Finished Jun 09 01:11:51 PM PDT 24
Peak memory 217096 kb
Host smart-bf6ad2ae-a7c2-473b-a1d8-39fc4f0257ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694990254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.694990254
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1932586450
Short name T688
Test name
Test status
Simulation time 119860090 ps
CPU time 1.25 seconds
Started Jun 09 01:11:43 PM PDT 24
Finished Jun 09 01:11:45 PM PDT 24
Peak memory 217100 kb
Host smart-2bd87f49-0bd1-4c6b-9a8a-56659502d240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932586450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1932586450
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3309200944
Short name T36
Test name
Test status
Simulation time 196576788 ps
CPU time 0.95 seconds
Started Jun 09 01:11:43 PM PDT 24
Finished Jun 09 01:11:45 PM PDT 24
Peak memory 206728 kb
Host smart-afe6b8d5-dadc-4228-8bf9-ac0f86379d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309200944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3309200944
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.965705118
Short name T889
Test name
Test status
Simulation time 6616063219 ps
CPU time 22.67 seconds
Started Jun 09 01:11:50 PM PDT 24
Finished Jun 09 01:12:13 PM PDT 24
Peak memory 233672 kb
Host smart-193c1910-193c-4e59-a2a9-bcab20821195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965705118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.965705118
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3691877032
Short name T47
Test name
Test status
Simulation time 13955396 ps
CPU time 0.74 seconds
Started Jun 09 01:11:54 PM PDT 24
Finished Jun 09 01:11:55 PM PDT 24
Peak memory 205824 kb
Host smart-c79f88b0-a41d-4768-8637-4e3f581ca066
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691877032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3691877032
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2362700403
Short name T829
Test name
Test status
Simulation time 3984076228 ps
CPU time 10.59 seconds
Started Jun 09 01:11:49 PM PDT 24
Finished Jun 09 01:11:59 PM PDT 24
Peak memory 225452 kb
Host smart-a61dce23-8e43-481c-9479-04f5e0e61bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362700403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2362700403
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1253881999
Short name T486
Test name
Test status
Simulation time 19821365 ps
CPU time 0.79 seconds
Started Jun 09 01:11:50 PM PDT 24
Finished Jun 09 01:11:51 PM PDT 24
Peak memory 207868 kb
Host smart-cf7e4d9f-1b9e-4484-937a-50a79763ca7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253881999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1253881999
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.137126604
Short name T170
Test name
Test status
Simulation time 5207916991 ps
CPU time 70.11 seconds
Started Jun 09 01:11:52 PM PDT 24
Finished Jun 09 01:13:02 PM PDT 24
Peak memory 254072 kb
Host smart-9e0724a4-8155-445c-98f1-8f17efad2c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137126604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.137126604
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1977785518
Short name T85
Test name
Test status
Simulation time 4002820303 ps
CPU time 64.16 seconds
Started Jun 09 01:11:57 PM PDT 24
Finished Jun 09 01:13:02 PM PDT 24
Peak memory 250304 kb
Host smart-b2e6fecb-6659-4610-bfaf-15f1a723666b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977785518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1977785518
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3195013514
Short name T556
Test name
Test status
Simulation time 5596929797 ps
CPU time 57.06 seconds
Started Jun 09 01:11:57 PM PDT 24
Finished Jun 09 01:12:54 PM PDT 24
Peak memory 241848 kb
Host smart-5397437d-c40c-44a4-bd68-0fa050254101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195013514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3195013514
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3946497185
Short name T447
Test name
Test status
Simulation time 367720380 ps
CPU time 3.07 seconds
Started Jun 09 01:11:49 PM PDT 24
Finished Jun 09 01:11:52 PM PDT 24
Peak memory 233456 kb
Host smart-18b6a908-17d7-4a77-906a-5571db3ca590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946497185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3946497185
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3070587761
Short name T289
Test name
Test status
Simulation time 1875262779 ps
CPU time 3.63 seconds
Started Jun 09 01:11:49 PM PDT 24
Finished Jun 09 01:11:53 PM PDT 24
Peak memory 225260 kb
Host smart-b5690d1d-1156-4541-ae6b-3861e0a1aac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070587761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3070587761
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1499844696
Short name T53
Test name
Test status
Simulation time 2223953467 ps
CPU time 15.02 seconds
Started Jun 09 01:11:51 PM PDT 24
Finished Jun 09 01:12:06 PM PDT 24
Peak memory 250064 kb
Host smart-11885cd7-3c2f-4fdd-8cc1-b24ee09dd1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499844696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1499844696
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.577934593
Short name T13
Test name
Test status
Simulation time 3224758228 ps
CPU time 13.02 seconds
Started Jun 09 01:11:49 PM PDT 24
Finished Jun 09 01:12:02 PM PDT 24
Peak memory 241708 kb
Host smart-e5a9e2ef-ea6c-4e7c-9eac-d39c4058c22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577934593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.577934593
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3291440451
Short name T252
Test name
Test status
Simulation time 11562848906 ps
CPU time 6.33 seconds
Started Jun 09 01:11:49 PM PDT 24
Finished Jun 09 01:11:55 PM PDT 24
Peak memory 225436 kb
Host smart-8a94cad5-0450-4cac-8ace-03aed083c362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291440451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3291440451
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.204127129
Short name T410
Test name
Test status
Simulation time 2425982840 ps
CPU time 13.95 seconds
Started Jun 09 01:11:51 PM PDT 24
Finished Jun 09 01:12:05 PM PDT 24
Peak memory 220056 kb
Host smart-20db1705-0658-498e-aa26-36bb8a1b78e5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=204127129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.204127129
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1307511776
Short name T728
Test name
Test status
Simulation time 37974225499 ps
CPU time 94.37 seconds
Started Jun 09 01:11:56 PM PDT 24
Finished Jun 09 01:13:30 PM PDT 24
Peak memory 250144 kb
Host smart-91a1cd68-5269-47c5-9b42-0fb7443f5ebb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307511776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1307511776
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.750177584
Short name T815
Test name
Test status
Simulation time 2116858657 ps
CPU time 20.75 seconds
Started Jun 09 01:11:49 PM PDT 24
Finished Jun 09 01:12:10 PM PDT 24
Peak memory 217364 kb
Host smart-9ac7b516-cf60-4cff-a5b0-28af350ffa36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750177584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.750177584
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.672154347
Short name T495
Test name
Test status
Simulation time 32558246769 ps
CPU time 15.48 seconds
Started Jun 09 01:11:51 PM PDT 24
Finished Jun 09 01:12:07 PM PDT 24
Peak memory 217304 kb
Host smart-b317afda-dde6-4f73-9426-3d3a1e3fd131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672154347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.672154347
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1535330524
Short name T720
Test name
Test status
Simulation time 113397858 ps
CPU time 1.15 seconds
Started Jun 09 01:11:50 PM PDT 24
Finished Jun 09 01:11:51 PM PDT 24
Peak memory 208712 kb
Host smart-19ef579e-9c4f-407e-b8ed-3eb3b2632d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535330524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1535330524
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1405838438
Short name T647
Test name
Test status
Simulation time 56319618 ps
CPU time 0.9 seconds
Started Jun 09 01:11:49 PM PDT 24
Finished Jun 09 01:11:51 PM PDT 24
Peak memory 206684 kb
Host smart-eb69fa53-3000-4a3b-8b44-de76be81c413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405838438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1405838438
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.6508728
Short name T267
Test name
Test status
Simulation time 1228971646 ps
CPU time 5.97 seconds
Started Jun 09 01:11:49 PM PDT 24
Finished Jun 09 01:11:55 PM PDT 24
Peak memory 225288 kb
Host smart-57089cf5-8cf7-455f-879d-cf9735c0f726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6508728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.6508728
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2797368191
Short name T129
Test name
Test status
Simulation time 16136432 ps
CPU time 0.76 seconds
Started Jun 09 01:12:00 PM PDT 24
Finished Jun 09 01:12:01 PM PDT 24
Peak memory 205680 kb
Host smart-8c9aee52-b51f-4289-8ddf-3c9b7f467f80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797368191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2797368191
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3852030385
Short name T487
Test name
Test status
Simulation time 172753674 ps
CPU time 2.74 seconds
Started Jun 09 01:11:57 PM PDT 24
Finished Jun 09 01:12:00 PM PDT 24
Peak memory 233504 kb
Host smart-32f8a1ec-99cf-4242-8f3c-38fed8272426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852030385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3852030385
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.427277498
Short name T695
Test name
Test status
Simulation time 62145280 ps
CPU time 0.74 seconds
Started Jun 09 01:11:57 PM PDT 24
Finished Jun 09 01:11:59 PM PDT 24
Peak memory 207720 kb
Host smart-fb386799-9505-4896-85eb-699da8816840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427277498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.427277498
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3148730390
Short name T78
Test name
Test status
Simulation time 24487134812 ps
CPU time 191.3 seconds
Started Jun 09 01:12:00 PM PDT 24
Finished Jun 09 01:15:12 PM PDT 24
Peak memory 250048 kb
Host smart-e862eb50-bbb1-4b7a-afd3-73985a1959e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148730390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3148730390
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3630707839
Short name T171
Test name
Test status
Simulation time 54768858458 ps
CPU time 206.81 seconds
Started Jun 09 01:11:59 PM PDT 24
Finished Jun 09 01:15:26 PM PDT 24
Peak memory 250284 kb
Host smart-88181467-1239-44bf-92f7-ea391e5d8317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630707839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3630707839
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3709751724
Short name T596
Test name
Test status
Simulation time 10259558307 ps
CPU time 27.62 seconds
Started Jun 09 01:11:56 PM PDT 24
Finished Jun 09 01:12:24 PM PDT 24
Peak memory 252404 kb
Host smart-3602dc74-2f62-4780-b1e8-5310ee2a5dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709751724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3709751724
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2803901276
Short name T363
Test name
Test status
Simulation time 65849530 ps
CPU time 2.65 seconds
Started Jun 09 01:11:58 PM PDT 24
Finished Jun 09 01:12:01 PM PDT 24
Peak memory 233352 kb
Host smart-bdfb20ea-5b4c-41e9-948e-7b088cb2d1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803901276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2803901276
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2438100714
Short name T452
Test name
Test status
Simulation time 27864719549 ps
CPU time 19.19 seconds
Started Jun 09 01:11:57 PM PDT 24
Finished Jun 09 01:12:16 PM PDT 24
Peak memory 241776 kb
Host smart-8e0e2346-0741-4e2e-b201-fb971a9798f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438100714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2438100714
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1127519262
Short name T569
Test name
Test status
Simulation time 1830839406 ps
CPU time 5.32 seconds
Started Jun 09 01:11:56 PM PDT 24
Finished Jun 09 01:12:02 PM PDT 24
Peak memory 233564 kb
Host smart-a427ff9c-0397-45c4-b3e0-36bc0c1c01e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127519262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1127519262
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.252270857
Short name T631
Test name
Test status
Simulation time 555326813 ps
CPU time 3.8 seconds
Started Jun 09 01:11:56 PM PDT 24
Finished Jun 09 01:12:00 PM PDT 24
Peak memory 225284 kb
Host smart-53963615-a0be-467b-9527-a92c1c3ca1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252270857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.252270857
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.760908067
Short name T138
Test name
Test status
Simulation time 742394296 ps
CPU time 8.72 seconds
Started Jun 09 01:11:56 PM PDT 24
Finished Jun 09 01:12:05 PM PDT 24
Peak memory 223968 kb
Host smart-4e89fc66-b193-45c6-bf7c-bd6cf12eee41
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=760908067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.760908067
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1187456634
Short name T337
Test name
Test status
Simulation time 2971446122 ps
CPU time 17.16 seconds
Started Jun 09 01:11:56 PM PDT 24
Finished Jun 09 01:12:14 PM PDT 24
Peak memory 217408 kb
Host smart-086a39af-dabf-4b62-8438-be81c0a19bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187456634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1187456634
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.4150256550
Short name T426
Test name
Test status
Simulation time 2435041495 ps
CPU time 3.92 seconds
Started Jun 09 01:11:57 PM PDT 24
Finished Jun 09 01:12:01 PM PDT 24
Peak memory 217200 kb
Host smart-f5133096-3255-461f-9e75-457f9d514741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150256550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.4150256550
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.550630773
Short name T399
Test name
Test status
Simulation time 36608708 ps
CPU time 0.97 seconds
Started Jun 09 01:11:55 PM PDT 24
Finished Jun 09 01:11:56 PM PDT 24
Peak memory 208356 kb
Host smart-24d9f38e-bbf6-48ad-8e60-2dc81166a7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550630773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.550630773
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1714422501
Short name T821
Test name
Test status
Simulation time 40758824 ps
CPU time 0.79 seconds
Started Jun 09 01:11:56 PM PDT 24
Finished Jun 09 01:11:57 PM PDT 24
Peak memory 206696 kb
Host smart-21ae6bde-ec92-4da9-9345-78d5ad0779ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714422501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1714422501
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3222782477
Short name T261
Test name
Test status
Simulation time 582964886 ps
CPU time 3.72 seconds
Started Jun 09 01:11:55 PM PDT 24
Finished Jun 09 01:11:59 PM PDT 24
Peak memory 225324 kb
Host smart-a6719973-fe5b-459d-806b-130440d15268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222782477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3222782477
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3292235072
Short name T644
Test name
Test status
Simulation time 32525261 ps
CPU time 0.73 seconds
Started Jun 09 01:12:09 PM PDT 24
Finished Jun 09 01:12:10 PM PDT 24
Peak memory 206604 kb
Host smart-a2e362e5-c175-4729-9372-55bb1b06ac55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292235072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3292235072
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2724848965
Short name T397
Test name
Test status
Simulation time 863507999 ps
CPU time 2.03 seconds
Started Jun 09 01:12:00 PM PDT 24
Finished Jun 09 01:12:02 PM PDT 24
Peak memory 225336 kb
Host smart-014fc1dc-b35f-4f65-84ad-4fc41062ba39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724848965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2724848965
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1111847651
Short name T500
Test name
Test status
Simulation time 19072391 ps
CPU time 0.78 seconds
Started Jun 09 01:12:00 PM PDT 24
Finished Jun 09 01:12:01 PM PDT 24
Peak memory 206576 kb
Host smart-f24ca6ce-f14c-4419-9e3a-ce3dddef2bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111847651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1111847651
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3962426559
Short name T201
Test name
Test status
Simulation time 9792838562 ps
CPU time 34.49 seconds
Started Jun 09 01:12:10 PM PDT 24
Finished Jun 09 01:12:44 PM PDT 24
Peak memory 225468 kb
Host smart-c828f718-f5d5-44af-a733-f7fde35f6221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962426559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3962426559
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3246034493
Short name T233
Test name
Test status
Simulation time 45554117108 ps
CPU time 182.6 seconds
Started Jun 09 01:12:08 PM PDT 24
Finished Jun 09 01:15:11 PM PDT 24
Peak memory 251412 kb
Host smart-ee981378-b14b-49a2-a433-32926ac9ee47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246034493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3246034493
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.198762842
Short name T806
Test name
Test status
Simulation time 7390917989 ps
CPU time 40.21 seconds
Started Jun 09 01:12:05 PM PDT 24
Finished Jun 09 01:12:46 PM PDT 24
Peak memory 250120 kb
Host smart-f19b3255-e068-43b5-864a-7bdb65598612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198762842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.198762842
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2456938680
Short name T443
Test name
Test status
Simulation time 759303142 ps
CPU time 4.94 seconds
Started Jun 09 01:12:00 PM PDT 24
Finished Jun 09 01:12:06 PM PDT 24
Peak memory 225556 kb
Host smart-3c989e73-5230-4ec7-986f-eb4cf3517c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456938680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2456938680
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.302925591
Short name T270
Test name
Test status
Simulation time 181316947 ps
CPU time 3.32 seconds
Started Jun 09 01:11:58 PM PDT 24
Finished Jun 09 01:12:02 PM PDT 24
Peak memory 233560 kb
Host smart-d55c18ba-c1cb-4a7f-a430-aeaaea10f057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302925591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.302925591
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2658254388
Short name T657
Test name
Test status
Simulation time 878720933 ps
CPU time 14.14 seconds
Started Jun 09 01:11:59 PM PDT 24
Finished Jun 09 01:12:13 PM PDT 24
Peak memory 233548 kb
Host smart-aded3783-4a2a-4c03-882c-21df839faf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658254388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2658254388
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2979976496
Short name T275
Test name
Test status
Simulation time 2163899846 ps
CPU time 5.89 seconds
Started Jun 09 01:12:01 PM PDT 24
Finished Jun 09 01:12:07 PM PDT 24
Peak memory 220452 kb
Host smart-b1bb7470-8a2f-4f79-ab63-9aa7ca050b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979976496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2979976496
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3638046052
Short name T254
Test name
Test status
Simulation time 290600287 ps
CPU time 3.57 seconds
Started Jun 09 01:12:02 PM PDT 24
Finished Jun 09 01:12:06 PM PDT 24
Peak memory 225352 kb
Host smart-d1b9b0a7-7f04-4d67-9bf1-9cd4d347be9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638046052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3638046052
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.593916209
Short name T955
Test name
Test status
Simulation time 320938433 ps
CPU time 4.1 seconds
Started Jun 09 01:12:02 PM PDT 24
Finished Jun 09 01:12:06 PM PDT 24
Peak memory 220148 kb
Host smart-4580c853-b2a3-4b19-b09c-db891612402e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=593916209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.593916209
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3936280213
Short name T187
Test name
Test status
Simulation time 3865448548 ps
CPU time 48.11 seconds
Started Jun 09 01:12:10 PM PDT 24
Finished Jun 09 01:12:59 PM PDT 24
Peak memory 255056 kb
Host smart-87accf1f-71fd-4a3a-b526-0548f78e915c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936280213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3936280213
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.4161039263
Short name T897
Test name
Test status
Simulation time 745803848 ps
CPU time 7.77 seconds
Started Jun 09 01:12:02 PM PDT 24
Finished Jun 09 01:12:10 PM PDT 24
Peak memory 219088 kb
Host smart-86d14c03-d6e1-4726-a687-24ece6c6c736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161039263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.4161039263
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.817071989
Short name T156
Test name
Test status
Simulation time 18004779558 ps
CPU time 21.77 seconds
Started Jun 09 01:12:02 PM PDT 24
Finished Jun 09 01:12:24 PM PDT 24
Peak memory 217224 kb
Host smart-a4781cce-8b4e-4b20-80c2-e96955e792ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817071989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.817071989
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.958526558
Short name T589
Test name
Test status
Simulation time 40256853 ps
CPU time 1.03 seconds
Started Jun 09 01:12:02 PM PDT 24
Finished Jun 09 01:12:03 PM PDT 24
Peak memory 207692 kb
Host smart-9f6c086c-68de-4405-898b-45f413e1e1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958526558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.958526558
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1297110893
Short name T620
Test name
Test status
Simulation time 299153799 ps
CPU time 0.8 seconds
Started Jun 09 01:12:04 PM PDT 24
Finished Jun 09 01:12:05 PM PDT 24
Peak memory 206684 kb
Host smart-09daf4ee-4cee-402f-9763-b41637f22553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297110893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1297110893
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3432639200
Short name T200
Test name
Test status
Simulation time 2567963994 ps
CPU time 5.6 seconds
Started Jun 09 01:12:00 PM PDT 24
Finished Jun 09 01:12:05 PM PDT 24
Peak memory 233684 kb
Host smart-40dbd6f1-4a65-474d-b141-045d8540f913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432639200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3432639200
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3738207000
Short name T676
Test name
Test status
Simulation time 14554747 ps
CPU time 0.73 seconds
Started Jun 09 01:12:09 PM PDT 24
Finished Jun 09 01:12:10 PM PDT 24
Peak memory 206176 kb
Host smart-b8a5746a-2212-4243-8c14-c2a2a96cee35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738207000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3738207000
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1819269127
Short name T702
Test name
Test status
Simulation time 96666864 ps
CPU time 2.89 seconds
Started Jun 09 01:12:07 PM PDT 24
Finished Jun 09 01:12:10 PM PDT 24
Peak memory 233560 kb
Host smart-10f7441e-6904-4f6f-a2e9-79e07a59ca33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819269127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1819269127
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.863587916
Short name T866
Test name
Test status
Simulation time 64079001 ps
CPU time 0.75 seconds
Started Jun 09 01:12:08 PM PDT 24
Finished Jun 09 01:12:09 PM PDT 24
Peak memory 206392 kb
Host smart-7015064d-dbef-4b0d-bfd5-601df5103958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863587916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.863587916
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1009984444
Short name T601
Test name
Test status
Simulation time 87892989798 ps
CPU time 147.21 seconds
Started Jun 09 01:12:06 PM PDT 24
Finished Jun 09 01:14:33 PM PDT 24
Peak memory 250832 kb
Host smart-4affd337-5f67-4c00-9241-980a9cb1c49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009984444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1009984444
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2850448735
Short name T888
Test name
Test status
Simulation time 2800184337 ps
CPU time 56.39 seconds
Started Jun 09 01:12:07 PM PDT 24
Finished Jun 09 01:13:04 PM PDT 24
Peak memory 250104 kb
Host smart-1a939ecd-0278-4b00-ac66-bb0440941230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850448735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2850448735
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.816196953
Short name T517
Test name
Test status
Simulation time 19350168 ps
CPU time 0.81 seconds
Started Jun 09 01:12:09 PM PDT 24
Finished Jun 09 01:12:10 PM PDT 24
Peak memory 218212 kb
Host smart-18881370-00c4-40f9-be5e-b230973d5756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816196953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.816196953
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1207044701
Short name T797
Test name
Test status
Simulation time 373895322 ps
CPU time 7.54 seconds
Started Jun 09 01:12:05 PM PDT 24
Finished Jun 09 01:12:13 PM PDT 24
Peak memory 225344 kb
Host smart-26919f1f-66a5-4028-afed-ee49465ac6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207044701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1207044701
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1343620601
Short name T939
Test name
Test status
Simulation time 746085844 ps
CPU time 3.19 seconds
Started Jun 09 01:12:07 PM PDT 24
Finished Jun 09 01:12:10 PM PDT 24
Peak memory 233520 kb
Host smart-65598822-247d-48c6-a784-987b358d5ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343620601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1343620601
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.76017808
Short name T269
Test name
Test status
Simulation time 397655796 ps
CPU time 3.85 seconds
Started Jun 09 01:12:05 PM PDT 24
Finished Jun 09 01:12:09 PM PDT 24
Peak memory 219512 kb
Host smart-c03829b1-5b0c-4e79-93ec-33b145096570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76017808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.76017808
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3562834378
Short name T297
Test name
Test status
Simulation time 6754937246 ps
CPU time 9.52 seconds
Started Jun 09 01:12:08 PM PDT 24
Finished Jun 09 01:12:18 PM PDT 24
Peak memory 233648 kb
Host smart-aa85696b-8860-448f-a7e2-5eff12ccb3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562834378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3562834378
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3156552761
Short name T667
Test name
Test status
Simulation time 373532125 ps
CPU time 5.13 seconds
Started Jun 09 01:12:06 PM PDT 24
Finished Jun 09 01:12:11 PM PDT 24
Peak memory 233536 kb
Host smart-b0531cc4-8401-411a-8331-0849dfda013c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156552761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3156552761
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2733892563
Short name T557
Test name
Test status
Simulation time 620369719 ps
CPU time 3.85 seconds
Started Jun 09 01:12:07 PM PDT 24
Finished Jun 09 01:12:11 PM PDT 24
Peak memory 223732 kb
Host smart-5230e3fb-f89f-468b-b139-b8619827787f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2733892563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2733892563
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2320345612
Short name T76
Test name
Test status
Simulation time 13758558309 ps
CPU time 64.87 seconds
Started Jun 09 01:12:08 PM PDT 24
Finished Jun 09 01:13:13 PM PDT 24
Peak memory 250348 kb
Host smart-c7e285f0-bd1c-4849-9a55-1e88f65a8696
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320345612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2320345612
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3924524015
Short name T346
Test name
Test status
Simulation time 1690706899 ps
CPU time 26.9 seconds
Started Jun 09 01:12:08 PM PDT 24
Finished Jun 09 01:12:35 PM PDT 24
Peak memory 217184 kb
Host smart-e0414242-99e2-46bd-83d3-8753f902f8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924524015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3924524015
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2047822304
Short name T900
Test name
Test status
Simulation time 3306171445 ps
CPU time 8.75 seconds
Started Jun 09 01:12:07 PM PDT 24
Finished Jun 09 01:12:16 PM PDT 24
Peak memory 217284 kb
Host smart-0e248b1b-58ed-4a24-ab58-b4501352bb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047822304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2047822304
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1123281355
Short name T624
Test name
Test status
Simulation time 28363203 ps
CPU time 0.79 seconds
Started Jun 09 01:12:08 PM PDT 24
Finished Jun 09 01:12:09 PM PDT 24
Peak memory 206696 kb
Host smart-92bb6c06-c987-4d1b-a448-785ba9fc88c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123281355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1123281355
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2673157988
Short name T933
Test name
Test status
Simulation time 72858617 ps
CPU time 0.77 seconds
Started Jun 09 01:12:07 PM PDT 24
Finished Jun 09 01:12:08 PM PDT 24
Peak memory 206704 kb
Host smart-f879a9f7-5d26-440d-b74e-abdabc41d229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673157988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2673157988
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2386568173
Short name T210
Test name
Test status
Simulation time 1626983701 ps
CPU time 3.29 seconds
Started Jun 09 01:12:08 PM PDT 24
Finished Jun 09 01:12:12 PM PDT 24
Peak memory 225236 kb
Host smart-0b013ef7-51b6-4896-946f-587187269a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386568173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2386568173
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2539714774
Short name T489
Test name
Test status
Simulation time 31932576 ps
CPU time 0.72 seconds
Started Jun 09 01:12:12 PM PDT 24
Finished Jun 09 01:12:14 PM PDT 24
Peak memory 206588 kb
Host smart-1a94b2ca-eb8e-49af-881c-e65c62e5b062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539714774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2539714774
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2575191558
Short name T936
Test name
Test status
Simulation time 34609625 ps
CPU time 2.45 seconds
Started Jun 09 01:12:12 PM PDT 24
Finished Jun 09 01:12:14 PM PDT 24
Peak memory 233504 kb
Host smart-763b3e09-7445-4346-9758-49d5bb306fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575191558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2575191558
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2624889246
Short name T20
Test name
Test status
Simulation time 49124913 ps
CPU time 0.77 seconds
Started Jun 09 01:12:06 PM PDT 24
Finished Jun 09 01:12:07 PM PDT 24
Peak memory 207696 kb
Host smart-b8e2deaf-eac6-43ee-8feb-fa66cd9faa69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624889246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2624889246
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.307109742
Short name T520
Test name
Test status
Simulation time 20271896 ps
CPU time 0.73 seconds
Started Jun 09 01:12:13 PM PDT 24
Finished Jun 09 01:12:14 PM PDT 24
Peak memory 216660 kb
Host smart-56d613e1-b534-46e0-a0a3-6fcc3b21a889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307109742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.307109742
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3633521
Short name T130
Test name
Test status
Simulation time 28859952137 ps
CPU time 51.23 seconds
Started Jun 09 01:12:15 PM PDT 24
Finished Jun 09 01:13:06 PM PDT 24
Peak memory 250124 kb
Host smart-e98f9ca9-083c-4376-b81a-207449f18aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3633521
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.4037386040
Short name T523
Test name
Test status
Simulation time 1321618723 ps
CPU time 8.41 seconds
Started Jun 09 01:12:12 PM PDT 24
Finished Jun 09 01:12:20 PM PDT 24
Peak memory 225328 kb
Host smart-33adfd75-7c9a-401b-8c8b-d618eb08044b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037386040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.4037386040
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2414197238
Short name T706
Test name
Test status
Simulation time 828275314 ps
CPU time 10.23 seconds
Started Jun 09 01:12:11 PM PDT 24
Finished Jun 09 01:12:22 PM PDT 24
Peak memory 225280 kb
Host smart-05859eea-5d86-4706-a284-62f0c0ac1c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414197238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2414197238
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1235703761
Short name T927
Test name
Test status
Simulation time 443550491 ps
CPU time 2.71 seconds
Started Jun 09 01:12:12 PM PDT 24
Finished Jun 09 01:12:15 PM PDT 24
Peak memory 225276 kb
Host smart-9e995450-e909-4903-9eaa-189600afba8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235703761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1235703761
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1180092984
Short name T292
Test name
Test status
Simulation time 1580758503 ps
CPU time 7.3 seconds
Started Jun 09 01:12:12 PM PDT 24
Finished Jun 09 01:12:19 PM PDT 24
Peak memory 233480 kb
Host smart-b5855a0b-202a-4884-a9b4-8cc4c6a64df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180092984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1180092984
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3131551968
Short name T650
Test name
Test status
Simulation time 81194920 ps
CPU time 2.67 seconds
Started Jun 09 01:12:07 PM PDT 24
Finished Jun 09 01:12:10 PM PDT 24
Peak memory 233516 kb
Host smart-3da37692-2021-46d9-a46a-458ebbaa1aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131551968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3131551968
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2603269617
Short name T378
Test name
Test status
Simulation time 983581830 ps
CPU time 14.45 seconds
Started Jun 09 01:12:13 PM PDT 24
Finished Jun 09 01:12:28 PM PDT 24
Peak memory 223352 kb
Host smart-e89be89e-76dc-4b41-976d-55daa82f349c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2603269617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2603269617
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2803500417
Short name T305
Test name
Test status
Simulation time 34437859156 ps
CPU time 378.12 seconds
Started Jun 09 01:12:12 PM PDT 24
Finished Jun 09 01:18:30 PM PDT 24
Peak memory 258292 kb
Host smart-d5ad8910-75e0-495a-922b-edb1ecb16049
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803500417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2803500417
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2607506407
Short name T654
Test name
Test status
Simulation time 5634227730 ps
CPU time 15.96 seconds
Started Jun 09 01:12:08 PM PDT 24
Finished Jun 09 01:12:25 PM PDT 24
Peak memory 217296 kb
Host smart-08cd421d-bdb8-4f73-a1f0-0a694fe1561d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607506407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2607506407
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1277429404
Short name T82
Test name
Test status
Simulation time 6610589283 ps
CPU time 18.57 seconds
Started Jun 09 01:12:06 PM PDT 24
Finished Jun 09 01:12:25 PM PDT 24
Peak memory 217200 kb
Host smart-5d41dcb4-ef32-4529-b41d-56842650ca60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277429404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1277429404
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1574701280
Short name T74
Test name
Test status
Simulation time 30637080 ps
CPU time 0.7 seconds
Started Jun 09 01:12:08 PM PDT 24
Finished Jun 09 01:12:09 PM PDT 24
Peak memory 206408 kb
Host smart-5b1b1f50-af14-4c64-8bf6-7b43226d39f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574701280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1574701280
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1446988679
Short name T1
Test name
Test status
Simulation time 45388059 ps
CPU time 0.71 seconds
Started Jun 09 01:12:09 PM PDT 24
Finished Jun 09 01:12:10 PM PDT 24
Peak memory 206692 kb
Host smart-1742eb5a-1ef7-42ff-bb7d-705ffce5efbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446988679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1446988679
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1427376741
Short name T512
Test name
Test status
Simulation time 88622521 ps
CPU time 2.14 seconds
Started Jun 09 01:12:11 PM PDT 24
Finished Jun 09 01:12:14 PM PDT 24
Peak memory 225100 kb
Host smart-9f72fa1a-13b2-41c1-8411-7c6b2225d394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427376741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1427376741
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3569660174
Short name T445
Test name
Test status
Simulation time 16257962 ps
CPU time 0.74 seconds
Started Jun 09 01:12:18 PM PDT 24
Finished Jun 09 01:12:20 PM PDT 24
Peak memory 206244 kb
Host smart-4da67647-04e7-483b-b3c8-0dc6e2872fc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569660174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3569660174
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2021288070
Short name T434
Test name
Test status
Simulation time 438977745 ps
CPU time 3.43 seconds
Started Jun 09 01:12:19 PM PDT 24
Finished Jun 09 01:12:23 PM PDT 24
Peak memory 225360 kb
Host smart-8ab24fca-9e2e-441c-8f16-6c43f332da95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021288070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2021288070
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3339384912
Short name T388
Test name
Test status
Simulation time 32563849 ps
CPU time 0.78 seconds
Started Jun 09 01:12:15 PM PDT 24
Finished Jun 09 01:12:16 PM PDT 24
Peak memory 206384 kb
Host smart-4157cb01-8950-4730-b62b-13ebea56c471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339384912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3339384912
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3495595502
Short name T819
Test name
Test status
Simulation time 23988194 ps
CPU time 0.77 seconds
Started Jun 09 01:12:20 PM PDT 24
Finished Jun 09 01:12:21 PM PDT 24
Peak memory 216656 kb
Host smart-04d13778-052d-4d77-943b-5261b6261337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495595502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3495595502
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1739239606
Short name T225
Test name
Test status
Simulation time 5354077715 ps
CPU time 129.2 seconds
Started Jun 09 01:12:18 PM PDT 24
Finished Jun 09 01:14:27 PM PDT 24
Peak memory 253364 kb
Host smart-ff6df5f2-5290-405b-8622-5489a4d1f43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739239606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1739239606
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1567230817
Short name T868
Test name
Test status
Simulation time 12626998112 ps
CPU time 28.1 seconds
Started Jun 09 01:12:21 PM PDT 24
Finished Jun 09 01:12:49 PM PDT 24
Peak memory 225552 kb
Host smart-aa175c0a-12e4-4154-be0b-72cc3042a0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567230817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1567230817
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3126473007
Short name T460
Test name
Test status
Simulation time 3438726613 ps
CPU time 26.47 seconds
Started Jun 09 01:12:18 PM PDT 24
Finished Jun 09 01:12:45 PM PDT 24
Peak memory 225476 kb
Host smart-2976bec3-021c-47c0-8d93-ca2fa01c8fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126473007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3126473007
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2146042719
Short name T689
Test name
Test status
Simulation time 2833037165 ps
CPU time 8.64 seconds
Started Jun 09 01:12:20 PM PDT 24
Finished Jun 09 01:12:29 PM PDT 24
Peak memory 225412 kb
Host smart-5f042275-14cb-4311-b0c4-a19d48536dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146042719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2146042719
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2390972184
Short name T571
Test name
Test status
Simulation time 77733608 ps
CPU time 2.32 seconds
Started Jun 09 01:12:18 PM PDT 24
Finished Jun 09 01:12:21 PM PDT 24
Peak memory 224812 kb
Host smart-c303cf3c-d99f-4c96-bed2-d23635b333ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390972184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2390972184
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2147528753
Short name T856
Test name
Test status
Simulation time 11333647558 ps
CPU time 10.04 seconds
Started Jun 09 01:12:20 PM PDT 24
Finished Jun 09 01:12:30 PM PDT 24
Peak memory 233824 kb
Host smart-044fac9e-f689-4271-b161-821ba4f2ed71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147528753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2147528753
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.714322197
Short name T891
Test name
Test status
Simulation time 3156364818 ps
CPU time 16.43 seconds
Started Jun 09 01:12:18 PM PDT 24
Finished Jun 09 01:12:35 PM PDT 24
Peak memory 233664 kb
Host smart-caf7dbd2-c692-49ed-ba2d-6d9b20667520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714322197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.714322197
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.407099597
Short name T773
Test name
Test status
Simulation time 738976037 ps
CPU time 5.74 seconds
Started Jun 09 01:12:21 PM PDT 24
Finished Jun 09 01:12:27 PM PDT 24
Peak memory 221276 kb
Host smart-2e209166-7024-466d-b655-56fcd2e9f4af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=407099597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.407099597
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1631218402
Short name T152
Test name
Test status
Simulation time 2172299273 ps
CPU time 31.96 seconds
Started Jun 09 01:12:18 PM PDT 24
Finished Jun 09 01:12:50 PM PDT 24
Peak memory 250128 kb
Host smart-a58e0652-ea18-43c8-b0ec-f8486b52a1b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631218402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1631218402
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3044390310
Short name T579
Test name
Test status
Simulation time 1052730063 ps
CPU time 3.53 seconds
Started Jun 09 01:12:12 PM PDT 24
Finished Jun 09 01:12:16 PM PDT 24
Peak memory 217212 kb
Host smart-470bbd1b-9899-49e0-a401-2b00b79959c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044390310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3044390310
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1411005876
Short name T666
Test name
Test status
Simulation time 31516380108 ps
CPU time 18.4 seconds
Started Jun 09 01:12:12 PM PDT 24
Finished Jun 09 01:12:31 PM PDT 24
Peak memory 217288 kb
Host smart-c0de7430-a416-4df3-89c9-c980eb7c9088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411005876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1411005876
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1681576003
Short name T737
Test name
Test status
Simulation time 15070131 ps
CPU time 1.07 seconds
Started Jun 09 01:12:12 PM PDT 24
Finished Jun 09 01:12:14 PM PDT 24
Peak memory 208708 kb
Host smart-ff40b27d-975f-464a-b794-be96ec9d626e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681576003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1681576003
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2925765121
Short name T873
Test name
Test status
Simulation time 24658066 ps
CPU time 0.77 seconds
Started Jun 09 01:12:14 PM PDT 24
Finished Jun 09 01:12:15 PM PDT 24
Peak memory 206684 kb
Host smart-51a4c750-dcc8-4fec-8f3e-25fe1e6aba6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925765121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2925765121
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1920877110
Short name T763
Test name
Test status
Simulation time 4464721664 ps
CPU time 10.06 seconds
Started Jun 09 01:12:22 PM PDT 24
Finished Jun 09 01:12:32 PM PDT 24
Peak memory 233668 kb
Host smart-000ccb59-9c15-4e02-8d6d-8315f3329f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920877110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1920877110
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.4207062237
Short name T9
Test name
Test status
Simulation time 44397806 ps
CPU time 0.69 seconds
Started Jun 09 01:09:22 PM PDT 24
Finished Jun 09 01:09:23 PM PDT 24
Peak memory 205680 kb
Host smart-f5b05fd1-7cd4-404a-99e6-582dac6b9f02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207062237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.4
207062237
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1536006280
Short name T940
Test name
Test status
Simulation time 2978644593 ps
CPU time 8.2 seconds
Started Jun 09 01:09:09 PM PDT 24
Finished Jun 09 01:09:18 PM PDT 24
Peak memory 225360 kb
Host smart-1da26bdb-2300-48ec-9d0f-4844bff9c8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536006280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1536006280
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2346934789
Short name T73
Test name
Test status
Simulation time 16943052 ps
CPU time 0.79 seconds
Started Jun 09 01:09:10 PM PDT 24
Finished Jun 09 01:09:11 PM PDT 24
Peak memory 207448 kb
Host smart-b9af85b9-464b-4520-a802-fc2c60637160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346934789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2346934789
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.609842512
Short name T896
Test name
Test status
Simulation time 7853729936 ps
CPU time 29.39 seconds
Started Jun 09 01:09:09 PM PDT 24
Finished Jun 09 01:09:39 PM PDT 24
Peak memory 240916 kb
Host smart-23269bdb-a1fc-4c87-a765-532ccd7060b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609842512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.609842512
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2646668498
Short name T198
Test name
Test status
Simulation time 6907249844 ps
CPU time 99.57 seconds
Started Jun 09 01:09:09 PM PDT 24
Finished Jun 09 01:10:49 PM PDT 24
Peak memory 269520 kb
Host smart-543c8768-5d9b-4c17-b70e-40f41380b64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646668498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2646668498
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.505925032
Short name T126
Test name
Test status
Simulation time 57760353641 ps
CPU time 133.7 seconds
Started Jun 09 01:09:11 PM PDT 24
Finished Jun 09 01:11:25 PM PDT 24
Peak memory 250108 kb
Host smart-e063ee1a-65c5-4084-8f67-b92e5af30289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505925032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
505925032
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2477155940
Short name T324
Test name
Test status
Simulation time 12232699192 ps
CPU time 54.77 seconds
Started Jun 09 01:09:09 PM PDT 24
Finished Jun 09 01:10:04 PM PDT 24
Peak memory 233636 kb
Host smart-2c2427a5-0e47-4ce0-85d9-bcdbebe9c078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477155940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2477155940
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3310441887
Short name T244
Test name
Test status
Simulation time 13858243627 ps
CPU time 30.55 seconds
Started Jun 09 01:09:10 PM PDT 24
Finished Jun 09 01:09:41 PM PDT 24
Peak memory 233660 kb
Host smart-48108a1e-d243-42ee-9b3c-737428898b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310441887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3310441887
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4166943231
Short name T216
Test name
Test status
Simulation time 130009160168 ps
CPU time 85.81 seconds
Started Jun 09 01:09:12 PM PDT 24
Finished Jun 09 01:10:38 PM PDT 24
Peak memory 241768 kb
Host smart-e0f3bbb4-90bb-49c2-a202-66fd74ad4a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166943231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4166943231
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.82246076
Short name T948
Test name
Test status
Simulation time 8041421843 ps
CPU time 5.8 seconds
Started Jun 09 01:09:10 PM PDT 24
Finished Jun 09 01:09:16 PM PDT 24
Peak memory 233660 kb
Host smart-eef4bf19-9418-4bd4-acc3-739ba30fc0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82246076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.82246076
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3890742417
Short name T247
Test name
Test status
Simulation time 1213916328 ps
CPU time 8.6 seconds
Started Jun 09 01:09:11 PM PDT 24
Finished Jun 09 01:09:20 PM PDT 24
Peak memory 233548 kb
Host smart-cdad622c-83db-47b5-9457-f6bc372aae81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890742417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3890742417
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3006508169
Short name T451
Test name
Test status
Simulation time 600854566 ps
CPU time 3.69 seconds
Started Jun 09 01:09:09 PM PDT 24
Finished Jun 09 01:09:13 PM PDT 24
Peak memory 219856 kb
Host smart-d98d2a98-0797-4ae1-8109-8762410b7d25
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3006508169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3006508169
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2976229316
Short name T64
Test name
Test status
Simulation time 395534017 ps
CPU time 1.15 seconds
Started Jun 09 01:09:09 PM PDT 24
Finished Jun 09 01:09:10 PM PDT 24
Peak memory 236292 kb
Host smart-ddb5ea78-1ab0-4b96-bc29-f962b419951f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976229316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2976229316
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.498227439
Short name T298
Test name
Test status
Simulation time 1742659211 ps
CPU time 40.86 seconds
Started Jun 09 01:09:09 PM PDT 24
Finished Jun 09 01:09:50 PM PDT 24
Peak memory 254648 kb
Host smart-80f76bf7-6d0d-46d0-b7e4-284bb75deff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498227439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.498227439
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1345248454
Short name T860
Test name
Test status
Simulation time 830245770 ps
CPU time 5.38 seconds
Started Jun 09 01:09:11 PM PDT 24
Finished Jun 09 01:09:17 PM PDT 24
Peak memory 217116 kb
Host smart-7bf7d889-7b66-45a2-9cdb-9e3610f3693a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345248454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1345248454
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.83228996
Short name T454
Test name
Test status
Simulation time 77337286 ps
CPU time 1.28 seconds
Started Jun 09 01:09:11 PM PDT 24
Finished Jun 09 01:09:13 PM PDT 24
Peak memory 208712 kb
Host smart-80a13ab0-2523-4e69-bd27-3dc997b7dfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83228996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.83228996
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3269559946
Short name T507
Test name
Test status
Simulation time 19584129 ps
CPU time 0.72 seconds
Started Jun 09 01:09:10 PM PDT 24
Finished Jun 09 01:09:11 PM PDT 24
Peak memory 206628 kb
Host smart-d936dcd7-ac49-4855-90b3-cc012ff334e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269559946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3269559946
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1414257005
Short name T758
Test name
Test status
Simulation time 30848306 ps
CPU time 0.77 seconds
Started Jun 09 01:09:11 PM PDT 24
Finished Jun 09 01:09:12 PM PDT 24
Peak memory 206684 kb
Host smart-67d3cfcc-1c75-4c52-b37a-9e102de898a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414257005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1414257005
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2148842855
Short name T125
Test name
Test status
Simulation time 8381322848 ps
CPU time 5.67 seconds
Started Jun 09 01:09:12 PM PDT 24
Finished Jun 09 01:09:18 PM PDT 24
Peak memory 225468 kb
Host smart-ea718f3b-6590-4989-b6ed-8bb7f870b162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148842855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2148842855
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.4229694812
Short name T670
Test name
Test status
Simulation time 48463907 ps
CPU time 0.72 seconds
Started Jun 09 01:12:24 PM PDT 24
Finished Jun 09 01:12:25 PM PDT 24
Peak memory 206212 kb
Host smart-47cabfd5-a68a-41b0-8d70-12fda45955a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229694812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
4229694812
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.4135807143
Short name T412
Test name
Test status
Simulation time 97485546 ps
CPU time 2.57 seconds
Started Jun 09 01:12:24 PM PDT 24
Finished Jun 09 01:12:27 PM PDT 24
Peak memory 233560 kb
Host smart-5c543b36-e567-45cc-ae5a-1123ef8f9c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135807143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.4135807143
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.4228045235
Short name T587
Test name
Test status
Simulation time 14977342 ps
CPU time 0.81 seconds
Started Jun 09 01:12:19 PM PDT 24
Finished Jun 09 01:12:20 PM PDT 24
Peak memory 206944 kb
Host smart-81f18d9d-9ecf-4bbb-915f-c62645cb2163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228045235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.4228045235
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1279478562
Short name T206
Test name
Test status
Simulation time 8998712738 ps
CPU time 51.31 seconds
Started Jun 09 01:12:23 PM PDT 24
Finished Jun 09 01:13:14 PM PDT 24
Peak memory 250604 kb
Host smart-4fc0a7c7-3014-45d3-aef9-af2dc73aa6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279478562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1279478562
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.4035306274
Short name T855
Test name
Test status
Simulation time 13582104784 ps
CPU time 99.84 seconds
Started Jun 09 01:12:26 PM PDT 24
Finished Jun 09 01:14:06 PM PDT 24
Peak memory 258312 kb
Host smart-387abe85-1a31-4980-9291-ed2e15850439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035306274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.4035306274
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.928481682
Short name T273
Test name
Test status
Simulation time 8254434429 ps
CPU time 103.74 seconds
Started Jun 09 01:12:27 PM PDT 24
Finished Jun 09 01:14:11 PM PDT 24
Peak memory 262616 kb
Host smart-d20cfd1f-8bf1-4d57-9863-f08ba7f5b8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928481682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.928481682
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3987262506
Short name T892
Test name
Test status
Simulation time 1929524126 ps
CPU time 8.24 seconds
Started Jun 09 01:12:24 PM PDT 24
Finished Jun 09 01:12:33 PM PDT 24
Peak memory 233468 kb
Host smart-1edbbaaa-cec6-4119-9f8a-edb70f9add4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987262506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3987262506
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.735220708
Short name T810
Test name
Test status
Simulation time 25085608000 ps
CPU time 105.71 seconds
Started Jun 09 01:12:24 PM PDT 24
Finished Jun 09 01:14:11 PM PDT 24
Peak memory 238428 kb
Host smart-0a668907-e9be-445d-b8da-4d29d7e19116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735220708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.735220708
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2525305097
Short name T278
Test name
Test status
Simulation time 7940621572 ps
CPU time 22.25 seconds
Started Jun 09 01:12:26 PM PDT 24
Finished Jun 09 01:12:48 PM PDT 24
Peak memory 225488 kb
Host smart-92c16f9f-ef58-47c6-8520-1546d0c72320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525305097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2525305097
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1839650912
Short name T570
Test name
Test status
Simulation time 1042921498 ps
CPU time 7.79 seconds
Started Jun 09 01:12:28 PM PDT 24
Finished Jun 09 01:12:36 PM PDT 24
Peak memory 233484 kb
Host smart-6c5666d0-3a6d-4f1f-87d0-23bacc6d7cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839650912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1839650912
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3733162855
Short name T627
Test name
Test status
Simulation time 510815174 ps
CPU time 7.43 seconds
Started Jun 09 01:12:24 PM PDT 24
Finished Jun 09 01:12:32 PM PDT 24
Peak memory 223084 kb
Host smart-18218cb9-0afc-49ef-8430-df8e706c4ffa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3733162855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3733162855
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1033443150
Short name T770
Test name
Test status
Simulation time 83921254 ps
CPU time 0.71 seconds
Started Jun 09 01:12:20 PM PDT 24
Finished Jun 09 01:12:21 PM PDT 24
Peak memory 206524 kb
Host smart-9aad8492-86e5-4ccf-9a41-8cf448538b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033443150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1033443150
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.984912340
Short name T788
Test name
Test status
Simulation time 1884994821 ps
CPU time 5.34 seconds
Started Jun 09 01:12:20 PM PDT 24
Finished Jun 09 01:12:25 PM PDT 24
Peak memory 217160 kb
Host smart-80ed5501-ef90-4402-bcd8-00f7b74c2f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984912340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.984912340
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.606008044
Short name T651
Test name
Test status
Simulation time 276921911 ps
CPU time 1.58 seconds
Started Jun 09 01:12:23 PM PDT 24
Finished Jun 09 01:12:25 PM PDT 24
Peak memory 217160 kb
Host smart-ca3df3b6-5765-4a92-b5ac-0c60b48e3d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606008044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.606008044
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2152260336
Short name T490
Test name
Test status
Simulation time 47411794 ps
CPU time 0.85 seconds
Started Jun 09 01:12:21 PM PDT 24
Finished Jun 09 01:12:22 PM PDT 24
Peak memory 206704 kb
Host smart-c06bba8c-dfe7-49e8-88f7-bdb01c8d2094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152260336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2152260336
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2769037738
Short name T605
Test name
Test status
Simulation time 468826183 ps
CPU time 4.17 seconds
Started Jun 09 01:12:26 PM PDT 24
Finished Jun 09 01:12:31 PM PDT 24
Peak memory 233540 kb
Host smart-9c13b50f-05dd-4977-ae62-cd0d596dc452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769037738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2769037738
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2217559591
Short name T543
Test name
Test status
Simulation time 179926985 ps
CPU time 0.72 seconds
Started Jun 09 01:12:33 PM PDT 24
Finished Jun 09 01:12:34 PM PDT 24
Peak memory 206584 kb
Host smart-3a7d72ba-f7a0-4b6a-8662-bd9ab0e13121
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217559591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2217559591
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.675402493
Short name T734
Test name
Test status
Simulation time 502699971 ps
CPU time 3.78 seconds
Started Jun 09 01:12:25 PM PDT 24
Finished Jun 09 01:12:30 PM PDT 24
Peak memory 233516 kb
Host smart-97c6f2c6-4474-4201-baf4-e82b78cc1673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675402493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.675402493
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2483769878
Short name T953
Test name
Test status
Simulation time 20517232 ps
CPU time 0.79 seconds
Started Jun 09 01:12:25 PM PDT 24
Finished Jun 09 01:12:26 PM PDT 24
Peak memory 207700 kb
Host smart-604c942e-778e-4098-b5b9-a29d3f99c5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483769878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2483769878
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1630440766
Short name T173
Test name
Test status
Simulation time 10003925468 ps
CPU time 50.68 seconds
Started Jun 09 01:12:32 PM PDT 24
Finished Jun 09 01:13:23 PM PDT 24
Peak memory 250048 kb
Host smart-325241e9-0040-4cf1-86bc-12e3b5477969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630440766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1630440766
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3574627956
Short name T211
Test name
Test status
Simulation time 232575661328 ps
CPU time 422.12 seconds
Started Jun 09 01:12:32 PM PDT 24
Finished Jun 09 01:19:34 PM PDT 24
Peak memory 256424 kb
Host smart-57382c2d-1d2d-498e-82f5-005331475603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574627956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3574627956
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1254616484
Short name T729
Test name
Test status
Simulation time 1659641656 ps
CPU time 5.16 seconds
Started Jun 09 01:12:23 PM PDT 24
Finished Jun 09 01:12:29 PM PDT 24
Peak memory 233556 kb
Host smart-36e5e16a-ae26-4644-88cc-37a3bfa492e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254616484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1254616484
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2512706670
Short name T902
Test name
Test status
Simulation time 779819438 ps
CPU time 4.14 seconds
Started Jun 09 01:12:25 PM PDT 24
Finished Jun 09 01:12:30 PM PDT 24
Peak memory 233516 kb
Host smart-23140407-43df-490d-9077-20923d6ef2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512706670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2512706670
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.4286633932
Short name T365
Test name
Test status
Simulation time 8168295961 ps
CPU time 28.69 seconds
Started Jun 09 01:12:25 PM PDT 24
Finished Jun 09 01:12:54 PM PDT 24
Peak memory 241772 kb
Host smart-d42e95c6-8395-453a-99b0-fb4f5ff75ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286633932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.4286633932
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3328127195
Short name T823
Test name
Test status
Simulation time 21907295636 ps
CPU time 10.59 seconds
Started Jun 09 01:12:23 PM PDT 24
Finished Jun 09 01:12:34 PM PDT 24
Peak memory 225432 kb
Host smart-73542c8a-8d29-46de-bf40-d16e9c546603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328127195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3328127195
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.929976964
Short name T423
Test name
Test status
Simulation time 60327751 ps
CPU time 2.16 seconds
Started Jun 09 01:12:26 PM PDT 24
Finished Jun 09 01:12:28 PM PDT 24
Peak memory 228296 kb
Host smart-a51de985-9b6b-4966-9319-04463cd2a2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929976964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.929976964
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1948890180
Short name T759
Test name
Test status
Simulation time 477153496 ps
CPU time 8.29 seconds
Started Jun 09 01:12:25 PM PDT 24
Finished Jun 09 01:12:33 PM PDT 24
Peak memory 223024 kb
Host smart-1348d948-2f2c-4cae-8d6c-7eebefdd3340
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1948890180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1948890180
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.4089190235
Short name T597
Test name
Test status
Simulation time 38922298 ps
CPU time 0.99 seconds
Started Jun 09 01:12:32 PM PDT 24
Finished Jun 09 01:12:33 PM PDT 24
Peak memory 207720 kb
Host smart-3d8189ed-19c7-4ef1-98d3-ae3f1f2e15d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089190235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.4089190235
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1929590184
Short name T756
Test name
Test status
Simulation time 7624013744 ps
CPU time 22.75 seconds
Started Jun 09 01:12:27 PM PDT 24
Finished Jun 09 01:12:50 PM PDT 24
Peak memory 221068 kb
Host smart-773c2496-5456-46f8-8057-b17b31cb815f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929590184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1929590184
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1244341502
Short name T951
Test name
Test status
Simulation time 6353483461 ps
CPU time 5.3 seconds
Started Jun 09 01:12:24 PM PDT 24
Finished Jun 09 01:12:30 PM PDT 24
Peak memory 217276 kb
Host smart-bcbc244b-c812-43e6-95b1-1724cbd31a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244341502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1244341502
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3852923431
Short name T615
Test name
Test status
Simulation time 23490382 ps
CPU time 0.8 seconds
Started Jun 09 01:12:25 PM PDT 24
Finished Jun 09 01:12:27 PM PDT 24
Peak memory 207304 kb
Host smart-f22fcce5-3615-4f1a-b657-15396f70305c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852923431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3852923431
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.425854995
Short name T475
Test name
Test status
Simulation time 46127831 ps
CPU time 0.79 seconds
Started Jun 09 01:12:26 PM PDT 24
Finished Jun 09 01:12:27 PM PDT 24
Peak memory 206628 kb
Host smart-84fb0474-6889-4392-9a20-ad84b44fb399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425854995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.425854995
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3708930314
Short name T203
Test name
Test status
Simulation time 7820326067 ps
CPU time 4.97 seconds
Started Jun 09 01:12:25 PM PDT 24
Finished Jun 09 01:12:31 PM PDT 24
Peak memory 225464 kb
Host smart-d7bcb5ba-f83d-46fb-b0d5-c13c966d3367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708930314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3708930314
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.445458547
Short name T55
Test name
Test status
Simulation time 111514953 ps
CPU time 0.74 seconds
Started Jun 09 01:12:33 PM PDT 24
Finished Jun 09 01:12:34 PM PDT 24
Peak memory 206216 kb
Host smart-addaa1db-c875-48a1-9d92-ae535299c7fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445458547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.445458547
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1346606399
Short name T259
Test name
Test status
Simulation time 678763815 ps
CPU time 3.55 seconds
Started Jun 09 01:12:31 PM PDT 24
Finished Jun 09 01:12:35 PM PDT 24
Peak memory 225308 kb
Host smart-f15e33e7-0324-42bc-bf4f-dba884b69159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346606399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1346606399
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2071444698
Short name T904
Test name
Test status
Simulation time 12445579 ps
CPU time 0.72 seconds
Started Jun 09 01:12:31 PM PDT 24
Finished Jun 09 01:12:32 PM PDT 24
Peak memory 206616 kb
Host smart-71bb6b1e-77a4-43b6-afbb-88223a202ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071444698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2071444698
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2938291775
Short name T882
Test name
Test status
Simulation time 5077598424 ps
CPU time 100.01 seconds
Started Jun 09 01:12:32 PM PDT 24
Finished Jun 09 01:14:13 PM PDT 24
Peak memory 254756 kb
Host smart-8c67462b-ba31-48e2-813a-6e3c4b20b108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938291775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2938291775
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3331803085
Short name T311
Test name
Test status
Simulation time 289092266662 ps
CPU time 377.2 seconds
Started Jun 09 01:12:31 PM PDT 24
Finished Jun 09 01:18:49 PM PDT 24
Peak memory 261868 kb
Host smart-e0113219-fcc2-422a-be9c-fd3e1d8d4982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331803085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3331803085
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.4272587375
Short name T938
Test name
Test status
Simulation time 27172225694 ps
CPU time 177.65 seconds
Started Jun 09 01:12:32 PM PDT 24
Finished Jun 09 01:15:30 PM PDT 24
Peak memory 251512 kb
Host smart-7516a7e1-0023-428e-aea4-66f4b67b5e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272587375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.4272587375
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3003724389
Short name T864
Test name
Test status
Simulation time 1556924091 ps
CPU time 8.04 seconds
Started Jun 09 01:12:34 PM PDT 24
Finished Jun 09 01:12:43 PM PDT 24
Peak memory 233556 kb
Host smart-cc89a8b9-b992-486d-84bb-49cc67f37ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003724389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3003724389
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.737810533
Short name T242
Test name
Test status
Simulation time 334968287 ps
CPU time 3.75 seconds
Started Jun 09 01:12:32 PM PDT 24
Finished Jun 09 01:12:36 PM PDT 24
Peak memory 225344 kb
Host smart-c0fce79d-ca30-45bd-b4bd-aa572d6ed53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737810533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.737810533
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.157623423
Short name T417
Test name
Test status
Simulation time 312220101 ps
CPU time 4.55 seconds
Started Jun 09 01:12:30 PM PDT 24
Finished Jun 09 01:12:35 PM PDT 24
Peak memory 233540 kb
Host smart-0570ece2-6ac6-439a-897d-dde8688e84a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157623423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.157623423
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.30554858
Short name T277
Test name
Test status
Simulation time 739901917 ps
CPU time 2.82 seconds
Started Jun 09 01:12:32 PM PDT 24
Finished Jun 09 01:12:35 PM PDT 24
Peak memory 225280 kb
Host smart-37381bd0-7aba-4793-b5a4-ec6419948483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30554858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.30554858
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3536893324
Short name T11
Test name
Test status
Simulation time 1172914009 ps
CPU time 8.35 seconds
Started Jun 09 01:12:31 PM PDT 24
Finished Jun 09 01:12:40 PM PDT 24
Peak memory 233544 kb
Host smart-7dabf097-6a42-4f89-b8a4-5f4660742f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536893324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3536893324
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.877823999
Short name T139
Test name
Test status
Simulation time 646227685 ps
CPU time 3.72 seconds
Started Jun 09 01:12:30 PM PDT 24
Finished Jun 09 01:12:34 PM PDT 24
Peak memory 221992 kb
Host smart-8748456e-0061-4652-b1f5-1d4a9d92a028
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=877823999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.877823999
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2590313358
Short name T697
Test name
Test status
Simulation time 45654176056 ps
CPU time 437.95 seconds
Started Jun 09 01:12:30 PM PDT 24
Finished Jun 09 01:19:48 PM PDT 24
Peak memory 263920 kb
Host smart-11f77ec1-2ccb-4afc-b543-7a84ad7f1b4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590313358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2590313358
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.689108066
Short name T374
Test name
Test status
Simulation time 323841349 ps
CPU time 3.89 seconds
Started Jun 09 01:12:32 PM PDT 24
Finished Jun 09 01:12:36 PM PDT 24
Peak memory 217088 kb
Host smart-2ba0dbd4-8251-4ab0-bf50-f05ce470ea57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689108066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.689108066
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3887144697
Short name T713
Test name
Test status
Simulation time 11428408 ps
CPU time 0.71 seconds
Started Jun 09 01:12:31 PM PDT 24
Finished Jun 09 01:12:33 PM PDT 24
Peak memory 206480 kb
Host smart-423938a4-79c1-4ec7-a5b5-34e3bb23841a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887144697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3887144697
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3711286548
Short name T493
Test name
Test status
Simulation time 426881760 ps
CPU time 2.23 seconds
Started Jun 09 01:12:33 PM PDT 24
Finished Jun 09 01:12:36 PM PDT 24
Peak memory 217152 kb
Host smart-2c68a6ec-d080-4cea-8615-736c37bf8995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711286548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3711286548
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1073846686
Short name T805
Test name
Test status
Simulation time 48538283 ps
CPU time 0.82 seconds
Started Jun 09 01:12:31 PM PDT 24
Finished Jun 09 01:12:32 PM PDT 24
Peak memory 206624 kb
Host smart-4f5d10ef-358d-4ec3-8833-7bb9086c332c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073846686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1073846686
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.738258830
Short name T613
Test name
Test status
Simulation time 1094080315 ps
CPU time 4.8 seconds
Started Jun 09 01:12:32 PM PDT 24
Finished Jun 09 01:12:37 PM PDT 24
Peak memory 225344 kb
Host smart-b0ddc163-a8f7-4b0f-84df-04fe9f01099d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738258830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.738258830
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1870736886
Short name T771
Test name
Test status
Simulation time 16939912 ps
CPU time 0.75 seconds
Started Jun 09 01:12:37 PM PDT 24
Finished Jun 09 01:12:38 PM PDT 24
Peak memory 205680 kb
Host smart-eee8b321-8bd5-4d11-be9c-741213352f92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870736886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1870736886
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3770255051
Short name T86
Test name
Test status
Simulation time 5579686696 ps
CPU time 10.88 seconds
Started Jun 09 01:12:34 PM PDT 24
Finished Jun 09 01:12:46 PM PDT 24
Peak memory 225412 kb
Host smart-93827fbb-a302-4860-adaa-85813c278500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770255051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3770255051
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2186785150
Short name T21
Test name
Test status
Simulation time 58165918 ps
CPU time 0.8 seconds
Started Jun 09 01:12:34 PM PDT 24
Finished Jun 09 01:12:36 PM PDT 24
Peak memory 207392 kb
Host smart-a57d563b-6261-4504-8b33-1c0db2981b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186785150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2186785150
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1939733911
Short name T255
Test name
Test status
Simulation time 14440682510 ps
CPU time 38.39 seconds
Started Jun 09 01:12:35 PM PDT 24
Finished Jun 09 01:13:14 PM PDT 24
Peak memory 235928 kb
Host smart-6a643a98-12a4-48ef-abfc-6f891d06065e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939733911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1939733911
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.4199292646
Short name T316
Test name
Test status
Simulation time 6433075346 ps
CPU time 86.24 seconds
Started Jun 09 01:12:38 PM PDT 24
Finished Jun 09 01:14:05 PM PDT 24
Peak memory 256720 kb
Host smart-4130b3c3-f48d-4737-8804-2460101eb4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199292646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.4199292646
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2306478622
Short name T326
Test name
Test status
Simulation time 1236640041 ps
CPU time 6.38 seconds
Started Jun 09 01:12:38 PM PDT 24
Finished Jun 09 01:12:44 PM PDT 24
Peak memory 225344 kb
Host smart-d7feee06-4dba-4394-be74-78084420f878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306478622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2306478622
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2798696894
Short name T777
Test name
Test status
Simulation time 499788467 ps
CPU time 7.69 seconds
Started Jun 09 01:12:35 PM PDT 24
Finished Jun 09 01:12:44 PM PDT 24
Peak memory 233540 kb
Host smart-6bdc6235-aed7-4b54-9c7b-d9167fd2ebd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798696894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2798696894
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1281161699
Short name T96
Test name
Test status
Simulation time 11338236614 ps
CPU time 27.73 seconds
Started Jun 09 01:12:37 PM PDT 24
Finished Jun 09 01:13:05 PM PDT 24
Peak memory 233608 kb
Host smart-fd2c296a-b274-42c7-97be-6116f0f389d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281161699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1281161699
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1468358323
Short name T280
Test name
Test status
Simulation time 5631635039 ps
CPU time 11.3 seconds
Started Jun 09 01:12:35 PM PDT 24
Finished Jun 09 01:12:47 PM PDT 24
Peak memory 233684 kb
Host smart-62ef9677-8a02-44ca-b5b8-456cff2c47fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468358323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1468358323
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2709775854
Short name T446
Test name
Test status
Simulation time 21752628385 ps
CPU time 14.18 seconds
Started Jun 09 01:12:32 PM PDT 24
Finished Jun 09 01:12:47 PM PDT 24
Peak memory 225408 kb
Host smart-ce246126-8326-4535-a02e-54e9f1f3ef7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709775854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2709775854
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3163124299
Short name T41
Test name
Test status
Simulation time 3013423811 ps
CPU time 9.91 seconds
Started Jun 09 01:12:37 PM PDT 24
Finished Jun 09 01:12:47 PM PDT 24
Peak memory 222508 kb
Host smart-3d452b90-1ab7-44b4-ad9e-2c556cf91ffa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3163124299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3163124299
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1300871620
Short name T313
Test name
Test status
Simulation time 57612237132 ps
CPU time 439.72 seconds
Started Jun 09 01:12:34 PM PDT 24
Finished Jun 09 01:19:54 PM PDT 24
Peak memory 257168 kb
Host smart-f2de2e8d-cd91-47e6-a235-9a484f62d9ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300871620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1300871620
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1583593483
Short name T344
Test name
Test status
Simulation time 21717643179 ps
CPU time 33.6 seconds
Started Jun 09 01:12:31 PM PDT 24
Finished Jun 09 01:13:05 PM PDT 24
Peak memory 217176 kb
Host smart-dcf05373-d4bc-47cd-8fbf-c1795b0c2cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583593483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1583593483
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3250969213
Short name T390
Test name
Test status
Simulation time 798979706 ps
CPU time 2.81 seconds
Started Jun 09 01:12:33 PM PDT 24
Finished Jun 09 01:12:36 PM PDT 24
Peak memory 208576 kb
Host smart-69de4ae3-f8a1-43cf-84f2-cccd51359a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250969213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3250969213
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1793830636
Short name T348
Test name
Test status
Simulation time 38776239 ps
CPU time 0.92 seconds
Started Jun 09 01:12:31 PM PDT 24
Finished Jun 09 01:12:33 PM PDT 24
Peak memory 207812 kb
Host smart-e1ee9c95-9653-43dd-944a-aa61397870a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793830636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1793830636
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.726502866
Short name T484
Test name
Test status
Simulation time 31280583 ps
CPU time 0.87 seconds
Started Jun 09 01:12:30 PM PDT 24
Finished Jun 09 01:12:32 PM PDT 24
Peak memory 206836 kb
Host smart-cbbbc500-0175-44f9-9087-824039199f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726502866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.726502866
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2970463035
Short name T942
Test name
Test status
Simulation time 432269253 ps
CPU time 4.65 seconds
Started Jun 09 01:12:33 PM PDT 24
Finished Jun 09 01:12:38 PM PDT 24
Peak memory 225584 kb
Host smart-df5ca93c-96cb-47ea-b6cb-d4936850312f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970463035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2970463035
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.4197643045
Short name T584
Test name
Test status
Simulation time 48116637 ps
CPU time 0.73 seconds
Started Jun 09 01:12:45 PM PDT 24
Finished Jun 09 01:12:46 PM PDT 24
Peak memory 205676 kb
Host smart-32dc13e7-1369-46c7-878f-142c1161a287
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197643045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
4197643045
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3432696763
Short name T884
Test name
Test status
Simulation time 4541127603 ps
CPU time 10 seconds
Started Jun 09 01:12:42 PM PDT 24
Finished Jun 09 01:12:53 PM PDT 24
Peak memory 233664 kb
Host smart-5fb4db0d-b530-4145-8b24-c663264db154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432696763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3432696763
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.622677263
Short name T362
Test name
Test status
Simulation time 12864855 ps
CPU time 0.76 seconds
Started Jun 09 01:12:35 PM PDT 24
Finished Jun 09 01:12:36 PM PDT 24
Peak memory 206348 kb
Host smart-e4623aa0-99d8-48c6-a675-cb7d9afd4cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622677263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.622677263
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.148067080
Short name T903
Test name
Test status
Simulation time 21691601183 ps
CPU time 76.48 seconds
Started Jun 09 01:12:41 PM PDT 24
Finished Jun 09 01:13:58 PM PDT 24
Peak memory 250064 kb
Host smart-5b862917-d16c-4890-a21b-144487504ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148067080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.148067080
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.408463501
Short name T790
Test name
Test status
Simulation time 41033267735 ps
CPU time 168.86 seconds
Started Jun 09 01:12:43 PM PDT 24
Finished Jun 09 01:15:32 PM PDT 24
Peak memory 251132 kb
Host smart-e01e0602-8352-47fc-9777-92b76a715647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408463501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.408463501
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1485389879
Short name T834
Test name
Test status
Simulation time 152968591588 ps
CPU time 220.53 seconds
Started Jun 09 01:12:40 PM PDT 24
Finished Jun 09 01:16:21 PM PDT 24
Peak memory 256672 kb
Host smart-ac40f729-9849-4b89-9cdb-ae32a9ca24fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485389879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1485389879
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1270771358
Short name T322
Test name
Test status
Simulation time 1106257358 ps
CPU time 20.77 seconds
Started Jun 09 01:12:43 PM PDT 24
Finished Jun 09 01:13:04 PM PDT 24
Peak memory 233560 kb
Host smart-bee19cf8-b1f6-46f5-8c1c-7e9578a9b9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270771358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1270771358
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.4081311393
Short name T851
Test name
Test status
Simulation time 748121280 ps
CPU time 9.24 seconds
Started Jun 09 01:12:36 PM PDT 24
Finished Jun 09 01:12:45 PM PDT 24
Peak memory 225444 kb
Host smart-61d9cc2f-ae92-4197-82b1-0d82f51cb22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081311393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.4081311393
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3949739404
Short name T492
Test name
Test status
Simulation time 310305658 ps
CPU time 7.53 seconds
Started Jun 09 01:12:35 PM PDT 24
Finished Jun 09 01:12:43 PM PDT 24
Peak memory 233480 kb
Host smart-e0d56e56-ae29-49eb-9ba1-f7853a0dbf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949739404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3949739404
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1804705045
Short name T281
Test name
Test status
Simulation time 2803156468 ps
CPU time 10.47 seconds
Started Jun 09 01:12:34 PM PDT 24
Finished Jun 09 01:12:45 PM PDT 24
Peak memory 225408 kb
Host smart-86d9d444-c4ff-46c4-affc-9259c4d3e439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804705045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1804705045
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3984851711
Short name T264
Test name
Test status
Simulation time 5055415937 ps
CPU time 4.18 seconds
Started Jun 09 01:12:33 PM PDT 24
Finished Jun 09 01:12:38 PM PDT 24
Peak memory 233680 kb
Host smart-cd781811-410b-4beb-87fb-e08958e71617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984851711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3984851711
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.884375248
Short name T538
Test name
Test status
Simulation time 1714136420 ps
CPU time 11.02 seconds
Started Jun 09 01:12:40 PM PDT 24
Finished Jun 09 01:12:52 PM PDT 24
Peak memory 220236 kb
Host smart-ac763cfa-b675-4f48-8953-e3b9ce040d2e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=884375248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.884375248
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3264608512
Short name T744
Test name
Test status
Simulation time 52156777678 ps
CPU time 202.6 seconds
Started Jun 09 01:12:43 PM PDT 24
Finished Jun 09 01:16:06 PM PDT 24
Peak memory 266496 kb
Host smart-7950d6ca-c15d-47cf-8f50-0a676fd42e6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264608512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3264608512
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.370122434
Short name T698
Test name
Test status
Simulation time 74837827 ps
CPU time 0.71 seconds
Started Jun 09 01:12:33 PM PDT 24
Finished Jun 09 01:12:35 PM PDT 24
Peak memory 206492 kb
Host smart-f8c194db-73b3-49c1-839e-867c5e01959b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370122434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.370122434
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3188883322
Short name T607
Test name
Test status
Simulation time 1105175484 ps
CPU time 4.9 seconds
Started Jun 09 01:12:36 PM PDT 24
Finished Jun 09 01:12:41 PM PDT 24
Peak memory 217248 kb
Host smart-1f0a6a17-e6ee-4314-975d-34e0bfa72070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188883322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3188883322
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1489740142
Short name T722
Test name
Test status
Simulation time 156137590 ps
CPU time 1.79 seconds
Started Jun 09 01:12:34 PM PDT 24
Finished Jun 09 01:12:36 PM PDT 24
Peak memory 217184 kb
Host smart-a89d3b64-4224-449b-95b9-f6d825d6b759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489740142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1489740142
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1040067359
Short name T901
Test name
Test status
Simulation time 616903882 ps
CPU time 0.85 seconds
Started Jun 09 01:12:36 PM PDT 24
Finished Jun 09 01:12:37 PM PDT 24
Peak memory 206704 kb
Host smart-47dddd5b-6d40-4e8f-94c8-f2ec316b91b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040067359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1040067359
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1527679476
Short name T852
Test name
Test status
Simulation time 829701748 ps
CPU time 5.15 seconds
Started Jun 09 01:12:40 PM PDT 24
Finished Jun 09 01:12:45 PM PDT 24
Peak memory 225268 kb
Host smart-02f9d1c8-cb3f-41f8-8792-b8e640d416a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527679476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1527679476
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.4138842061
Short name T839
Test name
Test status
Simulation time 26434319 ps
CPU time 0.74 seconds
Started Jun 09 01:12:48 PM PDT 24
Finished Jun 09 01:12:49 PM PDT 24
Peak memory 205692 kb
Host smart-4c54ef2d-2519-4fac-b4f9-90e45314cd59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138842061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
4138842061
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3172292805
Short name T878
Test name
Test status
Simulation time 51967097 ps
CPU time 2.65 seconds
Started Jun 09 01:12:43 PM PDT 24
Finished Jun 09 01:12:46 PM PDT 24
Peak memory 233560 kb
Host smart-aba4e9cd-a6d2-4a63-bf83-6498fceeadb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172292805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3172292805
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3083913203
Short name T506
Test name
Test status
Simulation time 63395214 ps
CPU time 0.79 seconds
Started Jun 09 01:12:41 PM PDT 24
Finished Jun 09 01:12:42 PM PDT 24
Peak memory 207700 kb
Host smart-475d0a35-7561-4051-aa60-26d0af82cba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083913203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3083913203
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1286347617
Short name T769
Test name
Test status
Simulation time 45882849188 ps
CPU time 166.32 seconds
Started Jun 09 01:12:42 PM PDT 24
Finished Jun 09 01:15:29 PM PDT 24
Peak memory 250056 kb
Host smart-2e0e752d-39ba-41c4-80f0-fd04bf3776db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286347617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1286347617
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1864044239
Short name T719
Test name
Test status
Simulation time 17222250366 ps
CPU time 53.8 seconds
Started Jun 09 01:12:48 PM PDT 24
Finished Jun 09 01:13:42 PM PDT 24
Peak memory 241904 kb
Host smart-d7e3da0d-135e-4650-9f66-e5951874f46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864044239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1864044239
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3880990819
Short name T438
Test name
Test status
Simulation time 421811601 ps
CPU time 8.52 seconds
Started Jun 09 01:12:42 PM PDT 24
Finished Jun 09 01:12:50 PM PDT 24
Peak memory 225548 kb
Host smart-643b7741-2e5a-42e2-95ff-192993a32e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880990819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3880990819
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1328456141
Short name T213
Test name
Test status
Simulation time 675023256 ps
CPU time 4.95 seconds
Started Jun 09 01:12:44 PM PDT 24
Finished Jun 09 01:12:49 PM PDT 24
Peak memory 233520 kb
Host smart-5fab252c-3994-4f7e-b1ea-fad337761b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328456141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1328456141
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.941722541
Short name T690
Test name
Test status
Simulation time 264296557 ps
CPU time 3.53 seconds
Started Jun 09 01:12:43 PM PDT 24
Finished Jun 09 01:12:47 PM PDT 24
Peak memory 233540 kb
Host smart-6ef7587c-f2b3-46f1-88d3-d27d04d34841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941722541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.941722541
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2452739245
Short name T820
Test name
Test status
Simulation time 6585685534 ps
CPU time 9.57 seconds
Started Jun 09 01:12:41 PM PDT 24
Finished Jun 09 01:12:51 PM PDT 24
Peak memory 225488 kb
Host smart-bb440451-4901-4ae1-9e38-9ac200bf8cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452739245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2452739245
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.830104588
Short name T295
Test name
Test status
Simulation time 43488297017 ps
CPU time 11.89 seconds
Started Jun 09 01:12:42 PM PDT 24
Finished Jun 09 01:12:54 PM PDT 24
Peak memory 233620 kb
Host smart-a4b8a5e1-df90-4068-bb01-9a98cb396a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830104588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.830104588
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.122543574
Short name T580
Test name
Test status
Simulation time 180705508 ps
CPU time 3.79 seconds
Started Jun 09 01:12:42 PM PDT 24
Finished Jun 09 01:12:46 PM PDT 24
Peak memory 220352 kb
Host smart-ac6d25cb-1934-43c4-aa74-25e5e33be28d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=122543574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.122543574
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.4112596841
Short name T775
Test name
Test status
Simulation time 451038035 ps
CPU time 1.15 seconds
Started Jun 09 01:12:47 PM PDT 24
Finished Jun 09 01:12:48 PM PDT 24
Peak memory 208104 kb
Host smart-c0c5ac68-ea09-4591-83ed-efad4c6dc961
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112596841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.4112596841
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.4083645941
Short name T665
Test name
Test status
Simulation time 3575160066 ps
CPU time 25.65 seconds
Started Jun 09 01:12:41 PM PDT 24
Finished Jun 09 01:13:06 PM PDT 24
Peak memory 217256 kb
Host smart-81cafd50-455d-46ab-a9a9-8f6d33a10762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083645941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.4083645941
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3554204797
Short name T408
Test name
Test status
Simulation time 20622013204 ps
CPU time 15.38 seconds
Started Jun 09 01:12:43 PM PDT 24
Finished Jun 09 01:12:58 PM PDT 24
Peak memory 217264 kb
Host smart-4b251c05-dc22-4d46-a7a2-a843b9418d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554204797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3554204797
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3588698540
Short name T794
Test name
Test status
Simulation time 161440442 ps
CPU time 5.78 seconds
Started Jun 09 01:12:42 PM PDT 24
Finished Jun 09 01:12:48 PM PDT 24
Peak memory 217152 kb
Host smart-2ecc0a30-359f-4517-8b55-7a590454d759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588698540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3588698540
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.296702866
Short name T918
Test name
Test status
Simulation time 159343811 ps
CPU time 0.74 seconds
Started Jun 09 01:12:43 PM PDT 24
Finished Jun 09 01:12:44 PM PDT 24
Peak memory 206684 kb
Host smart-08d7ad93-2c6f-4706-8742-321d083b649c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296702866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.296702866
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.949284742
Short name T568
Test name
Test status
Simulation time 1250629891 ps
CPU time 5.88 seconds
Started Jun 09 01:12:40 PM PDT 24
Finished Jun 09 01:12:46 PM PDT 24
Peak memory 234732 kb
Host smart-a96652c9-2bdb-40aa-8bbc-30ac10b90aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949284742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.949284742
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1260024032
Short name T863
Test name
Test status
Simulation time 24065804 ps
CPU time 0.72 seconds
Started Jun 09 01:12:48 PM PDT 24
Finished Jun 09 01:12:49 PM PDT 24
Peak memory 206260 kb
Host smart-7d5ea043-333b-4a35-88b3-1de8c03cfd75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260024032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1260024032
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2352353280
Short name T766
Test name
Test status
Simulation time 2547110117 ps
CPU time 4.5 seconds
Started Jun 09 01:12:46 PM PDT 24
Finished Jun 09 01:12:51 PM PDT 24
Peak memory 233704 kb
Host smart-43b36d80-228b-4a41-b3ad-0d2d9ea856b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352353280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2352353280
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.645045589
Short name T566
Test name
Test status
Simulation time 35125903 ps
CPU time 0.81 seconds
Started Jun 09 01:12:49 PM PDT 24
Finished Jun 09 01:12:51 PM PDT 24
Peak memory 207660 kb
Host smart-926af0a8-04f6-4712-a54c-934846e74975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645045589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.645045589
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2820225501
Short name T409
Test name
Test status
Simulation time 18985577993 ps
CPU time 81.95 seconds
Started Jun 09 01:12:47 PM PDT 24
Finished Jun 09 01:14:09 PM PDT 24
Peak memory 250748 kb
Host smart-39bba56c-a382-45f8-8186-444fddba1d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820225501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2820225501
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.136223225
Short name T947
Test name
Test status
Simulation time 100403231896 ps
CPU time 206.39 seconds
Started Jun 09 01:12:48 PM PDT 24
Finished Jun 09 01:16:14 PM PDT 24
Peak memory 251596 kb
Host smart-4ccf4ba8-771b-4af0-ab39-85a6ec94d2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136223225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.136223225
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.4115674282
Short name T46
Test name
Test status
Simulation time 12503322192 ps
CPU time 93.08 seconds
Started Jun 09 01:12:56 PM PDT 24
Finished Jun 09 01:14:30 PM PDT 24
Peak memory 256896 kb
Host smart-5a7ea4c5-1174-48c3-8319-fd728640776e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115674282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.4115674282
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3063980449
Short name T522
Test name
Test status
Simulation time 96086769 ps
CPU time 4.82 seconds
Started Jun 09 01:12:48 PM PDT 24
Finished Jun 09 01:12:54 PM PDT 24
Peak memory 241728 kb
Host smart-57f6ffe7-ec48-4510-80f3-5442068e8151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063980449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3063980449
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.457685269
Short name T872
Test name
Test status
Simulation time 502619894 ps
CPU time 8.91 seconds
Started Jun 09 01:12:49 PM PDT 24
Finished Jun 09 01:12:58 PM PDT 24
Peak memory 225284 kb
Host smart-87641fc8-cdbf-4b4b-8b86-df85542c7343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457685269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.457685269
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.780617426
Short name T787
Test name
Test status
Simulation time 1187108033 ps
CPU time 8.37 seconds
Started Jun 09 01:12:45 PM PDT 24
Finished Jun 09 01:12:54 PM PDT 24
Peak memory 241540 kb
Host smart-b404644b-1752-4e01-88c5-b8cdd8078374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780617426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.780617426
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1797679925
Short name T661
Test name
Test status
Simulation time 1374407394 ps
CPU time 10.37 seconds
Started Jun 09 01:12:46 PM PDT 24
Finished Jun 09 01:12:56 PM PDT 24
Peak memory 233480 kb
Host smart-8d6f0145-4ac7-4cb1-a5ab-5a330d047818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797679925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1797679925
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3451300144
Short name T916
Test name
Test status
Simulation time 413706005 ps
CPU time 5.09 seconds
Started Jun 09 01:12:45 PM PDT 24
Finished Jun 09 01:12:51 PM PDT 24
Peak memory 233560 kb
Host smart-fa974e0e-e277-4e9d-b33d-3f3d0459897d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451300144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3451300144
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.716251946
Short name T960
Test name
Test status
Simulation time 134752375 ps
CPU time 3.8 seconds
Started Jun 09 01:12:45 PM PDT 24
Finished Jun 09 01:12:49 PM PDT 24
Peak memory 224040 kb
Host smart-34ae7a9d-fc07-4708-a173-85d6cd633083
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=716251946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.716251946
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2165725583
Short name T817
Test name
Test status
Simulation time 68319798 ps
CPU time 0.94 seconds
Started Jun 09 01:12:46 PM PDT 24
Finished Jun 09 01:12:48 PM PDT 24
Peak memory 207560 kb
Host smart-b7349592-3dcb-4388-80ca-e255bcb852f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165725583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2165725583
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2941829100
Short name T437
Test name
Test status
Simulation time 17990185 ps
CPU time 0.71 seconds
Started Jun 09 01:12:47 PM PDT 24
Finished Jun 09 01:12:48 PM PDT 24
Peak memory 206504 kb
Host smart-cc60554f-4003-45ab-a6fd-5220191f0606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941829100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2941829100
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.102548296
Short name T813
Test name
Test status
Simulation time 935768061 ps
CPU time 1.93 seconds
Started Jun 09 01:12:45 PM PDT 24
Finished Jun 09 01:12:48 PM PDT 24
Peak memory 208704 kb
Host smart-76279656-279e-4eda-824f-10e914c91757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102548296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.102548296
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2483533422
Short name T406
Test name
Test status
Simulation time 22832912 ps
CPU time 0.76 seconds
Started Jun 09 01:12:47 PM PDT 24
Finished Jun 09 01:12:48 PM PDT 24
Peak memory 206696 kb
Host smart-c85fb9f9-46ca-4217-a271-a3dc081dff39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483533422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2483533422
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.4097942778
Short name T159
Test name
Test status
Simulation time 444399308 ps
CPU time 0.86 seconds
Started Jun 09 01:12:46 PM PDT 24
Finished Jun 09 01:12:47 PM PDT 24
Peak memory 206924 kb
Host smart-9aaef06c-e630-4ab0-a249-4bc6db060f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097942778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.4097942778
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3710318855
Short name T246
Test name
Test status
Simulation time 318924887 ps
CPU time 3.11 seconds
Started Jun 09 01:12:47 PM PDT 24
Finished Jun 09 01:12:50 PM PDT 24
Peak memory 233536 kb
Host smart-02be8495-2b1f-4a99-90e2-f9b2a24cc04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710318855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3710318855
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1929937057
Short name T357
Test name
Test status
Simulation time 40560937 ps
CPU time 0.73 seconds
Started Jun 09 01:12:54 PM PDT 24
Finished Jun 09 01:12:55 PM PDT 24
Peak memory 206248 kb
Host smart-091096bd-69e7-4571-8f49-ddefd580bcfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929937057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1929937057
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.709339888
Short name T387
Test name
Test status
Simulation time 3587615822 ps
CPU time 14.94 seconds
Started Jun 09 01:12:53 PM PDT 24
Finished Jun 09 01:13:08 PM PDT 24
Peak memory 225476 kb
Host smart-c1645bdd-7411-4472-90a4-c7488ad95bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709339888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.709339888
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3022563888
Short name T560
Test name
Test status
Simulation time 31271558 ps
CPU time 0.79 seconds
Started Jun 09 01:12:49 PM PDT 24
Finished Jun 09 01:12:50 PM PDT 24
Peak memory 207396 kb
Host smart-9a49f126-b311-4d96-bbeb-6d149d92b3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022563888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3022563888
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.31920645
Short name T238
Test name
Test status
Simulation time 470462819 ps
CPU time 8.4 seconds
Started Jun 09 01:12:54 PM PDT 24
Finished Jun 09 01:13:02 PM PDT 24
Peak memory 225372 kb
Host smart-7a3cc3dc-eec4-4889-8bd7-bb39ce3d6e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31920645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.31920645
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1753442148
Short name T801
Test name
Test status
Simulation time 2508505118 ps
CPU time 24.27 seconds
Started Jun 09 01:12:53 PM PDT 24
Finished Jun 09 01:13:17 PM PDT 24
Peak memory 241856 kb
Host smart-3e263535-1610-4f69-ad79-14f18f69815a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753442148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1753442148
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3013241045
Short name T736
Test name
Test status
Simulation time 11565033876 ps
CPU time 101.96 seconds
Started Jun 09 01:12:52 PM PDT 24
Finished Jun 09 01:14:34 PM PDT 24
Peak memory 250100 kb
Host smart-633a5ff7-3811-4208-be08-ee4a6c76bbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013241045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3013241045
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1046951599
Short name T325
Test name
Test status
Simulation time 398437307 ps
CPU time 12.41 seconds
Started Jun 09 01:12:52 PM PDT 24
Finished Jun 09 01:13:05 PM PDT 24
Peak memory 248988 kb
Host smart-86faaf62-4218-401d-b0ce-dc2afc300a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046951599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1046951599
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.657039915
Short name T662
Test name
Test status
Simulation time 546763690 ps
CPU time 9.01 seconds
Started Jun 09 01:12:52 PM PDT 24
Finished Jun 09 01:13:01 PM PDT 24
Peak memory 219452 kb
Host smart-a767f8e0-1743-423d-9716-aed9592db139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657039915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.657039915
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.811129580
Short name T785
Test name
Test status
Simulation time 6458817511 ps
CPU time 71.26 seconds
Started Jun 09 01:12:54 PM PDT 24
Finished Jun 09 01:14:05 PM PDT 24
Peak memory 233612 kb
Host smart-e6b0af4b-477d-4605-b0ed-0d221c978dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811129580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.811129580
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2325506251
Short name T42
Test name
Test status
Simulation time 4610331179 ps
CPU time 15.53 seconds
Started Jun 09 01:12:52 PM PDT 24
Finished Jun 09 01:13:08 PM PDT 24
Peak memory 233580 kb
Host smart-847e12dc-aaa8-4d98-9138-d2e81633adff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325506251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2325506251
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.4214052189
Short name T440
Test name
Test status
Simulation time 2960239560 ps
CPU time 5.96 seconds
Started Jun 09 01:12:53 PM PDT 24
Finished Jun 09 01:13:00 PM PDT 24
Peak memory 225472 kb
Host smart-93337780-5a11-4164-b2cd-5d47d909c5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214052189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.4214052189
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1507298803
Short name T645
Test name
Test status
Simulation time 184982745 ps
CPU time 3.69 seconds
Started Jun 09 01:12:52 PM PDT 24
Finished Jun 09 01:12:56 PM PDT 24
Peak memory 219708 kb
Host smart-65a0daaa-1a1d-4736-b593-925b9f6dc787
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1507298803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1507298803
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1637785741
Short name T149
Test name
Test status
Simulation time 198647813 ps
CPU time 1 seconds
Started Jun 09 01:12:53 PM PDT 24
Finished Jun 09 01:12:54 PM PDT 24
Peak memory 207356 kb
Host smart-22c2db7f-bf9b-44c0-9b57-0972bc851828
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637785741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1637785741
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2991497083
Short name T518
Test name
Test status
Simulation time 11064544848 ps
CPU time 30.04 seconds
Started Jun 09 01:12:47 PM PDT 24
Finished Jun 09 01:13:17 PM PDT 24
Peak memory 217304 kb
Host smart-d4142055-e10d-402f-b6aa-3455a3549f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991497083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2991497083
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4104859108
Short name T496
Test name
Test status
Simulation time 1854400356 ps
CPU time 5.32 seconds
Started Jun 09 01:12:48 PM PDT 24
Finished Jun 09 01:12:53 PM PDT 24
Peak memory 217108 kb
Host smart-23e634ba-9b3b-4620-9f10-db66a9b9df8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104859108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4104859108
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3870409069
Short name T762
Test name
Test status
Simulation time 137367414 ps
CPU time 6.33 seconds
Started Jun 09 01:12:52 PM PDT 24
Finished Jun 09 01:12:59 PM PDT 24
Peak memory 217096 kb
Host smart-e223dfca-938f-4cfb-a06f-05e21af5e897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870409069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3870409069
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1783782152
Short name T83
Test name
Test status
Simulation time 63664107 ps
CPU time 0.72 seconds
Started Jun 09 01:12:53 PM PDT 24
Finished Jun 09 01:12:54 PM PDT 24
Peak memory 206620 kb
Host smart-636b6dbc-8277-4918-8df1-5c43930d1edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783782152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1783782152
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3083338306
Short name T239
Test name
Test status
Simulation time 1707611976 ps
CPU time 5.49 seconds
Started Jun 09 01:12:54 PM PDT 24
Finished Jun 09 01:12:59 PM PDT 24
Peak memory 233492 kb
Host smart-cdb07272-1c0a-4e8e-9140-317444505b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083338306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3083338306
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1113545811
Short name T380
Test name
Test status
Simulation time 19328345 ps
CPU time 0.68 seconds
Started Jun 09 01:12:57 PM PDT 24
Finished Jun 09 01:12:58 PM PDT 24
Peak memory 205616 kb
Host smart-db931616-fa48-4108-9cf2-d90fdb14ffa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113545811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1113545811
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2507546486
Short name T894
Test name
Test status
Simulation time 132573853 ps
CPU time 2.23 seconds
Started Jun 09 01:12:55 PM PDT 24
Finished Jun 09 01:12:58 PM PDT 24
Peak memory 225348 kb
Host smart-7a84a790-5de1-496b-bef4-536b1fcc2e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507546486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2507546486
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2659078616
Short name T808
Test name
Test status
Simulation time 13357989 ps
CPU time 0.74 seconds
Started Jun 09 01:12:53 PM PDT 24
Finished Jun 09 01:12:55 PM PDT 24
Peak memory 206340 kb
Host smart-ede0a17b-a084-4826-84e0-469ca0384d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659078616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2659078616
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2612081169
Short name T411
Test name
Test status
Simulation time 3704960670 ps
CPU time 17.84 seconds
Started Jun 09 01:12:58 PM PDT 24
Finished Jun 09 01:13:16 PM PDT 24
Peak memory 234176 kb
Host smart-0f8b62e9-473b-4685-b0fd-00bad0e39eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612081169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2612081169
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2561239247
Short name T172
Test name
Test status
Simulation time 3021452945 ps
CPU time 66.05 seconds
Started Jun 09 01:12:59 PM PDT 24
Finished Jun 09 01:14:06 PM PDT 24
Peak memory 265740 kb
Host smart-1497828e-827d-4d60-81fe-53a5023142a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561239247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2561239247
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.109899093
Short name T315
Test name
Test status
Simulation time 311820115806 ps
CPU time 391.34 seconds
Started Jun 09 01:13:00 PM PDT 24
Finished Jun 09 01:19:32 PM PDT 24
Peak memory 256372 kb
Host smart-639b1597-0bde-4112-8382-3e57d0482093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109899093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.109899093
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2153432146
Short name T600
Test name
Test status
Simulation time 101615220 ps
CPU time 4.87 seconds
Started Jun 09 01:12:59 PM PDT 24
Finished Jun 09 01:13:04 PM PDT 24
Peak memory 233560 kb
Host smart-8d810228-404d-4f43-b359-5b2a17930c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153432146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2153432146
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3282841390
Short name T825
Test name
Test status
Simulation time 298987165 ps
CPU time 7.66 seconds
Started Jun 09 01:12:57 PM PDT 24
Finished Jun 09 01:13:05 PM PDT 24
Peak memory 233536 kb
Host smart-d761f50e-df9c-4c94-b994-53e65ca66197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282841390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3282841390
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3854148759
Short name T227
Test name
Test status
Simulation time 28921722170 ps
CPU time 46 seconds
Started Jun 09 01:12:58 PM PDT 24
Finished Jun 09 01:13:44 PM PDT 24
Peak memory 231808 kb
Host smart-4cb6c247-f514-4af1-a8c8-317fa734e4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854148759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3854148759
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.4264477181
Short name T818
Test name
Test status
Simulation time 12732682123 ps
CPU time 22.31 seconds
Started Jun 09 01:12:57 PM PDT 24
Finished Jun 09 01:13:19 PM PDT 24
Peak memory 249576 kb
Host smart-3937bbee-e3fe-4099-9415-1686e546a56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264477181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.4264477181
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.4233369842
Short name T862
Test name
Test status
Simulation time 970932006 ps
CPU time 4.87 seconds
Started Jun 09 01:12:53 PM PDT 24
Finished Jun 09 01:12:59 PM PDT 24
Peak memory 233556 kb
Host smart-7d9dc37f-f14b-4407-9445-71ebfc3c9829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233369842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.4233369842
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3673757974
Short name T634
Test name
Test status
Simulation time 4061566756 ps
CPU time 23.2 seconds
Started Jun 09 01:12:58 PM PDT 24
Finished Jun 09 01:13:21 PM PDT 24
Peak memory 220348 kb
Host smart-a622b7d2-180b-4ac2-8e6b-2889ba25af61
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3673757974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3673757974
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3568805846
Short name T581
Test name
Test status
Simulation time 476885044 ps
CPU time 1.05 seconds
Started Jun 09 01:12:58 PM PDT 24
Finished Jun 09 01:12:59 PM PDT 24
Peak memory 208724 kb
Host smart-3abbe21b-1e89-4e87-b143-edcf91ad69f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568805846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3568805846
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3579418840
Short name T347
Test name
Test status
Simulation time 3266310888 ps
CPU time 31.42 seconds
Started Jun 09 01:12:53 PM PDT 24
Finished Jun 09 01:13:25 PM PDT 24
Peak memory 217304 kb
Host smart-9fd10fe9-90b3-45f7-90ae-fbdc0bc75447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579418840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3579418840
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1926549992
Short name T458
Test name
Test status
Simulation time 1029587951 ps
CPU time 3.45 seconds
Started Jun 09 01:12:54 PM PDT 24
Finished Jun 09 01:12:58 PM PDT 24
Peak memory 217168 kb
Host smart-aee8e043-07d6-45da-a833-0e4d8aed334e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926549992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1926549992
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2628381987
Short name T585
Test name
Test status
Simulation time 50641912 ps
CPU time 1.04 seconds
Started Jun 09 01:12:52 PM PDT 24
Finished Jun 09 01:12:53 PM PDT 24
Peak memory 208680 kb
Host smart-95952288-4b49-482b-932c-d36ea51e8124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628381987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2628381987
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3478841479
Short name T716
Test name
Test status
Simulation time 22564401 ps
CPU time 0.75 seconds
Started Jun 09 01:12:53 PM PDT 24
Finished Jun 09 01:12:54 PM PDT 24
Peak memory 206708 kb
Host smart-dbbaf6b0-1847-43cd-90a0-9f1d8a46e73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478841479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3478841479
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.991856123
Short name T618
Test name
Test status
Simulation time 3447555555 ps
CPU time 7.97 seconds
Started Jun 09 01:12:58 PM PDT 24
Finished Jun 09 01:13:06 PM PDT 24
Peak memory 233616 kb
Host smart-0fda71fe-182e-4cce-955f-eb1b2bc41210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991856123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.991856123
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.707467129
Short name T481
Test name
Test status
Simulation time 62133514 ps
CPU time 0.69 seconds
Started Jun 09 01:13:07 PM PDT 24
Finished Jun 09 01:13:08 PM PDT 24
Peak memory 205684 kb
Host smart-dca58708-6a36-4c78-8b77-ca4478780df4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707467129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.707467129
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3974305245
Short name T262
Test name
Test status
Simulation time 508374106 ps
CPU time 2.58 seconds
Started Jun 09 01:13:04 PM PDT 24
Finished Jun 09 01:13:07 PM PDT 24
Peak memory 225304 kb
Host smart-bd3d214f-ed2c-4df3-a232-33a475ffa89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974305245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3974305245
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.126671900
Short name T350
Test name
Test status
Simulation time 65176302 ps
CPU time 0.83 seconds
Started Jun 09 01:12:59 PM PDT 24
Finished Jun 09 01:13:00 PM PDT 24
Peak memory 207396 kb
Host smart-7b0251bb-27c9-47c8-b289-96725d425125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126671900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.126671900
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3061532636
Short name T28
Test name
Test status
Simulation time 202779715895 ps
CPU time 114.2 seconds
Started Jun 09 01:13:03 PM PDT 24
Finished Jun 09 01:14:57 PM PDT 24
Peak memory 249600 kb
Host smart-9de97ef0-82af-4a57-af71-7b669939eefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061532636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3061532636
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1358953500
Short name T503
Test name
Test status
Simulation time 48316110196 ps
CPU time 73.98 seconds
Started Jun 09 01:13:04 PM PDT 24
Finished Jun 09 01:14:19 PM PDT 24
Peak memory 255964 kb
Host smart-5be0608e-33b0-47c2-b489-0ad14c838e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358953500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1358953500
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.218047768
Short name T544
Test name
Test status
Simulation time 2407062341 ps
CPU time 15.96 seconds
Started Jun 09 01:13:04 PM PDT 24
Finished Jun 09 01:13:20 PM PDT 24
Peak memory 224404 kb
Host smart-12913a65-d753-4aa4-a584-d55872b82a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218047768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.218047768
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3523417888
Short name T646
Test name
Test status
Simulation time 9769815069 ps
CPU time 26.78 seconds
Started Jun 09 01:13:05 PM PDT 24
Finished Jun 09 01:13:32 PM PDT 24
Peak memory 241772 kb
Host smart-2ea8b8fd-b9b9-4158-8f3f-00004939d874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523417888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3523417888
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.4275315915
Short name T774
Test name
Test status
Simulation time 59921463 ps
CPU time 2.35 seconds
Started Jun 09 01:12:57 PM PDT 24
Finished Jun 09 01:13:00 PM PDT 24
Peak memory 227524 kb
Host smart-d077aafe-be51-4374-a3a7-b991ff2a3c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275315915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.4275315915
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.523054454
Short name T514
Test name
Test status
Simulation time 727168210 ps
CPU time 15.25 seconds
Started Jun 09 01:12:58 PM PDT 24
Finished Jun 09 01:13:14 PM PDT 24
Peak memory 233488 kb
Host smart-11eae1ac-6a83-4ef9-8933-25f9ed5335af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523054454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.523054454
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3333891583
Short name T714
Test name
Test status
Simulation time 3811805060 ps
CPU time 9.41 seconds
Started Jun 09 01:13:01 PM PDT 24
Finished Jun 09 01:13:11 PM PDT 24
Peak memory 225472 kb
Host smart-c0b8d66c-51f4-4d12-89ba-dda01532f004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333891583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3333891583
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1901666172
Short name T764
Test name
Test status
Simulation time 2389187145 ps
CPU time 13.82 seconds
Started Jun 09 01:13:00 PM PDT 24
Finished Jun 09 01:13:14 PM PDT 24
Peak memory 241192 kb
Host smart-69f5b1d0-60b8-4b29-97cb-af49e06bb211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901666172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1901666172
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3054538923
Short name T52
Test name
Test status
Simulation time 728758896 ps
CPU time 8.4 seconds
Started Jun 09 01:13:03 PM PDT 24
Finished Jun 09 01:13:12 PM PDT 24
Peak memory 224016 kb
Host smart-de5dd72e-1841-4f78-b479-b9b7673022a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3054538923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3054538923
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1244731749
Short name T318
Test name
Test status
Simulation time 80092120389 ps
CPU time 371.49 seconds
Started Jun 09 01:13:02 PM PDT 24
Finished Jun 09 01:19:14 PM PDT 24
Peak memory 258304 kb
Host smart-60aa021c-af7d-47b2-b998-f4fc820ca74c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244731749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1244731749
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3990024367
Short name T340
Test name
Test status
Simulation time 2259186934 ps
CPU time 15.28 seconds
Started Jun 09 01:12:57 PM PDT 24
Finished Jun 09 01:13:12 PM PDT 24
Peak memory 217208 kb
Host smart-356586ad-1f4f-44ca-83e1-a1cfe3661f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990024367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3990024367
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1427462541
Short name T628
Test name
Test status
Simulation time 694200825 ps
CPU time 5.6 seconds
Started Jun 09 01:12:59 PM PDT 24
Finished Jun 09 01:13:05 PM PDT 24
Peak memory 217076 kb
Host smart-b0693457-d87f-4337-b6e1-46fef7e18465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427462541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1427462541
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.389351783
Short name T950
Test name
Test status
Simulation time 37950874 ps
CPU time 1.77 seconds
Started Jun 09 01:12:56 PM PDT 24
Finished Jun 09 01:12:58 PM PDT 24
Peak memory 208912 kb
Host smart-6c894e37-6c5e-4509-bb41-8bf07a5465cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389351783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.389351783
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3185477590
Short name T49
Test name
Test status
Simulation time 136290897 ps
CPU time 0.9 seconds
Started Jun 09 01:12:58 PM PDT 24
Finished Jun 09 01:12:59 PM PDT 24
Peak memory 206700 kb
Host smart-7fab6b7f-1500-44cc-8e55-e845b0155890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185477590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3185477590
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2895707453
Short name T798
Test name
Test status
Simulation time 799285395 ps
CPU time 4.61 seconds
Started Jun 09 01:13:04 PM PDT 24
Finished Jun 09 01:13:09 PM PDT 24
Peak memory 233524 kb
Host smart-25e79165-dab2-47b8-b5f1-5333a6706a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895707453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2895707453
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3020080831
Short name T56
Test name
Test status
Simulation time 22451886 ps
CPU time 0.73 seconds
Started Jun 09 01:09:25 PM PDT 24
Finished Jun 09 01:09:26 PM PDT 24
Peak memory 206248 kb
Host smart-46f89a3f-fc98-4146-90ca-59bdc3d3a1f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020080831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
020080831
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.4209585342
Short name T616
Test name
Test status
Simulation time 88023458 ps
CPU time 2.79 seconds
Started Jun 09 01:09:17 PM PDT 24
Finished Jun 09 01:09:20 PM PDT 24
Peak memory 233476 kb
Host smart-5dadf58d-60d9-4b58-852d-160e42eb9a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209585342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.4209585342
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.931180589
Short name T366
Test name
Test status
Simulation time 44296873 ps
CPU time 0.72 seconds
Started Jun 09 01:09:18 PM PDT 24
Finished Jun 09 01:09:19 PM PDT 24
Peak memory 207732 kb
Host smart-e3445da6-52f8-4bd6-8455-c8be2de8ef46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931180589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.931180589
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2388969033
Short name T664
Test name
Test status
Simulation time 4007208912 ps
CPU time 47.54 seconds
Started Jun 09 01:09:22 PM PDT 24
Finished Jun 09 01:10:10 PM PDT 24
Peak memory 250048 kb
Host smart-257b2ae2-9611-478a-a1cc-2eeeaf609111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388969033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2388969033
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2325411845
Short name T19
Test name
Test status
Simulation time 17191512277 ps
CPU time 59.98 seconds
Started Jun 09 01:09:17 PM PDT 24
Finished Jun 09 01:10:17 PM PDT 24
Peak memory 250132 kb
Host smart-7cf43598-d1db-4945-821c-68026caafbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325411845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2325411845
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1648545493
Short name T75
Test name
Test status
Simulation time 226906935455 ps
CPU time 246.97 seconds
Started Jun 09 01:09:22 PM PDT 24
Finished Jun 09 01:13:29 PM PDT 24
Peak memory 256724 kb
Host smart-ed8d3c6c-6996-4773-995a-7ee0f7ffc27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648545493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1648545493
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.943046062
Short name T789
Test name
Test status
Simulation time 2194085681 ps
CPU time 10.45 seconds
Started Jun 09 01:09:20 PM PDT 24
Finished Jun 09 01:09:31 PM PDT 24
Peak memory 250028 kb
Host smart-5cbc2b3f-176a-4471-9e9e-8404de9008b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943046062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.943046062
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.576641447
Short name T830
Test name
Test status
Simulation time 198134098 ps
CPU time 4.65 seconds
Started Jun 09 01:09:17 PM PDT 24
Finished Jun 09 01:09:22 PM PDT 24
Peak memory 233540 kb
Host smart-6467ac7a-0021-495f-83eb-4a2117740e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576641447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.576641447
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.187342493
Short name T686
Test name
Test status
Simulation time 25399626459 ps
CPU time 63 seconds
Started Jun 09 01:09:17 PM PDT 24
Finished Jun 09 01:10:20 PM PDT 24
Peak memory 232304 kb
Host smart-dda195ab-6d14-439c-88e7-ae167bc740c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187342493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.187342493
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1154346969
Short name T682
Test name
Test status
Simulation time 793320693 ps
CPU time 9.33 seconds
Started Jun 09 01:09:19 PM PDT 24
Finished Jun 09 01:09:29 PM PDT 24
Peak memory 233520 kb
Host smart-b61d2807-bcdf-4d7a-a6dd-ceb67828804e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154346969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1154346969
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3430033982
Short name T6
Test name
Test status
Simulation time 2321605834 ps
CPU time 11 seconds
Started Jun 09 01:09:16 PM PDT 24
Finished Jun 09 01:09:28 PM PDT 24
Peak memory 233664 kb
Host smart-4956c465-b288-4f7d-af21-f64b3b9054c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430033982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3430033982
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3277657704
Short name T39
Test name
Test status
Simulation time 229089225 ps
CPU time 3.51 seconds
Started Jun 09 01:09:17 PM PDT 24
Finished Jun 09 01:09:21 PM PDT 24
Peak memory 220156 kb
Host smart-4c73be27-8813-4195-9fae-6e92cdd96fb8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3277657704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3277657704
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3343724045
Short name T844
Test name
Test status
Simulation time 2246876841 ps
CPU time 26.9 seconds
Started Jun 09 01:09:18 PM PDT 24
Finished Jun 09 01:09:45 PM PDT 24
Peak memory 217240 kb
Host smart-0727c481-7c98-4c7e-8b83-83c9aae4c76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343724045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3343724045
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3066178507
Short name T723
Test name
Test status
Simulation time 299294298 ps
CPU time 1.71 seconds
Started Jun 09 01:09:17 PM PDT 24
Finished Jun 09 01:09:19 PM PDT 24
Peak memory 207972 kb
Host smart-18ab7ce0-6807-49a1-a18c-85c65f7eaf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066178507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3066178507
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.87706511
Short name T343
Test name
Test status
Simulation time 712128458 ps
CPU time 8.8 seconds
Started Jun 09 01:09:21 PM PDT 24
Finished Jun 09 01:09:30 PM PDT 24
Peak memory 217108 kb
Host smart-5391ac9a-5dd4-4d0d-9880-ed5985a5c982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87706511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.87706511
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1634161027
Short name T614
Test name
Test status
Simulation time 88845514 ps
CPU time 0.86 seconds
Started Jun 09 01:09:18 PM PDT 24
Finished Jun 09 01:09:19 PM PDT 24
Peak memory 206696 kb
Host smart-19ed8693-63ac-4801-8a21-ecf8eab8e18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634161027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1634161027
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1291101593
Short name T524
Test name
Test status
Simulation time 57676896 ps
CPU time 2.51 seconds
Started Jun 09 01:09:22 PM PDT 24
Finished Jun 09 01:09:25 PM PDT 24
Peak memory 233568 kb
Host smart-1b6614b1-a72e-4df1-9b96-d1456aac65c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291101593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1291101593
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3133819907
Short name T735
Test name
Test status
Simulation time 100680835 ps
CPU time 0.69 seconds
Started Jun 09 01:09:28 PM PDT 24
Finished Jun 09 01:09:29 PM PDT 24
Peak memory 206256 kb
Host smart-b642ee12-a89e-49fc-9eda-6ea4475d26c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133819907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
133819907
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2850321855
Short name T906
Test name
Test status
Simulation time 1253445245 ps
CPU time 17.09 seconds
Started Jun 09 01:09:22 PM PDT 24
Finished Jun 09 01:09:39 PM PDT 24
Peak memory 225264 kb
Host smart-a30f1841-7670-4ebf-b981-c99b3827bb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850321855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2850321855
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.315726632
Short name T562
Test name
Test status
Simulation time 14757748 ps
CPU time 0.79 seconds
Started Jun 09 01:09:33 PM PDT 24
Finished Jun 09 01:09:34 PM PDT 24
Peak memory 207748 kb
Host smart-cc8508f6-08ba-426b-a75c-f4cd3ba81ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315726632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.315726632
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2497684664
Short name T164
Test name
Test status
Simulation time 23013340382 ps
CPU time 82.03 seconds
Started Jun 09 01:09:23 PM PDT 24
Finished Jun 09 01:10:45 PM PDT 24
Peak memory 239380 kb
Host smart-ed6b2ad2-d88f-4b9f-a434-a42f2a4f26d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497684664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2497684664
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1428132590
Short name T243
Test name
Test status
Simulation time 3938502464 ps
CPU time 97.48 seconds
Started Jun 09 01:09:22 PM PDT 24
Finished Jun 09 01:11:00 PM PDT 24
Peak memory 253712 kb
Host smart-d24f0f26-b454-4139-b160-73283480ae99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428132590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1428132590
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.380650981
Short name T44
Test name
Test status
Simulation time 91690140066 ps
CPU time 185.73 seconds
Started Jun 09 01:09:23 PM PDT 24
Finished Jun 09 01:12:29 PM PDT 24
Peak memory 251972 kb
Host smart-8d511527-716d-4f1b-aff5-dbb930de0611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380650981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
380650981
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2257764840
Short name T456
Test name
Test status
Simulation time 377490592 ps
CPU time 7.11 seconds
Started Jun 09 01:09:33 PM PDT 24
Finished Jun 09 01:09:40 PM PDT 24
Peak memory 233796 kb
Host smart-a1abaef4-dc48-4a9d-b802-20595d0a7470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257764840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2257764840
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3117657763
Short name T468
Test name
Test status
Simulation time 270153509 ps
CPU time 5.79 seconds
Started Jun 09 01:09:23 PM PDT 24
Finished Jun 09 01:09:29 PM PDT 24
Peak memory 233536 kb
Host smart-9a4d8bcd-b7e5-4735-bff7-e522012d53ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117657763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3117657763
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2822321866
Short name T611
Test name
Test status
Simulation time 466130676 ps
CPU time 9.07 seconds
Started Jun 09 01:09:35 PM PDT 24
Finished Jun 09 01:09:45 PM PDT 24
Peak memory 233520 kb
Host smart-1d1943e1-820d-4b0a-930f-f75668180ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822321866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2822321866
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3261800410
Short name T732
Test name
Test status
Simulation time 107912353 ps
CPU time 2.51 seconds
Started Jun 09 01:09:35 PM PDT 24
Finished Jun 09 01:09:38 PM PDT 24
Peak memory 233576 kb
Host smart-8a4681cb-1209-48e8-9852-1fe8de3d1df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261800410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3261800410
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.873969962
Short name T914
Test name
Test status
Simulation time 1253415544 ps
CPU time 7.36 seconds
Started Jun 09 01:09:21 PM PDT 24
Finished Jun 09 01:09:29 PM PDT 24
Peak memory 233540 kb
Host smart-b7ba0875-7b06-4104-807c-954a925a1ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873969962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.873969962
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3062070871
Short name T655
Test name
Test status
Simulation time 381028565 ps
CPU time 3.88 seconds
Started Jun 09 01:09:21 PM PDT 24
Finished Jun 09 01:09:26 PM PDT 24
Peak memory 223432 kb
Host smart-3dade17d-0060-4d96-9cf8-667f4468e94b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3062070871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3062070871
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3010717140
Short name T530
Test name
Test status
Simulation time 14267536 ps
CPU time 0.73 seconds
Started Jun 09 01:09:19 PM PDT 24
Finished Jun 09 01:09:20 PM PDT 24
Peak memory 206740 kb
Host smart-b75c6fb1-ae29-49e9-8745-6cdf6ba6ec7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010717140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3010717140
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3887561242
Short name T846
Test name
Test status
Simulation time 7966538034 ps
CPU time 9.05 seconds
Started Jun 09 01:09:22 PM PDT 24
Finished Jun 09 01:09:31 PM PDT 24
Peak memory 217284 kb
Host smart-d7581726-d191-4ab8-956f-3a45a438cceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887561242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3887561242
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.250866023
Short name T470
Test name
Test status
Simulation time 42185247 ps
CPU time 0.94 seconds
Started Jun 09 01:09:33 PM PDT 24
Finished Jun 09 01:09:34 PM PDT 24
Peak memory 207808 kb
Host smart-4fb033f2-02e5-4deb-9cdd-e562c882192f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250866023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.250866023
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.544689806
Short name T920
Test name
Test status
Simulation time 21215429 ps
CPU time 0.82 seconds
Started Jun 09 01:09:25 PM PDT 24
Finished Jun 09 01:09:26 PM PDT 24
Peak memory 206660 kb
Host smart-b12ba200-630f-4aab-9bc0-606c2cf1b4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544689806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.544689806
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1216460496
Short name T843
Test name
Test status
Simulation time 5001616110 ps
CPU time 7.03 seconds
Started Jun 09 01:09:23 PM PDT 24
Finished Jun 09 01:09:30 PM PDT 24
Peak memory 241236 kb
Host smart-98f5a897-4bc9-4166-b6ac-5d6d5ac1cfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216460496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1216460496
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1401207242
Short name T742
Test name
Test status
Simulation time 11695743 ps
CPU time 0.71 seconds
Started Jun 09 01:09:33 PM PDT 24
Finished Jun 09 01:09:34 PM PDT 24
Peak memory 206272 kb
Host smart-d1028647-dd9d-45bd-b192-3abfa95a1686
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401207242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
401207242
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1087131201
Short name T588
Test name
Test status
Simulation time 1216280788 ps
CPU time 9.93 seconds
Started Jun 09 01:09:42 PM PDT 24
Finished Jun 09 01:09:52 PM PDT 24
Peak memory 225296 kb
Host smart-fb9e04c2-a0a7-4577-a06f-8cd4202b0a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087131201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1087131201
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1999533797
Short name T392
Test name
Test status
Simulation time 57812893 ps
CPU time 0.75 seconds
Started Jun 09 01:09:28 PM PDT 24
Finished Jun 09 01:09:29 PM PDT 24
Peak memory 207712 kb
Host smart-3fc16c97-aa05-4436-a5d6-763f4c9c14bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999533797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1999533797
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1001993526
Short name T174
Test name
Test status
Simulation time 12927874064 ps
CPU time 45.87 seconds
Started Jun 09 01:09:33 PM PDT 24
Finished Jun 09 01:10:19 PM PDT 24
Peak memory 237656 kb
Host smart-915737db-efb4-4d1a-9c9b-61d2433c57c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001993526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1001993526
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.857760157
Short name T158
Test name
Test status
Simulation time 159772312491 ps
CPU time 309.06 seconds
Started Jun 09 01:09:35 PM PDT 24
Finished Jun 09 01:14:44 PM PDT 24
Peak memory 250112 kb
Host smart-c5e12ac6-8ec1-460a-ae20-66a2c151eb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857760157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.857760157
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.78207166
Short name T591
Test name
Test status
Simulation time 6592238457 ps
CPU time 28.19 seconds
Started Jun 09 01:09:33 PM PDT 24
Finished Jun 09 01:10:01 PM PDT 24
Peak memory 250048 kb
Host smart-d79f24a6-c847-4404-ad98-aea1b1a631bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78207166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.78207166
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2121778932
Short name T193
Test name
Test status
Simulation time 68195782 ps
CPU time 3.12 seconds
Started Jun 09 01:09:32 PM PDT 24
Finished Jun 09 01:09:35 PM PDT 24
Peak memory 233532 kb
Host smart-2c07bf6e-4669-4121-865c-15dac513a909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121778932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2121778932
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2086169958
Short name T715
Test name
Test status
Simulation time 910219149 ps
CPU time 10.91 seconds
Started Jun 09 01:09:35 PM PDT 24
Finished Jun 09 01:09:46 PM PDT 24
Peak memory 225264 kb
Host smart-383bbee9-45da-4a29-9eb2-5b8ba5ba4d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086169958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2086169958
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2527862325
Short name T812
Test name
Test status
Simulation time 5000377846 ps
CPU time 9.07 seconds
Started Jun 09 01:09:28 PM PDT 24
Finished Jun 09 01:09:37 PM PDT 24
Peak memory 233664 kb
Host smart-a97885e6-b361-4456-95c5-bbf9a88b4333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527862325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2527862325
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2962628637
Short name T370
Test name
Test status
Simulation time 92506300 ps
CPU time 2.26 seconds
Started Jun 09 01:09:29 PM PDT 24
Finished Jun 09 01:09:31 PM PDT 24
Peak memory 223896 kb
Host smart-8188d201-e0eb-4083-bbb8-16b1e9cf5dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962628637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2962628637
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3292790457
Short name T816
Test name
Test status
Simulation time 4114912432 ps
CPU time 24.91 seconds
Started Jun 09 01:09:35 PM PDT 24
Finished Jun 09 01:10:00 PM PDT 24
Peak memory 220840 kb
Host smart-6de5be61-fb9d-4e49-8f06-f745c0aa003e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3292790457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3292790457
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.4040704411
Short name T854
Test name
Test status
Simulation time 13947603253 ps
CPU time 66.87 seconds
Started Jun 09 01:09:36 PM PDT 24
Finished Jun 09 01:10:43 PM PDT 24
Peak memory 236128 kb
Host smart-643bae99-1999-459d-9770-56bee5c58912
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040704411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.4040704411
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3669532247
Short name T922
Test name
Test status
Simulation time 27806745607 ps
CPU time 36.87 seconds
Started Jun 09 01:09:27 PM PDT 24
Finished Jun 09 01:10:05 PM PDT 24
Peak memory 217304 kb
Host smart-e699a380-a3b8-48ae-982f-2e151e4ecbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669532247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3669532247
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1942524042
Short name T861
Test name
Test status
Simulation time 21886313462 ps
CPU time 10.25 seconds
Started Jun 09 01:09:28 PM PDT 24
Finished Jun 09 01:09:39 PM PDT 24
Peak memory 217244 kb
Host smart-23908408-913b-4f71-8a1e-bfb41b272824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942524042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1942524042
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2140230561
Short name T2
Test name
Test status
Simulation time 201075027 ps
CPU time 1.16 seconds
Started Jun 09 01:09:28 PM PDT 24
Finished Jun 09 01:09:29 PM PDT 24
Peak memory 208836 kb
Host smart-92982aa5-c9cf-4770-8d49-15971efd5f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140230561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2140230561
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.269858798
Short name T832
Test name
Test status
Simulation time 44493145 ps
CPU time 0.81 seconds
Started Jun 09 01:09:27 PM PDT 24
Finished Jun 09 01:09:29 PM PDT 24
Peak memory 206704 kb
Host smart-4a591c81-2033-45f2-8465-76692bc45485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269858798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.269858798
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.239731480
Short name T649
Test name
Test status
Simulation time 63670066 ps
CPU time 2.13 seconds
Started Jun 09 01:09:40 PM PDT 24
Finished Jun 09 01:09:42 PM PDT 24
Peak memory 224812 kb
Host smart-36b92de6-e2ad-4b2e-8204-ba6b21ff11c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239731480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.239731480
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3558785988
Short name T899
Test name
Test status
Simulation time 31989984 ps
CPU time 0.68 seconds
Started Jun 09 01:09:41 PM PDT 24
Finished Jun 09 01:09:42 PM PDT 24
Peak memory 206272 kb
Host smart-20df1c2a-96e1-473d-b464-1a8abaf22071
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558785988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
558785988
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2895064884
Short name T35
Test name
Test status
Simulation time 638402589 ps
CPU time 2.91 seconds
Started Jun 09 01:09:40 PM PDT 24
Finished Jun 09 01:09:43 PM PDT 24
Peak memory 225352 kb
Host smart-72a4418a-b299-40bc-bfd8-0da1d63430c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895064884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2895064884
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3522041888
Short name T353
Test name
Test status
Simulation time 72988515 ps
CPU time 0.85 seconds
Started Jun 09 01:09:34 PM PDT 24
Finished Jun 09 01:09:36 PM PDT 24
Peak memory 207716 kb
Host smart-b27323fb-a4ae-49d4-a156-ace2bd61b06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522041888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3522041888
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1865698855
Short name T26
Test name
Test status
Simulation time 6894649190 ps
CPU time 51.11 seconds
Started Jun 09 01:09:39 PM PDT 24
Finished Jun 09 01:10:31 PM PDT 24
Peak memory 250028 kb
Host smart-1ea46baf-985c-4070-96cd-c304ec9b9768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865698855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1865698855
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.879859380
Short name T549
Test name
Test status
Simulation time 3637027134 ps
CPU time 16.95 seconds
Started Jun 09 01:09:41 PM PDT 24
Finished Jun 09 01:09:58 PM PDT 24
Peak memory 237528 kb
Host smart-e9b6ca86-91be-41bf-98dd-d2cc313a5cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879859380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.879859380
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2926314568
Short name T491
Test name
Test status
Simulation time 16474503052 ps
CPU time 128.94 seconds
Started Jun 09 01:09:42 PM PDT 24
Finished Jun 09 01:11:51 PM PDT 24
Peak memory 249872 kb
Host smart-1b97d79d-fad8-4c96-aa27-9ce7f1512c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926314568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2926314568
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1116571253
Short name T745
Test name
Test status
Simulation time 1502459839 ps
CPU time 8.56 seconds
Started Jun 09 01:09:33 PM PDT 24
Finished Jun 09 01:09:42 PM PDT 24
Peak memory 233760 kb
Host smart-9443e951-3a6c-41d8-87c9-9384774d3d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116571253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1116571253
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3652202575
Short name T595
Test name
Test status
Simulation time 1598753495 ps
CPU time 13.61 seconds
Started Jun 09 01:09:36 PM PDT 24
Finished Jun 09 01:09:50 PM PDT 24
Peak memory 225228 kb
Host smart-61c8edb8-0107-476d-8559-d99a181b007d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652202575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3652202575
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2012772094
Short name T652
Test name
Test status
Simulation time 1316608743 ps
CPU time 16.14 seconds
Started Jun 09 01:09:35 PM PDT 24
Finished Jun 09 01:09:52 PM PDT 24
Peak memory 233524 kb
Host smart-d4a39bce-0895-46bc-a9bb-27d2784c737e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012772094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2012772094
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2942715038
Short name T241
Test name
Test status
Simulation time 4984991552 ps
CPU time 15.45 seconds
Started Jun 09 01:09:34 PM PDT 24
Finished Jun 09 01:09:50 PM PDT 24
Peak memory 241196 kb
Host smart-2c162651-c003-4e2d-b7ac-393fe8089ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942715038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2942715038
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.4017667998
Short name T876
Test name
Test status
Simulation time 35069044426 ps
CPU time 28.86 seconds
Started Jun 09 01:09:33 PM PDT 24
Finished Jun 09 01:10:03 PM PDT 24
Peak memory 241608 kb
Host smart-ff21e3b2-a21b-43c4-981f-2a2042518b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017667998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.4017667998
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3051509530
Short name T640
Test name
Test status
Simulation time 1344747476 ps
CPU time 6.08 seconds
Started Jun 09 01:09:33 PM PDT 24
Finished Jun 09 01:09:40 PM PDT 24
Peak memory 222872 kb
Host smart-1fd0e645-c3cf-4543-bbe3-ffa67b82472a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3051509530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3051509530
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3651966980
Short name T153
Test name
Test status
Simulation time 124241252971 ps
CPU time 272.36 seconds
Started Jun 09 01:09:41 PM PDT 24
Finished Jun 09 01:14:13 PM PDT 24
Peak memory 266460 kb
Host smart-140de3a9-5d1d-40c6-8b19-23ea52dca538
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651966980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3651966980
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1743417811
Short name T776
Test name
Test status
Simulation time 5769991736 ps
CPU time 36.47 seconds
Started Jun 09 01:09:34 PM PDT 24
Finished Jun 09 01:10:11 PM PDT 24
Peak memory 217240 kb
Host smart-75172253-8ca6-46f8-833b-dd63433a92fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743417811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1743417811
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.406216043
Short name T610
Test name
Test status
Simulation time 18914402387 ps
CPU time 16.57 seconds
Started Jun 09 01:09:32 PM PDT 24
Finished Jun 09 01:09:49 PM PDT 24
Peak memory 217176 kb
Host smart-a6242bbb-d1b2-46a3-94b8-35f63e22a792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406216043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.406216043
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.539116216
Short name T685
Test name
Test status
Simulation time 1573128813 ps
CPU time 5.78 seconds
Started Jun 09 01:09:35 PM PDT 24
Finished Jun 09 01:09:41 PM PDT 24
Peak memory 217164 kb
Host smart-65d6c256-f923-4b87-a8f4-8ef520ab11ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539116216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.539116216
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2413715979
Short name T354
Test name
Test status
Simulation time 65900250 ps
CPU time 0.72 seconds
Started Jun 09 01:09:33 PM PDT 24
Finished Jun 09 01:09:34 PM PDT 24
Peak memory 206700 kb
Host smart-67e18590-ff8f-4dfb-a772-ebe7d5149684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413715979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2413715979
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1692669547
Short name T257
Test name
Test status
Simulation time 2260240657 ps
CPU time 7.87 seconds
Started Jun 09 01:09:41 PM PDT 24
Finished Jun 09 01:09:49 PM PDT 24
Peak memory 225448 kb
Host smart-07234bce-2f3e-46a9-b601-53a37b6e9cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692669547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1692669547
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1200396800
Short name T679
Test name
Test status
Simulation time 15015681 ps
CPU time 0.73 seconds
Started Jun 09 01:09:45 PM PDT 24
Finished Jun 09 01:09:46 PM PDT 24
Peak memory 205696 kb
Host smart-1bca03fe-1057-49fb-be20-6db5c714174b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200396800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
200396800
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.47145513
Short name T128
Test name
Test status
Simulation time 157618810 ps
CPU time 3 seconds
Started Jun 09 01:09:46 PM PDT 24
Finished Jun 09 01:09:49 PM PDT 24
Peak memory 225344 kb
Host smart-90f0d586-9084-4af8-9e4e-a8e2bb374575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47145513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.47145513
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1676545476
Short name T552
Test name
Test status
Simulation time 35593823 ps
CPU time 0.84 seconds
Started Jun 09 01:09:39 PM PDT 24
Finished Jun 09 01:09:40 PM PDT 24
Peak memory 206696 kb
Host smart-ffce1980-e142-4876-b748-f9fabf6ceb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676545476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1676545476
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1972455532
Short name T361
Test name
Test status
Simulation time 39818980 ps
CPU time 0.88 seconds
Started Jun 09 01:09:45 PM PDT 24
Finished Jun 09 01:09:47 PM PDT 24
Peak memory 216896 kb
Host smart-246901df-5089-45a2-9b58-12fa8157c875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972455532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1972455532
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3139465656
Short name T302
Test name
Test status
Simulation time 10735866077 ps
CPU time 75.82 seconds
Started Jun 09 01:09:45 PM PDT 24
Finished Jun 09 01:11:01 PM PDT 24
Peak memory 267436 kb
Host smart-be5a8ff8-8366-4c41-9da5-cf27771ce7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139465656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3139465656
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.4087134574
Short name T893
Test name
Test status
Simulation time 6382960453 ps
CPU time 25.58 seconds
Started Jun 09 01:09:45 PM PDT 24
Finished Jun 09 01:10:11 PM PDT 24
Peak memory 241928 kb
Host smart-dec8b8e2-864e-448b-b43d-cb04b4899572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087134574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.4087134574
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3024503766
Short name T321
Test name
Test status
Simulation time 827970603 ps
CPU time 14.37 seconds
Started Jun 09 01:09:47 PM PDT 24
Finished Jun 09 01:10:02 PM PDT 24
Peak memory 233556 kb
Host smart-731ed6df-e29c-4a9d-89f4-0eab52353113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024503766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3024503766
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.507941613
Short name T519
Test name
Test status
Simulation time 2113474133 ps
CPU time 8.81 seconds
Started Jun 09 01:09:42 PM PDT 24
Finished Jun 09 01:09:51 PM PDT 24
Peak memory 225036 kb
Host smart-668273c0-2682-467a-b660-3dd42f248730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507941613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.507941613
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3272344719
Short name T542
Test name
Test status
Simulation time 7434767139 ps
CPU time 43.46 seconds
Started Jun 09 01:09:39 PM PDT 24
Finished Jun 09 01:10:23 PM PDT 24
Peak memory 250060 kb
Host smart-0ffa74c1-5bd4-494a-bffb-738758821e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272344719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3272344719
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1990925914
Short name T303
Test name
Test status
Simulation time 1952670001 ps
CPU time 8.02 seconds
Started Jun 09 01:09:39 PM PDT 24
Finished Jun 09 01:09:48 PM PDT 24
Peak memory 225284 kb
Host smart-2b544e51-a790-4056-8a10-25800f3df9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990925914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1990925914
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2853375313
Short name T828
Test name
Test status
Simulation time 4641306203 ps
CPU time 14.79 seconds
Started Jun 09 01:09:41 PM PDT 24
Finished Jun 09 01:09:56 PM PDT 24
Peak memory 225488 kb
Host smart-0f240a73-ae88-4630-b9ee-f66f796655a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853375313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2853375313
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2131872436
Short name T885
Test name
Test status
Simulation time 3002409610 ps
CPU time 12.07 seconds
Started Jun 09 01:09:44 PM PDT 24
Finished Jun 09 01:09:57 PM PDT 24
Peak memory 221468 kb
Host smart-6fa38735-fd5d-4465-a6e5-6d623a8eb36c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2131872436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2131872436
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.459186074
Short name T154
Test name
Test status
Simulation time 35192800397 ps
CPU time 73.09 seconds
Started Jun 09 01:09:46 PM PDT 24
Finished Jun 09 01:10:59 PM PDT 24
Peak memory 266556 kb
Host smart-1036ea0d-742d-40d1-a4eb-17951cdba54f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459186074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.459186074
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.123886358
Short name T515
Test name
Test status
Simulation time 6956438054 ps
CPU time 6.87 seconds
Started Jun 09 01:09:39 PM PDT 24
Finished Jun 09 01:09:46 PM PDT 24
Peak memory 217240 kb
Host smart-6886d60d-923e-4a58-b170-9d4308f9d6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123886358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.123886358
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.157991073
Short name T677
Test name
Test status
Simulation time 2243312140 ps
CPU time 3.04 seconds
Started Jun 09 01:09:39 PM PDT 24
Finished Jun 09 01:09:43 PM PDT 24
Peak memory 217048 kb
Host smart-05cb2202-a61e-4d9b-a18f-1a49d7e93085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157991073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.157991073
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1892757025
Short name T367
Test name
Test status
Simulation time 321280439 ps
CPU time 6.48 seconds
Started Jun 09 01:09:42 PM PDT 24
Finished Jun 09 01:09:49 PM PDT 24
Peak memory 217116 kb
Host smart-d0125010-bb46-431f-961a-747d1d6839a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892757025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1892757025
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.831610990
Short name T754
Test name
Test status
Simulation time 34916351 ps
CPU time 0.78 seconds
Started Jun 09 01:09:41 PM PDT 24
Finished Jun 09 01:09:42 PM PDT 24
Peak memory 206704 kb
Host smart-384ac1e4-0655-4767-921b-e014af8bb0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831610990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.831610990
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3058463314
Short name T847
Test name
Test status
Simulation time 2002782244 ps
CPU time 6.74 seconds
Started Jun 09 01:09:44 PM PDT 24
Finished Jun 09 01:09:52 PM PDT 24
Peak memory 225340 kb
Host smart-bb98c277-d8df-4857-a44e-7ee1fc56918f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058463314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3058463314
Directory /workspace/9.spi_device_upload/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%