Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3170929	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3664198

1

T1

882

T2

196

T3

888

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3896875	1			T1	4		T2	1		T3	3
values[0x0]	1467981	1			T1	445		T2	130		T3	453
values[0x1]	1470271	1			T1	437		T2	113		T3	435

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2264120	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4571007

1

T1

883

T2

204

T3

889

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24395	1			T5	14		T7	57		T12	4
valid_sources[0x01]	23869	1			T5	5		T7	70		T12	6
valid_sources[0x02]	25864	1			T2	1		T5	6		T7	61
valid_sources[0x03]	26797	1			T5	11		T6	446		T7	67
valid_sources[0x04]	24852	1			T2	2		T5	11		T7	43
valid_sources[0x05]	23797	1			T2	6		T5	9		T7	61
valid_sources[0x06]	26245	1			T2	1		T5	9		T7	55
valid_sources[0x07]	29568	1			T5	10		T7	66		T13	9
valid_sources[0x08]	27461	1			T5	18		T7	67		T12	8
valid_sources[0x09]	27763	1			T5	7		T7	42		T12	5
valid_sources[0x0a]	25590	1			T5	19		T7	59		T12	7
valid_sources[0x0b]	25718	1			T5	25		T7	63		T12	4
valid_sources[0x0c]	29114	1			T5	8		T7	49		T12	7
valid_sources[0x0d]	25724	1			T5	6		T7	64		T12	5
valid_sources[0x0e]	25573	1			T5	7		T7	54		T12	2
valid_sources[0x0f]	31373	1			T2	1		T5	5		T7	56
valid_sources[0x10]	26313	1			T5	15		T7	51		T12	4
valid_sources[0x11]	26248	1			T5	7		T7	58		T12	7
valid_sources[0x12]	24902	1			T5	20		T7	57		T12	1
valid_sources[0x13]	30957	1			T5	9		T6	897		T7	58
valid_sources[0x14]	25461	1			T5	4		T7	55		T12	3
valid_sources[0x15]	35412	1			T5	12		T7	43		T12	2
valid_sources[0x16]	31265	1			T5	14		T7	59		T10	202
valid_sources[0x17]	25999	1			T5	8		T7	59		T12	2
valid_sources[0x18]	25964	1			T5	4		T7	76		T9	3
valid_sources[0x19]	26209	1			T5	12		T7	59		T12	6
valid_sources[0x1a]	24896	1			T5	15		T7	59		T12	3
valid_sources[0x1b]	28851	1			T5	3		T7	60		T12	7
valid_sources[0x1c]	32225	1			T5	14		T7	48		T12	2
valid_sources[0x1d]	31088	1			T5	21		T7	56		T13	8
valid_sources[0x1e]	39285	1			T5	8		T6	31		T7	59
valid_sources[0x1f]	26661	1			T5	19		T6	158		T7	64
valid_sources[0x20]	25367	1			T5	10		T7	65		T12	3
valid_sources[0x21]	26513	1			T5	17		T7	49		T13	2
valid_sources[0x22]	23660	1			T5	22		T7	73		T11	1
valid_sources[0x23]	28592	1			T2	1		T5	14		T6	25
valid_sources[0x24]	27444	1			T5	6		T7	46		T12	1
valid_sources[0x25]	29920	1			T5	1		T7	68		T12	4
valid_sources[0x26]	25682	1			T5	5		T7	67		T9	2
valid_sources[0x27]	36987	1			T5	13		T7	60		T12	3
valid_sources[0x28]	24815	1			T2	3		T5	10		T7	54
valid_sources[0x29]	27862	1			T2	4		T5	17		T7	73
valid_sources[0x2a]	24629	1			T5	15		T7	54		T12	1
valid_sources[0x2b]	25884	1			T5	3		T7	52		T9	9
valid_sources[0x2c]	24937	1			T5	4		T7	48		T12	3
valid_sources[0x2d]	25705	1			T5	9		T7	76		T12	4
valid_sources[0x2e]	27509	1			T5	14		T7	60		T12	9
valid_sources[0x2f]	25845	1			T5	15		T7	58		T11	258
valid_sources[0x30]	26971	1			T5	8		T7	50		T12	6
valid_sources[0x31]	26246	1			T2	9		T5	5		T7	71
valid_sources[0x32]	26354	1			T2	6		T5	15		T7	52
valid_sources[0x33]	29558	1			T5	16		T7	86		T12	2
valid_sources[0x34]	24340	1			T5	7		T7	63		T12	1
valid_sources[0x35]	24980	1			T5	7		T7	71		T12	4
valid_sources[0x36]	24785	1			T5	14		T7	65		T12	1
valid_sources[0x37]	27559	1			T5	12		T7	60		T12	2
valid_sources[0x38]	26474	1			T5	19		T7	56		T9	1
valid_sources[0x39]	25819	1			T2	4		T5	4		T7	53
valid_sources[0x3a]	27656	1			T2	3		T5	16		T7	59
valid_sources[0x3b]	27305	1			T5	6		T7	63		T12	4
valid_sources[0x3c]	27644	1			T5	12		T7	51		T12	1
valid_sources[0x3d]	25255	1			T2	2		T5	14		T7	41
valid_sources[0x3e]	25301	1			T5	21		T7	50		T12	2
valid_sources[0x3f]	24932	1			T5	4		T7	53		T12	7
valid_sources[0x40]	27544	1			T5	5		T7	51		T12	6
valid_sources[0x41]	26542	1			T5	12		T7	63		T12	5
valid_sources[0x42]	27538	1			T5	13		T6	293		T7	57
valid_sources[0x43]	26652	1			T5	17		T7	67		T12	4
valid_sources[0x44]	30265	1			T5	5		T7	52		T12	2
valid_sources[0x45]	29807	1			T5	6		T7	71		T12	2
valid_sources[0x46]	27623	1			T2	7		T5	19		T7	68
valid_sources[0x47]	26266	1			T5	22		T7	78		T11	1409
valid_sources[0x48]	24123	1			T2	3		T5	5		T7	59
valid_sources[0x49]	25008	1			T5	11		T7	72		T12	7
valid_sources[0x4a]	23832	1			T5	9		T7	53		T12	3
valid_sources[0x4b]	26883	1			T5	6		T7	66		T12	1
valid_sources[0x4c]	27475	1			T1	450		T5	9		T7	67
valid_sources[0x4d]	25072	1			T5	7		T7	58		T12	2
valid_sources[0x4e]	26728	1			T5	11		T7	71		T11	983
valid_sources[0x4f]	30772	1			T5	27		T7	62		T8	6388
valid_sources[0x50]	28474	1			T2	9		T5	13		T7	40
valid_sources[0x51]	23892	1			T2	1		T5	9		T6	208
valid_sources[0x52]	43980	1			T5	8		T7	50		T11	258
valid_sources[0x53]	25758	1			T5	8		T7	67		T12	2
valid_sources[0x54]	26668	1			T5	7		T7	65		T10	3
valid_sources[0x55]	24417	1			T2	4		T5	3		T7	73
valid_sources[0x56]	24229	1			T2	3		T5	9		T7	49
valid_sources[0x57]	23397	1			T2	8		T5	11		T7	47
valid_sources[0x58]	25327	1			T2	2		T5	14		T7	71
valid_sources[0x59]	29713	1			T5	18		T7	53		T12	3
valid_sources[0x5a]	29072	1			T5	11		T6	3		T7	62
valid_sources[0x5b]	25731	1			T2	25		T5	13		T7	53
valid_sources[0x5c]	26930	1			T5	4		T7	51		T12	2
valid_sources[0x5d]	24976	1			T5	12		T7	51		T12	8
valid_sources[0x5e]	28451	1			T2	5		T5	5		T7	65
valid_sources[0x5f]	25294	1			T5	12		T7	67		T12	1
valid_sources[0x60]	25437	1			T5	13		T7	68		T12	2
valid_sources[0x61]	25529	1			T2	8		T5	11		T7	59
valid_sources[0x62]	27851	1			T5	13		T6	113		T7	64
valid_sources[0x63]	26425	1			T5	9		T7	65		T12	3
valid_sources[0x64]	25134	1			T5	4		T7	44		T12	6
valid_sources[0x65]	24210	1			T2	2		T5	10		T7	61
valid_sources[0x66]	24659	1			T5	13		T7	51		T11	353
valid_sources[0x67]	27340	1			T5	6		T7	46		T12	2
valid_sources[0x68]	25424	1			T5	6		T7	62		T12	4
valid_sources[0x69]	23990	1			T5	7		T7	47		T12	1
valid_sources[0x6a]	31153	1			T5	16		T7	55		T12	3
valid_sources[0x6b]	26018	1			T5	13		T7	54		T12	6
valid_sources[0x6c]	26219	1			T5	7		T7	59		T12	3
valid_sources[0x6d]	31491	1			T5	11		T7	46		T36	3
valid_sources[0x6e]	25658	1			T5	2		T7	58		T12	5
valid_sources[0x6f]	26113	1			T5	23		T7	59		T12	6
valid_sources[0x70]	27714	1			T2	5		T5	11		T7	63
valid_sources[0x71]	26688	1			T5	6		T7	51		T12	6
valid_sources[0x72]	29542	1			T5	9		T7	68		T12	5
valid_sources[0x73]	32150	1			T5	8		T7	62		T10	1058
valid_sources[0x74]	28332	1			T5	6		T7	55		T12	2
valid_sources[0x75]	27914	1			T5	7		T7	72		T13	3
valid_sources[0x76]	28467	1			T5	5		T7	55		T12	2
valid_sources[0x77]	26991	1			T5	5		T7	48		T12	2
valid_sources[0x78]	26992	1			T5	5		T7	42		T12	2
valid_sources[0x79]	25849	1			T5	5		T6	1		T7	59
valid_sources[0x7a]	29036	1			T5	25		T7	53		T12	3
valid_sources[0x7b]	24993	1			T5	6		T6	1		T7	78
valid_sources[0x7c]	25175	1			T5	8		T7	77		T12	5
valid_sources[0x7d]	25332	1			T2	3		T5	6		T7	62
valid_sources[0x7e]	23542	1			T5	9		T7	57		T13	7
valid_sources[0x7f]	27141	1			T5	6		T7	66		T12	4
valid_sources[0x80]	24888	1			T5	11		T7	64		T11	918

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1011742

1

T1

3

T2

1

T3

2

values[0x0]

all_enables

biggest_size

1335950

1

T1

443

T2

102

T3

453

values[0x1]

all_enables

biggest_size

1316506

1

T1

436

T2

93

T3

433