Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3193321

1

T1

4

T2

48

T3

3

full_word

3665465

1

T1

882

T2

196

T3

888

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6858376	1			T1	886		T2	244		T3	891
auto[TlIntgErrCmd]	126	1			T99	4		T94	8		T95	4
auto[TlIntgErrData]	152	1			T94	5		T95	4		T147	16
auto[TlIntgErrBoth]	132	1			T99	6		T94	7		T95	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3900631

1

T1

4

T2

1

T3

3

auto[1]

2958155

1

T1

882

T2

243

T3

888

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2888423	1			T1	1		T3	1		T5	940
auto[TlIntgErrNone]	partial	auto[1]	304526	1			T1	3		T2	48		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	1011999	1			T1	3		T2	1		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	2653428	1			T1	879		T2	195		T3	886
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T94	3		T95	2		T147	3
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T99	4		T94	4		T95	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T147	1		T251	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T94	1		T150	1		T249	1
auto[TlIntgErrData]	partial	auto[0]	80	1			T94	4		T147	10		T248	3
auto[TlIntgErrData]	partial	auto[1]	53	1			T94	1		T95	1		T147	6
auto[TlIntgErrData]	full_word	auto[0]	13	1			T95	3		T149	2		T150	2
auto[TlIntgErrData]	full_word	auto[1]	6	1			T251	1		T152	1		T249	1
auto[TlIntgErrBoth]	partial	auto[0]	56	1			T94	4		T95	1		T147	3
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T99	6		T94	3		T147	6
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T251	1		T152	1		T250	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T95	1		T149	1		T251	1