Module Definition
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Module Instance : tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_spi_in_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_spi_out_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_csb_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_csb_rst_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_csb_rst_out_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_csb_rst_out_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_tpm_csb_rst_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tpm_rst_out_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_tpm_rst_out_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spid_status.u_csb_rst_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_csb_rst_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 357097964 357091339 0 0
selKnown1 118917160 118916411 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 357097964 357091339 0 0
T1 99201 99195 0 0
T2 174009 174005 0 0
T3 61965 61959 0 0
T4 144639 144635 0 0
T5 383055 383049 0 0
T6 211617 211613 0 0
T7 2036685 2036679 0 0
T8 59574 59568 0 0
T9 17 13 0 0
T10 38784 38778 0 0
T11 43668 130968 0 0
T12 8 10 0 0
T13 28 40 0 0
T14 20 19 0 0
T15 4 3 0 0
T16 5 4 0 0
T17 3 2 0 0
T18 0 1 0 0
T19 0 1 0 0
T20 0 1 0 0
T21 0 1 0 0
T22 1 0 0 0
T23 1 0 0 0
T24 1 0 0 0
T25 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 118917160 118916411 0 0
T1 33056 33055 0 0
T2 58002 58001 0 0
T3 20638 20637 0 0
T4 48212 48211 0 0
T5 127664 127663 0 0
T6 70538 70537 0 0
T7 678637 678636 0 0
T8 19847 19846 0 0
T10 12924 12923 0 0
T11 43646 43645 0 0

Line Coverage for Instance : tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 118917160 118916411 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 118917160 118916411 0 0
T1 33056 33055 0 0
T2 58002 58001 0 0
T3 20638 20637 0 0
T4 48212 48211 0 0
T5 127664 127663 0 0
T6 70538 70537 0 0
T7 678637 678636 0 0
T8 19847 19846 0 0
T10 12924 12923 0 0
T11 43646 43645 0 0

Line Coverage for Instance : tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 118918049 118917143 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 118918049 118917143 0 0
T1 33057 33056 0 0
T2 58003 58002 0 0
T3 20639 20638 0 0
T4 48213 48212 0 0
T5 127665 127664 0 0
T6 70539 70538 0 0
T7 678638 678637 0 0
T8 19848 19847 0 0
T9 1 0 0 0
T10 12925 12924 0 0
T11 0 43646 0 0

Line Coverage for Instance : tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T3,T5
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T5
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 51737 50831 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 51737 50831 0 0
T1 11 10 0 0
T2 1 0 0 0
T3 17 16 0 0
T4 1 0 0 0
T5 21 20 0 0
T6 1 0 0 0
T7 258 257 0 0
T8 11 10 0 0
T9 8 7 0 0
T10 4 3 0 0
T11 0 11 0 0
T12 0 4 0 0
T13 0 14 0 0

Line Coverage for Instance : tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T5
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T3,T5

Assert Coverage for Instance : tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 50831 50212 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 50831 50212 0 0
T1 10 9 0 0
T3 16 15 0 0
T5 20 19 0 0
T7 257 256 0 0
T8 10 9 0 0
T9 7 6 0 0
T10 3 2 0 0
T11 11 10 0 0
T12 4 3 0 0
T13 14 13 0 0

Line Coverage for Instance : tb.dut.u_csb_rst_out_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_csb_rst_out_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T5
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T3,T5

Assert Coverage for Instance : tb.dut.u_csb_rst_out_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 49936 49379 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 49936 49379 0 0
T1 10 9 0 0
T3 16 15 0 0
T5 20 19 0 0
T7 257 256 0 0
T8 10 9 0 0
T10 3 2 0 0
T11 11 10 0 0
T12 4 3 0 0
T13 14 13 0 0
T14 20 19 0 0

Line Coverage for Instance : tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T6
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T4,T6

Assert Coverage for Instance : tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 63997 63618 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 63997 63618 0 0
T2 230 229 0 0
T4 214 213 0 0
T6 156 155 0 0
T9 7 6 0 0
T15 18 17 0 0
T16 225 224 0 0
T17 285 284 0 0
T24 39 38 0 0
T25 14 13 0 0
T26 0 362 0 0
T27 1 0 0 0

Line Coverage for Instance : tb.dut.u_tpm_rst_out_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_tpm_rst_out_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T6
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T4,T6

Assert Coverage for Instance : tb.dut.u_tpm_rst_out_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 63108 62790 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 63108 62790 0 0
T2 230 229 0 0
T4 214 213 0 0
T6 156 155 0 0
T16 225 224 0 0
T17 275 274 0 0
T24 39 38 0 0
T25 14 13 0 0
T26 363 362 0 0
T27 1 0 0 0
T28 389 388 0 0
T29 0 73 0 0

Line Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T6
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T4,T6

Assert Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 63997 63618 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 63997 63618 0 0
T2 230 229 0 0
T4 214 213 0 0
T6 156 155 0 0
T9 7 6 0 0
T15 18 17 0 0
T16 225 224 0 0
T17 285 284 0 0
T24 39 38 0 0
T25 14 13 0 0
T26 0 362 0 0
T27 1 0 0 0

Line Coverage for Instance : tb.dut.u_spid_status.u_csb_rst_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_spid_status.u_csb_rst_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_spid_status.u_csb_rst_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1100 194 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1100 194 0 0
T15 4 3 0 0
T16 5 4 0 0
T17 3 2 0 0
T18 0 1 0 0
T19 0 1 0 0
T20 0 1 0 0
T21 0 1 0 0
T22 1 0 0 0
T23 1 0 0 0
T24 1 0 0 0
T25 1 0 0 0
T26 1 0 0 0
T27 1 0 0 0
T28 1 0 0 0
T30 0 1 0 0
T31 0 3 0 0
T32 0 1 0 0

Line Coverage for Instance : tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 118918049 118917143 0 0
selKnown1 118917160 118916411 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 118918049 118917143 0 0
T1 33057 33056 0 0
T2 58003 58002 0 0
T3 20639 20638 0 0
T4 48213 48212 0 0
T5 127665 127664 0 0
T6 70539 70538 0 0
T7 678638 678637 0 0
T8 19848 19847 0 0
T9 1 0 0 0
T10 12925 12924 0 0
T11 0 43646 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 118917160 118916411 0 0
T1 33056 33055 0 0
T2 58002 58001 0 0
T3 20638 20637 0 0
T4 48212 48211 0 0
T5 127664 127663 0 0
T6 70538 70537 0 0
T7 678637 678636 0 0
T8 19847 19846 0 0
T10 12924 12923 0 0
T11 43646 43645 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%