Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.63	93.89	84.31	97.00		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.63	93.89	84.31	97.00		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T15
1	0	Covered	T7,T11,T15
1	1	Covered	T7,T11,T15

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T15
1	0	Covered	T7,T11,T15
1	1	Covered	T7,T11,T15

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1042352286	2109	0	0
SrcPulseCheck_M	356751480	2109	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042352286	2109	0	0
T7	481572	6	0	0
T8	168625	0	0	0
T9	2111	0	0	0
T10	8142	0	0	0
T11	618504	5	0	0
T12	80490	0	0	0
T13	27366	0	0	0
T14	839984	0	0	0
T15	245554	12	0	0
T16	1234452	38	0	0
T17	474514	2	0	0
T22	256215	6	0	0
T23	156686	7	0	0
T24	178782	6	0	0
T25	3729	0	0	0
T26	367324	0	0	0
T27	1216	0	0	0
T28	382179	9	0	0
T29	0	11	0	0
T36	47296	0	0	0
T46	0	3	0	0
T47	0	7	0	0
T62	0	7	0	0
T65	569932	8	0	0
T92	0	5	0	0
T140	0	5	0	0
T141	0	7	0	0
T142	0	9	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	2	0	0
T146	9374	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	356751480	2109	0	0
T7	678637	6	0	0
T8	19847	0	0	0
T10	12924	0	0	0
T11	87292	5	0	0
T12	9140	0	0	0
T13	43432	0	0	0
T14	117438	0	0	0
T15	300546	12	0	0
T16	296614	38	0	0
T17	1610576	2	0	0
T22	721132	6	0	0
T23	18660	7	0	0
T24	155517	6	0	0
T25	1355	0	0	0
T26	120801	0	0	0
T27	424	0	0	0
T28	631014	9	0	0
T29	0	11	0	0
T36	115864	0	0	0
T46	0	3	0	0
T47	0	7	0	0
T62	0	7	0	0
T65	457073	8	0	0
T92	0	5	0	0
T140	0	5	0	0
T141	0	7	0	0
T142	0	9	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	2	0	0
T146	9156	0	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T23,T46,T47
1	0	Covered	T23,T46,T47
1	1	Covered	T23,T46,T47

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T23,T46,T47
1	0	Covered	T23,T46,T47
1	1	Covered	T23,T46,T47

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	347450762	154	0	0
SrcPulseCheck_M	118917160	154	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347450762	154	0	0
T16	617226	0	0	0
T17	237257	0	0	0
T23	78343	2	0	0
T24	178782	0	0	0
T25	3729	0	0	0
T26	367324	0	0	0
T27	1216	0	0	0
T28	382179	0	0	0
T46	0	2	0	0
T47	0	2	0	0
T62	0	2	0	0
T65	569932	0	0	0
T140	0	3	0	0
T141	0	2	0	0
T142	0	5	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	9374	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	154	0	0
T16	148307	0	0	0
T17	805288	0	0	0
T23	9330	2	0	0
T24	155517	0	0	0
T25	1355	0	0	0
T26	120801	0	0	0
T27	424	0	0	0
T28	631014	0	0	0
T46	0	2	0	0
T47	0	2	0	0
T62	0	2	0	0
T65	457073	0	0	0
T140	0	3	0	0
T141	0	2	0	0
T142	0	5	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	9156	0	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T23,T46
1	0	Covered	T11,T23,T46
1	1	Covered	T11,T23,T47

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T23,T46
1	0	Covered	T11,T23,T47
1	1	Covered	T11,T23,T46

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	347450762	304	0	0
SrcPulseCheck_M	118917160	304	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347450762	304	0	0
T11	309252	5	0	0
T12	40245	0	0	0
T13	13683	0	0	0
T14	419992	0	0	0
T15	122777	0	0	0
T16	617226	0	0	0
T17	237257	0	0	0
T22	256215	0	0	0
T23	78343	5	0	0
T36	23648	0	0	0
T46	0	1	0	0
T47	0	5	0	0
T62	0	5	0	0
T92	0	5	0	0
T140	0	2	0	0
T141	0	5	0	0
T142	0	4	0	0
T145	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	304	0	0
T11	43646	5	0	0
T12	4570	0	0	0
T13	21716	0	0	0
T14	58719	0	0	0
T15	150273	0	0	0
T16	148307	0	0	0
T17	805288	0	0	0
T22	360566	0	0	0
T23	9330	5	0	0
T36	57932	0	0	0
T46	0	1	0	0
T47	0	5	0	0
T62	0	5	0	0
T92	0	5	0	0
T140	0	2	0	0
T141	0	5	0	0
T142	0	4	0	0
T145	0	1	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T15,T22
1	0	Covered	T7,T15,T22
1	1	Covered	T7,T15,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T15,T22
1	0	Covered	T7,T15,T22
1	1	Covered	T7,T15,T22

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	347450762	1651	0	0
SrcPulseCheck_M	118917160	1651	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347450762	1651	0	0
T7	481572	6	0	0
T8	168625	0	0	0
T9	2111	0	0	0
T10	8142	0	0	0
T11	309252	0	0	0
T12	40245	0	0	0
T13	13683	0	0	0
T14	419992	0	0	0
T15	122777	12	0	0
T16	0	38	0	0
T17	0	2	0	0
T22	0	6	0	0
T24	0	6	0	0
T28	0	9	0	0
T29	0	11	0	0
T36	23648	0	0	0
T50	0	6	0	0
T65	0	8	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	1651	0	0
T7	678637	6	0	0
T8	19847	0	0	0
T10	12924	0	0	0
T11	43646	0	0	0
T12	4570	0	0	0
T13	21716	0	0	0
T14	58719	0	0	0
T15	150273	12	0	0
T16	0	38	0	0
T17	0	2	0	0
T22	360566	6	0	0
T24	0	6	0	0
T28	0	9	0	0
T29	0	11	0	0
T36	57932	0	0	0
T50	0	6	0	0
T65	0	8	0	0