Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	349964600	2352476	0	0
DepthKnown_A	349964600	349836304	0	0
RvalidKnown_A	349964600	349836304	0	0
WreadyKnown_A	349964600	349836304	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	2352476	0	0
T1	39111	1663	0	0
T2	34563	0	0	0
T3	12144	832	0	0
T4	74412	0	0	0
T5	74803	832	0	0
T6	78070	0	0	0
T7	481572	9985	0	0
T8	168625	832	0	0
T9	2111	0	0	0
T10	8142	832	0	0
T11	0	4242	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	349836304	0	0
T1	39111	39015	0	0
T2	34563	34479	0	0
T3	12144	12060	0	0
T4	74412	74318	0	0
T5	74803	74741	0	0
T6	78070	77977	0	0
T7	481572	481567	0	0
T8	168625	168569	0	0
T9	2111	2011	0	0
T10	8142	8043	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	349836304	0	0
T1	39111	39015	0	0
T2	34563	34479	0	0
T3	12144	12060	0	0
T4	74412	74318	0	0
T5	74803	74741	0	0
T6	78070	77977	0	0
T7	481572	481567	0	0
T8	168625	168569	0	0
T9	2111	2011	0	0
T10	8142	8043	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	349836304	0	0
T1	39111	39015	0	0
T2	34563	34479	0	0
T3	12144	12060	0	0
T4	74412	74318	0	0
T5	74803	74741	0	0
T6	78070	77977	0	0
T7	481572	481567	0	0
T8	168625	168569	0	0
T9	2111	2011	0	0
T10	8142	8043	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	349964600	2621971	0	0
DepthKnown_A	349964600	349836304	0	0
RvalidKnown_A	349964600	349836304	0	0
WreadyKnown_A	349964600	349836304	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	2621971	0	0
T1	39111	832	0	0
T2	34563	0	0	0
T3	12144	832	0	0
T4	74412	0	0	0
T5	74803	3803	0	0
T6	78070	0	0	0
T7	481572	25396	0	0
T8	168625	2706	0	0
T9	2111	0	0	0
T10	8142	832	0	0
T11	0	2136	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	3887	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	349836304	0	0
T1	39111	39015	0	0
T2	34563	34479	0	0
T3	12144	12060	0	0
T4	74412	74318	0	0
T5	74803	74741	0	0
T6	78070	77977	0	0
T7	481572	481567	0	0
T8	168625	168569	0	0
T9	2111	2011	0	0
T10	8142	8043	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	349836304	0	0
T1	39111	39015	0	0
T2	34563	34479	0	0
T3	12144	12060	0	0
T4	74412	74318	0	0
T5	74803	74741	0	0
T6	78070	77977	0	0
T7	481572	481567	0	0
T8	168625	168569	0	0
T9	2111	2011	0	0
T10	8142	8043	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	349836304	0	0
T1	39111	39015	0	0
T2	34563	34479	0	0
T3	12144	12060	0	0
T4	74412	74318	0	0
T5	74803	74741	0	0
T6	78070	77977	0	0
T7	481572	481567	0	0
T8	168625	168569	0	0
T9	2111	2011	0	0
T10	8142	8043	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	349964600	148349	0	0
DepthKnown_A	349964600	349836304	0	0
RvalidKnown_A	349964600	349836304	0	0
WreadyKnown_A	349964600	349836304	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	148349	0	0
T6	78070	244	0	0
T7	481572	129	0	0
T8	168625	0	0	0
T9	2111	0	0	0
T10	8142	0	0	0
T11	309252	0	0	0
T12	40245	0	0	0
T13	13683	0	0	0
T14	419992	0	0	0
T15	0	96	0	0
T16	0	1262	0	0
T17	0	522	0	0
T22	0	128	0	0
T24	0	185	0	0
T26	0	841	0	0
T27	0	12	0	0
T28	0	1086	0	0
T36	23648	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	349836304	0	0
T1	39111	39015	0	0
T2	34563	34479	0	0
T3	12144	12060	0	0
T4	74412	74318	0	0
T5	74803	74741	0	0
T6	78070	77977	0	0
T7	481572	481567	0	0
T8	168625	168569	0	0
T9	2111	2011	0	0
T10	8142	8043	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	349836304	0	0
T1	39111	39015	0	0
T2	34563	34479	0	0
T3	12144	12060	0	0
T4	74412	74318	0	0
T5	74803	74741	0	0
T6	78070	77977	0	0
T7	481572	481567	0	0
T8	168625	168569	0	0
T9	2111	2011	0	0
T10	8142	8043	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	349836304	0	0
T1	39111	39015	0	0
T2	34563	34479	0	0
T3	12144	12060	0	0
T4	74412	74318	0	0
T5	74803	74741	0	0
T6	78070	77977	0	0
T7	481572	481567	0	0
T8	168625	168569	0	0
T9	2111	2011	0	0
T10	8142	8043	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	349964600	332560	0	0
DepthKnown_A	349964600	349836304	0	0
RvalidKnown_A	349964600	349836304	0	0
WreadyKnown_A	349964600	349836304	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	332560	0	0
T6	78070	244	0	0
T7	481572	613	0	0
T8	168625	0	0	0
T9	2111	0	0	0
T10	8142	0	0	0
T11	309252	0	0	0
T12	40245	0	0	0
T13	13683	0	0	0
T14	419992	0	0	0
T15	0	96	0	0
T16	0	4568	0	0
T17	0	522	0	0
T22	0	396	0	0
T24	0	185	0	0
T26	0	3763	0	0
T27	0	12	0	0
T28	0	4962	0	0
T36	23648	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	349836304	0	0
T1	39111	39015	0	0
T2	34563	34479	0	0
T3	12144	12060	0	0
T4	74412	74318	0	0
T5	74803	74741	0	0
T6	78070	77977	0	0
T7	481572	481567	0	0
T8	168625	168569	0	0
T9	2111	2011	0	0
T10	8142	8043	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	349836304	0	0
T1	39111	39015	0	0
T2	34563	34479	0	0
T3	12144	12060	0	0
T4	74412	74318	0	0
T5	74803	74741	0	0
T6	78070	77977	0	0
T7	481572	481567	0	0
T8	168625	168569	0	0
T9	2111	2011	0	0
T10	8142	8043	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	349836304	0	0
T1	39111	39015	0	0
T2	34563	34479	0	0
T3	12144	12060	0	0
T4	74412	74318	0	0
T5	74803	74741	0	0
T6	78070	77977	0	0
T7	481572	481567	0	0
T8	168625	168569	0	0
T9	2111	2011	0	0
T10	8142	8043	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	349964600	5570711	0	0
DepthKnown_A	349964600	349836304	0	0
RvalidKnown_A	349964600	349836304	0	0
WreadyKnown_A	349964600	349836304	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	5570711	0	0
T1	39111	54	0	0
T2	34563	244	0	0
T3	12144	59	0	0
T4	74412	374	0	0
T5	74803	2018	0	0
T6	78070	2604	0	0
T7	481572	7479	0	0
T8	168625	5556	0	0
T9	2111	65	0	0
T10	8142	433	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	349836304	0	0
T1	39111	39015	0	0
T2	34563	34479	0	0
T3	12144	12060	0	0
T4	74412	74318	0	0
T5	74803	74741	0	0
T6	78070	77977	0	0
T7	481572	481567	0	0
T8	168625	168569	0	0
T9	2111	2011	0	0
T10	8142	8043	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	349836304	0	0
T1	39111	39015	0	0
T2	34563	34479	0	0
T3	12144	12060	0	0
T4	74412	74318	0	0
T5	74803	74741	0	0
T6	78070	77977	0	0
T7	481572	481567	0	0
T8	168625	168569	0	0
T9	2111	2011	0	0
T10	8142	8043	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	349836304	0	0
T1	39111	39015	0	0
T2	34563	34479	0	0
T3	12144	12060	0	0
T4	74412	74318	0	0
T5	74803	74741	0	0
T6	78070	77977	0	0
T7	481572	481567	0	0
T8	168625	168569	0	0
T9	2111	2011	0	0
T10	8142	8043	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	349964600	12108615	0	0
DepthKnown_A	349964600	349836304	0	0
RvalidKnown_A	349964600	349836304	0	0
WreadyKnown_A	349964600	349836304	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	12108615	0	0
T1	39111	54	0	0
T2	34563	244	0	0
T3	12144	59	0	0
T4	74412	374	0	0
T5	74803	8918	0	0
T6	78070	2571	0	0
T7	481572	32252	0	0
T8	168625	17279	0	0
T9	2111	258	0	0
T10	8142	431	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	349836304	0	0
T1	39111	39015	0	0
T2	34563	34479	0	0
T3	12144	12060	0	0
T4	74412	74318	0	0
T5	74803	74741	0	0
T6	78070	77977	0	0
T7	481572	481567	0	0
T8	168625	168569	0	0
T9	2111	2011	0	0
T10	8142	8043	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	349836304	0	0
T1	39111	39015	0	0
T2	34563	34479	0	0
T3	12144	12060	0	0
T4	74412	74318	0	0
T5	74803	74741	0	0
T6	78070	77977	0	0
T7	481572	481567	0	0
T8	168625	168569	0	0
T9	2111	2011	0	0
T10	8142	8043	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349964600	349836304	0	0
T1	39111	39015	0	0
T2	34563	34479	0	0
T3	12144	12060	0	0
T4	74412	74318	0	0
T5	74803	74741	0	0
T6	78070	77977	0	0
T7	481572	481567	0	0
T8	168625	168569	0	0
T9	2111	2011	0	0
T10	8142	8043	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0