Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T16,T17
1	0	Covered	T6,T16,T17

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Unreachable
1	1	Covered	T6,T16,T17

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T15,T22

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T15,T22
1	0	Covered	T7,T15,T22

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Unreachable
1	1	Covered	T7,T15,T22

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T15
1	0	Covered	T1,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	585285082	465064551	0	0
CheckNGreaterZero_A	2718	2718	0	0
GntImpliesReady_A	585285082	2818610	0	0
GntImpliesValid_A	585285082	2818610	0	0
GrantKnown_A	585285082	465064551	0	0
IdxKnown_A	585285082	465064551	0	0
IndexIsCorrect_A	585285082	2818610	0	0
LockArbDecision_A	585285082	0	0	0
NoReadyValidNoGrant_A	585285082	0	0	0
ReadyAndValidImplyGrant_A	585285082	2818610	0	0
ReqAndReadyImplyGrant_A	585285082	2818610	0	0
ReqImpliesValid_A	585285082	2818610	0	0
ReqStaysHighUntilGranted0_M	585285082	0	0	0
RoundRobin_A	585285082	9	0	906
ValidKnown_A	585285082	465064551	0	0
gen_data_port_assertion.DataFlow_A	585285082	2818610	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585285082	465064551	0	0
T1	72167	71753	0	0
T2	150567	90871	0	0
T3	53420	32698	0	0
T4	170836	120182	0	0
T5	330131	202405	0	0
T6	219146	145777	0	0
T7	1838846	1158589	0	0
T8	208319	188275	0	0
T9	2111	2011	0	0
T10	33990	20555	0	0
T11	87292	43646	0	0
T12	4570	4192	0	0
T13	0	21716	0	0
T14	0	58384	0	0
T16	0	55384	0	0
T17	0	331928	0	0
T24	0	18760	0	0
T25	0	1008	0	0
T26	0	116072	0	0
T27	0	424	0	0
T28	0	100504	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2718	2718	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585285082	2818610	0	0
T1	39111	832	0	0
T2	34563	0	0	0
T3	12144	832	0	0
T4	74412	0	0	0
T5	74803	832	0	0
T6	148608	2433	0	0
T7	1838846	12997	0	0
T8	208319	832	0	0
T9	2111	0	0	0
T10	33990	832	0	0
T11	87292	2112	0	0
T12	9140	832	0	0
T13	43432	832	0	0
T14	117438	0	0	0
T15	300546	407	0	0
T16	0	14791	0	0
T17	0	3212	0	0
T22	360566	1133	0	0
T24	0	883	0	0
T26	0	4531	0	0
T27	0	48	0	0
T28	0	10810	0	0
T29	0	3973	0	0
T36	115864	0	0	0
T48	0	1134	0	0
T49	0	4988	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585285082	2818610	0	0
T1	39111	832	0	0
T2	34563	0	0	0
T3	12144	832	0	0
T4	74412	0	0	0
T5	74803	832	0	0
T6	148608	2433	0	0
T7	1838846	12997	0	0
T8	208319	832	0	0
T9	2111	0	0	0
T10	33990	832	0	0
T11	87292	2112	0	0
T12	9140	832	0	0
T13	43432	832	0	0
T14	117438	0	0	0
T15	300546	407	0	0
T16	0	14791	0	0
T17	0	3212	0	0
T22	360566	1133	0	0
T24	0	883	0	0
T26	0	4531	0	0
T27	0	48	0	0
T28	0	10810	0	0
T29	0	3973	0	0
T36	115864	0	0	0
T48	0	1134	0	0
T49	0	4988	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585285082	465064551	0	0
T1	72167	71753	0	0
T2	150567	90871	0	0
T3	53420	32698	0	0
T4	170836	120182	0	0
T5	330131	202405	0	0
T6	219146	145777	0	0
T7	1838846	1158589	0	0
T8	208319	188275	0	0
T9	2111	2011	0	0
T10	33990	20555	0	0
T11	87292	43646	0	0
T12	4570	4192	0	0
T13	0	21716	0	0
T14	0	58384	0	0
T16	0	55384	0	0
T17	0	331928	0	0
T24	0	18760	0	0
T25	0	1008	0	0
T26	0	116072	0	0
T27	0	424	0	0
T28	0	100504	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585285082	465064551	0	0
T1	72167	71753	0	0
T2	150567	90871	0	0
T3	53420	32698	0	0
T4	170836	120182	0	0
T5	330131	202405	0	0
T6	219146	145777	0	0
T7	1838846	1158589	0	0
T8	208319	188275	0	0
T9	2111	2011	0	0
T10	33990	20555	0	0
T11	87292	43646	0	0
T12	4570	4192	0	0
T13	0	21716	0	0
T14	0	58384	0	0
T16	0	55384	0	0
T17	0	331928	0	0
T24	0	18760	0	0
T25	0	1008	0	0
T26	0	116072	0	0
T27	0	424	0	0
T28	0	100504	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585285082	2818610	0	0
T1	39111	832	0	0
T2	34563	0	0	0
T3	12144	832	0	0
T4	74412	0	0	0
T5	74803	832	0	0
T6	148608	2433	0	0
T7	1838846	12997	0	0
T8	208319	832	0	0
T9	2111	0	0	0
T10	33990	832	0	0
T11	87292	2112	0	0
T12	9140	832	0	0
T13	43432	832	0	0
T14	117438	0	0	0
T15	300546	407	0	0
T16	0	14791	0	0
T17	0	3212	0	0
T22	360566	1133	0	0
T24	0	883	0	0
T26	0	4531	0	0
T27	0	48	0	0
T28	0	10810	0	0
T29	0	3973	0	0
T36	115864	0	0	0
T48	0	1134	0	0
T49	0	4988	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585285082	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585285082	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585285082	2818610	0	0
T1	39111	832	0	0
T2	34563	0	0	0
T3	12144	832	0	0
T4	74412	0	0	0
T5	74803	832	0	0
T6	148608	2433	0	0
T7	1838846	12997	0	0
T8	208319	832	0	0
T9	2111	0	0	0
T10	33990	832	0	0
T11	87292	2112	0	0
T12	9140	832	0	0
T13	43432	832	0	0
T14	117438	0	0	0
T15	300546	407	0	0
T16	0	14791	0	0
T17	0	3212	0	0
T22	360566	1133	0	0
T24	0	883	0	0
T26	0	4531	0	0
T27	0	48	0	0
T28	0	10810	0	0
T29	0	3973	0	0
T36	115864	0	0	0
T48	0	1134	0	0
T49	0	4988	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585285082	2818610	0	0
T1	39111	832	0	0
T2	34563	0	0	0
T3	12144	832	0	0
T4	74412	0	0	0
T5	74803	832	0	0
T6	148608	2433	0	0
T7	1838846	12997	0	0
T8	208319	832	0	0
T9	2111	0	0	0
T10	33990	832	0	0
T11	87292	2112	0	0
T12	9140	832	0	0
T13	43432	832	0	0
T14	117438	0	0	0
T15	300546	407	0	0
T16	0	14791	0	0
T17	0	3212	0	0
T22	360566	1133	0	0
T24	0	883	0	0
T26	0	4531	0	0
T27	0	48	0	0
T28	0	10810	0	0
T29	0	3973	0	0
T36	115864	0	0	0
T48	0	1134	0	0
T49	0	4988	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585285082	2818610	0	0
T1	39111	832	0	0
T2	34563	0	0	0
T3	12144	832	0	0
T4	74412	0	0	0
T5	74803	832	0	0
T6	148608	2433	0	0
T7	1838846	12997	0	0
T8	208319	832	0	0
T9	2111	0	0	0
T10	33990	832	0	0
T11	87292	2112	0	0
T12	9140	832	0	0
T13	43432	832	0	0
T14	117438	0	0	0
T15	300546	407	0	0
T16	0	14791	0	0
T17	0	3212	0	0
T22	360566	1133	0	0
T24	0	883	0	0
T26	0	4531	0	0
T27	0	48	0	0
T28	0	10810	0	0
T29	0	3973	0	0
T36	115864	0	0	0
T48	0	1134	0	0
T49	0	4988	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	585285082	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585285082	9	0	906
T21	0	1	0	0
T40	205531	1	0	1
T41	868152	0	0	1
T42	71405	0	0	1
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	371249	0	0	1
T59	52919	0	0	1
T60	177934	0	0	1
T61	166487	0	0	1
T62	42029	0	0	1
T63	1600	0	0	1
T64	10167	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585285082	465064551	0	0
T1	72167	71753	0	0
T2	150567	90871	0	0
T3	53420	32698	0	0
T4	170836	120182	0	0
T5	330131	202405	0	0
T6	219146	145777	0	0
T7	1838846	1158589	0	0
T8	208319	188275	0	0
T9	2111	2011	0	0
T10	33990	20555	0	0
T11	87292	43646	0	0
T12	4570	4192	0	0
T13	0	21716	0	0
T14	0	58384	0	0
T16	0	55384	0	0
T17	0	331928	0	0
T24	0	18760	0	0
T25	0	1008	0	0
T26	0	116072	0	0
T27	0	424	0	0
T28	0	100504	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585285082	2818610	0	0
T1	39111	832	0	0
T2	34563	0	0	0
T3	12144	832	0	0
T4	74412	0	0	0
T5	74803	832	0	0
T6	148608	2433	0	0
T7	1838846	12997	0	0
T8	208319	832	0	0
T9	2111	0	0	0
T10	33990	832	0	0
T11	87292	2112	0	0
T12	9140	832	0	0
T13	43432	832	0	0
T14	117438	0	0	0
T15	300546	407	0	0
T16	0	14791	0	0
T17	0	3212	0	0
T22	360566	1133	0	0
T24	0	883	0	0
T26	0	4531	0	0
T27	0	48	0	0
T28	0	10810	0	0
T29	0	3973	0	0
T36	115864	0	0	0
T48	0	1134	0	0
T49	0	4988	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T16,T17
1	0	Covered	T6,T16,T17

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Unreachable
1	1	Covered	T6,T16,T17

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T16,T17
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T16,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T16,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	118917160	26627251	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	118917160	581025	0	0
GntImpliesValid_A	118917160	581025	0	0
GrantKnown_A	118917160	26627251	0	0
IdxKnown_A	118917160	26627251	0	0
IndexIsCorrect_A	118917160	581025	0	0
LockArbDecision_A	118917160	0	0	0
NoReadyValidNoGrant_A	118917160	0	0	0
ReadyAndValidImplyGrant_A	118917160	581025	0	0
ReqAndReadyImplyGrant_A	118917160	581025	0	0
ReqImpliesValid_A	118917160	581025	0	0
ReqStaysHighUntilGranted0_M	118917160	0	0	0
RoundRobin_A	118917160	0	0	0
ValidKnown_A	118917160	26627251	0	0
gen_data_port_assertion.DataFlow_A	118917160	581025	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	26627251	0	0
T2	58002	56392	0	0
T3	20638	0	0	0
T4	48212	45864	0	0
T5	127664	0	0	0
T6	70538	67800	0	0
T7	678637	0	0	0
T8	19847	0	0	0
T10	12924	0	0	0
T11	43646	0	0	0
T12	4570	0	0	0
T16	0	55384	0	0
T17	0	331928	0	0
T24	0	18760	0	0
T25	0	1008	0	0
T26	0	116072	0	0
T27	0	424	0	0
T28	0	100504	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	581025	0	0
T6	70538	1598	0	0
T7	678637	0	0	0
T8	19847	0	0	0
T10	12924	0	0	0
T11	43646	0	0	0
T12	4570	0	0	0
T13	21716	0	0	0
T14	58719	0	0	0
T15	150273	0	0	0
T16	0	2081	0	0
T17	0	3209	0	0
T24	0	615	0	0
T26	0	4531	0	0
T27	0	48	0	0
T28	0	4276	0	0
T29	0	868	0	0
T36	57932	0	0	0
T48	0	1134	0	0
T49	0	4988	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	581025	0	0
T6	70538	1598	0	0
T7	678637	0	0	0
T8	19847	0	0	0
T10	12924	0	0	0
T11	43646	0	0	0
T12	4570	0	0	0
T13	21716	0	0	0
T14	58719	0	0	0
T15	150273	0	0	0
T16	0	2081	0	0
T17	0	3209	0	0
T24	0	615	0	0
T26	0	4531	0	0
T27	0	48	0	0
T28	0	4276	0	0
T29	0	868	0	0
T36	57932	0	0	0
T48	0	1134	0	0
T49	0	4988	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	26627251	0	0
T2	58002	56392	0	0
T3	20638	0	0	0
T4	48212	45864	0	0
T5	127664	0	0	0
T6	70538	67800	0	0
T7	678637	0	0	0
T8	19847	0	0	0
T10	12924	0	0	0
T11	43646	0	0	0
T12	4570	0	0	0
T16	0	55384	0	0
T17	0	331928	0	0
T24	0	18760	0	0
T25	0	1008	0	0
T26	0	116072	0	0
T27	0	424	0	0
T28	0	100504	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	26627251	0	0
T2	58002	56392	0	0
T3	20638	0	0	0
T4	48212	45864	0	0
T5	127664	0	0	0
T6	70538	67800	0	0
T7	678637	0	0	0
T8	19847	0	0	0
T10	12924	0	0	0
T11	43646	0	0	0
T12	4570	0	0	0
T16	0	55384	0	0
T17	0	331928	0	0
T24	0	18760	0	0
T25	0	1008	0	0
T26	0	116072	0	0
T27	0	424	0	0
T28	0	100504	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	581025	0	0
T6	70538	1598	0	0
T7	678637	0	0	0
T8	19847	0	0	0
T10	12924	0	0	0
T11	43646	0	0	0
T12	4570	0	0	0
T13	21716	0	0	0
T14	58719	0	0	0
T15	150273	0	0	0
T16	0	2081	0	0
T17	0	3209	0	0
T24	0	615	0	0
T26	0	4531	0	0
T27	0	48	0	0
T28	0	4276	0	0
T29	0	868	0	0
T36	57932	0	0	0
T48	0	1134	0	0
T49	0	4988	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	581025	0	0
T6	70538	1598	0	0
T7	678637	0	0	0
T8	19847	0	0	0
T10	12924	0	0	0
T11	43646	0	0	0
T12	4570	0	0	0
T13	21716	0	0	0
T14	58719	0	0	0
T15	150273	0	0	0
T16	0	2081	0	0
T17	0	3209	0	0
T24	0	615	0	0
T26	0	4531	0	0
T27	0	48	0	0
T28	0	4276	0	0
T29	0	868	0	0
T36	57932	0	0	0
T48	0	1134	0	0
T49	0	4988	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	581025	0	0
T6	70538	1598	0	0
T7	678637	0	0	0
T8	19847	0	0	0
T10	12924	0	0	0
T11	43646	0	0	0
T12	4570	0	0	0
T13	21716	0	0	0
T14	58719	0	0	0
T15	150273	0	0	0
T16	0	2081	0	0
T17	0	3209	0	0
T24	0	615	0	0
T26	0	4531	0	0
T27	0	48	0	0
T28	0	4276	0	0
T29	0	868	0	0
T36	57932	0	0	0
T48	0	1134	0	0
T49	0	4988	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	581025	0	0
T6	70538	1598	0	0
T7	678637	0	0	0
T8	19847	0	0	0
T10	12924	0	0	0
T11	43646	0	0	0
T12	4570	0	0	0
T13	21716	0	0	0
T14	58719	0	0	0
T15	150273	0	0	0
T16	0	2081	0	0
T17	0	3209	0	0
T24	0	615	0	0
T26	0	4531	0	0
T27	0	48	0	0
T28	0	4276	0	0
T29	0	868	0	0
T36	57932	0	0	0
T48	0	1134	0	0
T49	0	4988	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	26627251	0	0
T2	58002	56392	0	0
T3	20638	0	0	0
T4	48212	45864	0	0
T5	127664	0	0	0
T6	70538	67800	0	0
T7	678637	0	0	0
T8	19847	0	0	0
T10	12924	0	0	0
T11	43646	0	0	0
T12	4570	0	0	0
T16	0	55384	0	0
T17	0	331928	0	0
T24	0	18760	0	0
T25	0	1008	0	0
T26	0	116072	0	0
T27	0	424	0	0
T28	0	100504	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	581025	0	0
T6	70538	1598	0	0
T7	678637	0	0	0
T8	19847	0	0	0
T10	12924	0	0	0
T11	43646	0	0	0
T12	4570	0	0	0
T13	21716	0	0	0
T14	58719	0	0	0
T15	150273	0	0	0
T16	0	2081	0	0
T17	0	3209	0	0
T24	0	615	0	0
T26	0	4531	0	0
T27	0	48	0	0
T28	0	4276	0	0
T29	0	868	0	0
T36	57932	0	0	0
T48	0	1134	0	0
T49	0	4988	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T15,T22

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T15,T22
1	0	Covered	T7,T15,T22

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Unreachable
1	1	Covered	T7,T15,T22

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T15,T22
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T15,T22
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T15,T22
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T15,T22
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	118917160	91069677	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	118917160	385708	0	0
GntImpliesValid_A	118917160	385708	0	0
GrantKnown_A	118917160	91069677	0	0
IdxKnown_A	118917160	91069677	0	0
IndexIsCorrect_A	118917160	385708	0	0
LockArbDecision_A	118917160	0	0	0
NoReadyValidNoGrant_A	118917160	0	0	0
ReadyAndValidImplyGrant_A	118917160	385708	0	0
ReqAndReadyImplyGrant_A	118917160	385708	0	0
ReqImpliesValid_A	118917160	385708	0	0
ReqStaysHighUntilGranted0_M	118917160	0	0	0
RoundRobin_A	118917160	0	0	0
ValidKnown_A	118917160	91069677	0	0
gen_data_port_assertion.DataFlow_A	118917160	385708	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	91069677	0	0
T1	33056	32738	0	0
T2	58002	0	0	0
T3	20638	20638	0	0
T4	48212	0	0	0
T5	127664	127664	0	0
T6	70538	0	0	0
T7	678637	677022	0	0
T8	19847	19706	0	0
T10	12924	12512	0	0
T11	43646	43646	0	0
T12	0	4192	0	0
T13	0	21716	0	0
T14	0	58384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	385708	0	0
T7	678637	5370	0	0
T8	19847	0	0	0
T10	12924	0	0	0
T11	43646	0	0	0
T12	4570	0	0	0
T13	21716	0	0	0
T14	58719	0	0	0
T15	150273	407	0	0
T16	0	12710	0	0
T17	0	3	0	0
T22	360566	1133	0	0
T24	0	268	0	0
T28	0	6534	0	0
T29	0	3105	0	0
T36	57932	0	0	0
T50	0	1057	0	0
T65	0	314	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	385708	0	0
T7	678637	5370	0	0
T8	19847	0	0	0
T10	12924	0	0	0
T11	43646	0	0	0
T12	4570	0	0	0
T13	21716	0	0	0
T14	58719	0	0	0
T15	150273	407	0	0
T16	0	12710	0	0
T17	0	3	0	0
T22	360566	1133	0	0
T24	0	268	0	0
T28	0	6534	0	0
T29	0	3105	0	0
T36	57932	0	0	0
T50	0	1057	0	0
T65	0	314	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	91069677	0	0
T1	33056	32738	0	0
T2	58002	0	0	0
T3	20638	20638	0	0
T4	48212	0	0	0
T5	127664	127664	0	0
T6	70538	0	0	0
T7	678637	677022	0	0
T8	19847	19706	0	0
T10	12924	12512	0	0
T11	43646	43646	0	0
T12	0	4192	0	0
T13	0	21716	0	0
T14	0	58384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	91069677	0	0
T1	33056	32738	0	0
T2	58002	0	0	0
T3	20638	20638	0	0
T4	48212	0	0	0
T5	127664	127664	0	0
T6	70538	0	0	0
T7	678637	677022	0	0
T8	19847	19706	0	0
T10	12924	12512	0	0
T11	43646	43646	0	0
T12	0	4192	0	0
T13	0	21716	0	0
T14	0	58384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	385708	0	0
T7	678637	5370	0	0
T8	19847	0	0	0
T10	12924	0	0	0
T11	43646	0	0	0
T12	4570	0	0	0
T13	21716	0	0	0
T14	58719	0	0	0
T15	150273	407	0	0
T16	0	12710	0	0
T17	0	3	0	0
T22	360566	1133	0	0
T24	0	268	0	0
T28	0	6534	0	0
T29	0	3105	0	0
T36	57932	0	0	0
T50	0	1057	0	0
T65	0	314	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	385708	0	0
T7	678637	5370	0	0
T8	19847	0	0	0
T10	12924	0	0	0
T11	43646	0	0	0
T12	4570	0	0	0
T13	21716	0	0	0
T14	58719	0	0	0
T15	150273	407	0	0
T16	0	12710	0	0
T17	0	3	0	0
T22	360566	1133	0	0
T24	0	268	0	0
T28	0	6534	0	0
T29	0	3105	0	0
T36	57932	0	0	0
T50	0	1057	0	0
T65	0	314	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	385708	0	0
T7	678637	5370	0	0
T8	19847	0	0	0
T10	12924	0	0	0
T11	43646	0	0	0
T12	4570	0	0	0
T13	21716	0	0	0
T14	58719	0	0	0
T15	150273	407	0	0
T16	0	12710	0	0
T17	0	3	0	0
T22	360566	1133	0	0
T24	0	268	0	0
T28	0	6534	0	0
T29	0	3105	0	0
T36	57932	0	0	0
T50	0	1057	0	0
T65	0	314	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	385708	0	0
T7	678637	5370	0	0
T8	19847	0	0	0
T10	12924	0	0	0
T11	43646	0	0	0
T12	4570	0	0	0
T13	21716	0	0	0
T14	58719	0	0	0
T15	150273	407	0	0
T16	0	12710	0	0
T17	0	3	0	0
T22	360566	1133	0	0
T24	0	268	0	0
T28	0	6534	0	0
T29	0	3105	0	0
T36	57932	0	0	0
T50	0	1057	0	0
T65	0	314	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	91069677	0	0
T1	33056	32738	0	0
T2	58002	0	0	0
T3	20638	20638	0	0
T4	48212	0	0	0
T5	127664	127664	0	0
T6	70538	0	0	0
T7	678637	677022	0	0
T8	19847	19706	0	0
T10	12924	12512	0	0
T11	43646	43646	0	0
T12	0	4192	0	0
T13	0	21716	0	0
T14	0	58384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118917160	385708	0	0
T7	678637	5370	0	0
T8	19847	0	0	0
T10	12924	0	0	0
T11	43646	0	0	0
T12	4570	0	0	0
T13	21716	0	0	0
T14	58719	0	0	0
T15	150273	407	0	0
T16	0	12710	0	0
T17	0	3	0	0
T22	360566	1133	0	0
T24	0	268	0	0
T28	0	6534	0	0
T29	0	3105	0	0
T36	57932	0	0	0
T50	0	1057	0	0
T65	0	314	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T15
1	0	Covered	T1,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	347450762	347367623	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	347450762	1851877	0	0
GntImpliesValid_A	347450762	1851877	0	0
GrantKnown_A	347450762	347367623	0	0
IdxKnown_A	347450762	347367623	0	0
IndexIsCorrect_A	347450762	1851877	0	0
LockArbDecision_A	347450762	0	0	0
NoReadyValidNoGrant_A	347450762	0	0	0
ReadyAndValidImplyGrant_A	347450762	1851877	0	0
ReqAndReadyImplyGrant_A	347450762	1851877	0	0
ReqImpliesValid_A	347450762	1851877	0	0
ReqStaysHighUntilGranted0_M	347450762	0	0	0
RoundRobin_A	347450762	9	0	906
ValidKnown_A	347450762	347367623	0	0
gen_data_port_assertion.DataFlow_A	347450762	1851877	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347450762	347367623	0	0
T1	39111	39015	0	0
T2	34563	34479	0	0
T3	12144	12060	0	0
T4	74412	74318	0	0
T5	74803	74741	0	0
T6	78070	77977	0	0
T7	481572	481567	0	0
T8	168625	168569	0	0
T9	2111	2011	0	0
T10	8142	8043	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347450762	1851877	0	0
T1	39111	832	0	0
T2	34563	0	0	0
T3	12144	832	0	0
T4	74412	0	0	0
T5	74803	832	0	0
T6	78070	835	0	0
T7	481572	7627	0	0
T8	168625	832	0	0
T9	2111	0	0	0
T10	8142	832	0	0
T11	0	2112	0	0
T12	0	832	0	0
T13	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347450762	1851877	0	0
T1	39111	832	0	0
T2	34563	0	0	0
T3	12144	832	0	0
T4	74412	0	0	0
T5	74803	832	0	0
T6	78070	835	0	0
T7	481572	7627	0	0
T8	168625	832	0	0
T9	2111	0	0	0
T10	8142	832	0	0
T11	0	2112	0	0
T12	0	832	0	0
T13	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347450762	347367623	0	0
T1	39111	39015	0	0
T2	34563	34479	0	0
T3	12144	12060	0	0
T4	74412	74318	0	0
T5	74803	74741	0	0
T6	78070	77977	0	0
T7	481572	481567	0	0
T8	168625	168569	0	0
T9	2111	2011	0	0
T10	8142	8043	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347450762	347367623	0	0
T1	39111	39015	0	0
T2	34563	34479	0	0
T3	12144	12060	0	0
T4	74412	74318	0	0
T5	74803	74741	0	0
T6	78070	77977	0	0
T7	481572	481567	0	0
T8	168625	168569	0	0
T9	2111	2011	0	0
T10	8142	8043	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347450762	1851877	0	0
T1	39111	832	0	0
T2	34563	0	0	0
T3	12144	832	0	0
T4	74412	0	0	0
T5	74803	832	0	0
T6	78070	835	0	0
T7	481572	7627	0	0
T8	168625	832	0	0
T9	2111	0	0	0
T10	8142	832	0	0
T11	0	2112	0	0
T12	0	832	0	0
T13	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347450762	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347450762	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347450762	1851877	0	0
T1	39111	832	0	0
T2	34563	0	0	0
T3	12144	832	0	0
T4	74412	0	0	0
T5	74803	832	0	0
T6	78070	835	0	0
T7	481572	7627	0	0
T8	168625	832	0	0
T9	2111	0	0	0
T10	8142	832	0	0
T11	0	2112	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347450762	1851877	0	0
T1	39111	832	0	0
T2	34563	0	0	0
T3	12144	832	0	0
T4	74412	0	0	0
T5	74803	832	0	0
T6	78070	835	0	0
T7	481572	7627	0	0
T8	168625	832	0	0
T9	2111	0	0	0
T10	8142	832	0	0
T11	0	2112	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347450762	1851877	0	0
T1	39111	832	0	0
T2	34563	0	0	0
T3	12144	832	0	0
T4	74412	0	0	0
T5	74803	832	0	0
T6	78070	835	0	0
T7	481572	7627	0	0
T8	168625	832	0	0
T9	2111	0	0	0
T10	8142	832	0	0
T11	0	2112	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	347450762	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347450762	9	0	906
T21	0	1	0	0
T40	205531	1	0	1
T41	868152	0	0	1
T42	71405	0	0	1
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	371249	0	0	1
T59	52919	0	0	1
T60	177934	0	0	1
T61	166487	0	0	1
T62	42029	0	0	1
T63	1600	0	0	1
T64	10167	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347450762	347367623	0	0
T1	39111	39015	0	0
T2	34563	34479	0	0
T3	12144	12060	0	0
T4	74412	74318	0	0
T5	74803	74741	0	0
T6	78070	77977	0	0
T7	481572	481567	0	0
T8	168625	168569	0	0
T9	2111	2011	0	0
T10	8142	8043	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347450762	1851877	0	0
T1	39111	832	0	0
T2	34563	0	0	0
T3	12144	832	0	0
T4	74412	0	0	0
T5	74803	832	0	0
T6	78070	835	0	0
T7	481572	7627	0	0
T8	168625	832	0	0
T9	2111	0	0	0
T10	8142	832	0	0
T11	0	2112	0	0
T12	0	832	0	0
T13	0	832	0	0