Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
3886 |
0 |
0 |
T69 |
1881 |
2 |
0 |
0 |
T70 |
3755 |
7 |
0 |
0 |
T71 |
1818 |
69 |
0 |
0 |
T94 |
72789 |
6 |
0 |
0 |
T95 |
10491 |
1 |
0 |
0 |
T96 |
4381 |
251 |
0 |
0 |
T97 |
7868 |
106 |
0 |
0 |
T98 |
12695 |
141 |
0 |
0 |
T108 |
1877 |
5 |
0 |
0 |
T147 |
28706 |
4 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
2511 |
0 |
0 |
T94 |
72789 |
81 |
0 |
0 |
T99 |
31870 |
12 |
0 |
0 |
T109 |
6193 |
8 |
0 |
0 |
T112 |
6838 |
9 |
0 |
0 |
T117 |
10390 |
5 |
0 |
0 |
T148 |
2198 |
2 |
0 |
0 |
T149 |
103830 |
90 |
0 |
0 |
T150 |
95743 |
64 |
0 |
0 |
T151 |
12643 |
27 |
0 |
0 |
T152 |
108413 |
143 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
2701 |
0 |
0 |
T94 |
72789 |
80 |
0 |
0 |
T99 |
31870 |
18 |
0 |
0 |
T112 |
6838 |
11 |
0 |
0 |
T117 |
10390 |
5 |
0 |
0 |
T119 |
11814 |
2 |
0 |
0 |
T148 |
2198 |
2 |
0 |
0 |
T149 |
103830 |
127 |
0 |
0 |
T150 |
95743 |
86 |
0 |
0 |
T151 |
12643 |
30 |
0 |
0 |
T152 |
108413 |
114 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
3162 |
0 |
0 |
T94 |
72789 |
163 |
0 |
0 |
T99 |
31870 |
30 |
0 |
0 |
T109 |
6193 |
11 |
0 |
0 |
T112 |
6838 |
19 |
0 |
0 |
T119 |
11814 |
4 |
0 |
0 |
T148 |
2198 |
2 |
0 |
0 |
T149 |
103830 |
216 |
0 |
0 |
T150 |
95743 |
131 |
0 |
0 |
T151 |
12643 |
50 |
0 |
0 |
T152 |
108413 |
220 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
12140 |
0 |
0 |
T94 |
72789 |
1042 |
0 |
0 |
T99 |
31870 |
317 |
0 |
0 |
T109 |
6193 |
113 |
0 |
0 |
T117 |
10390 |
83 |
0 |
0 |
T119 |
11814 |
331 |
0 |
0 |
T148 |
2198 |
7 |
0 |
0 |
T149 |
103830 |
2170 |
0 |
0 |
T150 |
95743 |
1140 |
0 |
0 |
T151 |
12643 |
31 |
0 |
0 |
T152 |
108413 |
2333 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
11082 |
0 |
0 |
T94 |
72789 |
1257 |
0 |
0 |
T99 |
31870 |
338 |
0 |
0 |
T109 |
6193 |
87 |
0 |
0 |
T112 |
6838 |
127 |
0 |
0 |
T117 |
10390 |
213 |
0 |
0 |
T119 |
11814 |
119 |
0 |
0 |
T149 |
103830 |
1256 |
0 |
0 |
T150 |
95743 |
1148 |
0 |
0 |
T151 |
12643 |
34 |
0 |
0 |
T152 |
108413 |
2055 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
11359 |
0 |
0 |
T94 |
72789 |
1339 |
0 |
0 |
T99 |
31870 |
345 |
0 |
0 |
T109 |
6193 |
4 |
0 |
0 |
T112 |
6838 |
62 |
0 |
0 |
T117 |
10390 |
8 |
0 |
0 |
T119 |
11814 |
329 |
0 |
0 |
T149 |
103830 |
1380 |
0 |
0 |
T150 |
95743 |
977 |
0 |
0 |
T151 |
12643 |
9 |
0 |
0 |
T152 |
108413 |
2223 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
11357 |
0 |
0 |
T94 |
72789 |
1005 |
0 |
0 |
T99 |
31870 |
404 |
0 |
0 |
T109 |
6193 |
11 |
0 |
0 |
T112 |
6838 |
150 |
0 |
0 |
T117 |
10390 |
117 |
0 |
0 |
T148 |
2198 |
5 |
0 |
0 |
T149 |
103830 |
1685 |
0 |
0 |
T150 |
95743 |
1060 |
0 |
0 |
T151 |
12643 |
23 |
0 |
0 |
T152 |
108413 |
1906 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
12259 |
0 |
0 |
T94 |
72789 |
1367 |
0 |
0 |
T99 |
31870 |
409 |
0 |
0 |
T109 |
6193 |
141 |
0 |
0 |
T112 |
6838 |
75 |
0 |
0 |
T117 |
10390 |
157 |
0 |
0 |
T148 |
2198 |
4 |
0 |
0 |
T149 |
103830 |
2039 |
0 |
0 |
T150 |
95743 |
1082 |
0 |
0 |
T151 |
12643 |
31 |
0 |
0 |
T152 |
108413 |
1895 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
12087 |
0 |
0 |
T94 |
72789 |
1227 |
0 |
0 |
T99 |
31870 |
390 |
0 |
0 |
T109 |
6193 |
131 |
0 |
0 |
T112 |
6838 |
112 |
0 |
0 |
T117 |
10390 |
81 |
0 |
0 |
T119 |
11814 |
251 |
0 |
0 |
T149 |
103830 |
1734 |
0 |
0 |
T150 |
95743 |
803 |
0 |
0 |
T151 |
12643 |
13 |
0 |
0 |
T152 |
108413 |
2506 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
10759 |
0 |
0 |
T94 |
72789 |
1502 |
0 |
0 |
T99 |
31870 |
287 |
0 |
0 |
T109 |
6193 |
4 |
0 |
0 |
T112 |
6838 |
74 |
0 |
0 |
T117 |
10390 |
123 |
0 |
0 |
T148 |
2198 |
3 |
0 |
0 |
T149 |
103830 |
1959 |
0 |
0 |
T150 |
95743 |
1064 |
0 |
0 |
T151 |
12643 |
34 |
0 |
0 |
T152 |
108413 |
1550 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
12237 |
0 |
0 |
T94 |
72789 |
1652 |
0 |
0 |
T99 |
31870 |
207 |
0 |
0 |
T109 |
6193 |
117 |
0 |
0 |
T112 |
6838 |
84 |
0 |
0 |
T117 |
10390 |
159 |
0 |
0 |
T119 |
11814 |
276 |
0 |
0 |
T148 |
2198 |
9 |
0 |
0 |
T149 |
103830 |
2034 |
0 |
0 |
T150 |
95743 |
980 |
0 |
0 |
T152 |
108413 |
1345 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
6136 |
0 |
0 |
T94 |
72789 |
609 |
0 |
0 |
T99 |
31870 |
193 |
0 |
0 |
T109 |
6193 |
64 |
0 |
0 |
T112 |
6838 |
41 |
0 |
0 |
T117 |
10390 |
46 |
0 |
0 |
T148 |
2198 |
7 |
0 |
0 |
T149 |
103830 |
714 |
0 |
0 |
T150 |
95743 |
427 |
0 |
0 |
T151 |
12643 |
11 |
0 |
0 |
T152 |
108413 |
723 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
6171 |
0 |
0 |
T94 |
72789 |
493 |
0 |
0 |
T99 |
31870 |
98 |
0 |
0 |
T109 |
6193 |
67 |
0 |
0 |
T112 |
6838 |
68 |
0 |
0 |
T117 |
10390 |
61 |
0 |
0 |
T148 |
2198 |
6 |
0 |
0 |
T149 |
103830 |
979 |
0 |
0 |
T150 |
95743 |
430 |
0 |
0 |
T151 |
12643 |
14 |
0 |
0 |
T152 |
108413 |
883 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
5769 |
0 |
0 |
T94 |
72789 |
452 |
0 |
0 |
T99 |
31870 |
142 |
0 |
0 |
T109 |
6193 |
9 |
0 |
0 |
T112 |
6838 |
35 |
0 |
0 |
T117 |
10390 |
30 |
0 |
0 |
T148 |
2198 |
2 |
0 |
0 |
T149 |
103830 |
670 |
0 |
0 |
T150 |
95743 |
537 |
0 |
0 |
T151 |
12643 |
12 |
0 |
0 |
T152 |
108413 |
611 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
6103 |
0 |
0 |
T94 |
72789 |
471 |
0 |
0 |
T99 |
31870 |
164 |
0 |
0 |
T109 |
6193 |
49 |
0 |
0 |
T112 |
6838 |
12 |
0 |
0 |
T117 |
10390 |
20 |
0 |
0 |
T148 |
2198 |
4 |
0 |
0 |
T149 |
103830 |
811 |
0 |
0 |
T150 |
95743 |
513 |
0 |
0 |
T151 |
12643 |
14 |
0 |
0 |
T152 |
108413 |
768 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
6040 |
0 |
0 |
T94 |
72789 |
475 |
0 |
0 |
T99 |
31870 |
217 |
0 |
0 |
T109 |
6193 |
12 |
0 |
0 |
T112 |
6838 |
49 |
0 |
0 |
T117 |
10390 |
10 |
0 |
0 |
T148 |
2198 |
6 |
0 |
0 |
T149 |
103830 |
957 |
0 |
0 |
T150 |
95743 |
457 |
0 |
0 |
T151 |
12643 |
34 |
0 |
0 |
T152 |
108413 |
846 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
5731 |
0 |
0 |
T94 |
72789 |
446 |
0 |
0 |
T99 |
31870 |
96 |
0 |
0 |
T109 |
6193 |
51 |
0 |
0 |
T112 |
6838 |
9 |
0 |
0 |
T117 |
10390 |
56 |
0 |
0 |
T148 |
2198 |
1 |
0 |
0 |
T149 |
103830 |
679 |
0 |
0 |
T150 |
95743 |
481 |
0 |
0 |
T151 |
12643 |
40 |
0 |
0 |
T152 |
108413 |
711 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
6202 |
0 |
0 |
T94 |
72789 |
677 |
0 |
0 |
T99 |
31870 |
120 |
0 |
0 |
T109 |
6193 |
28 |
0 |
0 |
T112 |
6838 |
41 |
0 |
0 |
T117 |
10390 |
46 |
0 |
0 |
T148 |
2198 |
6 |
0 |
0 |
T149 |
103830 |
955 |
0 |
0 |
T150 |
95743 |
409 |
0 |
0 |
T151 |
12643 |
3 |
0 |
0 |
T152 |
108413 |
797 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
5539 |
0 |
0 |
T94 |
72789 |
318 |
0 |
0 |
T99 |
31870 |
65 |
0 |
0 |
T109 |
6193 |
36 |
0 |
0 |
T112 |
6838 |
44 |
0 |
0 |
T117 |
10390 |
3 |
0 |
0 |
T148 |
2198 |
9 |
0 |
0 |
T149 |
103830 |
726 |
0 |
0 |
T150 |
95743 |
484 |
0 |
0 |
T151 |
12643 |
24 |
0 |
0 |
T152 |
108413 |
532 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
6032 |
0 |
0 |
T94 |
72789 |
712 |
0 |
0 |
T99 |
31870 |
94 |
0 |
0 |
T109 |
6193 |
56 |
0 |
0 |
T112 |
6838 |
32 |
0 |
0 |
T117 |
10390 |
37 |
0 |
0 |
T148 |
2198 |
2 |
0 |
0 |
T149 |
103830 |
808 |
0 |
0 |
T150 |
95743 |
387 |
0 |
0 |
T151 |
12643 |
19 |
0 |
0 |
T152 |
108413 |
674 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
6399 |
0 |
0 |
T94 |
72789 |
582 |
0 |
0 |
T99 |
31870 |
124 |
0 |
0 |
T109 |
6193 |
48 |
0 |
0 |
T112 |
6838 |
49 |
0 |
0 |
T117 |
10390 |
107 |
0 |
0 |
T148 |
2198 |
9 |
0 |
0 |
T149 |
103830 |
873 |
0 |
0 |
T150 |
95743 |
325 |
0 |
0 |
T151 |
12643 |
16 |
0 |
0 |
T152 |
108413 |
1171 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
6358 |
0 |
0 |
T94 |
72789 |
605 |
0 |
0 |
T99 |
31870 |
186 |
0 |
0 |
T109 |
6193 |
44 |
0 |
0 |
T112 |
6838 |
6 |
0 |
0 |
T117 |
10390 |
70 |
0 |
0 |
T148 |
2198 |
6 |
0 |
0 |
T149 |
103830 |
702 |
0 |
0 |
T150 |
95743 |
379 |
0 |
0 |
T151 |
12643 |
44 |
0 |
0 |
T152 |
108413 |
856 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
5983 |
0 |
0 |
T94 |
72789 |
473 |
0 |
0 |
T99 |
31870 |
118 |
0 |
0 |
T109 |
6193 |
6 |
0 |
0 |
T112 |
6838 |
61 |
0 |
0 |
T117 |
10390 |
60 |
0 |
0 |
T148 |
2198 |
3 |
0 |
0 |
T149 |
103830 |
585 |
0 |
0 |
T150 |
95743 |
388 |
0 |
0 |
T151 |
12643 |
26 |
0 |
0 |
T152 |
108413 |
878 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
5774 |
0 |
0 |
T94 |
72789 |
436 |
0 |
0 |
T99 |
31870 |
68 |
0 |
0 |
T109 |
6193 |
47 |
0 |
0 |
T112 |
6838 |
44 |
0 |
0 |
T117 |
10390 |
18 |
0 |
0 |
T148 |
2198 |
5 |
0 |
0 |
T149 |
103830 |
618 |
0 |
0 |
T150 |
95743 |
481 |
0 |
0 |
T151 |
12643 |
17 |
0 |
0 |
T152 |
108413 |
889 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
6149 |
0 |
0 |
T94 |
72789 |
561 |
0 |
0 |
T99 |
31870 |
117 |
0 |
0 |
T109 |
6193 |
59 |
0 |
0 |
T112 |
6838 |
29 |
0 |
0 |
T117 |
10390 |
50 |
0 |
0 |
T148 |
2198 |
4 |
0 |
0 |
T149 |
103830 |
939 |
0 |
0 |
T150 |
95743 |
523 |
0 |
0 |
T151 |
12643 |
47 |
0 |
0 |
T152 |
108413 |
674 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
6078 |
0 |
0 |
T94 |
72789 |
571 |
0 |
0 |
T99 |
31870 |
165 |
0 |
0 |
T109 |
6193 |
6 |
0 |
0 |
T112 |
6838 |
12 |
0 |
0 |
T117 |
10390 |
34 |
0 |
0 |
T148 |
2198 |
7 |
0 |
0 |
T149 |
103830 |
684 |
0 |
0 |
T150 |
95743 |
289 |
0 |
0 |
T151 |
12643 |
4 |
0 |
0 |
T152 |
108413 |
895 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
6298 |
0 |
0 |
T94 |
72789 |
336 |
0 |
0 |
T99 |
31870 |
131 |
0 |
0 |
T109 |
6193 |
4 |
0 |
0 |
T112 |
6838 |
7 |
0 |
0 |
T117 |
10390 |
31 |
0 |
0 |
T148 |
2198 |
4 |
0 |
0 |
T149 |
103830 |
848 |
0 |
0 |
T150 |
95743 |
476 |
0 |
0 |
T151 |
12643 |
26 |
0 |
0 |
T152 |
108413 |
1051 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
5906 |
0 |
0 |
T94 |
72789 |
569 |
0 |
0 |
T99 |
31870 |
67 |
0 |
0 |
T109 |
6193 |
13 |
0 |
0 |
T112 |
6838 |
64 |
0 |
0 |
T117 |
10390 |
93 |
0 |
0 |
T148 |
2198 |
2 |
0 |
0 |
T149 |
103830 |
824 |
0 |
0 |
T150 |
95743 |
438 |
0 |
0 |
T151 |
12643 |
12 |
0 |
0 |
T152 |
108413 |
609 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
5616 |
0 |
0 |
T94 |
72789 |
685 |
0 |
0 |
T99 |
31870 |
148 |
0 |
0 |
T109 |
6193 |
42 |
0 |
0 |
T112 |
6838 |
4 |
0 |
0 |
T117 |
10390 |
19 |
0 |
0 |
T148 |
2198 |
2 |
0 |
0 |
T149 |
103830 |
549 |
0 |
0 |
T150 |
95743 |
395 |
0 |
0 |
T151 |
12643 |
19 |
0 |
0 |
T152 |
108413 |
693 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
6107 |
0 |
0 |
T94 |
72789 |
452 |
0 |
0 |
T99 |
31870 |
195 |
0 |
0 |
T109 |
6193 |
54 |
0 |
0 |
T112 |
6838 |
13 |
0 |
0 |
T117 |
10390 |
40 |
0 |
0 |
T148 |
2198 |
1 |
0 |
0 |
T149 |
103830 |
826 |
0 |
0 |
T150 |
95743 |
474 |
0 |
0 |
T151 |
12643 |
16 |
0 |
0 |
T152 |
108413 |
829 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
6321 |
0 |
0 |
T94 |
72789 |
529 |
0 |
0 |
T99 |
31870 |
207 |
0 |
0 |
T109 |
6193 |
51 |
0 |
0 |
T112 |
6838 |
1 |
0 |
0 |
T117 |
10390 |
38 |
0 |
0 |
T119 |
11814 |
136 |
0 |
0 |
T149 |
103830 |
678 |
0 |
0 |
T150 |
95743 |
397 |
0 |
0 |
T151 |
12643 |
28 |
0 |
0 |
T152 |
108413 |
910 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
5801 |
0 |
0 |
T94 |
72789 |
542 |
0 |
0 |
T99 |
31870 |
200 |
0 |
0 |
T109 |
6193 |
5 |
0 |
0 |
T112 |
6838 |
15 |
0 |
0 |
T117 |
10390 |
49 |
0 |
0 |
T148 |
2198 |
6 |
0 |
0 |
T149 |
103830 |
618 |
0 |
0 |
T150 |
95743 |
345 |
0 |
0 |
T151 |
12643 |
23 |
0 |
0 |
T152 |
108413 |
789 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
5537 |
0 |
0 |
T94 |
72789 |
395 |
0 |
0 |
T99 |
31870 |
118 |
0 |
0 |
T109 |
6193 |
14 |
0 |
0 |
T112 |
6838 |
45 |
0 |
0 |
T117 |
10390 |
56 |
0 |
0 |
T148 |
2198 |
9 |
0 |
0 |
T149 |
103830 |
692 |
0 |
0 |
T150 |
95743 |
349 |
0 |
0 |
T151 |
12643 |
9 |
0 |
0 |
T152 |
108413 |
749 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
5726 |
0 |
0 |
T94 |
72789 |
446 |
0 |
0 |
T99 |
31870 |
37 |
0 |
0 |
T109 |
6193 |
3 |
0 |
0 |
T112 |
6838 |
28 |
0 |
0 |
T117 |
10390 |
30 |
0 |
0 |
T148 |
2198 |
2 |
0 |
0 |
T149 |
103830 |
696 |
0 |
0 |
T150 |
95743 |
584 |
0 |
0 |
T151 |
12643 |
13 |
0 |
0 |
T152 |
108413 |
888 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
6025 |
0 |
0 |
T94 |
72789 |
679 |
0 |
0 |
T99 |
31870 |
101 |
0 |
0 |
T109 |
6193 |
65 |
0 |
0 |
T112 |
6838 |
1 |
0 |
0 |
T117 |
10390 |
28 |
0 |
0 |
T119 |
11814 |
42 |
0 |
0 |
T149 |
103830 |
687 |
0 |
0 |
T150 |
95743 |
436 |
0 |
0 |
T151 |
12643 |
27 |
0 |
0 |
T152 |
108413 |
809 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
2797 |
0 |
0 |
T94 |
72789 |
104 |
0 |
0 |
T99 |
31870 |
34 |
0 |
0 |
T109 |
6193 |
11 |
0 |
0 |
T112 |
6838 |
8 |
0 |
0 |
T117 |
10390 |
12 |
0 |
0 |
T148 |
2198 |
6 |
0 |
0 |
T149 |
103830 |
161 |
0 |
0 |
T150 |
95743 |
65 |
0 |
0 |
T151 |
12643 |
32 |
0 |
0 |
T152 |
108413 |
158 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
2808 |
0 |
0 |
T94 |
72789 |
102 |
0 |
0 |
T99 |
31870 |
59 |
0 |
0 |
T109 |
6193 |
10 |
0 |
0 |
T117 |
10390 |
5 |
0 |
0 |
T119 |
11814 |
11 |
0 |
0 |
T148 |
2198 |
7 |
0 |
0 |
T149 |
103830 |
181 |
0 |
0 |
T150 |
95743 |
61 |
0 |
0 |
T151 |
12643 |
46 |
0 |
0 |
T152 |
108413 |
177 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
2655 |
0 |
0 |
T94 |
72789 |
105 |
0 |
0 |
T99 |
31870 |
10 |
0 |
0 |
T109 |
6193 |
9 |
0 |
0 |
T112 |
6838 |
12 |
0 |
0 |
T117 |
10390 |
10 |
0 |
0 |
T148 |
2198 |
8 |
0 |
0 |
T149 |
103830 |
144 |
0 |
0 |
T150 |
95743 |
114 |
0 |
0 |
T151 |
12643 |
37 |
0 |
0 |
T152 |
108413 |
171 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
2904 |
0 |
0 |
T94 |
72789 |
141 |
0 |
0 |
T99 |
31870 |
37 |
0 |
0 |
T109 |
6193 |
15 |
0 |
0 |
T117 |
10390 |
10 |
0 |
0 |
T119 |
11814 |
11 |
0 |
0 |
T148 |
2198 |
5 |
0 |
0 |
T149 |
103830 |
161 |
0 |
0 |
T150 |
95743 |
112 |
0 |
0 |
T151 |
12643 |
17 |
0 |
0 |
T152 |
108413 |
186 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
3496 |
0 |
0 |
T94 |
72789 |
165 |
0 |
0 |
T99 |
31870 |
37 |
0 |
0 |
T109 |
6193 |
14 |
0 |
0 |
T112 |
6838 |
26 |
0 |
0 |
T117 |
10390 |
12 |
0 |
0 |
T148 |
2198 |
8 |
0 |
0 |
T149 |
103830 |
289 |
0 |
0 |
T150 |
95743 |
133 |
0 |
0 |
T151 |
12643 |
8 |
0 |
0 |
T152 |
108413 |
337 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
5553 |
0 |
0 |
T18 |
5008 |
36 |
0 |
0 |
T19 |
274207 |
0 |
0 |
0 |
T34 |
0 |
57 |
0 |
0 |
T37 |
216538 |
0 |
0 |
0 |
T50 |
176728 |
0 |
0 |
0 |
T66 |
1371 |
0 |
0 |
0 |
T84 |
0 |
73 |
0 |
0 |
T90 |
5354 |
0 |
0 |
0 |
T153 |
0 |
24 |
0 |
0 |
T154 |
0 |
48 |
0 |
0 |
T155 |
0 |
51 |
0 |
0 |
T156 |
0 |
8 |
0 |
0 |
T157 |
0 |
69 |
0 |
0 |
T158 |
0 |
22 |
0 |
0 |
T159 |
0 |
6 |
0 |
0 |
T160 |
2685 |
0 |
0 |
0 |
T161 |
109298 |
0 |
0 |
0 |
T162 |
408851 |
0 |
0 |
0 |
T163 |
122595 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
2802 |
0 |
0 |
T94 |
72789 |
109 |
0 |
0 |
T99 |
31870 |
17 |
0 |
0 |
T109 |
6193 |
16 |
0 |
0 |
T112 |
6838 |
11 |
0 |
0 |
T117 |
10390 |
8 |
0 |
0 |
T148 |
2198 |
5 |
0 |
0 |
T149 |
103830 |
194 |
0 |
0 |
T150 |
95743 |
141 |
0 |
0 |
T151 |
12643 |
38 |
0 |
0 |
T152 |
108413 |
161 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
2730 |
0 |
0 |
T94 |
72789 |
111 |
0 |
0 |
T99 |
31870 |
44 |
0 |
0 |
T109 |
6193 |
4 |
0 |
0 |
T112 |
6838 |
9 |
0 |
0 |
T117 |
10390 |
13 |
0 |
0 |
T148 |
2198 |
4 |
0 |
0 |
T149 |
103830 |
165 |
0 |
0 |
T150 |
95743 |
94 |
0 |
0 |
T151 |
12643 |
27 |
0 |
0 |
T152 |
108413 |
150 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
2469 |
0 |
0 |
T94 |
72789 |
79 |
0 |
0 |
T99 |
31870 |
30 |
0 |
0 |
T109 |
6193 |
12 |
0 |
0 |
T119 |
11814 |
15 |
0 |
0 |
T122 |
118066 |
722 |
0 |
0 |
T148 |
2198 |
5 |
0 |
0 |
T149 |
103830 |
134 |
0 |
0 |
T150 |
95743 |
83 |
0 |
0 |
T151 |
12643 |
24 |
0 |
0 |
T152 |
108413 |
125 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
2616 |
0 |
0 |
T94 |
72789 |
73 |
0 |
0 |
T99 |
31870 |
16 |
0 |
0 |
T109 |
6193 |
5 |
0 |
0 |
T112 |
6838 |
1 |
0 |
0 |
T117 |
10390 |
5 |
0 |
0 |
T148 |
2198 |
5 |
0 |
0 |
T149 |
103830 |
89 |
0 |
0 |
T150 |
95743 |
75 |
0 |
0 |
T151 |
12643 |
39 |
0 |
0 |
T152 |
108413 |
141 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
2435 |
0 |
0 |
T94 |
72789 |
83 |
0 |
0 |
T99 |
31870 |
14 |
0 |
0 |
T109 |
6193 |
6 |
0 |
0 |
T112 |
6838 |
2 |
0 |
0 |
T117 |
10390 |
7 |
0 |
0 |
T148 |
2198 |
3 |
0 |
0 |
T149 |
103830 |
109 |
0 |
0 |
T150 |
95743 |
64 |
0 |
0 |
T151 |
12643 |
38 |
0 |
0 |
T152 |
108413 |
134 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
2478 |
0 |
0 |
T94 |
72789 |
99 |
0 |
0 |
T99 |
31870 |
35 |
0 |
0 |
T109 |
6193 |
6 |
0 |
0 |
T117 |
10390 |
6 |
0 |
0 |
T119 |
11814 |
6 |
0 |
0 |
T148 |
2198 |
3 |
0 |
0 |
T149 |
103830 |
141 |
0 |
0 |
T150 |
95743 |
77 |
0 |
0 |
T151 |
12643 |
6 |
0 |
0 |
T152 |
108413 |
107 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
3538 |
0 |
0 |
T94 |
72789 |
165 |
0 |
0 |
T99 |
31870 |
29 |
0 |
0 |
T109 |
6193 |
8 |
0 |
0 |
T112 |
6838 |
3 |
0 |
0 |
T117 |
10390 |
11 |
0 |
0 |
T119 |
11814 |
44 |
0 |
0 |
T149 |
103830 |
313 |
0 |
0 |
T150 |
95743 |
136 |
0 |
0 |
T151 |
12643 |
28 |
0 |
0 |
T152 |
108413 |
260 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
2557 |
0 |
0 |
T94 |
72789 |
75 |
0 |
0 |
T99 |
31870 |
33 |
0 |
0 |
T109 |
6193 |
6 |
0 |
0 |
T112 |
6838 |
18 |
0 |
0 |
T117 |
10390 |
10 |
0 |
0 |
T148 |
2198 |
2 |
0 |
0 |
T149 |
103830 |
138 |
0 |
0 |
T150 |
95743 |
44 |
0 |
0 |
T151 |
12643 |
19 |
0 |
0 |
T152 |
108413 |
111 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
3537 |
0 |
0 |
T94 |
72789 |
276 |
0 |
0 |
T99 |
31870 |
46 |
0 |
0 |
T109 |
6193 |
15 |
0 |
0 |
T112 |
6838 |
21 |
0 |
0 |
T117 |
10390 |
18 |
0 |
0 |
T148 |
2198 |
8 |
0 |
0 |
T149 |
103830 |
276 |
0 |
0 |
T150 |
95743 |
162 |
0 |
0 |
T151 |
12643 |
4 |
0 |
0 |
T152 |
108413 |
309 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
2979 |
0 |
0 |
T94 |
72789 |
119 |
0 |
0 |
T99 |
31870 |
46 |
0 |
0 |
T109 |
6193 |
13 |
0 |
0 |
T117 |
10390 |
11 |
0 |
0 |
T119 |
11814 |
16 |
0 |
0 |
T148 |
2198 |
2 |
0 |
0 |
T149 |
103830 |
161 |
0 |
0 |
T150 |
95743 |
83 |
0 |
0 |
T151 |
12643 |
50 |
0 |
0 |
T152 |
108413 |
158 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
2505 |
0 |
0 |
T94 |
72789 |
64 |
0 |
0 |
T99 |
31870 |
12 |
0 |
0 |
T109 |
6193 |
1 |
0 |
0 |
T112 |
6838 |
1 |
0 |
0 |
T119 |
11814 |
11 |
0 |
0 |
T122 |
118066 |
740 |
0 |
0 |
T149 |
103830 |
128 |
0 |
0 |
T150 |
95743 |
78 |
0 |
0 |
T151 |
12643 |
32 |
0 |
0 |
T152 |
108413 |
118 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
2488 |
0 |
0 |
T94 |
72789 |
79 |
0 |
0 |
T99 |
31870 |
25 |
0 |
0 |
T109 |
6193 |
7 |
0 |
0 |
T119 |
11814 |
5 |
0 |
0 |
T122 |
118066 |
757 |
0 |
0 |
T149 |
103830 |
127 |
0 |
0 |
T150 |
95743 |
55 |
0 |
0 |
T151 |
12643 |
8 |
0 |
0 |
T152 |
108413 |
121 |
0 |
0 |
T164 |
21087 |
64 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
2668 |
0 |
0 |
T94 |
72789 |
92 |
0 |
0 |
T99 |
31870 |
18 |
0 |
0 |
T109 |
6193 |
6 |
0 |
0 |
T117 |
10390 |
1 |
0 |
0 |
T119 |
11814 |
4 |
0 |
0 |
T148 |
2198 |
7 |
0 |
0 |
T149 |
103830 |
142 |
0 |
0 |
T150 |
95743 |
70 |
0 |
0 |
T151 |
12643 |
15 |
0 |
0 |
T152 |
108413 |
100 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
2568 |
0 |
0 |
T94 |
72789 |
78 |
0 |
0 |
T99 |
31870 |
4 |
0 |
0 |
T109 |
6193 |
4 |
0 |
0 |
T112 |
6838 |
3 |
0 |
0 |
T119 |
11814 |
17 |
0 |
0 |
T148 |
2198 |
3 |
0 |
0 |
T149 |
103830 |
130 |
0 |
0 |
T150 |
95743 |
69 |
0 |
0 |
T151 |
12643 |
16 |
0 |
0 |
T152 |
108413 |
110 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
2487 |
0 |
0 |
T94 |
72789 |
71 |
0 |
0 |
T99 |
31870 |
19 |
0 |
0 |
T109 |
6193 |
7 |
0 |
0 |
T117 |
10390 |
11 |
0 |
0 |
T119 |
11814 |
9 |
0 |
0 |
T122 |
118066 |
705 |
0 |
0 |
T149 |
103830 |
127 |
0 |
0 |
T150 |
95743 |
76 |
0 |
0 |
T151 |
12643 |
27 |
0 |
0 |
T152 |
108413 |
95 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349964600 |
2606 |
0 |
0 |
T94 |
72789 |
64 |
0 |
0 |
T99 |
31870 |
23 |
0 |
0 |
T109 |
6193 |
12 |
0 |
0 |
T112 |
6838 |
9 |
0 |
0 |
T117 |
10390 |
7 |
0 |
0 |
T148 |
2198 |
5 |
0 |
0 |
T149 |
103830 |
113 |
0 |
0 |
T150 |
95743 |
48 |
0 |
0 |
T151 |
12643 |
9 |
0 |
0 |
T152 |
108413 |
118 |
0 |
0 |