Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3415886	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3847436

1

T1

884

T2

23216

T3

894

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4088334	1			T1	3		T2	32191		T3	6
values[0x0]	1586427	1			T1	475		T2	11918		T3	462
values[0x1]	1588561	1			T1	408		T2	11693		T3	432

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2425368	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4837954

1

T1

884

T2

33481

T3

895

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27459	1			T2	218		T3	4		T5	10
valid_sources[0x01]	27199	1			T2	234		T3	5		T6	37
valid_sources[0x02]	27771	1			T2	217		T3	3		T4	1
valid_sources[0x03]	26696	1			T2	251		T3	2		T5	8
valid_sources[0x04]	28305	1			T2	201		T3	6		T5	6
valid_sources[0x05]	27617	1			T2	256		T4	1		T5	8
valid_sources[0x06]	29801	1			T2	232		T3	1		T5	25
valid_sources[0x07]	31992	1			T2	206		T3	1		T5	4
valid_sources[0x08]	46423	1			T2	233		T6	587		T11	132
valid_sources[0x09]	26676	1			T2	284		T3	5		T5	2
valid_sources[0x0a]	26053	1			T2	211		T3	1		T4	1
valid_sources[0x0b]	25688	1			T2	172		T3	4		T4	1
valid_sources[0x0c]	26993	1			T1	436		T2	240		T3	5
valid_sources[0x0d]	28089	1			T2	174		T3	1		T4	1
valid_sources[0x0e]	27237	1			T2	178		T3	2		T4	1
valid_sources[0x0f]	27318	1			T2	251		T3	3		T4	1
valid_sources[0x10]	26077	1			T2	260		T3	8		T4	1
valid_sources[0x11]	28529	1			T2	222		T3	8		T5	15
valid_sources[0x12]	25865	1			T2	239		T4	2		T5	5
valid_sources[0x13]	24819	1			T2	232		T3	1		T4	1
valid_sources[0x14]	26782	1			T2	221		T3	12		T4	3
valid_sources[0x15]	30831	1			T2	170		T4	1		T5	3
valid_sources[0x16]	31304	1			T2	218		T3	4		T4	4
valid_sources[0x17]	29059	1			T2	206		T3	4		T4	1
valid_sources[0x18]	28081	1			T2	229		T4	1		T5	5
valid_sources[0x19]	26208	1			T2	223		T3	2		T4	2
valid_sources[0x1a]	30782	1			T2	190		T4	1		T5	6
valid_sources[0x1b]	28363	1			T2	218		T3	2		T4	3
valid_sources[0x1c]	26122	1			T2	186		T3	4		T11	121
valid_sources[0x1d]	26468	1			T2	232		T3	5		T5	8
valid_sources[0x1e]	27020	1			T2	230		T3	4		T4	1
valid_sources[0x1f]	27481	1			T2	186		T3	7		T4	3
valid_sources[0x20]	30296	1			T2	219		T5	1		T6	5
valid_sources[0x21]	29142	1			T2	239		T3	1		T4	2
valid_sources[0x22]	27182	1			T2	249		T3	6		T4	2
valid_sources[0x23]	29174	1			T2	208		T3	1		T4	1
valid_sources[0x24]	38284	1			T2	171		T3	10		T4	2
valid_sources[0x25]	29238	1			T2	278		T5	7		T11	137
valid_sources[0x26]	29253	1			T2	191		T3	5		T4	1
valid_sources[0x27]	25147	1			T2	210		T3	4		T4	1
valid_sources[0x28]	26106	1			T2	186		T3	12		T4	1
valid_sources[0x29]	29550	1			T2	193		T3	1		T4	1
valid_sources[0x2a]	27753	1			T2	241		T3	1		T5	2
valid_sources[0x2b]	28198	1			T2	224		T3	1		T4	1
valid_sources[0x2c]	27363	1			T2	245		T3	4		T4	1
valid_sources[0x2d]	26935	1			T2	176		T5	11		T10	1
valid_sources[0x2e]	26104	1			T2	222		T4	4		T5	12
valid_sources[0x2f]	26861	1			T2	226		T3	1		T4	3
valid_sources[0x30]	24421	1			T2	231		T3	7		T5	7
valid_sources[0x31]	31491	1			T2	177		T3	6		T4	2
valid_sources[0x32]	30069	1			T2	218		T3	27		T4	3
valid_sources[0x33]	32095	1			T2	261		T4	4		T5	7
valid_sources[0x34]	40454	1			T2	239		T3	5		T4	3
valid_sources[0x35]	24703	1			T2	212		T3	10		T5	17
valid_sources[0x36]	29937	1			T2	228		T3	16		T5	11
valid_sources[0x37]	27653	1			T2	193		T3	10		T5	5
valid_sources[0x38]	28014	1			T2	219		T5	7		T6	3
valid_sources[0x39]	31690	1			T2	264		T5	4		T6	1
valid_sources[0x3a]	26113	1			T2	195		T3	5		T4	2
valid_sources[0x3b]	25991	1			T2	229		T3	2		T5	5
valid_sources[0x3c]	27258	1			T2	172		T3	5		T4	2
valid_sources[0x3d]	27670	1			T2	186		T4	3		T5	23
valid_sources[0x3e]	29906	1			T2	238		T3	1		T4	3
valid_sources[0x3f]	29082	1			T2	216		T3	3		T4	1
valid_sources[0x40]	36076	1			T2	197		T3	4		T5	7
valid_sources[0x41]	28755	1			T2	198		T4	1		T10	1
valid_sources[0x42]	28601	1			T2	225		T4	1		T5	3
valid_sources[0x43]	28832	1			T2	230		T3	5		T4	1
valid_sources[0x44]	28434	1			T2	226		T3	3		T6	1
valid_sources[0x45]	28481	1			T2	253		T3	3		T4	2
valid_sources[0x46]	29380	1			T2	183		T3	1		T5	11
valid_sources[0x47]	25508	1			T2	216		T5	4		T7	1
valid_sources[0x48]	26699	1			T2	218		T4	1		T5	1
valid_sources[0x49]	26394	1			T2	206		T4	5		T5	1
valid_sources[0x4a]	28657	1			T2	254		T4	1		T5	1
valid_sources[0x4b]	27810	1			T2	251		T3	8		T4	1
valid_sources[0x4c]	30454	1			T2	258		T4	1		T6	3
valid_sources[0x4d]	26773	1			T2	218		T3	8		T4	1
valid_sources[0x4e]	25414	1			T2	228		T3	3		T5	18
valid_sources[0x4f]	26193	1			T2	208		T3	17		T6	10
valid_sources[0x50]	27412	1			T2	302		T3	5		T4	1
valid_sources[0x51]	30035	1			T2	230		T4	1		T5	5
valid_sources[0x52]	28759	1			T2	200		T4	1		T5	1
valid_sources[0x53]	25336	1			T2	202		T3	4		T5	7
valid_sources[0x54]	26480	1			T2	216		T3	8		T6	23
valid_sources[0x55]	25456	1			T2	197		T4	4		T7	1
valid_sources[0x56]	28441	1			T2	194		T4	4		T6	15
valid_sources[0x57]	27338	1			T2	202		T3	3		T4	1
valid_sources[0x58]	27214	1			T2	180		T3	4		T4	2
valid_sources[0x59]	31442	1			T2	218		T3	5		T4	1
valid_sources[0x5a]	26919	1			T2	221		T3	1		T6	11
valid_sources[0x5b]	27460	1			T2	268		T3	4		T6	192
valid_sources[0x5c]	26585	1			T2	192		T3	3		T4	1
valid_sources[0x5d]	27894	1			T2	243		T3	5		T4	2
valid_sources[0x5e]	26306	1			T2	184		T5	7		T6	531
valid_sources[0x5f]	24299	1			T2	186		T3	4		T5	2
valid_sources[0x60]	25806	1			T2	214		T3	1		T4	2
valid_sources[0x61]	29731	1			T2	243		T5	14		T6	65
valid_sources[0x62]	26493	1			T2	203		T3	10		T4	2
valid_sources[0x63]	27699	1			T2	229		T5	3		T10	13
valid_sources[0x64]	34940	1			T2	174		T3	7		T5	13
valid_sources[0x65]	27773	1			T2	244		T3	6		T4	3
valid_sources[0x66]	31070	1			T2	219		T4	2		T6	1
valid_sources[0x67]	30575	1			T2	222		T3	3		T4	3
valid_sources[0x68]	26085	1			T2	174		T3	7		T5	1
valid_sources[0x69]	26963	1			T2	188		T3	2		T4	1
valid_sources[0x6a]	25784	1			T2	221		T3	8		T4	1
valid_sources[0x6b]	26053	1			T2	231		T3	4		T4	2
valid_sources[0x6c]	30818	1			T2	207		T3	3		T4	1
valid_sources[0x6d]	26525	1			T2	204		T3	5		T4	5
valid_sources[0x6e]	28129	1			T2	252		T4	1		T5	4
valid_sources[0x6f]	27246	1			T2	225		T3	2		T5	5
valid_sources[0x70]	28622	1			T2	233		T3	4		T4	1
valid_sources[0x71]	26809	1			T2	201		T5	6		T7	1
valid_sources[0x72]	29690	1			T2	231		T3	6		T4	1
valid_sources[0x73]	28117	1			T2	222		T4	1		T5	1
valid_sources[0x74]	27412	1			T2	218		T3	9		T4	1
valid_sources[0x75]	29096	1			T2	192		T3	6		T4	4
valid_sources[0x76]	24886	1			T2	204		T4	1		T5	2
valid_sources[0x77]	29815	1			T2	227		T3	3		T6	3
valid_sources[0x78]	26637	1			T2	214		T4	1		T5	18
valid_sources[0x79]	25308	1			T2	244		T5	5		T6	4
valid_sources[0x7a]	25077	1			T2	223		T3	2		T4	1
valid_sources[0x7b]	26212	1			T2	217		T3	5		T5	9
valid_sources[0x7c]	31353	1			T2	174		T3	6		T4	1
valid_sources[0x7d]	26243	1			T2	260		T3	4		T5	6
valid_sources[0x7e]	25901	1			T2	227		T4	1		T5	1
valid_sources[0x7f]	29335	1			T2	221		T3	3		T4	2
valid_sources[0x80]	30245	1			T2	243		T3	5		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

987387

1

T1

3

T2

2758

T3

2

values[0x0]

all_enables

biggest_size

1441094

1

T1

473

T2

10336

T3

461

values[0x1]

all_enables

biggest_size

1418955

1

T1

408

T2

10122

T3

431