Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3437479

1

T1

2

T2

32586

T3

6

full_word

3848653

1

T1

884

T2

23216

T3

894

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7285752	1			T1	886		T2	55802		T3	900
auto[TlIntgErrCmd]	123	1			T88	5		T89	8		T91	12
auto[TlIntgErrData]	126	1			T88	6		T89	11		T91	6
auto[TlIntgErrBoth]	131	1			T88	9		T89	11		T91	12

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4091558

1

T1

3

T2

32191

T3

6

auto[1]

3194574

1

T1

883

T2

23611

T3

894

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3103724	1			T2	29433		T3	4		T4	1
auto[TlIntgErrNone]	partial	auto[1]	333405	1			T1	2		T2	3153		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	987671	1			T1	3		T2	2758		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	2860952	1			T1	881		T2	20458		T3	892
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T88	2		T89	4		T91	6
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T88	2		T89	4		T91	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T88	1		T249	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T91	1		T102	2		T141	2
auto[TlIntgErrData]	partial	auto[0]	58	1			T88	5		T89	5		T91	3
auto[TlIntgErrData]	partial	auto[1]	60	1			T88	1		T89	5		T91	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T250	1		T251	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T89	1		T102	1		T252	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T88	3		T89	2		T91	3
auto[TlIntgErrBoth]	partial	auto[1]	74	1			T88	5		T89	6		T91	9
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T89	1		T249	3		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T88	1		T89	2		T102	1