Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	520720602	2698077	0	0
gen_wmask[1].MaskCheckPortA_A	520720602	2698077	0	0
gen_wmask[2].MaskCheckPortA_A	520720602	2698077	0	0
gen_wmask[3].MaskCheckPortA_A	520720602	2698077	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520720602	2698077	0	0
T1	66924	832	0	0
T2	890008	16439	0	0
T3	636772	832	0	0
T4	144400	0	0	0
T5	10694	263	0	0
T6	742832	9734	0	0
T7	4499	68	0	0
T8	279462	832	0	0
T9	1127	0	0	0
T10	94158	832	0	0
T11	236344	8530	0	0
T12	49354	832	0	0
T15	0	911	0	0
T24	0	1018	0	0
T26	0	3187	0	0
T27	0	934	0	0
T35	0	10608	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520720602	2698077	0	0
T1	66924	832	0	0
T2	890008	16439	0	0
T3	636772	832	0	0
T4	144400	0	0	0
T5	10694	263	0	0
T6	742832	9734	0	0
T7	4499	68	0	0
T8	279462	832	0	0
T9	1127	0	0	0
T10	94158	832	0	0
T11	236344	8530	0	0
T12	49354	832	0	0
T15	0	911	0	0
T24	0	1018	0	0
T26	0	3187	0	0
T27	0	934	0	0
T35	0	10608	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520720602	2698077	0	0
T1	66924	832	0	0
T2	890008	16439	0	0
T3	636772	832	0	0
T4	144400	0	0	0
T5	10694	263	0	0
T6	742832	9734	0	0
T7	4499	68	0	0
T8	279462	832	0	0
T9	1127	0	0	0
T10	94158	832	0	0
T11	236344	8530	0	0
T12	49354	832	0	0
T15	0	911	0	0
T24	0	1018	0	0
T26	0	3187	0	0
T27	0	934	0	0
T35	0	10608	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520720602	2698077	0	0
T1	66924	832	0	0
T2	890008	16439	0	0
T3	636772	832	0	0
T4	144400	0	0	0
T5	10694	263	0	0
T6	742832	9734	0	0
T7	4499	68	0	0
T8	279462	832	0	0
T9	1127	0	0	0
T10	94158	832	0	0
T11	236344	8530	0	0
T12	49354	832	0	0
T15	0	911	0	0
T24	0	1018	0	0
T26	0	3187	0	0
T27	0	934	0	0
T35	0	10608	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	394232911	1825717	0	0
gen_wmask[1].MaskCheckPortA_A	394232911	1825717	0	0
gen_wmask[2].MaskCheckPortA_A	394232911	1825717	0	0
gen_wmask[3].MaskCheckPortA_A	394232911	1825717	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394232911	1825717	0	0
T1	66924	832	0	0
T2	256924	8280	0	0
T3	531214	832	0	0
T4	111515	0	0	0
T5	7648	8	0	0
T6	387510	7935	0	0
T7	2939	19	0	0
T8	233211	832	0	0
T9	1127	0	0	0
T10	83998	832	0	0
T11	0	5920	0	0
T12	0	832	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394232911	1825717	0	0
T1	66924	832	0	0
T2	256924	8280	0	0
T3	531214	832	0	0
T4	111515	0	0	0
T5	7648	8	0	0
T6	387510	7935	0	0
T7	2939	19	0	0
T8	233211	832	0	0
T9	1127	0	0	0
T10	83998	832	0	0
T11	0	5920	0	0
T12	0	832	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394232911	1825717	0	0
T1	66924	832	0	0
T2	256924	8280	0	0
T3	531214	832	0	0
T4	111515	0	0	0
T5	7648	8	0	0
T6	387510	7935	0	0
T7	2939	19	0	0
T8	233211	832	0	0
T9	1127	0	0	0
T10	83998	832	0	0
T11	0	5920	0	0
T12	0	832	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394232911	1825717	0	0
T1	66924	832	0	0
T2	256924	8280	0	0
T3	531214	832	0	0
T4	111515	0	0	0
T5	7648	8	0	0
T6	387510	7935	0	0
T7	2939	19	0	0
T8	233211	832	0	0
T9	1127	0	0	0
T10	83998	832	0	0
T11	0	5920	0	0
T12	0	832	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	126487691	872360	0	0
gen_wmask[1].MaskCheckPortA_A	126487691	872360	0	0
gen_wmask[2].MaskCheckPortA_A	126487691	872360	0	0
gen_wmask[3].MaskCheckPortA_A	126487691	872360	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	872360	0	0
T2	633084	8159	0	0
T3	105558	0	0	0
T4	32885	0	0	0
T5	3046	255	0	0
T6	355322	1799	0	0
T7	1560	49	0	0
T8	46251	0	0	0
T10	10160	0	0	0
T11	236344	2610	0	0
T12	49354	0	0	0
T15	0	911	0	0
T24	0	1018	0	0
T26	0	3187	0	0
T27	0	934	0	0
T35	0	10608	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	872360	0	0
T2	633084	8159	0	0
T3	105558	0	0	0
T4	32885	0	0	0
T5	3046	255	0	0
T6	355322	1799	0	0
T7	1560	49	0	0
T8	46251	0	0	0
T10	10160	0	0	0
T11	236344	2610	0	0
T12	49354	0	0	0
T15	0	911	0	0
T24	0	1018	0	0
T26	0	3187	0	0
T27	0	934	0	0
T35	0	10608	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	872360	0	0
T2	633084	8159	0	0
T3	105558	0	0	0
T4	32885	0	0	0
T5	3046	255	0	0
T6	355322	1799	0	0
T7	1560	49	0	0
T8	46251	0	0	0
T10	10160	0	0	0
T11	236344	2610	0	0
T12	49354	0	0	0
T15	0	911	0	0
T24	0	1018	0	0
T26	0	3187	0	0
T27	0	934	0	0
T35	0	10608	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	872360	0	0
T2	633084	8159	0	0
T3	105558	0	0	0
T4	32885	0	0	0
T5	3046	255	0	0
T6	355322	1799	0	0
T7	1560	49	0	0
T8	46251	0	0	0
T10	10160	0	0	0
T11	236344	2610	0	0
T12	49354	0	0	0
T15	0	911	0	0
T24	0	1018	0	0
T26	0	3187	0	0
T27	0	934	0	0
T35	0	10608	0	0