Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396465795	2508949	0	0
DepthKnown_A	396465795	396341260	0	0
RvalidKnown_A	396465795	396341260	0	0
WreadyKnown_A	396465795	396341260	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	2508949	0	0
T1	66924	1663	0	0
T2	256924	9157	0	0
T3	531214	1663	0	0
T4	111515	0	0	0
T5	7648	0	0	0
T6	387510	11643	0	0
T7	2939	0	0	0
T8	233211	1663	0	0
T9	1127	0	0	0
T10	83998	832	0	0
T11	0	4994	0	0
T12	0	832	0	0
T14	0	832	0	0
T15	0	2495	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	396341260	0	0
T1	66924	66833	0	0
T2	256924	256918	0	0
T3	531214	531162	0	0
T4	111515	111438	0	0
T5	7648	7573	0	0
T6	387510	387446	0	0
T7	2939	2859	0	0
T8	233211	233149	0	0
T9	1127	1046	0	0
T10	83998	83918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	396341260	0	0
T1	66924	66833	0	0
T2	256924	256918	0	0
T3	531214	531162	0	0
T4	111515	111438	0	0
T5	7648	7573	0	0
T6	387510	387446	0	0
T7	2939	2859	0	0
T8	233211	233149	0	0
T9	1127	1046	0	0
T10	83998	83918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	396341260	0	0
T1	66924	66833	0	0
T2	256924	256918	0	0
T3	531214	531162	0	0
T4	111515	111438	0	0
T5	7648	7573	0	0
T6	387510	387446	0	0
T7	2939	2859	0	0
T8	233211	233149	0	0
T9	1127	1046	0	0
T10	83998	83918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396465795	2769450	0	0
DepthKnown_A	396465795	396341260	0	0
RvalidKnown_A	396465795	396341260	0	0
WreadyKnown_A	396465795	396341260	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	2769450	0	0
T1	66924	832	0	0
T2	256924	28532	0	0
T3	531214	832	0	0
T4	111515	0	0	0
T5	7648	0	0	0
T6	387510	7488	0	0
T7	2939	0	0	0
T8	233211	832	0	0
T9	1127	0	0	0
T10	83998	832	0	0
T11	0	16053	0	0
T12	0	832	0	0
T14	0	832	0	0
T15	0	1664	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	396341260	0	0
T1	66924	66833	0	0
T2	256924	256918	0	0
T3	531214	531162	0	0
T4	111515	111438	0	0
T5	7648	7573	0	0
T6	387510	387446	0	0
T7	2939	2859	0	0
T8	233211	233149	0	0
T9	1127	1046	0	0
T10	83998	83918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	396341260	0	0
T1	66924	66833	0	0
T2	256924	256918	0	0
T3	531214	531162	0	0
T4	111515	111438	0	0
T5	7648	7573	0	0
T6	387510	387446	0	0
T7	2939	2859	0	0
T8	233211	233149	0	0
T9	1127	1046	0	0
T10	83998	83918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	396341260	0	0
T1	66924	66833	0	0
T2	256924	256918	0	0
T3	531214	531162	0	0
T4	111515	111438	0	0
T5	7648	7573	0	0
T6	387510	387446	0	0
T7	2939	2859	0	0
T8	233211	233149	0	0
T9	1127	1046	0	0
T10	83998	83918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396465795	157203	0	0
DepthKnown_A	396465795	396341260	0	0
RvalidKnown_A	396465795	396341260	0	0
WreadyKnown_A	396465795	396341260	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	157203	0	0
T2	256924	817	0	0
T3	531214	0	0	0
T4	111515	0	0	0
T5	7648	64	0	0
T6	387510	271	0	0
T7	2939	13	0	0
T8	233211	0	0	0
T9	1127	0	0	0
T10	83998	0	0	0
T11	167518	674	0	0
T15	0	237	0	0
T24	0	260	0	0
T26	0	821	0	0
T27	0	174	0	0
T35	0	2129	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	396341260	0	0
T1	66924	66833	0	0
T2	256924	256918	0	0
T3	531214	531162	0	0
T4	111515	111438	0	0
T5	7648	7573	0	0
T6	387510	387446	0	0
T7	2939	2859	0	0
T8	233211	233149	0	0
T9	1127	1046	0	0
T10	83998	83918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	396341260	0	0
T1	66924	66833	0	0
T2	256924	256918	0	0
T3	531214	531162	0	0
T4	111515	111438	0	0
T5	7648	7573	0	0
T6	387510	387446	0	0
T7	2939	2859	0	0
T8	233211	233149	0	0
T9	1127	1046	0	0
T10	83998	83918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	396341260	0	0
T1	66924	66833	0	0
T2	256924	256918	0	0
T3	531214	531162	0	0
T4	111515	111438	0	0
T5	7648	7573	0	0
T6	387510	387446	0	0
T7	2939	2859	0	0
T8	233211	233149	0	0
T9	1127	1046	0	0
T10	83998	83918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396465795	358631	0	0
DepthKnown_A	396465795	396341260	0	0
RvalidKnown_A	396465795	396341260	0	0
WreadyKnown_A	396465795	396341260	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	358631	0	0
T2	256924	3751	0	0
T3	531214	0	0	0
T4	111515	0	0	0
T5	7648	64	0	0
T6	387510	268	0	0
T7	2939	51	0	0
T8	233211	0	0	0
T9	1127	0	0	0
T10	83998	0	0	0
T11	167518	3069	0	0
T15	0	237	0	0
T24	0	260	0	0
T26	0	821	0	0
T27	0	565	0	0
T35	0	2129	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	396341260	0	0
T1	66924	66833	0	0
T2	256924	256918	0	0
T3	531214	531162	0	0
T4	111515	111438	0	0
T5	7648	7573	0	0
T6	387510	387446	0	0
T7	2939	2859	0	0
T8	233211	233149	0	0
T9	1127	1046	0	0
T10	83998	83918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	396341260	0	0
T1	66924	66833	0	0
T2	256924	256918	0	0
T3	531214	531162	0	0
T4	111515	111438	0	0
T5	7648	7573	0	0
T6	387510	387446	0	0
T7	2939	2859	0	0
T8	233211	233149	0	0
T9	1127	1046	0	0
T10	83998	83918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	396341260	0	0
T1	66924	66833	0	0
T2	256924	256918	0	0
T3	531214	531162	0	0
T4	111515	111438	0	0
T5	7648	7573	0	0
T6	387510	387446	0	0
T7	2939	2859	0	0
T8	233211	233149	0	0
T9	1127	1046	0	0
T10	83998	83918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396465795	5901714	0	0
DepthKnown_A	396465795	396341260	0	0
RvalidKnown_A	396465795	396341260	0	0
WreadyKnown_A	396465795	396341260	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	5901714	0	0
T1	66924	54	0	0
T2	256924	52419	0	0
T3	531214	68	0	0
T4	111515	312	0	0
T5	7648	1304	0	0
T6	387510	4570	0	0
T7	2939	118	0	0
T8	233211	12714	0	0
T9	1127	25	0	0
T10	83998	51	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	396341260	0	0
T1	66924	66833	0	0
T2	256924	256918	0	0
T3	531214	531162	0	0
T4	111515	111438	0	0
T5	7648	7573	0	0
T6	387510	387446	0	0
T7	2939	2859	0	0
T8	233211	233149	0	0
T9	1127	1046	0	0
T10	83998	83918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	396341260	0	0
T1	66924	66833	0	0
T2	256924	256918	0	0
T3	531214	531162	0	0
T4	111515	111438	0	0
T5	7648	7573	0	0
T6	387510	387446	0	0
T7	2939	2859	0	0
T8	233211	233149	0	0
T9	1127	1046	0	0
T10	83998	83918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	396341260	0	0
T1	66924	66833	0	0
T2	256924	256918	0	0
T3	531214	531162	0	0
T4	111515	111438	0	0
T5	7648	7573	0	0
T6	387510	387446	0	0
T7	2939	2859	0	0
T8	233211	233149	0	0
T9	1127	1046	0	0
T10	83998	83918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396465795	12460419	0	0
DepthKnown_A	396465795	396341260	0	0
RvalidKnown_A	396465795	396341260	0	0
WreadyKnown_A	396465795	396341260	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	12460419	0	0
T1	66924	54	0	0
T2	256924	210464	0	0
T3	531214	184	0	0
T4	111515	312	0	0
T5	7648	1304	0	0
T6	387510	4492	0	0
T7	2939	597	0	0
T8	233211	12714	0	0
T9	1127	25	0	0
T10	83998	51	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	396341260	0	0
T1	66924	66833	0	0
T2	256924	256918	0	0
T3	531214	531162	0	0
T4	111515	111438	0	0
T5	7648	7573	0	0
T6	387510	387446	0	0
T7	2939	2859	0	0
T8	233211	233149	0	0
T9	1127	1046	0	0
T10	83998	83918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	396341260	0	0
T1	66924	66833	0	0
T2	256924	256918	0	0
T3	531214	531162	0	0
T4	111515	111438	0	0
T5	7648	7573	0	0
T6	387510	387446	0	0
T7	2939	2859	0	0
T8	233211	233149	0	0
T9	1127	1046	0	0
T10	83998	83918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396465795	396341260	0	0
T1	66924	66833	0	0
T2	256924	256918	0	0
T3	531214	531162	0	0
T4	111515	111438	0	0
T5	7648	7573	0	0
T6	387510	387446	0	0
T7	2939	2859	0	0
T8	233211	233149	0	0
T9	1127	1046	0	0
T10	83998	83918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0