Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Covered	T2,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T11
1	0	Covered	T2,T6,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T6,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	647208293	519446498	0	0
CheckNGreaterZero_A	2718	2718	0	0
GntImpliesReady_A	647208293	3046017	0	0
GntImpliesValid_A	647208293	3046017	0	0
GrantKnown_A	647208293	519446498	0	0
IdxKnown_A	647208293	519446498	0	0
IndexIsCorrect_A	647208293	3046017	0	0
LockArbDecision_A	647208293	0	0	0
NoReadyValidNoGrant_A	647208293	0	0	0
ReadyAndValidImplyGrant_A	647208293	3046017	0	0
ReqAndReadyImplyGrant_A	647208293	3046017	0	0
ReqImpliesValid_A	647208293	3046017	0	0
ReqStaysHighUntilGranted0_M	647208293	0	0	0
RoundRobin_A	647208293	4	0	906
ValidKnown_A	647208293	519446498	0	0
gen_data_port_assertion.DataFlow_A	647208293	3046017	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	647208293	519446498	0	0
T1	127973	127537	0	0
T2	1523092	885126	0	0
T3	742330	636720	0	0
T4	177285	142958	0	0
T5	13740	10253	0	0
T6	1098154	741324	0	0
T7	6059	4419	0	0
T8	325713	279093	0	0
T9	1127	1046	0	0
T10	104318	94078	0	0
T11	472688	232479	0	0
T12	49354	49354	0	0
T14	0	25482	0	0
T15	0	248219	0	0
T24	0	35640	0	0
T26	0	83480	0	0
T27	0	13776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2718	2718	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	647208293	3046017	0	0
T1	66924	832	0	0
T2	1523092	18138	0	0
T3	742330	832	0	0
T4	177285	0	0	0
T5	13740	336	0	0
T6	1098154	10512	0	0
T7	6059	101	0	0
T8	325713	832	0	0
T9	1127	0	0	0
T10	104318	832	0	0
T11	472688	11134	0	0
T12	98708	832	0	0
T15	0	1278	0	0
T17	0	5185	0	0
T24	0	1542	0	0
T26	0	4533	0	0
T27	0	1118	0	0
T35	0	12989	0	0
T45	0	645	0	0
T46	0	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	647208293	3046017	0	0
T1	66924	832	0	0
T2	1523092	18138	0	0
T3	742330	832	0	0
T4	177285	0	0	0
T5	13740	336	0	0
T6	1098154	10512	0	0
T7	6059	101	0	0
T8	325713	832	0	0
T9	1127	0	0	0
T10	104318	832	0	0
T11	472688	11134	0	0
T12	98708	832	0	0
T15	0	1278	0	0
T17	0	5185	0	0
T24	0	1542	0	0
T26	0	4533	0	0
T27	0	1118	0	0
T35	0	12989	0	0
T45	0	645	0	0
T46	0	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	647208293	519446498	0	0
T1	127973	127537	0	0
T2	1523092	885126	0	0
T3	742330	636720	0	0
T4	177285	142958	0	0
T5	13740	10253	0	0
T6	1098154	741324	0	0
T7	6059	4419	0	0
T8	325713	279093	0	0
T9	1127	1046	0	0
T10	104318	94078	0	0
T11	472688	232479	0	0
T12	49354	49354	0	0
T14	0	25482	0	0
T15	0	248219	0	0
T24	0	35640	0	0
T26	0	83480	0	0
T27	0	13776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	647208293	519446498	0	0
T1	127973	127537	0	0
T2	1523092	885126	0	0
T3	742330	636720	0	0
T4	177285	142958	0	0
T5	13740	10253	0	0
T6	1098154	741324	0	0
T7	6059	4419	0	0
T8	325713	279093	0	0
T9	1127	1046	0	0
T10	104318	94078	0	0
T11	472688	232479	0	0
T12	49354	49354	0	0
T14	0	25482	0	0
T15	0	248219	0	0
T24	0	35640	0	0
T26	0	83480	0	0
T27	0	13776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	647208293	3046017	0	0
T1	66924	832	0	0
T2	1523092	18138	0	0
T3	742330	832	0	0
T4	177285	0	0	0
T5	13740	336	0	0
T6	1098154	10512	0	0
T7	6059	101	0	0
T8	325713	832	0	0
T9	1127	0	0	0
T10	104318	832	0	0
T11	472688	11134	0	0
T12	98708	832	0	0
T15	0	1278	0	0
T17	0	5185	0	0
T24	0	1542	0	0
T26	0	4533	0	0
T27	0	1118	0	0
T35	0	12989	0	0
T45	0	645	0	0
T46	0	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	647208293	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	647208293	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	647208293	3046017	0	0
T1	66924	832	0	0
T2	1523092	18138	0	0
T3	742330	832	0	0
T4	177285	0	0	0
T5	13740	336	0	0
T6	1098154	10512	0	0
T7	6059	101	0	0
T8	325713	832	0	0
T9	1127	0	0	0
T10	104318	832	0	0
T11	472688	11134	0	0
T12	98708	832	0	0
T15	0	1278	0	0
T17	0	5185	0	0
T24	0	1542	0	0
T26	0	4533	0	0
T27	0	1118	0	0
T35	0	12989	0	0
T45	0	645	0	0
T46	0	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	647208293	3046017	0	0
T1	66924	832	0	0
T2	1523092	18138	0	0
T3	742330	832	0	0
T4	177285	0	0	0
T5	13740	336	0	0
T6	1098154	10512	0	0
T7	6059	101	0	0
T8	325713	832	0	0
T9	1127	0	0	0
T10	104318	832	0	0
T11	472688	11134	0	0
T12	98708	832	0	0
T15	0	1278	0	0
T17	0	5185	0	0
T24	0	1542	0	0
T26	0	4533	0	0
T27	0	1118	0	0
T35	0	12989	0	0
T45	0	645	0	0
T46	0	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	647208293	3046017	0	0
T1	66924	832	0	0
T2	1523092	18138	0	0
T3	742330	832	0	0
T4	177285	0	0	0
T5	13740	336	0	0
T6	1098154	10512	0	0
T7	6059	101	0	0
T8	325713	832	0	0
T9	1127	0	0	0
T10	104318	832	0	0
T11	472688	11134	0	0
T12	98708	832	0	0
T15	0	1278	0	0
T17	0	5185	0	0
T24	0	1542	0	0
T26	0	4533	0	0
T27	0	1118	0	0
T35	0	12989	0	0
T45	0	645	0	0
T46	0	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	647208293	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	647208293	4	0	906
T47	133441	1	0	1
T48	0	2	0	0
T49	0	1	0	0
T50	163051	0	0	1
T51	363373	0	0	1
T52	600362	0	0	1
T53	427087	0	0	1
T54	308792	0	0	1
T55	509141	0	0	1
T56	325562	0	0	1
T57	129998	0	0	1
T58	658123	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	647208293	519446498	0	0
T1	127973	127537	0	0
T2	1523092	885126	0	0
T3	742330	636720	0	0
T4	177285	142958	0	0
T5	13740	10253	0	0
T6	1098154	741324	0	0
T7	6059	4419	0	0
T8	325713	279093	0	0
T9	1127	1046	0	0
T10	104318	94078	0	0
T11	472688	232479	0	0
T12	49354	49354	0	0
T14	0	25482	0	0
T15	0	248219	0	0
T24	0	35640	0	0
T26	0	83480	0	0
T27	0	13776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	647208293	3046017	0	0
T1	66924	832	0	0
T2	1523092	18138	0	0
T3	742330	832	0	0
T4	177285	0	0	0
T5	13740	336	0	0
T6	1098154	10512	0	0
T7	6059	101	0	0
T8	325713	832	0	0
T9	1127	0	0	0
T10	104318	832	0	0
T11	472688	11134	0	0
T12	98708	832	0	0
T15	0	1278	0	0
T17	0	5185	0	0
T24	0	1542	0	0
T26	0	4533	0	0
T27	0	1118	0	0
T35	0	12989	0	0
T45	0	645	0	0
T46	0	7	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Covered	T2,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	126487691	25567213	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	126487691	616543	0	0
GntImpliesValid_A	126487691	616543	0	0
GrantKnown_A	126487691	25567213	0	0
IdxKnown_A	126487691	25567213	0	0
IndexIsCorrect_A	126487691	616543	0	0
LockArbDecision_A	126487691	0	0	0
NoReadyValidNoGrant_A	126487691	0	0	0
ReadyAndValidImplyGrant_A	126487691	616543	0	0
ReqAndReadyImplyGrant_A	126487691	616543	0	0
ReqImpliesValid_A	126487691	616543	0	0
ReqStaysHighUntilGranted0_M	126487691	0	0	0
RoundRobin_A	126487691	0	0	0
ValidKnown_A	126487691	25567213	0	0
gen_data_port_assertion.DataFlow_A	126487691	616543	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	25567213	0	0
T2	633084	78976	0	0
T3	105558	0	0	0
T4	32885	31520	0	0
T5	3046	2680	0	0
T6	355322	53664	0	0
T7	1560	1560	0	0
T8	46251	0	0	0
T10	10160	0	0	0
T11	236344	107472	0	0
T12	49354	0	0	0
T15	0	111728	0	0
T24	0	35640	0	0
T26	0	83480	0	0
T27	0	13776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	616543	0	0
T2	633084	3025	0	0
T3	105558	0	0	0
T4	32885	0	0	0
T5	3046	264	0	0
T6	355322	1273	0	0
T7	1560	69	0	0
T8	46251	0	0	0
T10	10160	0	0	0
T11	236344	4524	0	0
T12	49354	0	0	0
T15	0	1276	0	0
T24	0	1542	0	0
T26	0	4275	0	0
T27	0	599	0	0
T35	0	8340	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	616543	0	0
T2	633084	3025	0	0
T3	105558	0	0	0
T4	32885	0	0	0
T5	3046	264	0	0
T6	355322	1273	0	0
T7	1560	69	0	0
T8	46251	0	0	0
T10	10160	0	0	0
T11	236344	4524	0	0
T12	49354	0	0	0
T15	0	1276	0	0
T24	0	1542	0	0
T26	0	4275	0	0
T27	0	599	0	0
T35	0	8340	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	25567213	0	0
T2	633084	78976	0	0
T3	105558	0	0	0
T4	32885	31520	0	0
T5	3046	2680	0	0
T6	355322	53664	0	0
T7	1560	1560	0	0
T8	46251	0	0	0
T10	10160	0	0	0
T11	236344	107472	0	0
T12	49354	0	0	0
T15	0	111728	0	0
T24	0	35640	0	0
T26	0	83480	0	0
T27	0	13776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	25567213	0	0
T2	633084	78976	0	0
T3	105558	0	0	0
T4	32885	31520	0	0
T5	3046	2680	0	0
T6	355322	53664	0	0
T7	1560	1560	0	0
T8	46251	0	0	0
T10	10160	0	0	0
T11	236344	107472	0	0
T12	49354	0	0	0
T15	0	111728	0	0
T24	0	35640	0	0
T26	0	83480	0	0
T27	0	13776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	616543	0	0
T2	633084	3025	0	0
T3	105558	0	0	0
T4	32885	0	0	0
T5	3046	264	0	0
T6	355322	1273	0	0
T7	1560	69	0	0
T8	46251	0	0	0
T10	10160	0	0	0
T11	236344	4524	0	0
T12	49354	0	0	0
T15	0	1276	0	0
T24	0	1542	0	0
T26	0	4275	0	0
T27	0	599	0	0
T35	0	8340	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	616543	0	0
T2	633084	3025	0	0
T3	105558	0	0	0
T4	32885	0	0	0
T5	3046	264	0	0
T6	355322	1273	0	0
T7	1560	69	0	0
T8	46251	0	0	0
T10	10160	0	0	0
T11	236344	4524	0	0
T12	49354	0	0	0
T15	0	1276	0	0
T24	0	1542	0	0
T26	0	4275	0	0
T27	0	599	0	0
T35	0	8340	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	616543	0	0
T2	633084	3025	0	0
T3	105558	0	0	0
T4	32885	0	0	0
T5	3046	264	0	0
T6	355322	1273	0	0
T7	1560	69	0	0
T8	46251	0	0	0
T10	10160	0	0	0
T11	236344	4524	0	0
T12	49354	0	0	0
T15	0	1276	0	0
T24	0	1542	0	0
T26	0	4275	0	0
T27	0	599	0	0
T35	0	8340	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	616543	0	0
T2	633084	3025	0	0
T3	105558	0	0	0
T4	32885	0	0	0
T5	3046	264	0	0
T6	355322	1273	0	0
T7	1560	69	0	0
T8	46251	0	0	0
T10	10160	0	0	0
T11	236344	4524	0	0
T12	49354	0	0	0
T15	0	1276	0	0
T24	0	1542	0	0
T26	0	4275	0	0
T27	0	599	0	0
T35	0	8340	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	25567213	0	0
T2	633084	78976	0	0
T3	105558	0	0	0
T4	32885	31520	0	0
T5	3046	2680	0	0
T6	355322	53664	0	0
T7	1560	1560	0	0
T8	46251	0	0	0
T10	10160	0	0	0
T11	236344	107472	0	0
T12	49354	0	0	0
T15	0	111728	0	0
T24	0	35640	0	0
T26	0	83480	0	0
T27	0	13776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	616543	0	0
T2	633084	3025	0	0
T3	105558	0	0	0
T4	32885	0	0	0
T5	3046	264	0	0
T6	355322	1273	0	0
T7	1560	69	0	0
T8	46251	0	0	0
T10	10160	0	0	0
T11	236344	4524	0	0
T12	49354	0	0	0
T15	0	1276	0	0
T24	0	1542	0	0
T26	0	4275	0	0
T27	0	599	0	0
T35	0	8340	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T11
1	0	Covered	T2,T6,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T6,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T6,T11
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	126487691	99727586	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	126487691	455884	0	0
GntImpliesValid_A	126487691	455884	0	0
GrantKnown_A	126487691	99727586	0	0
IdxKnown_A	126487691	99727586	0	0
IndexIsCorrect_A	126487691	455884	0	0
LockArbDecision_A	126487691	0	0	0
NoReadyValidNoGrant_A	126487691	0	0	0
ReadyAndValidImplyGrant_A	126487691	455884	0	0
ReqAndReadyImplyGrant_A	126487691	455884	0	0
ReqImpliesValid_A	126487691	455884	0	0
ReqStaysHighUntilGranted0_M	126487691	0	0	0
RoundRobin_A	126487691	0	0	0
ValidKnown_A	126487691	99727586	0	0
gen_data_port_assertion.DataFlow_A	126487691	455884	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	99727586	0	0
T1	61049	60704	0	0
T2	633084	549232	0	0
T3	105558	105558	0	0
T4	32885	0	0	0
T5	3046	0	0	0
T6	355322	300214	0	0
T7	1560	0	0	0
T8	46251	45944	0	0
T10	10160	10160	0	0
T11	236344	125007	0	0
T12	0	49354	0	0
T14	0	25482	0	0
T15	0	136491	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	455884	0	0
T2	633084	5997	0	0
T3	105558	0	0	0
T4	32885	0	0	0
T5	3046	0	0	0
T6	355322	1014	0	0
T7	1560	0	0	0
T8	46251	0	0	0
T10	10160	0	0	0
T11	236344	8	0	0
T12	49354	0	0	0
T15	0	2	0	0
T17	0	5185	0	0
T26	0	258	0	0
T27	0	519	0	0
T35	0	4649	0	0
T45	0	645	0	0
T46	0	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	455884	0	0
T2	633084	5997	0	0
T3	105558	0	0	0
T4	32885	0	0	0
T5	3046	0	0	0
T6	355322	1014	0	0
T7	1560	0	0	0
T8	46251	0	0	0
T10	10160	0	0	0
T11	236344	8	0	0
T12	49354	0	0	0
T15	0	2	0	0
T17	0	5185	0	0
T26	0	258	0	0
T27	0	519	0	0
T35	0	4649	0	0
T45	0	645	0	0
T46	0	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	99727586	0	0
T1	61049	60704	0	0
T2	633084	549232	0	0
T3	105558	105558	0	0
T4	32885	0	0	0
T5	3046	0	0	0
T6	355322	300214	0	0
T7	1560	0	0	0
T8	46251	45944	0	0
T10	10160	10160	0	0
T11	236344	125007	0	0
T12	0	49354	0	0
T14	0	25482	0	0
T15	0	136491	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	99727586	0	0
T1	61049	60704	0	0
T2	633084	549232	0	0
T3	105558	105558	0	0
T4	32885	0	0	0
T5	3046	0	0	0
T6	355322	300214	0	0
T7	1560	0	0	0
T8	46251	45944	0	0
T10	10160	10160	0	0
T11	236344	125007	0	0
T12	0	49354	0	0
T14	0	25482	0	0
T15	0	136491	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	455884	0	0
T2	633084	5997	0	0
T3	105558	0	0	0
T4	32885	0	0	0
T5	3046	0	0	0
T6	355322	1014	0	0
T7	1560	0	0	0
T8	46251	0	0	0
T10	10160	0	0	0
T11	236344	8	0	0
T12	49354	0	0	0
T15	0	2	0	0
T17	0	5185	0	0
T26	0	258	0	0
T27	0	519	0	0
T35	0	4649	0	0
T45	0	645	0	0
T46	0	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	455884	0	0
T2	633084	5997	0	0
T3	105558	0	0	0
T4	32885	0	0	0
T5	3046	0	0	0
T6	355322	1014	0	0
T7	1560	0	0	0
T8	46251	0	0	0
T10	10160	0	0	0
T11	236344	8	0	0
T12	49354	0	0	0
T15	0	2	0	0
T17	0	5185	0	0
T26	0	258	0	0
T27	0	519	0	0
T35	0	4649	0	0
T45	0	645	0	0
T46	0	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	455884	0	0
T2	633084	5997	0	0
T3	105558	0	0	0
T4	32885	0	0	0
T5	3046	0	0	0
T6	355322	1014	0	0
T7	1560	0	0	0
T8	46251	0	0	0
T10	10160	0	0	0
T11	236344	8	0	0
T12	49354	0	0	0
T15	0	2	0	0
T17	0	5185	0	0
T26	0	258	0	0
T27	0	519	0	0
T35	0	4649	0	0
T45	0	645	0	0
T46	0	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	455884	0	0
T2	633084	5997	0	0
T3	105558	0	0	0
T4	32885	0	0	0
T5	3046	0	0	0
T6	355322	1014	0	0
T7	1560	0	0	0
T8	46251	0	0	0
T10	10160	0	0	0
T11	236344	8	0	0
T12	49354	0	0	0
T15	0	2	0	0
T17	0	5185	0	0
T26	0	258	0	0
T27	0	519	0	0
T35	0	4649	0	0
T45	0	645	0	0
T46	0	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	99727586	0	0
T1	61049	60704	0	0
T2	633084	549232	0	0
T3	105558	105558	0	0
T4	32885	0	0	0
T5	3046	0	0	0
T6	355322	300214	0	0
T7	1560	0	0	0
T8	46251	45944	0	0
T10	10160	10160	0	0
T11	236344	125007	0	0
T12	0	49354	0	0
T14	0	25482	0	0
T15	0	136491	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126487691	455884	0	0
T2	633084	5997	0	0
T3	105558	0	0	0
T4	32885	0	0	0
T5	3046	0	0	0
T6	355322	1014	0	0
T7	1560	0	0	0
T8	46251	0	0	0
T10	10160	0	0	0
T11	236344	8	0	0
T12	49354	0	0	0
T15	0	2	0	0
T17	0	5185	0	0
T26	0	258	0	0
T27	0	519	0	0
T35	0	4649	0	0
T45	0	645	0	0
T46	0	7	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394232911	394151699	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	394232911	1973590	0	0
GntImpliesValid_A	394232911	1973590	0	0
GrantKnown_A	394232911	394151699	0	0
IdxKnown_A	394232911	394151699	0	0
IndexIsCorrect_A	394232911	1973590	0	0
LockArbDecision_A	394232911	0	0	0
NoReadyValidNoGrant_A	394232911	0	0	0
ReadyAndValidImplyGrant_A	394232911	1973590	0	0
ReqAndReadyImplyGrant_A	394232911	1973590	0	0
ReqImpliesValid_A	394232911	1973590	0	0
ReqStaysHighUntilGranted0_M	394232911	0	0	0
RoundRobin_A	394232911	4	0	906
ValidKnown_A	394232911	394151699	0	0
gen_data_port_assertion.DataFlow_A	394232911	1973590	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394232911	394151699	0	0
T1	66924	66833	0	0
T2	256924	256918	0	0
T3	531214	531162	0	0
T4	111515	111438	0	0
T5	7648	7573	0	0
T6	387510	387446	0	0
T7	2939	2859	0	0
T8	233211	233149	0	0
T9	1127	1046	0	0
T10	83998	83918	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394232911	1973590	0	0
T1	66924	832	0	0
T2	256924	9116	0	0
T3	531214	832	0	0
T4	111515	0	0	0
T5	7648	72	0	0
T6	387510	8225	0	0
T7	2939	32	0	0
T8	233211	832	0	0
T9	1127	0	0	0
T10	83998	832	0	0
T11	0	6602	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394232911	1973590	0	0
T1	66924	832	0	0
T2	256924	9116	0	0
T3	531214	832	0	0
T4	111515	0	0	0
T5	7648	72	0	0
T6	387510	8225	0	0
T7	2939	32	0	0
T8	233211	832	0	0
T9	1127	0	0	0
T10	83998	832	0	0
T11	0	6602	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394232911	394151699	0	0
T1	66924	66833	0	0
T2	256924	256918	0	0
T3	531214	531162	0	0
T4	111515	111438	0	0
T5	7648	7573	0	0
T6	387510	387446	0	0
T7	2939	2859	0	0
T8	233211	233149	0	0
T9	1127	1046	0	0
T10	83998	83918	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394232911	394151699	0	0
T1	66924	66833	0	0
T2	256924	256918	0	0
T3	531214	531162	0	0
T4	111515	111438	0	0
T5	7648	7573	0	0
T6	387510	387446	0	0
T7	2939	2859	0	0
T8	233211	233149	0	0
T9	1127	1046	0	0
T10	83998	83918	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394232911	1973590	0	0
T1	66924	832	0	0
T2	256924	9116	0	0
T3	531214	832	0	0
T4	111515	0	0	0
T5	7648	72	0	0
T6	387510	8225	0	0
T7	2939	32	0	0
T8	233211	832	0	0
T9	1127	0	0	0
T10	83998	832	0	0
T11	0	6602	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394232911	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394232911	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394232911	1973590	0	0
T1	66924	832	0	0
T2	256924	9116	0	0
T3	531214	832	0	0
T4	111515	0	0	0
T5	7648	72	0	0
T6	387510	8225	0	0
T7	2939	32	0	0
T8	233211	832	0	0
T9	1127	0	0	0
T10	83998	832	0	0
T11	0	6602	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394232911	1973590	0	0
T1	66924	832	0	0
T2	256924	9116	0	0
T3	531214	832	0	0
T4	111515	0	0	0
T5	7648	72	0	0
T6	387510	8225	0	0
T7	2939	32	0	0
T8	233211	832	0	0
T9	1127	0	0	0
T10	83998	832	0	0
T11	0	6602	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394232911	1973590	0	0
T1	66924	832	0	0
T2	256924	9116	0	0
T3	531214	832	0	0
T4	111515	0	0	0
T5	7648	72	0	0
T6	387510	8225	0	0
T7	2939	32	0	0
T8	233211	832	0	0
T9	1127	0	0	0
T10	83998	832	0	0
T11	0	6602	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394232911	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394232911	4	0	906
T47	133441	1	0	1
T48	0	2	0	0
T49	0	1	0	0
T50	163051	0	0	1
T51	363373	0	0	1
T52	600362	0	0	1
T53	427087	0	0	1
T54	308792	0	0	1
T55	509141	0	0	1
T56	325562	0	0	1
T57	129998	0	0	1
T58	658123	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394232911	394151699	0	0
T1	66924	66833	0	0
T2	256924	256918	0	0
T3	531214	531162	0	0
T4	111515	111438	0	0
T5	7648	7573	0	0
T6	387510	387446	0	0
T7	2939	2859	0	0
T8	233211	233149	0	0
T9	1127	1046	0	0
T10	83998	83918	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394232911	1973590	0	0
T1	66924	832	0	0
T2	256924	9116	0	0
T3	531214	832	0	0
T4	111515	0	0	0
T5	7648	72	0	0
T6	387510	8225	0	0
T7	2939	32	0	0
T8	233211	832	0	0
T9	1127	0	0	0
T10	83998	832	0	0
T11	0	6602	0	0
T12	0	832	0	0