Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3249340	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3650536

1

T1

931

T2

963

T3

51245

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3889669	1			T1	1		T2	179		T3	83828
values[0x0]	1503999	1			T1	550		T2	461		T3	26495
values[0x1]	1506208	1			T1	587		T2	429		T3	26715

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2308290	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4591586

1

T1

990

T2

982

T3

78648

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23416	1			T1	9		T2	1		T3	575
valid_sources[0x01]	26678	1			T1	4		T3	580		T5	58
valid_sources[0x02]	28412	1			T1	3		T2	8		T3	530
valid_sources[0x03]	24851	1			T1	5		T2	13		T3	647
valid_sources[0x04]	27784	1			T1	3		T2	5		T3	474
valid_sources[0x05]	26872	1			T1	6		T2	16		T3	528
valid_sources[0x06]	25157	1			T1	4		T2	8		T3	570
valid_sources[0x07]	33118	1			T1	3		T2	3		T3	530
valid_sources[0x08]	25293	1			T2	4		T3	594		T5	35
valid_sources[0x09]	25615	1			T1	6		T2	14		T3	498
valid_sources[0x0a]	29863	1			T1	5		T2	4		T3	480
valid_sources[0x0b]	25780	1			T1	2		T2	2		T3	612
valid_sources[0x0c]	35398	1			T1	7		T2	13		T3	523
valid_sources[0x0d]	24310	1			T1	4		T2	9		T3	534
valid_sources[0x0e]	27345	1			T1	8		T3	568		T5	42
valid_sources[0x0f]	25866	1			T1	3		T2	10		T3	548
valid_sources[0x10]	26792	1			T1	1		T2	11		T3	503
valid_sources[0x11]	26265	1			T1	3		T2	1		T3	557
valid_sources[0x12]	24810	1			T1	10		T2	1		T3	516
valid_sources[0x13]	25573	1			T1	9		T2	2		T3	559
valid_sources[0x14]	41044	1			T1	4		T3	541		T4	504
valid_sources[0x15]	25848	1			T1	7		T3	513		T5	45
valid_sources[0x16]	25500	1			T1	2		T2	5		T3	552
valid_sources[0x17]	27617	1			T1	5		T3	524		T5	71
valid_sources[0x18]	33442	1			T1	6		T2	13		T3	491
valid_sources[0x19]	27618	1			T1	1		T3	564		T5	67
valid_sources[0x1a]	25328	1			T1	3		T2	6		T3	550
valid_sources[0x1b]	27269	1			T1	5		T2	5		T3	571
valid_sources[0x1c]	25193	1			T1	2		T2	5		T3	509
valid_sources[0x1d]	25665	1			T1	4		T2	3		T3	533
valid_sources[0x1e]	23237	1			T1	6		T2	2		T3	553
valid_sources[0x1f]	25927	1			T1	1		T3	493		T5	30
valid_sources[0x20]	25835	1			T1	3		T2	4		T3	536
valid_sources[0x21]	28420	1			T1	2		T2	1		T3	507
valid_sources[0x22]	24418	1			T1	5		T2	1		T3	508
valid_sources[0x23]	26116	1			T1	2		T2	6		T3	597
valid_sources[0x24]	24650	1			T1	6		T2	3		T3	467
valid_sources[0x25]	26466	1			T1	13		T3	567		T5	46
valid_sources[0x26]	26473	1			T1	5		T2	3		T3	535
valid_sources[0x27]	28018	1			T1	2		T3	543		T5	41
valid_sources[0x28]	32786	1			T1	3		T2	1		T3	600
valid_sources[0x29]	26379	1			T1	5		T2	1		T3	482
valid_sources[0x2a]	27715	1			T3	543		T5	49		T8	5
valid_sources[0x2b]	29419	1			T1	2		T3	519		T5	51
valid_sources[0x2c]	30534	1			T1	4		T2	7		T3	523
valid_sources[0x2d]	26025	1			T1	2		T2	1		T3	527
valid_sources[0x2e]	26586	1			T1	5		T2	3		T3	535
valid_sources[0x2f]	24372	1			T1	5		T2	3		T3	570
valid_sources[0x30]	23307	1			T1	3		T3	565		T5	50
valid_sources[0x31]	27477	1			T1	2		T2	2		T3	520
valid_sources[0x32]	27656	1			T1	1		T2	5		T3	542
valid_sources[0x33]	28607	1			T1	5		T2	3		T3	508
valid_sources[0x34]	24149	1			T1	4		T3	464		T5	44
valid_sources[0x35]	29178	1			T1	7		T2	14		T3	566
valid_sources[0x36]	26472	1			T1	2		T3	605		T5	49
valid_sources[0x37]	26920	1			T1	7		T2	1		T3	535
valid_sources[0x38]	27473	1			T1	7		T3	595		T5	45
valid_sources[0x39]	24093	1			T1	5		T2	2		T3	499
valid_sources[0x3a]	25605	1			T1	1		T2	2		T3	486
valid_sources[0x3b]	26561	1			T1	5		T2	8		T3	472
valid_sources[0x3c]	24615	1			T1	1		T2	7		T3	500
valid_sources[0x3d]	27484	1			T1	1		T2	2		T3	492
valid_sources[0x3e]	26393	1			T1	1		T2	1		T3	546
valid_sources[0x3f]	24892	1			T1	8		T2	5		T3	491
valid_sources[0x40]	28514	1			T1	3		T3	487		T5	48
valid_sources[0x41]	24075	1			T1	6		T2	3		T3	504
valid_sources[0x42]	26220	1			T1	4		T2	3		T3	557
valid_sources[0x43]	25145	1			T1	1		T2	10		T3	566
valid_sources[0x44]	37648	1			T1	14		T2	4		T3	536
valid_sources[0x45]	24780	1			T1	4		T2	6		T3	606
valid_sources[0x46]	26377	1			T1	2		T2	1		T3	575
valid_sources[0x47]	36292	1			T1	1		T2	6		T3	513
valid_sources[0x48]	23498	1			T1	3		T3	565		T5	45
valid_sources[0x49]	24056	1			T1	1		T3	519		T5	45
valid_sources[0x4a]	25291	1			T1	11		T3	455		T5	38
valid_sources[0x4b]	24632	1			T1	4		T3	533		T5	32
valid_sources[0x4c]	25210	1			T1	2		T2	4		T3	481
valid_sources[0x4d]	25571	1			T1	3		T2	7		T3	511
valid_sources[0x4e]	25691	1			T2	1		T3	434		T5	52
valid_sources[0x4f]	24822	1			T1	7		T2	7		T3	527
valid_sources[0x50]	27572	1			T1	3		T2	14		T3	490
valid_sources[0x51]	26645	1			T1	4		T3	549		T5	38
valid_sources[0x52]	27113	1			T1	3		T2	2		T3	512
valid_sources[0x53]	26622	1			T1	3		T2	8		T3	571
valid_sources[0x54]	23994	1			T1	5		T2	1		T3	518
valid_sources[0x55]	26547	1			T1	5		T2	1		T3	531
valid_sources[0x56]	25733	1			T1	2		T2	8		T3	597
valid_sources[0x57]	24133	1			T1	10		T2	1		T3	517
valid_sources[0x58]	24197	1			T1	2		T3	556		T5	58
valid_sources[0x59]	28873	1			T1	3		T2	3		T3	566
valid_sources[0x5a]	29054	1			T1	6		T3	540		T5	47
valid_sources[0x5b]	25311	1			T1	12		T2	13		T3	553
valid_sources[0x5c]	25827	1			T2	18		T3	570		T5	55
valid_sources[0x5d]	25696	1			T1	5		T2	8		T3	525
valid_sources[0x5e]	31739	1			T1	3		T2	2		T3	588
valid_sources[0x5f]	26868	1			T1	7		T2	5		T3	524
valid_sources[0x60]	25875	1			T1	6		T3	612		T5	52
valid_sources[0x61]	25453	1			T1	8		T2	2		T3	519
valid_sources[0x62]	27018	1			T1	14		T2	4		T3	566
valid_sources[0x63]	26687	1			T1	4		T2	7		T3	556
valid_sources[0x64]	25599	1			T1	4		T2	2		T3	518
valid_sources[0x65]	24943	1			T1	2		T2	2		T3	552
valid_sources[0x66]	25113	1			T1	5		T2	3		T3	550
valid_sources[0x67]	27624	1			T1	5		T3	483		T5	37
valid_sources[0x68]	27141	1			T1	2		T3	572		T5	41
valid_sources[0x69]	31934	1			T1	8		T2	16		T3	512
valid_sources[0x6a]	25319	1			T1	5		T2	2		T3	525
valid_sources[0x6b]	25430	1			T1	11		T2	12		T3	496
valid_sources[0x6c]	25064	1			T1	5		T2	5		T3	551
valid_sources[0x6d]	26548	1			T1	9		T2	10		T3	628
valid_sources[0x6e]	29599	1			T1	9		T3	573		T5	55
valid_sources[0x6f]	32047	1			T1	6		T3	524		T5	46
valid_sources[0x70]	28594	1			T1	4		T3	522		T5	37
valid_sources[0x71]	26233	1			T1	11		T2	9		T3	473
valid_sources[0x72]	26004	1			T1	2		T2	1		T3	558
valid_sources[0x73]	23767	1			T1	2		T2	6		T3	555
valid_sources[0x74]	26847	1			T1	2		T2	5		T3	579
valid_sources[0x75]	27221	1			T2	6		T3	539		T5	54
valid_sources[0x76]	32229	1			T1	2		T3	577		T5	54
valid_sources[0x77]	26659	1			T1	8		T2	16		T3	502
valid_sources[0x78]	26600	1			T1	7		T3	558		T5	35
valid_sources[0x79]	27814	1			T1	4		T2	6		T3	492
valid_sources[0x7a]	23970	1			T1	7		T2	4		T3	547
valid_sources[0x7b]	24961	1			T1	4		T3	522		T5	48
valid_sources[0x7c]	25913	1			T1	1		T2	6		T3	531
valid_sources[0x7d]	28471	1			T1	3		T3	541		T5	43
valid_sources[0x7e]	25506	1			T1	10		T2	8		T3	489
valid_sources[0x7f]	25244	1			T1	8		T2	5		T3	522
valid_sources[0x80]	24396	1			T3	524		T5	60		T8	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

943296

1

T1

1

T2

82

T3

6221

values[0x0]

all_enables

biggest_size

1364294

1

T1

448

T2

457

T3

22585

values[0x1]

all_enables

biggest_size

1342946

1

T1

482

T2

424

T3

22439