Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3271768

1

T1

207

T2

106

T3

85793

full_word

3651764

1

T1

931

T2

963

T3

51245

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6923082	1			T1	1138		T2	1069		T3	137038
auto[TlIntgErrCmd]	150	1			T99	2		T101	7		T102	5
auto[TlIntgErrData]	153	1			T99	7		T101	12		T102	4
auto[TlIntgErrBoth]	147	1			T99	1		T101	11		T102	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3893484

1

T1

1

T2

179

T3

83828

auto[1]

3030048

1

T1

1137

T2

890

T3

53210

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2949680	1			T2	97		T3	77607		T5	3115
auto[TlIntgErrNone]	partial	auto[1]	321677	1			T1	207		T2	9		T3	8186
auto[TlIntgErrNone]	full_word	auto[0]	943594	1			T1	1		T2	82		T3	6221
auto[TlIntgErrNone]	full_word	auto[1]	2708131	1			T1	930		T2	881		T3	45024
auto[TlIntgErrCmd]	partial	auto[0]	67	1			T99	1		T101	5		T102	3
auto[TlIntgErrCmd]	partial	auto[1]	71	1			T99	1		T101	2		T102	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T242	1		T245	1		T246	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T241	1		T146	1		T147	2
auto[TlIntgErrData]	partial	auto[0]	81	1			T99	6		T101	4		T102	3
auto[TlIntgErrData]	partial	auto[1]	59	1			T99	1		T101	7		T102	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T241	1		T244	1		T245	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T101	1		T146	1		T247	3
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T101	5		T241	2		T244	5
auto[TlIntgErrBoth]	partial	auto[1]	86	1			T99	1		T101	6		T241	6
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T241	1		T147	1		T245	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T102	1		T241	1		T146	1