Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	464364087	2565545	0	0
gen_wmask[1].MaskCheckPortA_A	464364087	2565545	0	0
gen_wmask[2].MaskCheckPortA_A	464364087	2565545	0	0
gen_wmask[3].MaskCheckPortA_A	464364087	2565545	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464364087	2565545	0	0
T2	32782	832	0	0
T3	794624	20269	0	0
T4	166082	0	0	0
T5	1264723	10319	0	0
T6	758397	0	0	0
T7	1210	0	0	0
T8	278156	832	0	0
T9	1101593	17446	0	0
T10	387605	0	0	0
T11	77121	0	0	0
T12	2889	832	0	0
T13	23053	832	0	0
T14	0	1344	0	0
T15	0	21009	0	0
T16	0	12615	0	0
T28	0	4	0	0
T43	0	3640	0	0
T45	0	4343	0	0
T46	0	141	0	0
T47	0	111	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464364087	2565545	0	0
T2	32782	832	0	0
T3	794624	20269	0	0
T4	166082	0	0	0
T5	1264723	10319	0	0
T6	758397	0	0	0
T7	1210	0	0	0
T8	278156	832	0	0
T9	1101593	17446	0	0
T10	387605	0	0	0
T11	77121	0	0	0
T12	2889	832	0	0
T13	23053	832	0	0
T14	0	1344	0	0
T15	0	21009	0	0
T16	0	12615	0	0
T28	0	4	0	0
T43	0	3640	0	0
T45	0	4343	0	0
T46	0	141	0	0
T47	0	111	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464364087	2565545	0	0
T2	32782	832	0	0
T3	794624	20269	0	0
T4	166082	0	0	0
T5	1264723	10319	0	0
T6	758397	0	0	0
T7	1210	0	0	0
T8	278156	832	0	0
T9	1101593	17446	0	0
T10	387605	0	0	0
T11	77121	0	0	0
T12	2889	832	0	0
T13	23053	832	0	0
T14	0	1344	0	0
T15	0	21009	0	0
T16	0	12615	0	0
T28	0	4	0	0
T43	0	3640	0	0
T45	0	4343	0	0
T46	0	141	0	0
T47	0	111	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464364087	2565545	0	0
T2	32782	832	0	0
T3	794624	20269	0	0
T4	166082	0	0	0
T5	1264723	10319	0	0
T6	758397	0	0	0
T7	1210	0	0	0
T8	278156	832	0	0
T9	1101593	17446	0	0
T10	387605	0	0	0
T11	77121	0	0	0
T12	2889	832	0	0
T13	23053	832	0	0
T14	0	1344	0	0
T15	0	21009	0	0
T16	0	12615	0	0
T28	0	4	0	0
T43	0	3640	0	0
T45	0	4343	0	0
T46	0	141	0	0
T47	0	111	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	344691966	1694471	0	0
gen_wmask[1].MaskCheckPortA_A	344691966	1694471	0	0
gen_wmask[2].MaskCheckPortA_A	344691966	1694471	0	0
gen_wmask[3].MaskCheckPortA_A	344691966	1694471	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344691966	1694471	0	0
T2	32782	832	0	0
T3	681772	11960	0	0
T4	88890	0	0	0
T5	663875	5964	0	0
T6	671226	0	0	0
T7	1210	0	0	0
T8	209733	832	0	0
T9	318808	9826	0	0
T10	273577	0	0	0
T11	24889	0	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	1344	0	0
T15	0	9152	0	0
T16	0	9152	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344691966	1694471	0	0
T2	32782	832	0	0
T3	681772	11960	0	0
T4	88890	0	0	0
T5	663875	5964	0	0
T6	671226	0	0	0
T7	1210	0	0	0
T8	209733	832	0	0
T9	318808	9826	0	0
T10	273577	0	0	0
T11	24889	0	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	1344	0	0
T15	0	9152	0	0
T16	0	9152	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344691966	1694471	0	0
T2	32782	832	0	0
T3	681772	11960	0	0
T4	88890	0	0	0
T5	663875	5964	0	0
T6	671226	0	0	0
T7	1210	0	0	0
T8	209733	832	0	0
T9	318808	9826	0	0
T10	273577	0	0	0
T11	24889	0	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	1344	0	0
T15	0	9152	0	0
T16	0	9152	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344691966	1694471	0	0
T2	32782	832	0	0
T3	681772	11960	0	0
T4	88890	0	0	0
T5	663875	5964	0	0
T6	671226	0	0	0
T7	1210	0	0	0
T8	209733	832	0	0
T9	318808	9826	0	0
T10	273577	0	0	0
T11	24889	0	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	1344	0	0
T15	0	9152	0	0
T16	0	9152	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	119672121	871074	0	0
gen_wmask[1].MaskCheckPortA_A	119672121	871074	0	0
gen_wmask[2].MaskCheckPortA_A	119672121	871074	0	0
gen_wmask[3].MaskCheckPortA_A	119672121	871074	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	871074	0	0
T3	112852	8309	0	0
T4	77192	0	0	0
T5	600848	4355	0	0
T6	87171	0	0	0
T8	68423	0	0	0
T9	782785	7620	0	0
T10	114028	0	0	0
T11	52232	0	0	0
T12	2889	0	0	0
T13	23053	0	0	0
T15	0	11857	0	0
T16	0	3463	0	0
T28	0	4	0	0
T43	0	3640	0	0
T45	0	4343	0	0
T46	0	141	0	0
T47	0	111	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	871074	0	0
T3	112852	8309	0	0
T4	77192	0	0	0
T5	600848	4355	0	0
T6	87171	0	0	0
T8	68423	0	0	0
T9	782785	7620	0	0
T10	114028	0	0	0
T11	52232	0	0	0
T12	2889	0	0	0
T13	23053	0	0	0
T15	0	11857	0	0
T16	0	3463	0	0
T28	0	4	0	0
T43	0	3640	0	0
T45	0	4343	0	0
T46	0	141	0	0
T47	0	111	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	871074	0	0
T3	112852	8309	0	0
T4	77192	0	0	0
T5	600848	4355	0	0
T6	87171	0	0	0
T8	68423	0	0	0
T9	782785	7620	0	0
T10	114028	0	0	0
T11	52232	0	0	0
T12	2889	0	0	0
T13	23053	0	0	0
T15	0	11857	0	0
T16	0	3463	0	0
T28	0	4	0	0
T43	0	3640	0	0
T45	0	4343	0	0
T46	0	141	0	0
T47	0	111	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	871074	0	0
T3	112852	8309	0	0
T4	77192	0	0	0
T5	600848	4355	0	0
T6	87171	0	0	0
T8	68423	0	0	0
T9	782785	7620	0	0
T10	114028	0	0	0
T11	52232	0	0	0
T12	2889	0	0	0
T13	23053	0	0	0
T15	0	11857	0	0
T16	0	3463	0	0
T28	0	4	0	0
T43	0	3640	0	0
T45	0	4343	0	0
T46	0	141	0	0
T47	0	111	0	0