Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T9
1	0	Covered	T3,T5,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T3,T5,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T9
1	0	Covered	T3,T5,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Unreachable
1	1	Covered	T3,T5,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T9
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	584036208	463094409	0	0
CheckNGreaterZero_A	2718	2718	0	0
GntImpliesReady_A	584036208	2897024	0	0
GntImpliesValid_A	584036208	2897024	0	0
GrantKnown_A	584036208	463094409	0	0
IdxKnown_A	584036208	463094409	0	0
IndexIsCorrect_A	584036208	2897024	0	0
LockArbDecision_A	584036208	0	0	0
NoReadyValidNoGrant_A	584036208	0	0	0
ReadyAndValidImplyGrant_A	584036208	2897024	0	0
ReqAndReadyImplyGrant_A	584036208	2897024	0	0
ReqImpliesValid_A	584036208	2897024	0	0
ReqStaysHighUntilGranted0_M	584036208	0	0	0
RoundRobin_A	584036208	2	0	906
ValidKnown_A	584036208	463094409	0	0
gen_data_port_assertion.DataFlow_A	584036208	2897024	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584036208	463094409	0	0
T1	712936	708203	0	0
T2	76636	54609	0	0
T3	907476	898973	0	0
T4	243274	161253	0	0
T5	1865571	1262295	0	0
T6	845568	752319	0	0
T7	1210	1153	0	0
T8	346579	277858	0	0
T9	1884378	1095869	0	0
T10	501633	381555	0	0
T11	104464	50048	0	0
T12	2889	2296	0	0
T13	0	22610	0	0
T14	0	114675	0	0
T15	0	901955	0	0
T16	0	771073	0	0
T27	0	60592	0	0
T28	0	496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2718	2718	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584036208	2897024	0	0
T2	32782	832	0	0
T3	907476	22897	0	0
T4	243274	0	0	0
T5	1865571	10861	0	0
T6	845568	0	0	0
T7	1210	0	0	0
T8	346579	832	0	0
T9	1884378	18706	0	0
T10	501633	0	0	0
T11	129353	0	0	0
T12	5778	832	0	0
T13	46106	832	0	0
T14	0	1344	0	0
T15	0	21420	0	0
T16	0	12760	0	0
T28	0	8	0	0
T39	0	5213	0	0
T43	0	5609	0	0
T44	0	1296	0	0
T45	0	5137	0	0
T46	0	170	0	0
T47	0	173	0	0
T49	0	4117	0	0
T50	0	205	0	0
T51	0	121	0	0
T52	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584036208	2897024	0	0
T2	32782	832	0	0
T3	907476	22897	0	0
T4	243274	0	0	0
T5	1865571	10861	0	0
T6	845568	0	0	0
T7	1210	0	0	0
T8	346579	832	0	0
T9	1884378	18706	0	0
T10	501633	0	0	0
T11	129353	0	0	0
T12	5778	832	0	0
T13	46106	832	0	0
T14	0	1344	0	0
T15	0	21420	0	0
T16	0	12760	0	0
T28	0	8	0	0
T39	0	5213	0	0
T43	0	5609	0	0
T44	0	1296	0	0
T45	0	5137	0	0
T46	0	170	0	0
T47	0	173	0	0
T49	0	4117	0	0
T50	0	205	0	0
T51	0	121	0	0
T52	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584036208	463094409	0	0
T1	712936	708203	0	0
T2	76636	54609	0	0
T3	907476	898973	0	0
T4	243274	161253	0	0
T5	1865571	1262295	0	0
T6	845568	752319	0	0
T7	1210	1153	0	0
T8	346579	277858	0	0
T9	1884378	1095869	0	0
T10	501633	381555	0	0
T11	104464	50048	0	0
T12	2889	2296	0	0
T13	0	22610	0	0
T14	0	114675	0	0
T15	0	901955	0	0
T16	0	771073	0	0
T27	0	60592	0	0
T28	0	496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584036208	463094409	0	0
T1	712936	708203	0	0
T2	76636	54609	0	0
T3	907476	898973	0	0
T4	243274	161253	0	0
T5	1865571	1262295	0	0
T6	845568	752319	0	0
T7	1210	1153	0	0
T8	346579	277858	0	0
T9	1884378	1095869	0	0
T10	501633	381555	0	0
T11	104464	50048	0	0
T12	2889	2296	0	0
T13	0	22610	0	0
T14	0	114675	0	0
T15	0	901955	0	0
T16	0	771073	0	0
T27	0	60592	0	0
T28	0	496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584036208	2897024	0	0
T2	32782	832	0	0
T3	907476	22897	0	0
T4	243274	0	0	0
T5	1865571	10861	0	0
T6	845568	0	0	0
T7	1210	0	0	0
T8	346579	832	0	0
T9	1884378	18706	0	0
T10	501633	0	0	0
T11	129353	0	0	0
T12	5778	832	0	0
T13	46106	832	0	0
T14	0	1344	0	0
T15	0	21420	0	0
T16	0	12760	0	0
T28	0	8	0	0
T39	0	5213	0	0
T43	0	5609	0	0
T44	0	1296	0	0
T45	0	5137	0	0
T46	0	170	0	0
T47	0	173	0	0
T49	0	4117	0	0
T50	0	205	0	0
T51	0	121	0	0
T52	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584036208	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584036208	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584036208	2897024	0	0
T2	32782	832	0	0
T3	907476	22897	0	0
T4	243274	0	0	0
T5	1865571	10861	0	0
T6	845568	0	0	0
T7	1210	0	0	0
T8	346579	832	0	0
T9	1884378	18706	0	0
T10	501633	0	0	0
T11	129353	0	0	0
T12	5778	832	0	0
T13	46106	832	0	0
T14	0	1344	0	0
T15	0	21420	0	0
T16	0	12760	0	0
T28	0	8	0	0
T39	0	5213	0	0
T43	0	5609	0	0
T44	0	1296	0	0
T45	0	5137	0	0
T46	0	170	0	0
T47	0	173	0	0
T49	0	4117	0	0
T50	0	205	0	0
T51	0	121	0	0
T52	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584036208	2897024	0	0
T2	32782	832	0	0
T3	907476	22897	0	0
T4	243274	0	0	0
T5	1865571	10861	0	0
T6	845568	0	0	0
T7	1210	0	0	0
T8	346579	832	0	0
T9	1884378	18706	0	0
T10	501633	0	0	0
T11	129353	0	0	0
T12	5778	832	0	0
T13	46106	832	0	0
T14	0	1344	0	0
T15	0	21420	0	0
T16	0	12760	0	0
T28	0	8	0	0
T39	0	5213	0	0
T43	0	5609	0	0
T44	0	1296	0	0
T45	0	5137	0	0
T46	0	170	0	0
T47	0	173	0	0
T49	0	4117	0	0
T50	0	205	0	0
T51	0	121	0	0
T52	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584036208	2897024	0	0
T2	32782	832	0	0
T3	907476	22897	0	0
T4	243274	0	0	0
T5	1865571	10861	0	0
T6	845568	0	0	0
T7	1210	0	0	0
T8	346579	832	0	0
T9	1884378	18706	0	0
T10	501633	0	0	0
T11	129353	0	0	0
T12	5778	832	0	0
T13	46106	832	0	0
T14	0	1344	0	0
T15	0	21420	0	0
T16	0	12760	0	0
T28	0	8	0	0
T39	0	5213	0	0
T43	0	5609	0	0
T44	0	1296	0	0
T45	0	5137	0	0
T46	0	170	0	0
T47	0	173	0	0
T49	0	4117	0	0
T50	0	205	0	0
T51	0	121	0	0
T52	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	584036208	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584036208	2	0	906
T30	648511	0	0	1
T40	175952	1	0	1
T53	0	1	0	0
T54	24128	0	0	1
T55	1135	0	0	1
T56	143126	0	0	1
T57	4457	0	0	1
T58	56466	0	0	1
T59	213213	0	0	1
T60	129319	0	0	1
T61	15187	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584036208	463094409	0	0
T1	712936	708203	0	0
T2	76636	54609	0	0
T3	907476	898973	0	0
T4	243274	161253	0	0
T5	1865571	1262295	0	0
T6	845568	752319	0	0
T7	1210	1153	0	0
T8	346579	277858	0	0
T9	1884378	1095869	0	0
T10	501633	381555	0	0
T11	104464	50048	0	0
T12	2889	2296	0	0
T13	0	22610	0	0
T14	0	114675	0	0
T15	0	901955	0	0
T16	0	771073	0	0
T27	0	60592	0	0
T28	0	496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584036208	2897024	0	0
T2	32782	832	0	0
T3	907476	22897	0	0
T4	243274	0	0	0
T5	1865571	10861	0	0
T6	845568	0	0	0
T7	1210	0	0	0
T8	346579	832	0	0
T9	1884378	18706	0	0
T10	501633	0	0	0
T11	129353	0	0	0
T12	5778	832	0	0
T13	46106	832	0	0
T14	0	1344	0	0
T15	0	21420	0	0
T16	0	12760	0	0
T28	0	8	0	0
T39	0	5213	0	0
T43	0	5609	0	0
T44	0	1296	0	0
T45	0	5137	0	0
T46	0	170	0	0
T47	0	173	0	0
T49	0	4117	0	0
T50	0	205	0	0
T51	0	121	0	0
T52	0	8	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T9
1	0	Covered	T3,T5,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T3,T5,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T5,T9
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	119672121	26755336	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	119672121	588800	0	0
GntImpliesValid_A	119672121	588800	0	0
GrantKnown_A	119672121	26755336	0	0
IdxKnown_A	119672121	26755336	0	0
IndexIsCorrect_A	119672121	588800	0	0
LockArbDecision_A	119672121	0	0	0
NoReadyValidNoGrant_A	119672121	0	0	0
ReadyAndValidImplyGrant_A	119672121	588800	0	0
ReqAndReadyImplyGrant_A	119672121	588800	0	0
ReqImpliesValid_A	119672121	588800	0	0
ReqStaysHighUntilGranted0_M	119672121	0	0	0
RoundRobin_A	119672121	0	0	0
ValidKnown_A	119672121	26755336	0	0
gen_data_port_assertion.DataFlow_A	119672121	588800	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	26755336	0	0
T1	113286	108616	0	0
T2	21927	0	0	0
T3	112852	116952	0	0
T4	77192	72440	0	0
T5	600848	20280	0	0
T6	87171	81168	0	0
T8	68423	0	0	0
T9	782785	52464	0	0
T10	114028	108032	0	0
T11	52232	50048	0	0
T27	0	60592	0	0
T28	0	496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	588800	0	0
T3	112852	4980	0	0
T4	77192	0	0	0
T5	600848	474	0	0
T6	87171	0	0	0
T8	68423	0	0	0
T9	782785	1805	0	0
T10	114028	0	0	0
T11	52232	0	0	0
T12	2889	0	0	0
T13	23053	0	0	0
T28	0	8	0	0
T39	0	5213	0	0
T43	0	5609	0	0
T45	0	2877	0	0
T46	0	170	0	0
T47	0	173	0	0
T51	0	121	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	588800	0	0
T3	112852	4980	0	0
T4	77192	0	0	0
T5	600848	474	0	0
T6	87171	0	0	0
T8	68423	0	0	0
T9	782785	1805	0	0
T10	114028	0	0	0
T11	52232	0	0	0
T12	2889	0	0	0
T13	23053	0	0	0
T28	0	8	0	0
T39	0	5213	0	0
T43	0	5609	0	0
T45	0	2877	0	0
T46	0	170	0	0
T47	0	173	0	0
T51	0	121	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	26755336	0	0
T1	113286	108616	0	0
T2	21927	0	0	0
T3	112852	116952	0	0
T4	77192	72440	0	0
T5	600848	20280	0	0
T6	87171	81168	0	0
T8	68423	0	0	0
T9	782785	52464	0	0
T10	114028	108032	0	0
T11	52232	50048	0	0
T27	0	60592	0	0
T28	0	496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	26755336	0	0
T1	113286	108616	0	0
T2	21927	0	0	0
T3	112852	116952	0	0
T4	77192	72440	0	0
T5	600848	20280	0	0
T6	87171	81168	0	0
T8	68423	0	0	0
T9	782785	52464	0	0
T10	114028	108032	0	0
T11	52232	50048	0	0
T27	0	60592	0	0
T28	0	496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	588800	0	0
T3	112852	4980	0	0
T4	77192	0	0	0
T5	600848	474	0	0
T6	87171	0	0	0
T8	68423	0	0	0
T9	782785	1805	0	0
T10	114028	0	0	0
T11	52232	0	0	0
T12	2889	0	0	0
T13	23053	0	0	0
T28	0	8	0	0
T39	0	5213	0	0
T43	0	5609	0	0
T45	0	2877	0	0
T46	0	170	0	0
T47	0	173	0	0
T51	0	121	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	588800	0	0
T3	112852	4980	0	0
T4	77192	0	0	0
T5	600848	474	0	0
T6	87171	0	0	0
T8	68423	0	0	0
T9	782785	1805	0	0
T10	114028	0	0	0
T11	52232	0	0	0
T12	2889	0	0	0
T13	23053	0	0	0
T28	0	8	0	0
T39	0	5213	0	0
T43	0	5609	0	0
T45	0	2877	0	0
T46	0	170	0	0
T47	0	173	0	0
T51	0	121	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	588800	0	0
T3	112852	4980	0	0
T4	77192	0	0	0
T5	600848	474	0	0
T6	87171	0	0	0
T8	68423	0	0	0
T9	782785	1805	0	0
T10	114028	0	0	0
T11	52232	0	0	0
T12	2889	0	0	0
T13	23053	0	0	0
T28	0	8	0	0
T39	0	5213	0	0
T43	0	5609	0	0
T45	0	2877	0	0
T46	0	170	0	0
T47	0	173	0	0
T51	0	121	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	588800	0	0
T3	112852	4980	0	0
T4	77192	0	0	0
T5	600848	474	0	0
T6	87171	0	0	0
T8	68423	0	0	0
T9	782785	1805	0	0
T10	114028	0	0	0
T11	52232	0	0	0
T12	2889	0	0	0
T13	23053	0	0	0
T28	0	8	0	0
T39	0	5213	0	0
T43	0	5609	0	0
T45	0	2877	0	0
T46	0	170	0	0
T47	0	173	0	0
T51	0	121	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	26755336	0	0
T1	113286	108616	0	0
T2	21927	0	0	0
T3	112852	116952	0	0
T4	77192	72440	0	0
T5	600848	20280	0	0
T6	87171	81168	0	0
T8	68423	0	0	0
T9	782785	52464	0	0
T10	114028	108032	0	0
T11	52232	50048	0	0
T27	0	60592	0	0
T28	0	496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	588800	0	0
T3	112852	4980	0	0
T4	77192	0	0	0
T5	600848	474	0	0
T6	87171	0	0	0
T8	68423	0	0	0
T9	782785	1805	0	0
T10	114028	0	0	0
T11	52232	0	0	0
T12	2889	0	0	0
T13	23053	0	0	0
T28	0	8	0	0
T39	0	5213	0	0
T43	0	5609	0	0
T45	0	2877	0	0
T46	0	170	0	0
T47	0	173	0	0
T51	0	121	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T9
1	0	Covered	T3,T5,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Unreachable
1	1	Covered	T3,T5,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T5,T9
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	119672121	91732374	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	119672121	474203	0	0
GntImpliesValid_A	119672121	474203	0	0
GrantKnown_A	119672121	91732374	0	0
IdxKnown_A	119672121	91732374	0	0
IndexIsCorrect_A	119672121	474203	0	0
LockArbDecision_A	119672121	0	0	0
NoReadyValidNoGrant_A	119672121	0	0	0
ReadyAndValidImplyGrant_A	119672121	474203	0	0
ReqAndReadyImplyGrant_A	119672121	474203	0	0
ReqImpliesValid_A	119672121	474203	0	0
ReqStaysHighUntilGranted0_M	119672121	0	0	0
RoundRobin_A	119672121	0	0	0
ValidKnown_A	119672121	91732374	0	0
gen_data_port_assertion.DataFlow_A	119672121	474203	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	91732374	0	0
T2	21927	21927	0	0
T3	112852	100254	0	0
T4	77192	0	0	0
T5	600848	578237	0	0
T6	87171	0	0	0
T8	68423	68224	0	0
T9	782785	724607	0	0
T10	114028	0	0	0
T11	52232	0	0	0
T12	2889	2296	0	0
T13	0	22610	0	0
T14	0	114675	0	0
T15	0	901955	0	0
T16	0	771073	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	474203	0	0
T3	112852	4585	0	0
T4	77192	0	0	0
T5	600848	4030	0	0
T6	87171	0	0	0
T8	68423	0	0	0
T9	782785	6551	0	0
T10	114028	0	0	0
T11	52232	0	0	0
T12	2889	0	0	0
T13	23053	0	0	0
T15	0	11857	0	0
T16	0	3463	0	0
T44	0	1296	0	0
T45	0	2260	0	0
T49	0	4117	0	0
T50	0	205	0	0
T52	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	474203	0	0
T3	112852	4585	0	0
T4	77192	0	0	0
T5	600848	4030	0	0
T6	87171	0	0	0
T8	68423	0	0	0
T9	782785	6551	0	0
T10	114028	0	0	0
T11	52232	0	0	0
T12	2889	0	0	0
T13	23053	0	0	0
T15	0	11857	0	0
T16	0	3463	0	0
T44	0	1296	0	0
T45	0	2260	0	0
T49	0	4117	0	0
T50	0	205	0	0
T52	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	91732374	0	0
T2	21927	21927	0	0
T3	112852	100254	0	0
T4	77192	0	0	0
T5	600848	578237	0	0
T6	87171	0	0	0
T8	68423	68224	0	0
T9	782785	724607	0	0
T10	114028	0	0	0
T11	52232	0	0	0
T12	2889	2296	0	0
T13	0	22610	0	0
T14	0	114675	0	0
T15	0	901955	0	0
T16	0	771073	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	91732374	0	0
T2	21927	21927	0	0
T3	112852	100254	0	0
T4	77192	0	0	0
T5	600848	578237	0	0
T6	87171	0	0	0
T8	68423	68224	0	0
T9	782785	724607	0	0
T10	114028	0	0	0
T11	52232	0	0	0
T12	2889	2296	0	0
T13	0	22610	0	0
T14	0	114675	0	0
T15	0	901955	0	0
T16	0	771073	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	474203	0	0
T3	112852	4585	0	0
T4	77192	0	0	0
T5	600848	4030	0	0
T6	87171	0	0	0
T8	68423	0	0	0
T9	782785	6551	0	0
T10	114028	0	0	0
T11	52232	0	0	0
T12	2889	0	0	0
T13	23053	0	0	0
T15	0	11857	0	0
T16	0	3463	0	0
T44	0	1296	0	0
T45	0	2260	0	0
T49	0	4117	0	0
T50	0	205	0	0
T52	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	474203	0	0
T3	112852	4585	0	0
T4	77192	0	0	0
T5	600848	4030	0	0
T6	87171	0	0	0
T8	68423	0	0	0
T9	782785	6551	0	0
T10	114028	0	0	0
T11	52232	0	0	0
T12	2889	0	0	0
T13	23053	0	0	0
T15	0	11857	0	0
T16	0	3463	0	0
T44	0	1296	0	0
T45	0	2260	0	0
T49	0	4117	0	0
T50	0	205	0	0
T52	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	474203	0	0
T3	112852	4585	0	0
T4	77192	0	0	0
T5	600848	4030	0	0
T6	87171	0	0	0
T8	68423	0	0	0
T9	782785	6551	0	0
T10	114028	0	0	0
T11	52232	0	0	0
T12	2889	0	0	0
T13	23053	0	0	0
T15	0	11857	0	0
T16	0	3463	0	0
T44	0	1296	0	0
T45	0	2260	0	0
T49	0	4117	0	0
T50	0	205	0	0
T52	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	474203	0	0
T3	112852	4585	0	0
T4	77192	0	0	0
T5	600848	4030	0	0
T6	87171	0	0	0
T8	68423	0	0	0
T9	782785	6551	0	0
T10	114028	0	0	0
T11	52232	0	0	0
T12	2889	0	0	0
T13	23053	0	0	0
T15	0	11857	0	0
T16	0	3463	0	0
T44	0	1296	0	0
T45	0	2260	0	0
T49	0	4117	0	0
T50	0	205	0	0
T52	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	91732374	0	0
T2	21927	21927	0	0
T3	112852	100254	0	0
T4	77192	0	0	0
T5	600848	578237	0	0
T6	87171	0	0	0
T8	68423	68224	0	0
T9	782785	724607	0	0
T10	114028	0	0	0
T11	52232	0	0	0
T12	2889	2296	0	0
T13	0	22610	0	0
T14	0	114675	0	0
T15	0	901955	0	0
T16	0	771073	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119672121	474203	0	0
T3	112852	4585	0	0
T4	77192	0	0	0
T5	600848	4030	0	0
T6	87171	0	0	0
T8	68423	0	0	0
T9	782785	6551	0	0
T10	114028	0	0	0
T11	52232	0	0	0
T12	2889	0	0	0
T13	23053	0	0	0
T15	0	11857	0	0
T16	0	3463	0	0
T44	0	1296	0	0
T45	0	2260	0	0
T49	0	4117	0	0
T50	0	205	0	0
T52	0	8	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T9
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	344691966	344606699	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	344691966	1834021	0	0
GntImpliesValid_A	344691966	1834021	0	0
GrantKnown_A	344691966	344606699	0	0
IdxKnown_A	344691966	344606699	0	0
IndexIsCorrect_A	344691966	1834021	0	0
LockArbDecision_A	344691966	0	0	0
NoReadyValidNoGrant_A	344691966	0	0	0
ReadyAndValidImplyGrant_A	344691966	1834021	0	0
ReqAndReadyImplyGrant_A	344691966	1834021	0	0
ReqImpliesValid_A	344691966	1834021	0	0
ReqStaysHighUntilGranted0_M	344691966	0	0	0
RoundRobin_A	344691966	2	0	906
ValidKnown_A	344691966	344606699	0	0
gen_data_port_assertion.DataFlow_A	344691966	1834021	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344691966	344606699	0	0
T1	599650	599587	0	0
T2	32782	32682	0	0
T3	681772	681767	0	0
T4	88890	88813	0	0
T5	663875	663778	0	0
T6	671226	671151	0	0
T7	1210	1153	0	0
T8	209733	209634	0	0
T9	318808	318798	0	0
T10	273577	273523	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344691966	1834021	0	0
T2	32782	832	0	0
T3	681772	13332	0	0
T4	88890	0	0	0
T5	663875	6357	0	0
T6	671226	0	0	0
T7	1210	0	0	0
T8	209733	832	0	0
T9	318808	10350	0	0
T10	273577	0	0	0
T11	24889	0	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	1344	0	0
T15	0	9563	0	0
T16	0	9297	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344691966	1834021	0	0
T2	32782	832	0	0
T3	681772	13332	0	0
T4	88890	0	0	0
T5	663875	6357	0	0
T6	671226	0	0	0
T7	1210	0	0	0
T8	209733	832	0	0
T9	318808	10350	0	0
T10	273577	0	0	0
T11	24889	0	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	1344	0	0
T15	0	9563	0	0
T16	0	9297	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344691966	344606699	0	0
T1	599650	599587	0	0
T2	32782	32682	0	0
T3	681772	681767	0	0
T4	88890	88813	0	0
T5	663875	663778	0	0
T6	671226	671151	0	0
T7	1210	1153	0	0
T8	209733	209634	0	0
T9	318808	318798	0	0
T10	273577	273523	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344691966	344606699	0	0
T1	599650	599587	0	0
T2	32782	32682	0	0
T3	681772	681767	0	0
T4	88890	88813	0	0
T5	663875	663778	0	0
T6	671226	671151	0	0
T7	1210	1153	0	0
T8	209733	209634	0	0
T9	318808	318798	0	0
T10	273577	273523	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344691966	1834021	0	0
T2	32782	832	0	0
T3	681772	13332	0	0
T4	88890	0	0	0
T5	663875	6357	0	0
T6	671226	0	0	0
T7	1210	0	0	0
T8	209733	832	0	0
T9	318808	10350	0	0
T10	273577	0	0	0
T11	24889	0	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	1344	0	0
T15	0	9563	0	0
T16	0	9297	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344691966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344691966	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344691966	1834021	0	0
T2	32782	832	0	0
T3	681772	13332	0	0
T4	88890	0	0	0
T5	663875	6357	0	0
T6	671226	0	0	0
T7	1210	0	0	0
T8	209733	832	0	0
T9	318808	10350	0	0
T10	273577	0	0	0
T11	24889	0	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	1344	0	0
T15	0	9563	0	0
T16	0	9297	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344691966	1834021	0	0
T2	32782	832	0	0
T3	681772	13332	0	0
T4	88890	0	0	0
T5	663875	6357	0	0
T6	671226	0	0	0
T7	1210	0	0	0
T8	209733	832	0	0
T9	318808	10350	0	0
T10	273577	0	0	0
T11	24889	0	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	1344	0	0
T15	0	9563	0	0
T16	0	9297	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344691966	1834021	0	0
T2	32782	832	0	0
T3	681772	13332	0	0
T4	88890	0	0	0
T5	663875	6357	0	0
T6	671226	0	0	0
T7	1210	0	0	0
T8	209733	832	0	0
T9	318808	10350	0	0
T10	273577	0	0	0
T11	24889	0	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	1344	0	0
T15	0	9563	0	0
T16	0	9297	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	344691966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344691966	2	0	906
T30	648511	0	0	1
T40	175952	1	0	1
T53	0	1	0	0
T54	24128	0	0	1
T55	1135	0	0	1
T56	143126	0	0	1
T57	4457	0	0	1
T58	56466	0	0	1
T59	213213	0	0	1
T60	129319	0	0	1
T61	15187	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344691966	344606699	0	0
T1	599650	599587	0	0
T2	32782	32682	0	0
T3	681772	681767	0	0
T4	88890	88813	0	0
T5	663875	663778	0	0
T6	671226	671151	0	0
T7	1210	1153	0	0
T8	209733	209634	0	0
T9	318808	318798	0	0
T10	273577	273523	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344691966	1834021	0	0
T2	32782	832	0	0
T3	681772	13332	0	0
T4	88890	0	0	0
T5	663875	6357	0	0
T6	671226	0	0	0
T7	1210	0	0	0
T8	209733	832	0	0
T9	318808	10350	0	0
T10	273577	0	0	0
T11	24889	0	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	1344	0	0
T15	0	9563	0	0
T16	0	9297	0	0