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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.99 98.30 93.93 98.62 89.36 97.14 95.45 99.15


Total test records in report: 1081
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1004 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.4250411878 Jun 13 01:48:02 PM PDT 24 Jun 13 01:48:04 PM PDT 24 43391081 ps
T1005 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2285660161 Jun 13 01:47:36 PM PDT 24 Jun 13 01:47:39 PM PDT 24 103545867 ps
T1006 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3373447522 Jun 13 01:47:37 PM PDT 24 Jun 13 01:47:42 PM PDT 24 171294419 ps
T1007 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.444146030 Jun 13 01:47:52 PM PDT 24 Jun 13 01:47:54 PM PDT 24 10694683 ps
T1008 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1514711988 Jun 13 01:47:52 PM PDT 24 Jun 13 01:47:56 PM PDT 24 103211397 ps
T1009 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3250094572 Jun 13 01:47:22 PM PDT 24 Jun 13 01:47:24 PM PDT 24 175901824 ps
T1010 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1977202227 Jun 13 01:47:55 PM PDT 24 Jun 13 01:47:57 PM PDT 24 65061366 ps
T1011 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.199125581 Jun 13 01:47:38 PM PDT 24 Jun 13 01:47:42 PM PDT 24 86364077 ps
T1012 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.798923575 Jun 13 01:47:31 PM PDT 24 Jun 13 01:47:52 PM PDT 24 295016565 ps
T1013 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2353640215 Jun 13 01:47:36 PM PDT 24 Jun 13 01:47:38 PM PDT 24 64261696 ps
T1014 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.874756479 Jun 13 01:47:37 PM PDT 24 Jun 13 01:47:42 PM PDT 24 168564408 ps
T1015 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3255829202 Jun 13 01:47:36 PM PDT 24 Jun 13 01:47:39 PM PDT 24 149847541 ps
T1016 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.538487578 Jun 13 01:47:51 PM PDT 24 Jun 13 01:47:53 PM PDT 24 45046114 ps
T1017 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1285899507 Jun 13 01:47:20 PM PDT 24 Jun 13 01:47:22 PM PDT 24 69194477 ps
T1018 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.914548401 Jun 13 01:47:23 PM PDT 24 Jun 13 01:47:26 PM PDT 24 48027511 ps
T1019 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2560158718 Jun 13 01:47:53 PM PDT 24 Jun 13 01:47:59 PM PDT 24 287010200 ps
T1020 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.453467613 Jun 13 01:47:37 PM PDT 24 Jun 13 01:47:42 PM PDT 24 106462831 ps
T1021 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.465154915 Jun 13 01:47:52 PM PDT 24 Jun 13 01:47:54 PM PDT 24 29736264 ps
T1022 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.47680367 Jun 13 01:47:37 PM PDT 24 Jun 13 01:47:40 PM PDT 24 170609888 ps
T1023 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.549025774 Jun 13 01:47:19 PM PDT 24 Jun 13 01:47:21 PM PDT 24 509811972 ps
T1024 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.201751395 Jun 13 01:47:23 PM PDT 24 Jun 13 01:47:28 PM PDT 24 60977944 ps
T1025 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2053408721 Jun 13 01:47:43 PM PDT 24 Jun 13 01:47:47 PM PDT 24 2376954134 ps
T1026 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3561998893 Jun 13 01:47:45 PM PDT 24 Jun 13 01:47:49 PM PDT 24 222154420 ps
T1027 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1655208305 Jun 13 01:47:38 PM PDT 24 Jun 13 01:47:44 PM PDT 24 1712637343 ps
T1028 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2926401074 Jun 13 01:47:42 PM PDT 24 Jun 13 01:47:45 PM PDT 24 311361527 ps
T1029 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.881543234 Jun 13 01:47:42 PM PDT 24 Jun 13 01:47:47 PM PDT 24 540567967 ps
T1030 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.797983561 Jun 13 01:47:23 PM PDT 24 Jun 13 01:47:27 PM PDT 24 194888083 ps
T1031 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1739748088 Jun 13 01:47:36 PM PDT 24 Jun 13 01:47:40 PM PDT 24 123425604 ps
T1032 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.931395882 Jun 13 01:47:43 PM PDT 24 Jun 13 01:47:49 PM PDT 24 1145322504 ps
T1033 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.490005781 Jun 13 01:47:23 PM PDT 24 Jun 13 01:47:29 PM PDT 24 63638121 ps
T1034 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.4240054415 Jun 13 01:47:54 PM PDT 24 Jun 13 01:47:57 PM PDT 24 51974235 ps
T1035 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.191893833 Jun 13 01:47:43 PM PDT 24 Jun 13 01:47:45 PM PDT 24 52106932 ps
T1036 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.404580908 Jun 13 01:47:31 PM PDT 24 Jun 13 01:47:34 PM PDT 24 25369654 ps
T1037 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2038512567 Jun 13 01:47:36 PM PDT 24 Jun 13 01:47:40 PM PDT 24 359006592 ps
T1038 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1261997344 Jun 13 01:47:45 PM PDT 24 Jun 13 01:48:03 PM PDT 24 686810803 ps
T1039 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2387839573 Jun 13 01:47:54 PM PDT 24 Jun 13 01:47:56 PM PDT 24 14305760 ps
T1040 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2901405988 Jun 13 01:47:51 PM PDT 24 Jun 13 01:47:54 PM PDT 24 37936123 ps
T1041 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4045903881 Jun 13 01:47:26 PM PDT 24 Jun 13 01:47:27 PM PDT 24 63426628 ps
T1042 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4124711641 Jun 13 01:47:53 PM PDT 24 Jun 13 01:47:56 PM PDT 24 13482087 ps
T1043 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1464613920 Jun 13 01:47:23 PM PDT 24 Jun 13 01:47:25 PM PDT 24 127126143 ps
T1044 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1525137053 Jun 13 01:47:31 PM PDT 24 Jun 13 01:48:09 PM PDT 24 2445448204 ps
T1045 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2832642141 Jun 13 01:47:51 PM PDT 24 Jun 13 01:47:52 PM PDT 24 15460573 ps
T90 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2530035640 Jun 13 01:47:30 PM PDT 24 Jun 13 01:47:32 PM PDT 24 22726563 ps
T1046 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2359601241 Jun 13 01:47:43 PM PDT 24 Jun 13 01:47:46 PM PDT 24 38016182 ps
T1047 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.471586388 Jun 13 01:47:44 PM PDT 24 Jun 13 01:47:50 PM PDT 24 1571297348 ps
T1048 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1010935873 Jun 13 01:47:26 PM PDT 24 Jun 13 01:47:27 PM PDT 24 36256897 ps
T1049 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.476120492 Jun 13 01:47:17 PM PDT 24 Jun 13 01:47:18 PM PDT 24 38713517 ps
T1050 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1504346524 Jun 13 01:47:54 PM PDT 24 Jun 13 01:47:57 PM PDT 24 40569978 ps
T1051 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1312633988 Jun 13 01:47:11 PM PDT 24 Jun 13 01:47:16 PM PDT 24 154875414 ps
T1052 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3068929751 Jun 13 01:47:51 PM PDT 24 Jun 13 01:47:54 PM PDT 24 12537488 ps
T1053 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.773675786 Jun 13 01:47:52 PM PDT 24 Jun 13 01:47:57 PM PDT 24 606863382 ps
T1054 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3286539367 Jun 13 01:47:52 PM PDT 24 Jun 13 01:47:55 PM PDT 24 100794902 ps
T1055 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2347486388 Jun 13 01:47:38 PM PDT 24 Jun 13 01:47:42 PM PDT 24 69610814 ps
T247 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2037948442 Jun 13 01:47:51 PM PDT 24 Jun 13 01:48:10 PM PDT 24 1748410536 ps
T1056 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3930421274 Jun 13 01:47:52 PM PDT 24 Jun 13 01:47:54 PM PDT 24 12357633 ps
T1057 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3403171208 Jun 13 01:47:39 PM PDT 24 Jun 13 01:47:44 PM PDT 24 153769867 ps
T1058 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2413862072 Jun 13 01:47:16 PM PDT 24 Jun 13 01:47:24 PM PDT 24 109766069 ps
T1059 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1528507675 Jun 13 01:47:38 PM PDT 24 Jun 13 01:47:42 PM PDT 24 94220209 ps
T1060 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1972775642 Jun 13 01:47:23 PM PDT 24 Jun 13 01:48:01 PM PDT 24 2171690519 ps
T91 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2293558089 Jun 13 01:47:19 PM PDT 24 Jun 13 01:47:21 PM PDT 24 210745060 ps
T1061 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.378068975 Jun 13 01:47:36 PM PDT 24 Jun 13 01:47:41 PM PDT 24 60099196 ps
T1062 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4169441048 Jun 13 01:47:35 PM PDT 24 Jun 13 01:47:38 PM PDT 24 426191950 ps
T1063 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2637497281 Jun 13 01:47:19 PM PDT 24 Jun 13 01:47:44 PM PDT 24 1079013818 ps
T1064 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.780900967 Jun 13 01:47:50 PM PDT 24 Jun 13 01:47:54 PM PDT 24 117689642 ps
T1065 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1777630859 Jun 13 01:47:22 PM PDT 24 Jun 13 01:47:25 PM PDT 24 57446502 ps
T1066 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2877496274 Jun 13 01:47:30 PM PDT 24 Jun 13 01:47:32 PM PDT 24 33046435 ps
T1067 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3733402702 Jun 13 01:47:32 PM PDT 24 Jun 13 01:47:33 PM PDT 24 22019292 ps
T1068 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.863741925 Jun 13 01:47:52 PM PDT 24 Jun 13 01:47:56 PM PDT 24 106377946 ps
T1069 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3902740782 Jun 13 01:47:36 PM PDT 24 Jun 13 01:47:40 PM PDT 24 81687571 ps
T1070 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.983420283 Jun 13 01:47:54 PM PDT 24 Jun 13 01:48:09 PM PDT 24 201085282 ps
T1071 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4169512582 Jun 13 01:47:38 PM PDT 24 Jun 13 01:47:49 PM PDT 24 4664721166 ps
T1072 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3937372474 Jun 13 01:47:24 PM PDT 24 Jun 13 01:47:28 PM PDT 24 458625750 ps
T1073 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2409437747 Jun 13 01:47:21 PM PDT 24 Jun 13 01:47:24 PM PDT 24 96652607 ps
T1074 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2975172695 Jun 13 01:47:43 PM PDT 24 Jun 13 01:47:49 PM PDT 24 129799422 ps
T1075 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2958033457 Jun 13 01:48:00 PM PDT 24 Jun 13 01:48:01 PM PDT 24 40561266 ps
T1076 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1121864939 Jun 13 01:47:39 PM PDT 24 Jun 13 01:48:03 PM PDT 24 4484040357 ps
T1077 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3206366682 Jun 13 01:47:47 PM PDT 24 Jun 13 01:47:51 PM PDT 24 44861914 ps
T1078 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.304877573 Jun 13 01:47:24 PM PDT 24 Jun 13 01:47:26 PM PDT 24 37356146 ps
T1079 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3878521675 Jun 13 01:47:53 PM PDT 24 Jun 13 01:47:59 PM PDT 24 180659310 ps
T1080 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3678737304 Jun 13 01:47:19 PM PDT 24 Jun 13 01:47:21 PM PDT 24 79607187 ps
T1081 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3074658449 Jun 13 01:47:24 PM PDT 24 Jun 13 01:48:09 PM PDT 24 5478070567 ps

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.786969507
Short name T3
Test name
Test status
Simulation time 68177297994 ps
CPU time 729.36 seconds
Started Jun 13 12:32:37 PM PDT 24
Finished Jun 13 12:44:48 PM PDT 24
Peak memory 257976 kb
Host smart-16d8dbad-df25-401f-b945-7a846962bdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786969507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.786969507
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2876832562
Short name T49
Test name
Test status
Simulation time 78200951049 ps
CPU time 657.82 seconds
Started Jun 13 01:48:09 PM PDT 24
Finished Jun 13 01:59:08 PM PDT 24
Peak memory 257172 kb
Host smart-3ba40a46-8493-4f29-8992-83e9d2a47d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876832562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2876832562
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1604340151
Short name T18
Test name
Test status
Simulation time 129300162510 ps
CPU time 277.03 seconds
Started Jun 13 12:33:33 PM PDT 24
Finished Jun 13 12:38:11 PM PDT 24
Peak memory 265124 kb
Host smart-41192436-c121-4883-8944-b2ea29ea37d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604340151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1604340151
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2266671050
Short name T66
Test name
Test status
Simulation time 111582206 ps
CPU time 2.79 seconds
Started Jun 13 01:47:54 PM PDT 24
Finished Jun 13 01:47:58 PM PDT 24
Peak memory 216860 kb
Host smart-d5d02c35-df92-4267-ab6b-4b74bab0ac85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266671050 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2266671050
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.764443159
Short name T21
Test name
Test status
Simulation time 37608243466 ps
CPU time 410.9 seconds
Started Jun 13 12:33:00 PM PDT 24
Finished Jun 13 12:39:52 PM PDT 24
Peak memory 274352 kb
Host smart-8acc7f36-1b2b-426b-891b-57f17a08e093
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764443159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.764443159
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2517653954
Short name T69
Test name
Test status
Simulation time 45470318 ps
CPU time 0.81 seconds
Started Jun 13 12:32:19 PM PDT 24
Finished Jun 13 12:32:22 PM PDT 24
Peak memory 216668 kb
Host smart-fc70f165-69da-491e-b6a1-17ddcf295de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517653954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2517653954
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3883515203
Short name T19
Test name
Test status
Simulation time 71233298336 ps
CPU time 179.17 seconds
Started Jun 13 12:33:03 PM PDT 24
Finished Jun 13 12:36:03 PM PDT 24
Peak memory 252868 kb
Host smart-c023a7ca-bad2-48bc-ba94-55bd924fd401
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883515203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3883515203
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3433844959
Short name T59
Test name
Test status
Simulation time 56109271469 ps
CPU time 279.13 seconds
Started Jun 13 12:33:07 PM PDT 24
Finished Jun 13 12:37:48 PM PDT 24
Peak memory 265032 kb
Host smart-223ee98e-0d75-4572-9b55-9951967d1cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433844959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3433844959
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2141232296
Short name T170
Test name
Test status
Simulation time 182440836253 ps
CPU time 373.93 seconds
Started Jun 13 12:32:48 PM PDT 24
Finished Jun 13 12:39:03 PM PDT 24
Peak memory 257968 kb
Host smart-c487b5fe-d81c-4702-b5f9-5d4611167344
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141232296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2141232296
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.738797159
Short name T241
Test name
Test status
Simulation time 311437329 ps
CPU time 19.71 seconds
Started Jun 13 01:47:53 PM PDT 24
Finished Jun 13 01:48:14 PM PDT 24
Peak memory 215484 kb
Host smart-919948dc-ca46-4212-850c-5c9a9c97925e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738797159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.738797159
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.104370622
Short name T78
Test name
Test status
Simulation time 287991895196 ps
CPU time 532.86 seconds
Started Jun 13 12:33:16 PM PDT 24
Finished Jun 13 12:42:14 PM PDT 24
Peak memory 263644 kb
Host smart-800818b4-798c-49f0-b7be-2aaa45cebcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104370622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.104370622
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3908340123
Short name T14
Test name
Test status
Simulation time 13889629260 ps
CPU time 81.07 seconds
Started Jun 13 12:45:45 PM PDT 24
Finished Jun 13 12:47:06 PM PDT 24
Peak memory 257952 kb
Host smart-2bdb346b-91bc-4c14-826d-4bc72804e5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908340123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3908340123
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.4009161471
Short name T340
Test name
Test status
Simulation time 18426777 ps
CPU time 0.72 seconds
Started Jun 13 12:32:48 PM PDT 24
Finished Jun 13 12:32:50 PM PDT 24
Peak memory 205408 kb
Host smart-d3b699d0-f9b3-415c-8ff7-40bb666fec2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009161471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
4009161471
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.4286237522
Short name T40
Test name
Test status
Simulation time 17773020660 ps
CPU time 196.89 seconds
Started Jun 13 12:33:36 PM PDT 24
Finished Jun 13 12:36:54 PM PDT 24
Peak memory 250572 kb
Host smart-57065464-2568-4c82-bdf0-2ebcbd086807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286237522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.4286237522
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.513067394
Short name T221
Test name
Test status
Simulation time 214820207786 ps
CPU time 500.77 seconds
Started Jun 13 01:32:38 PM PDT 24
Finished Jun 13 01:40:59 PM PDT 24
Peak memory 256032 kb
Host smart-f93d66a4-9d87-4bf5-9e76-3718ac598c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513067394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.513067394
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3574424891
Short name T85
Test name
Test status
Simulation time 4222391701 ps
CPU time 84.31 seconds
Started Jun 13 12:35:36 PM PDT 24
Finished Jun 13 12:37:04 PM PDT 24
Peak memory 257104 kb
Host smart-085d7d96-1f19-477a-a871-d32d36849807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574424891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3574424891
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3009151951
Short name T88
Test name
Test status
Simulation time 196563832 ps
CPU time 1.53 seconds
Started Jun 13 01:47:19 PM PDT 24
Finished Jun 13 01:47:21 PM PDT 24
Peak memory 216356 kb
Host smart-24c52a66-75b1-47c0-965f-1112a21d69ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009151951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3009151951
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1306650196
Short name T163
Test name
Test status
Simulation time 19163208719 ps
CPU time 204.49 seconds
Started Jun 13 12:32:45 PM PDT 24
Finished Jun 13 12:36:11 PM PDT 24
Peak memory 266068 kb
Host smart-e87b2081-202e-49a6-bfc2-ba9c879b2496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306650196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1306650196
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1226498963
Short name T100
Test name
Test status
Simulation time 237745152 ps
CPU time 3.47 seconds
Started Jun 13 01:47:37 PM PDT 24
Finished Jun 13 01:47:42 PM PDT 24
Peak memory 215564 kb
Host smart-33f6e4ba-1f1a-4cf2-a534-088d9e681493
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226498963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1226498963
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3203664723
Short name T31
Test name
Test status
Simulation time 3740020202 ps
CPU time 91.12 seconds
Started Jun 13 01:26:47 PM PDT 24
Finished Jun 13 01:28:20 PM PDT 24
Peak memory 256288 kb
Host smart-1b13c214-96ac-4ad4-b56e-80eb4a384d65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203664723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3203664723
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2718133333
Short name T53
Test name
Test status
Simulation time 19962378248 ps
CPU time 237.17 seconds
Started Jun 13 12:32:27 PM PDT 24
Finished Jun 13 12:36:26 PM PDT 24
Peak memory 256136 kb
Host smart-b41dd383-b4ac-4aee-95ac-d318ab2f7d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718133333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2718133333
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1799946742
Short name T71
Test name
Test status
Simulation time 325139156 ps
CPU time 1.18 seconds
Started Jun 13 12:32:07 PM PDT 24
Finished Jun 13 12:32:11 PM PDT 24
Peak memory 236428 kb
Host smart-e4092657-ef12-49d6-ad23-8067d5effbd1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799946742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1799946742
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.4078498861
Short name T162
Test name
Test status
Simulation time 11793022176 ps
CPU time 107.8 seconds
Started Jun 13 02:34:25 PM PDT 24
Finished Jun 13 02:36:14 PM PDT 24
Peak memory 255520 kb
Host smart-dbd4472a-6404-4696-b42a-f881306fb29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078498861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.4078498861
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2609089095
Short name T258
Test name
Test status
Simulation time 227447513517 ps
CPU time 614.64 seconds
Started Jun 13 12:33:03 PM PDT 24
Finished Jun 13 12:43:19 PM PDT 24
Peak memory 267248 kb
Host smart-7ab72523-20b2-4a91-b496-e8308cc78880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609089095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2609089095
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.493906446
Short name T173
Test name
Test status
Simulation time 26876736883 ps
CPU time 91.85 seconds
Started Jun 13 12:32:16 PM PDT 24
Finished Jun 13 12:33:50 PM PDT 24
Peak memory 263592 kb
Host smart-bd000666-105e-4e7f-b51c-760ef78d6e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493906446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.493906446
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2101595775
Short name T207
Test name
Test status
Simulation time 66332780612 ps
CPU time 640.12 seconds
Started Jun 13 12:32:28 PM PDT 24
Finished Jun 13 12:43:10 PM PDT 24
Peak memory 272104 kb
Host smart-d3d51bdc-808a-49cb-a049-d2a9c08aa959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101595775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2101595775
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.706622672
Short name T110
Test name
Test status
Simulation time 188989364 ps
CPU time 4.78 seconds
Started Jun 13 01:47:36 PM PDT 24
Finished Jun 13 01:47:43 PM PDT 24
Peak memory 216588 kb
Host smart-488f0c20-2d10-4737-964b-9498d5a460f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706622672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.706622672
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1383917379
Short name T209
Test name
Test status
Simulation time 9391017920 ps
CPU time 128.17 seconds
Started Jun 13 12:33:21 PM PDT 24
Finished Jun 13 12:35:34 PM PDT 24
Peak memory 261488 kb
Host smart-d8454007-52d2-4797-97aa-a770d0a30fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383917379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1383917379
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.4085376291
Short name T134
Test name
Test status
Simulation time 41711874527 ps
CPU time 401.39 seconds
Started Jun 13 12:33:17 PM PDT 24
Finished Jun 13 12:40:04 PM PDT 24
Peak memory 264652 kb
Host smart-27b602f9-251b-4765-bb66-11636b3acfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085376291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.4085376291
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2029163463
Short name T216
Test name
Test status
Simulation time 13863835086 ps
CPU time 68.44 seconds
Started Jun 13 12:33:02 PM PDT 24
Finished Jun 13 12:34:12 PM PDT 24
Peak memory 251824 kb
Host smart-6f43689e-bb79-44b9-989d-4699acbe8e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029163463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2029163463
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3261818769
Short name T20
Test name
Test status
Simulation time 7437170176 ps
CPU time 45.44 seconds
Started Jun 13 12:33:13 PM PDT 24
Finished Jun 13 12:34:00 PM PDT 24
Peak memory 241592 kb
Host smart-fb465fdd-402f-46b4-bc42-8ce0fddfe4e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261818769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3261818769
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3645904978
Short name T224
Test name
Test status
Simulation time 20671393862 ps
CPU time 268.98 seconds
Started Jun 13 12:32:10 PM PDT 24
Finished Jun 13 12:36:42 PM PDT 24
Peak memory 264516 kb
Host smart-857fdfa5-91cd-4f50-b22b-bf337bf84d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645904978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3645904978
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.4119609846
Short name T300
Test name
Test status
Simulation time 215996713 ps
CPU time 8.69 seconds
Started Jun 13 12:32:21 PM PDT 24
Finished Jun 13 12:32:33 PM PDT 24
Peak memory 225060 kb
Host smart-a263f4f0-a771-4709-a552-a9fb85b55abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119609846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.4119609846
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.223692570
Short name T227
Test name
Test status
Simulation time 30441886669 ps
CPU time 138.04 seconds
Started Jun 13 12:32:47 PM PDT 24
Finished Jun 13 12:35:06 PM PDT 24
Peak memory 266188 kb
Host smart-795c5786-0b86-41eb-b22e-f7e417008ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223692570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.223692570
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3711806540
Short name T4
Test name
Test status
Simulation time 925994727 ps
CPU time 5.42 seconds
Started Jun 13 12:33:09 PM PDT 24
Finished Jun 13 12:33:16 PM PDT 24
Peak memory 216748 kb
Host smart-0a631233-fc40-43d4-8ca9-a302da4160d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711806540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3711806540
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3612831834
Short name T15
Test name
Test status
Simulation time 241499407601 ps
CPU time 362.73 seconds
Started Jun 13 12:32:17 PM PDT 24
Finished Jun 13 12:38:22 PM PDT 24
Peak memory 266108 kb
Host smart-a2de3619-9cc0-461f-910f-fc10b88bc469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612831834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3612831834
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3694861197
Short name T180
Test name
Test status
Simulation time 68598996605 ps
CPU time 165.92 seconds
Started Jun 13 12:32:59 PM PDT 24
Finished Jun 13 12:35:47 PM PDT 24
Peak memory 251976 kb
Host smart-feeddf6f-745f-4b27-bbfb-aec8b265c49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694861197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3694861197
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.232271620
Short name T45
Test name
Test status
Simulation time 28688442466 ps
CPU time 276.03 seconds
Started Jun 13 12:33:13 PM PDT 24
Finished Jun 13 12:37:52 PM PDT 24
Peak memory 241296 kb
Host smart-7bfca722-7079-4aa1-b876-8d22476152bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232271620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.232271620
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1493194034
Short name T553
Test name
Test status
Simulation time 209580030534 ps
CPU time 291.7 seconds
Started Jun 13 01:03:21 PM PDT 24
Finished Jun 13 01:08:14 PM PDT 24
Peak memory 258076 kb
Host smart-ed384396-eb27-4224-8b0d-22c026ff730a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493194034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1493194034
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.401736861
Short name T218
Test name
Test status
Simulation time 45847357536 ps
CPU time 408.18 seconds
Started Jun 13 12:32:25 PM PDT 24
Finished Jun 13 12:39:16 PM PDT 24
Peak memory 264776 kb
Host smart-e4052803-b2e9-4677-87e1-ae98be6919ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401736861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.401736861
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2604428557
Short name T97
Test name
Test status
Simulation time 369032435 ps
CPU time 3.48 seconds
Started Jun 13 12:32:54 PM PDT 24
Finished Jun 13 12:33:00 PM PDT 24
Peak memory 225088 kb
Host smart-f1519091-0a74-4629-ac1b-7b5f46b492d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604428557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2604428557
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2413862072
Short name T1058
Test name
Test status
Simulation time 109766069 ps
CPU time 7.27 seconds
Started Jun 13 01:47:16 PM PDT 24
Finished Jun 13 01:47:24 PM PDT 24
Peak memory 215428 kb
Host smart-e47be8c1-8280-4d34-94c6-04c01bbc0c0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413862072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2413862072
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.181552309
Short name T246
Test name
Test status
Simulation time 116390053 ps
CPU time 7.01 seconds
Started Jun 13 01:47:38 PM PDT 24
Finished Jun 13 01:47:47 PM PDT 24
Peak memory 215408 kb
Host smart-5c27efff-1c6f-4304-b978-40b6e831715c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181552309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.181552309
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2969300498
Short name T743
Test name
Test status
Simulation time 666157936 ps
CPU time 16.28 seconds
Started Jun 13 12:32:31 PM PDT 24
Finished Jun 13 12:32:49 PM PDT 24
Peak memory 241472 kb
Host smart-c723dbe7-c92c-4dee-a830-1a209d91d6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969300498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2969300498
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3532900075
Short name T238
Test name
Test status
Simulation time 11276121917 ps
CPU time 33.15 seconds
Started Jun 13 12:32:37 PM PDT 24
Finished Jun 13 12:33:11 PM PDT 24
Peak memory 225140 kb
Host smart-84526377-395b-4415-b95f-ed1937c27d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532900075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3532900075
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1322237632
Short name T222
Test name
Test status
Simulation time 8065381345 ps
CPU time 132.07 seconds
Started Jun 13 12:33:06 PM PDT 24
Finished Jun 13 12:35:19 PM PDT 24
Peak memory 249740 kb
Host smart-59d60d94-d509-4cd6-bef9-eb7b5f2fc2eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322237632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1322237632
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3338069402
Short name T228
Test name
Test status
Simulation time 7147687710 ps
CPU time 119.53 seconds
Started Jun 13 12:32:54 PM PDT 24
Finished Jun 13 12:34:56 PM PDT 24
Peak memory 257188 kb
Host smart-4cdd31b6-99f7-47e5-8b3a-5438cda61ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338069402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3338069402
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2451064379
Short name T202
Test name
Test status
Simulation time 16748587562 ps
CPU time 131.22 seconds
Started Jun 13 12:33:16 PM PDT 24
Finished Jun 13 12:35:32 PM PDT 24
Peak memory 239276 kb
Host smart-446c89c5-c896-4685-9a37-4329c1a10dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451064379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2451064379
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.832558768
Short name T269
Test name
Test status
Simulation time 183595303043 ps
CPU time 420.45 seconds
Started Jun 13 12:33:35 PM PDT 24
Finished Jun 13 12:40:37 PM PDT 24
Peak memory 254316 kb
Host smart-082b9ec4-6fad-48b9-8caa-1f698b4e6308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832558768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.832558768
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3428715693
Short name T219
Test name
Test status
Simulation time 13614663116 ps
CPU time 82.16 seconds
Started Jun 13 01:21:02 PM PDT 24
Finished Jun 13 01:22:25 PM PDT 24
Peak memory 256416 kb
Host smart-896cc35c-dc77-4aa1-9111-fe10d0c943b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428715693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3428715693
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3305369936
Short name T192
Test name
Test status
Simulation time 109153500810 ps
CPU time 133.89 seconds
Started Jun 13 01:28:48 PM PDT 24
Finished Jun 13 01:31:02 PM PDT 24
Peak memory 250996 kb
Host smart-6eb62026-8554-4b64-aafe-f0f4af88dba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305369936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3305369936
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3262913469
Short name T237
Test name
Test status
Simulation time 40503012813 ps
CPU time 225.87 seconds
Started Jun 13 01:36:28 PM PDT 24
Finished Jun 13 01:40:16 PM PDT 24
Peak memory 257032 kb
Host smart-dc938953-22a7-4020-94b1-a603af670c41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262913469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3262913469
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.143104458
Short name T201
Test name
Test status
Simulation time 7910704576 ps
CPU time 123.94 seconds
Started Jun 13 12:32:25 PM PDT 24
Finished Jun 13 12:34:31 PM PDT 24
Peak memory 262300 kb
Host smart-401df009-6fd7-4ff5-9994-60fbd0beef60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143104458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.143104458
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.446283255
Short name T112
Test name
Test status
Simulation time 190430738 ps
CPU time 4.96 seconds
Started Jun 13 01:47:44 PM PDT 24
Finished Jun 13 01:47:51 PM PDT 24
Peak memory 216804 kb
Host smart-d0a4f056-fa26-45af-813a-8503b3f868f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446283255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.446283255
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.577089447
Short name T98
Test name
Test status
Simulation time 2106479153 ps
CPU time 6.29 seconds
Started Jun 13 12:32:29 PM PDT 24
Finished Jun 13 12:32:37 PM PDT 24
Peak memory 233272 kb
Host smart-9956bd4b-1970-441f-ac11-e9d3f2a326df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577089447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
577089447
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2133265819
Short name T123
Test name
Test status
Simulation time 203733576 ps
CPU time 8 seconds
Started Jun 13 01:47:17 PM PDT 24
Finished Jun 13 01:47:26 PM PDT 24
Peak memory 215416 kb
Host smart-6390902f-0743-43c2-a458-f43383be35b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133265819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2133265819
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3240709202
Short name T985
Test name
Test status
Simulation time 537609839 ps
CPU time 33.49 seconds
Started Jun 13 01:47:25 PM PDT 24
Finished Jun 13 01:47:59 PM PDT 24
Peak memory 207128 kb
Host smart-4138aeb0-a6a6-4c8c-892a-cc53e0c4df9e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240709202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3240709202
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2293558089
Short name T91
Test name
Test status
Simulation time 210745060 ps
CPU time 1.51 seconds
Started Jun 13 01:47:19 PM PDT 24
Finished Jun 13 01:47:21 PM PDT 24
Peak memory 216424 kb
Host smart-3fa87eed-a3a9-43b9-9faa-84ae64042bc1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293558089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2293558089
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1026845188
Short name T996
Test name
Test status
Simulation time 607683153 ps
CPU time 3.79 seconds
Started Jun 13 01:47:16 PM PDT 24
Finished Jun 13 01:47:21 PM PDT 24
Peak memory 217956 kb
Host smart-151f9e27-a6e4-4205-b6bd-2b75994d75f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026845188 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1026845188
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.978294744
Short name T121
Test name
Test status
Simulation time 277607546 ps
CPU time 1.94 seconds
Started Jun 13 01:47:26 PM PDT 24
Finished Jun 13 01:47:29 PM PDT 24
Peak memory 215308 kb
Host smart-3dd54d85-5a12-40f6-91e3-2fde184fbec7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978294744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.978294744
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1153009149
Short name T965
Test name
Test status
Simulation time 152852519 ps
CPU time 0.78 seconds
Started Jun 13 01:47:17 PM PDT 24
Finished Jun 13 01:47:19 PM PDT 24
Peak memory 203904 kb
Host smart-2f566fe9-4386-4a98-aa09-62210f31d706
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153009149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
153009149
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1096386370
Short name T120
Test name
Test status
Simulation time 268095339 ps
CPU time 2.39 seconds
Started Jun 13 01:47:15 PM PDT 24
Finished Jun 13 01:47:18 PM PDT 24
Peak memory 215404 kb
Host smart-1affe973-33cf-465b-929b-334d3e2e2767
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096386370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1096386370
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1010935873
Short name T1048
Test name
Test status
Simulation time 36256897 ps
CPU time 0.66 seconds
Started Jun 13 01:47:26 PM PDT 24
Finished Jun 13 01:47:27 PM PDT 24
Peak memory 203792 kb
Host smart-4bc82f15-6457-463f-a545-372e71165e1d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010935873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1010935873
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2564388484
Short name T1003
Test name
Test status
Simulation time 62798942 ps
CPU time 3.99 seconds
Started Jun 13 01:47:26 PM PDT 24
Finished Jun 13 01:47:30 PM PDT 24
Peak memory 215392 kb
Host smart-a53746ec-069c-4e4a-b346-b72f80392ae3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564388484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2564388484
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1312633988
Short name T1051
Test name
Test status
Simulation time 154875414 ps
CPU time 2.43 seconds
Started Jun 13 01:47:11 PM PDT 24
Finished Jun 13 01:47:16 PM PDT 24
Peak memory 215568 kb
Host smart-dd47ddd8-1253-4d35-aef8-f3ad0beeb2fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312633988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
312633988
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2637497281
Short name T1063
Test name
Test status
Simulation time 1079013818 ps
CPU time 24.59 seconds
Started Jun 13 01:47:19 PM PDT 24
Finished Jun 13 01:47:44 PM PDT 24
Peak memory 215468 kb
Host smart-7dd16c7e-4cac-4e32-9702-a05214178874
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637497281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2637497281
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.892028087
Short name T117
Test name
Test status
Simulation time 108912182 ps
CPU time 7.76 seconds
Started Jun 13 01:47:19 PM PDT 24
Finished Jun 13 01:47:28 PM PDT 24
Peak memory 207156 kb
Host smart-485ea8ad-51c8-4b7a-a448-6729009f6d77
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892028087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.892028087
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1846139637
Short name T993
Test name
Test status
Simulation time 3741750153 ps
CPU time 34.38 seconds
Started Jun 13 01:47:19 PM PDT 24
Finished Jun 13 01:47:54 PM PDT 24
Peak memory 207164 kb
Host smart-f101d74a-cb05-4c0f-b9ca-bff0854a0c21
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846139637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1846139637
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1410366871
Short name T113
Test name
Test status
Simulation time 173379535 ps
CPU time 1.7 seconds
Started Jun 13 01:47:19 PM PDT 24
Finished Jun 13 01:47:22 PM PDT 24
Peak memory 215468 kb
Host smart-dd60fb24-5745-449d-aa4a-3d3cc5c0ee62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410366871 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1410366871
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3678737304
Short name T1080
Test name
Test status
Simulation time 79607187 ps
CPU time 1.37 seconds
Started Jun 13 01:47:19 PM PDT 24
Finished Jun 13 01:47:21 PM PDT 24
Peak memory 215300 kb
Host smart-79fa1748-ce37-4950-a5d5-ef945c3fc8cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678737304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
678737304
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2256256038
Short name T955
Test name
Test status
Simulation time 22114729 ps
CPU time 0.75 seconds
Started Jun 13 01:47:16 PM PDT 24
Finished Jun 13 01:47:17 PM PDT 24
Peak memory 203904 kb
Host smart-1242fad9-caaa-45ff-9db1-ed2fd9abf5b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256256038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
256256038
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3159579978
Short name T126
Test name
Test status
Simulation time 28351465 ps
CPU time 2.1 seconds
Started Jun 13 01:47:19 PM PDT 24
Finished Jun 13 01:47:22 PM PDT 24
Peak memory 215468 kb
Host smart-ea419ccd-bb7a-40ad-822c-bd76a2d9fd32
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159579978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3159579978
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1578833918
Short name T982
Test name
Test status
Simulation time 43113918 ps
CPU time 0.68 seconds
Started Jun 13 01:47:27 PM PDT 24
Finished Jun 13 01:47:28 PM PDT 24
Peak memory 204128 kb
Host smart-144c7481-f120-4a75-bfbd-96e11d9de8ad
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578833918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1578833918
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.25823277
Short name T148
Test name
Test status
Simulation time 145323920 ps
CPU time 3.2 seconds
Started Jun 13 01:47:17 PM PDT 24
Finished Jun 13 01:47:21 PM PDT 24
Peak memory 215440 kb
Host smart-ccf4c288-18cb-4ec9-ba70-7715b6005149
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25823277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_same_csr_outstanding.25823277
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1285899507
Short name T1017
Test name
Test status
Simulation time 69194477 ps
CPU time 1.62 seconds
Started Jun 13 01:47:20 PM PDT 24
Finished Jun 13 01:47:22 PM PDT 24
Peak memory 215588 kb
Host smart-6f2cacf7-bebe-44e0-8161-a06543f1a121
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285899507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
285899507
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.47680367
Short name T1022
Test name
Test status
Simulation time 170609888 ps
CPU time 1.77 seconds
Started Jun 13 01:47:37 PM PDT 24
Finished Jun 13 01:47:40 PM PDT 24
Peak memory 215468 kb
Host smart-8e71d5d6-ff13-499e-acc2-ebb975135cea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47680367 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.47680367
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2285660161
Short name T1005
Test name
Test status
Simulation time 103545867 ps
CPU time 1.26 seconds
Started Jun 13 01:47:36 PM PDT 24
Finished Jun 13 01:47:39 PM PDT 24
Peak memory 207280 kb
Host smart-6a8b68b0-0c1d-48b6-af63-dfcddcb2d3d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285660161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2285660161
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2697525183
Short name T960
Test name
Test status
Simulation time 50771286 ps
CPU time 0.8 seconds
Started Jun 13 01:47:37 PM PDT 24
Finished Jun 13 01:47:40 PM PDT 24
Peak memory 203968 kb
Host smart-702eaa58-3bee-4905-8f76-e3a653a56932
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697525183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2697525183
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.453467613
Short name T1020
Test name
Test status
Simulation time 106462831 ps
CPU time 3.01 seconds
Started Jun 13 01:47:37 PM PDT 24
Finished Jun 13 01:47:42 PM PDT 24
Peak memory 215460 kb
Host smart-eb24a62f-a0be-4741-a1b2-ca04e421e654
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453467613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.453467613
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1528507675
Short name T1059
Test name
Test status
Simulation time 94220209 ps
CPU time 1.74 seconds
Started Jun 13 01:47:38 PM PDT 24
Finished Jun 13 01:47:42 PM PDT 24
Peak memory 215480 kb
Host smart-61d0591f-4318-456e-a98e-a757a923d288
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528507675 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1528507675
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4169441048
Short name T1062
Test name
Test status
Simulation time 426191950 ps
CPU time 2.61 seconds
Started Jun 13 01:47:35 PM PDT 24
Finished Jun 13 01:47:38 PM PDT 24
Peak memory 215336 kb
Host smart-9ba0c516-2e65-4e78-a537-dfcf74d40c4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169441048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
4169441048
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.946717408
Short name T962
Test name
Test status
Simulation time 10747864 ps
CPU time 0.73 seconds
Started Jun 13 01:47:38 PM PDT 24
Finished Jun 13 01:47:42 PM PDT 24
Peak memory 204252 kb
Host smart-176b1860-b78c-47ed-82e9-85ac94828a1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946717408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.946717408
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1655208305
Short name T1027
Test name
Test status
Simulation time 1712637343 ps
CPU time 4.15 seconds
Started Jun 13 01:47:38 PM PDT 24
Finished Jun 13 01:47:44 PM PDT 24
Peak memory 215456 kb
Host smart-3e2a9f90-cb74-49cd-906d-eeb05d69f802
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655208305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1655208305
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2157413857
Short name T147
Test name
Test status
Simulation time 10898282193 ps
CPU time 25.8 seconds
Started Jun 13 01:47:39 PM PDT 24
Finished Jun 13 01:48:08 PM PDT 24
Peak memory 215548 kb
Host smart-3b978766-2719-40a1-a0f8-fa88b0606cb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157413857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2157413857
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.341902327
Short name T992
Test name
Test status
Simulation time 85539554 ps
CPU time 2.66 seconds
Started Jun 13 01:47:43 PM PDT 24
Finished Jun 13 01:47:48 PM PDT 24
Peak memory 216920 kb
Host smart-7752ae89-040b-4411-9718-d8d73a829fb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341902327 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.341902327
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1054519592
Short name T119
Test name
Test status
Simulation time 141499366 ps
CPU time 1.98 seconds
Started Jun 13 01:47:48 PM PDT 24
Finished Jun 13 01:47:51 PM PDT 24
Peak memory 207200 kb
Host smart-c8dece32-fe79-4671-8cff-12d66ccaa6fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054519592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1054519592
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2195915894
Short name T958
Test name
Test status
Simulation time 19607696 ps
CPU time 0.76 seconds
Started Jun 13 01:47:44 PM PDT 24
Finished Jun 13 01:47:47 PM PDT 24
Peak memory 203912 kb
Host smart-3823d082-32e9-4364-b898-8025207e72ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195915894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2195915894
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3206366682
Short name T1077
Test name
Test status
Simulation time 44861914 ps
CPU time 2.72 seconds
Started Jun 13 01:47:47 PM PDT 24
Finished Jun 13 01:47:51 PM PDT 24
Peak memory 215436 kb
Host smart-a623a997-7c38-49e3-88fd-df97f8da3e2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206366682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3206366682
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1739748088
Short name T1031
Test name
Test status
Simulation time 123425604 ps
CPU time 3.68 seconds
Started Jun 13 01:47:36 PM PDT 24
Finished Jun 13 01:47:40 PM PDT 24
Peak memory 215504 kb
Host smart-945f7c78-a062-4778-b3c7-f768f207fe02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739748088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1739748088
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2301090772
Short name T245
Test name
Test status
Simulation time 8575538751 ps
CPU time 26.34 seconds
Started Jun 13 01:47:44 PM PDT 24
Finished Jun 13 01:48:12 PM PDT 24
Peak memory 215536 kb
Host smart-342ddbe7-f0d8-4fb7-92d0-38370baa044a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301090772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2301090772
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2009958942
Short name T970
Test name
Test status
Simulation time 119349885 ps
CPU time 3.36 seconds
Started Jun 13 01:47:44 PM PDT 24
Finished Jun 13 01:47:49 PM PDT 24
Peak memory 217584 kb
Host smart-a2ce864d-8185-4f70-933a-dde6a20e97a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009958942 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2009958942
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2926401074
Short name T1028
Test name
Test status
Simulation time 311361527 ps
CPU time 1.91 seconds
Started Jun 13 01:47:42 PM PDT 24
Finished Jun 13 01:47:45 PM PDT 24
Peak memory 215396 kb
Host smart-57f07ccc-e72d-42a1-9f33-4f8795c173c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926401074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2926401074
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.385011267
Short name T953
Test name
Test status
Simulation time 82213101 ps
CPU time 0.74 seconds
Started Jun 13 01:47:47 PM PDT 24
Finished Jun 13 01:47:49 PM PDT 24
Peak memory 204216 kb
Host smart-488ae9f5-a579-49d6-91d2-291dd48f7cc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385011267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.385011267
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.471586388
Short name T1047
Test name
Test status
Simulation time 1571297348 ps
CPU time 2.67 seconds
Started Jun 13 01:47:44 PM PDT 24
Finished Jun 13 01:47:50 PM PDT 24
Peak memory 215388 kb
Host smart-2da2a6e1-f1ad-40f1-b5d6-3baabe343ee3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471586388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.471586388
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.931395882
Short name T1032
Test name
Test status
Simulation time 1145322504 ps
CPU time 4.98 seconds
Started Jun 13 01:47:43 PM PDT 24
Finished Jun 13 01:47:49 PM PDT 24
Peak memory 215520 kb
Host smart-1c0cca1c-c91e-4378-848f-cd9a1ddbc9d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931395882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.931395882
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2706166160
Short name T102
Test name
Test status
Simulation time 601845449 ps
CPU time 8.45 seconds
Started Jun 13 01:47:44 PM PDT 24
Finished Jun 13 01:47:55 PM PDT 24
Peak memory 215464 kb
Host smart-ed8f6959-e91d-4e7c-96d9-e57d321e5174
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706166160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2706166160
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2975172695
Short name T1074
Test name
Test status
Simulation time 129799422 ps
CPU time 4.02 seconds
Started Jun 13 01:47:43 PM PDT 24
Finished Jun 13 01:47:49 PM PDT 24
Peak memory 217376 kb
Host smart-a53dbb0d-c9d4-4f35-8cb7-e23c8ef9ffca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975172695 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2975172695
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.881543234
Short name T1029
Test name
Test status
Simulation time 540567967 ps
CPU time 3.04 seconds
Started Jun 13 01:47:42 PM PDT 24
Finished Jun 13 01:47:47 PM PDT 24
Peak memory 215324 kb
Host smart-49921eee-ff61-4c0e-a7c7-4d4bb7611e83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881543234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.881543234
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.249016826
Short name T984
Test name
Test status
Simulation time 24306794 ps
CPU time 0.71 seconds
Started Jun 13 01:47:44 PM PDT 24
Finished Jun 13 01:47:47 PM PDT 24
Peak memory 203904 kb
Host smart-dfcb6bf7-db4e-4b00-b106-6b236cc36a09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249016826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.249016826
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.219785975
Short name T978
Test name
Test status
Simulation time 102727226 ps
CPU time 1.9 seconds
Started Jun 13 01:47:46 PM PDT 24
Finished Jun 13 01:47:50 PM PDT 24
Peak memory 216036 kb
Host smart-21d07876-0857-41f9-8929-ca6ac5e5e415
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219785975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.219785975
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3593581958
Short name T99
Test name
Test status
Simulation time 1293238228 ps
CPU time 7.67 seconds
Started Jun 13 01:47:42 PM PDT 24
Finished Jun 13 01:47:51 PM PDT 24
Peak memory 215696 kb
Host smart-bcf1859a-afe4-4bf9-843a-3e5025494836
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593581958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3593581958
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3561998893
Short name T1026
Test name
Test status
Simulation time 222154420 ps
CPU time 1.81 seconds
Started Jun 13 01:47:45 PM PDT 24
Finished Jun 13 01:47:49 PM PDT 24
Peak memory 215528 kb
Host smart-f4f18d0c-a390-4b31-ad76-ed150ce43e03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561998893 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3561998893
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2359601241
Short name T1046
Test name
Test status
Simulation time 38016182 ps
CPU time 1.41 seconds
Started Jun 13 01:47:43 PM PDT 24
Finished Jun 13 01:47:46 PM PDT 24
Peak memory 207076 kb
Host smart-0389fd31-596a-4d04-84bb-9ab57c9de6b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359601241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2359601241
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.191893833
Short name T1035
Test name
Test status
Simulation time 52106932 ps
CPU time 0.73 seconds
Started Jun 13 01:47:43 PM PDT 24
Finished Jun 13 01:47:45 PM PDT 24
Peak memory 203896 kb
Host smart-2e186938-4ea1-43be-a5eb-0a07c6610dc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191893833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.191893833
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4146686002
Short name T138
Test name
Test status
Simulation time 714655556 ps
CPU time 4.29 seconds
Started Jun 13 01:47:46 PM PDT 24
Finished Jun 13 01:47:52 PM PDT 24
Peak memory 215404 kb
Host smart-700a5964-4003-43b9-b728-ef0472fb3846
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146686002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.4146686002
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2069385392
Short name T67
Test name
Test status
Simulation time 560638923 ps
CPU time 3.86 seconds
Started Jun 13 01:47:43 PM PDT 24
Finished Jun 13 01:47:49 PM PDT 24
Peak memory 216536 kb
Host smart-a39b566a-196b-4a82-ad34-910dcdc17cfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069385392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2069385392
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1261997344
Short name T1038
Test name
Test status
Simulation time 686810803 ps
CPU time 15.65 seconds
Started Jun 13 01:47:45 PM PDT 24
Finished Jun 13 01:48:03 PM PDT 24
Peak memory 215424 kb
Host smart-07db1dd5-b6ca-4e9c-9552-2a46af964db8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261997344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1261997344
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.528543260
Short name T125
Test name
Test status
Simulation time 125665302 ps
CPU time 1.87 seconds
Started Jun 13 01:47:44 PM PDT 24
Finished Jun 13 01:47:48 PM PDT 24
Peak memory 207160 kb
Host smart-86aa6b0e-4875-4edc-bdee-88ad50973994
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528543260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.528543260
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.331939994
Short name T977
Test name
Test status
Simulation time 53244957 ps
CPU time 0.78 seconds
Started Jun 13 01:47:45 PM PDT 24
Finished Jun 13 01:47:48 PM PDT 24
Peak memory 203936 kb
Host smart-17f28b71-70c5-42b6-8b84-85aee73129d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331939994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.331939994
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1972890764
Short name T1000
Test name
Test status
Simulation time 42704947 ps
CPU time 2.76 seconds
Started Jun 13 01:47:51 PM PDT 24
Finished Jun 13 01:47:54 PM PDT 24
Peak memory 215476 kb
Host smart-852d6f5f-8e8b-438c-b9ec-f77c5076441a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972890764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1972890764
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2053408721
Short name T1025
Test name
Test status
Simulation time 2376954134 ps
CPU time 3.51 seconds
Started Jun 13 01:47:43 PM PDT 24
Finished Jun 13 01:47:47 PM PDT 24
Peak memory 217940 kb
Host smart-1796b814-1b62-4cbe-aa4a-d60a02a6ec8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053408721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2053408721
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2704921519
Short name T243
Test name
Test status
Simulation time 805832190 ps
CPU time 22.03 seconds
Started Jun 13 01:47:47 PM PDT 24
Finished Jun 13 01:48:11 PM PDT 24
Peak memory 215676 kb
Host smart-d7f79fb3-0beb-424d-93d1-f8eee26a4d58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704921519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2704921519
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.149682935
Short name T999
Test name
Test status
Simulation time 234885881 ps
CPU time 3.03 seconds
Started Jun 13 01:47:50 PM PDT 24
Finished Jun 13 01:47:55 PM PDT 24
Peak memory 216572 kb
Host smart-417f54f0-3260-4930-a361-8ad8c05c01c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149682935 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.149682935
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1327695682
Short name T995
Test name
Test status
Simulation time 341282458 ps
CPU time 2.03 seconds
Started Jun 13 01:47:52 PM PDT 24
Finished Jun 13 01:47:55 PM PDT 24
Peak memory 207116 kb
Host smart-ded97250-3cf9-4680-b87f-4905120bffac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327695682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1327695682
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.538487578
Short name T1016
Test name
Test status
Simulation time 45046114 ps
CPU time 0.76 seconds
Started Jun 13 01:47:51 PM PDT 24
Finished Jun 13 01:47:53 PM PDT 24
Peak memory 203960 kb
Host smart-f9e2be64-8c69-440e-9cf7-80b8f4c0071b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538487578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.538487578
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.780900967
Short name T1064
Test name
Test status
Simulation time 117689642 ps
CPU time 3.63 seconds
Started Jun 13 01:47:50 PM PDT 24
Finished Jun 13 01:47:54 PM PDT 24
Peak memory 215380 kb
Host smart-b9d4b0a6-f917-4e14-ae00-36b6806b7b88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780900967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.780900967
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.231979641
Short name T108
Test name
Test status
Simulation time 49847150 ps
CPU time 3.41 seconds
Started Jun 13 01:47:54 PM PDT 24
Finished Jun 13 01:47:59 PM PDT 24
Peak memory 215568 kb
Host smart-c6317c9e-6967-4cfe-b2bf-90550985fe0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231979641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.231979641
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.983420283
Short name T1070
Test name
Test status
Simulation time 201085282 ps
CPU time 12.8 seconds
Started Jun 13 01:47:54 PM PDT 24
Finished Jun 13 01:48:09 PM PDT 24
Peak memory 215408 kb
Host smart-a89222a4-7e38-4cfa-8961-3777464c3b61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983420283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.983420283
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.863741925
Short name T1068
Test name
Test status
Simulation time 106377946 ps
CPU time 2.8 seconds
Started Jun 13 01:47:52 PM PDT 24
Finished Jun 13 01:47:56 PM PDT 24
Peak memory 217112 kb
Host smart-13db22b8-7e44-492f-ba29-f79f5016b74a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863741925 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.863741925
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1514711988
Short name T1008
Test name
Test status
Simulation time 103211397 ps
CPU time 2.78 seconds
Started Jun 13 01:47:52 PM PDT 24
Finished Jun 13 01:47:56 PM PDT 24
Peak memory 215368 kb
Host smart-3e0e98b8-dbe3-439a-b2b7-792059efbf84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514711988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1514711988
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4124711641
Short name T1042
Test name
Test status
Simulation time 13482087 ps
CPU time 0.74 seconds
Started Jun 13 01:47:53 PM PDT 24
Finished Jun 13 01:47:56 PM PDT 24
Peak memory 203880 kb
Host smart-61159320-d4ca-4394-9e78-6ecab989c70a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124711641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
4124711641
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3878521675
Short name T1079
Test name
Test status
Simulation time 180659310 ps
CPU time 3.95 seconds
Started Jun 13 01:47:53 PM PDT 24
Finished Jun 13 01:47:59 PM PDT 24
Peak memory 215464 kb
Host smart-b75b8056-9918-432d-9f66-d84575e5bd7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878521675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3878521675
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.773675786
Short name T1053
Test name
Test status
Simulation time 606863382 ps
CPU time 3.01 seconds
Started Jun 13 01:47:52 PM PDT 24
Finished Jun 13 01:47:57 PM PDT 24
Peak memory 215588 kb
Host smart-00e68239-a07d-4cff-90c5-9e5d3f5ccb0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773675786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.773675786
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3286539367
Short name T1054
Test name
Test status
Simulation time 100794902 ps
CPU time 2.19 seconds
Started Jun 13 01:47:52 PM PDT 24
Finished Jun 13 01:47:55 PM PDT 24
Peak memory 216552 kb
Host smart-726a5a71-b56a-42dc-a337-9cb33dd6ca5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286539367 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3286539367
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1066974209
Short name T994
Test name
Test status
Simulation time 31534754 ps
CPU time 1.76 seconds
Started Jun 13 01:47:51 PM PDT 24
Finished Jun 13 01:47:55 PM PDT 24
Peak memory 207196 kb
Host smart-cb391767-cae2-4cae-955a-ed59c72aed4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066974209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1066974209
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3068423032
Short name T956
Test name
Test status
Simulation time 12736201 ps
CPU time 0.7 seconds
Started Jun 13 01:47:54 PM PDT 24
Finished Jun 13 01:47:56 PM PDT 24
Peak memory 203884 kb
Host smart-5e28693c-626d-426c-9280-9bc1386feba2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068423032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3068423032
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4188094876
Short name T975
Test name
Test status
Simulation time 53452015 ps
CPU time 3.55 seconds
Started Jun 13 01:47:51 PM PDT 24
Finished Jun 13 01:47:56 PM PDT 24
Peak memory 215424 kb
Host smart-a388acab-3072-4f2c-b8a6-dfd38e391ac0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188094876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.4188094876
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2560158718
Short name T1019
Test name
Test status
Simulation time 287010200 ps
CPU time 4.79 seconds
Started Jun 13 01:47:53 PM PDT 24
Finished Jun 13 01:47:59 PM PDT 24
Peak memory 215716 kb
Host smart-105feb2b-8fdc-404d-b1a0-71cae083c7b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560158718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2560158718
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2037948442
Short name T247
Test name
Test status
Simulation time 1748410536 ps
CPU time 18.35 seconds
Started Jun 13 01:47:51 PM PDT 24
Finished Jun 13 01:48:10 PM PDT 24
Peak memory 215484 kb
Host smart-1cef584e-900c-4178-b7aa-e6d8e602b4de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037948442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2037948442
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2316869457
Short name T979
Test name
Test status
Simulation time 114554388 ps
CPU time 8.15 seconds
Started Jun 13 01:47:23 PM PDT 24
Finished Jun 13 01:47:33 PM PDT 24
Peak memory 207216 kb
Host smart-2079ebc5-7709-4077-96e5-35a5a5eadc3d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316869457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2316869457
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3074658449
Short name T1081
Test name
Test status
Simulation time 5478070567 ps
CPU time 44.12 seconds
Started Jun 13 01:47:24 PM PDT 24
Finished Jun 13 01:48:09 PM PDT 24
Peak memory 207220 kb
Host smart-938aa2b4-02ba-4cad-aff7-a8edf59fd99e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074658449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3074658449
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.4281771609
Short name T89
Test name
Test status
Simulation time 20662830 ps
CPU time 1.16 seconds
Started Jun 13 01:47:24 PM PDT 24
Finished Jun 13 01:47:26 PM PDT 24
Peak memory 207152 kb
Host smart-ca29a7e1-0229-44d3-9340-f270a0f01ba2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281771609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.4281771609
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.914548401
Short name T1018
Test name
Test status
Simulation time 48027511 ps
CPU time 1.63 seconds
Started Jun 13 01:47:23 PM PDT 24
Finished Jun 13 01:47:26 PM PDT 24
Peak memory 215480 kb
Host smart-e62659c5-3674-42a4-9761-078fac8fdde7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914548401 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.914548401
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1777630859
Short name T1065
Test name
Test status
Simulation time 57446502 ps
CPU time 2.09 seconds
Started Jun 13 01:47:22 PM PDT 24
Finished Jun 13 01:47:25 PM PDT 24
Peak memory 215328 kb
Host smart-72ac8b39-394b-4760-b700-56686c50f0de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777630859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
777630859
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.476120492
Short name T1049
Test name
Test status
Simulation time 38713517 ps
CPU time 0.71 seconds
Started Jun 13 01:47:17 PM PDT 24
Finished Jun 13 01:47:18 PM PDT 24
Peak memory 203932 kb
Host smart-69833b57-9d9a-49dd-a40a-374dd1d2f804
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476120492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.476120492
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.549025774
Short name T1023
Test name
Test status
Simulation time 509811972 ps
CPU time 1.68 seconds
Started Jun 13 01:47:19 PM PDT 24
Finished Jun 13 01:47:21 PM PDT 24
Peak memory 215440 kb
Host smart-145e7679-31b6-490c-9b5d-23fe909a6a1a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549025774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.549025774
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4045903881
Short name T1041
Test name
Test status
Simulation time 63426628 ps
CPU time 0.66 seconds
Started Jun 13 01:47:26 PM PDT 24
Finished Jun 13 01:47:27 PM PDT 24
Peak memory 203800 kb
Host smart-9dcd7ae5-3e45-4a25-91d7-bf03509f8087
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045903881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.4045903881
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.201751395
Short name T1024
Test name
Test status
Simulation time 60977944 ps
CPU time 3.73 seconds
Started Jun 13 01:47:23 PM PDT 24
Finished Jun 13 01:47:28 PM PDT 24
Peak memory 215336 kb
Host smart-67b0a151-20e1-4c7b-ac93-ab5f886f6b17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201751395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.201751395
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3514091106
Short name T111
Test name
Test status
Simulation time 39013495 ps
CPU time 2.53 seconds
Started Jun 13 01:47:18 PM PDT 24
Finished Jun 13 01:47:21 PM PDT 24
Peak memory 215536 kb
Host smart-18ba66ff-be06-4b11-93e7-f5394b21b2df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514091106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
514091106
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.465369443
Short name T101
Test name
Test status
Simulation time 844810055 ps
CPU time 22.52 seconds
Started Jun 13 01:47:20 PM PDT 24
Finished Jun 13 01:47:44 PM PDT 24
Peak memory 215464 kb
Host smart-76aeeaaf-4b78-4008-b739-08dd11340226
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465369443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.465369443
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.4240054415
Short name T1034
Test name
Test status
Simulation time 51974235 ps
CPU time 0.72 seconds
Started Jun 13 01:47:54 PM PDT 24
Finished Jun 13 01:47:57 PM PDT 24
Peak memory 203904 kb
Host smart-213f69bd-a07c-4b9e-8cfb-d439e55bb884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240054415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
4240054415
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2629237483
Short name T980
Test name
Test status
Simulation time 45207247 ps
CPU time 0.77 seconds
Started Jun 13 01:47:51 PM PDT 24
Finished Jun 13 01:47:53 PM PDT 24
Peak memory 203924 kb
Host smart-3ebe836c-ff3e-435e-8079-64c8668d1074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629237483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2629237483
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3068929751
Short name T1052
Test name
Test status
Simulation time 12537488 ps
CPU time 0.72 seconds
Started Jun 13 01:47:51 PM PDT 24
Finished Jun 13 01:47:54 PM PDT 24
Peak memory 203736 kb
Host smart-f69ef083-9e16-466d-83ec-14196399cdd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068929751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3068929751
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2901405988
Short name T1040
Test name
Test status
Simulation time 37936123 ps
CPU time 0.75 seconds
Started Jun 13 01:47:51 PM PDT 24
Finished Jun 13 01:47:54 PM PDT 24
Peak memory 203968 kb
Host smart-299d6c4d-b8f1-43be-a2f2-4db3f965e383
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901405988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2901405988
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1382908594
Short name T971
Test name
Test status
Simulation time 14229093 ps
CPU time 0.72 seconds
Started Jun 13 01:47:53 PM PDT 24
Finished Jun 13 01:47:56 PM PDT 24
Peak memory 204212 kb
Host smart-7d2b08db-eb4c-46ea-b77e-60036c70333e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382908594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1382908594
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2387839573
Short name T1039
Test name
Test status
Simulation time 14305760 ps
CPU time 0.76 seconds
Started Jun 13 01:47:54 PM PDT 24
Finished Jun 13 01:47:56 PM PDT 24
Peak memory 204204 kb
Host smart-a301a898-9165-4a89-bd4f-8a7ee9c40d9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387839573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2387839573
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3930421274
Short name T1056
Test name
Test status
Simulation time 12357633 ps
CPU time 0.82 seconds
Started Jun 13 01:47:52 PM PDT 24
Finished Jun 13 01:47:54 PM PDT 24
Peak memory 203976 kb
Host smart-fba6ef38-5f38-4893-afdf-adfa570b80c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930421274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3930421274
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.786758475
Short name T990
Test name
Test status
Simulation time 12727780 ps
CPU time 0.69 seconds
Started Jun 13 01:47:51 PM PDT 24
Finished Jun 13 01:47:53 PM PDT 24
Peak memory 203896 kb
Host smart-f5402234-cdfd-4d30-848a-046e25bff5da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786758475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.786758475
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4215322557
Short name T957
Test name
Test status
Simulation time 76547544 ps
CPU time 0.75 seconds
Started Jun 13 01:47:52 PM PDT 24
Finished Jun 13 01:47:54 PM PDT 24
Peak memory 203900 kb
Host smart-1596f1ab-5913-4ba0-ad2e-d50d9e2055cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215322557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
4215322557
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3603353970
Short name T974
Test name
Test status
Simulation time 30989117 ps
CPU time 0.72 seconds
Started Jun 13 01:47:53 PM PDT 24
Finished Jun 13 01:47:56 PM PDT 24
Peak memory 203896 kb
Host smart-c3ae394e-483d-4832-97c8-73fa83cf7140
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603353970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3603353970
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2095173785
Short name T127
Test name
Test status
Simulation time 13444662551 ps
CPU time 15.28 seconds
Started Jun 13 01:47:23 PM PDT 24
Finished Jun 13 01:47:39 PM PDT 24
Peak memory 215412 kb
Host smart-5a03b39e-fbd8-4588-aa5b-0cfe41a8ba5c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095173785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2095173785
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1972775642
Short name T1060
Test name
Test status
Simulation time 2171690519 ps
CPU time 37.62 seconds
Started Jun 13 01:47:23 PM PDT 24
Finished Jun 13 01:48:01 PM PDT 24
Peak memory 215452 kb
Host smart-101c06f8-402a-461f-89dc-527c562c882d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972775642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1972775642
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.304877573
Short name T1078
Test name
Test status
Simulation time 37356146 ps
CPU time 1.19 seconds
Started Jun 13 01:47:24 PM PDT 24
Finished Jun 13 01:47:26 PM PDT 24
Peak memory 207052 kb
Host smart-f758b68c-d7b2-4fa1-84b8-fa2ad7334d77
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304877573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.304877573
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3250094572
Short name T1009
Test name
Test status
Simulation time 175901824 ps
CPU time 1.63 seconds
Started Jun 13 01:47:22 PM PDT 24
Finished Jun 13 01:47:24 PM PDT 24
Peak memory 215512 kb
Host smart-c708497b-49b0-47e7-8a83-99c5141ac34d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250094572 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3250094572
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3937372474
Short name T1072
Test name
Test status
Simulation time 458625750 ps
CPU time 2.82 seconds
Started Jun 13 01:47:24 PM PDT 24
Finished Jun 13 01:47:28 PM PDT 24
Peak memory 215296 kb
Host smart-6fb6b5c1-3ffb-42bc-9756-498dd3638eac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937372474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
937372474
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2657805546
Short name T963
Test name
Test status
Simulation time 53888861 ps
CPU time 0.75 seconds
Started Jun 13 01:47:23 PM PDT 24
Finished Jun 13 01:47:24 PM PDT 24
Peak memory 204172 kb
Host smart-d7fb1362-71f1-4e2b-a626-b0b315622294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657805546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
657805546
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2409437747
Short name T1073
Test name
Test status
Simulation time 96652607 ps
CPU time 1.96 seconds
Started Jun 13 01:47:21 PM PDT 24
Finished Jun 13 01:47:24 PM PDT 24
Peak memory 215416 kb
Host smart-93a51fa1-d176-49de-9eae-7bce61f3e8aa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409437747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2409437747
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1464613920
Short name T1043
Test name
Test status
Simulation time 127126143 ps
CPU time 0.66 seconds
Started Jun 13 01:47:23 PM PDT 24
Finished Jun 13 01:47:25 PM PDT 24
Peak memory 203792 kb
Host smart-a5dc81dc-2597-4d23-8d3c-e94f372d29d9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464613920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1464613920
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.797983561
Short name T1030
Test name
Test status
Simulation time 194888083 ps
CPU time 4.2 seconds
Started Jun 13 01:47:23 PM PDT 24
Finished Jun 13 01:47:27 PM PDT 24
Peak memory 215400 kb
Host smart-cba37925-e84b-471e-ba0d-3c575b837cc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797983561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.797983561
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.490005781
Short name T1033
Test name
Test status
Simulation time 63638121 ps
CPU time 4.36 seconds
Started Jun 13 01:47:23 PM PDT 24
Finished Jun 13 01:47:29 PM PDT 24
Peak memory 215604 kb
Host smart-80a64941-1724-47a3-b7d9-ce02ccadccb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490005781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.490005781
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.235547880
Short name T150
Test name
Test status
Simulation time 1282542756 ps
CPU time 7.52 seconds
Started Jun 13 01:47:24 PM PDT 24
Finished Jun 13 01:47:32 PM PDT 24
Peak memory 215556 kb
Host smart-7aa2b744-c893-46d6-8f42-88cf890184ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235547880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.235547880
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1504346524
Short name T1050
Test name
Test status
Simulation time 40569978 ps
CPU time 0.73 seconds
Started Jun 13 01:47:54 PM PDT 24
Finished Jun 13 01:47:57 PM PDT 24
Peak memory 203928 kb
Host smart-a25a91a2-5fa7-42d4-a2a4-eb3b0cef7083
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504346524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1504346524
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2832642141
Short name T1045
Test name
Test status
Simulation time 15460573 ps
CPU time 0.73 seconds
Started Jun 13 01:47:51 PM PDT 24
Finished Jun 13 01:47:52 PM PDT 24
Peak memory 204204 kb
Host smart-c979bbc8-4ff8-48f8-908f-7e381afb171e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832642141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2832642141
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.465154915
Short name T1021
Test name
Test status
Simulation time 29736264 ps
CPU time 0.72 seconds
Started Jun 13 01:47:52 PM PDT 24
Finished Jun 13 01:47:54 PM PDT 24
Peak memory 203908 kb
Host smart-c4970afb-3be3-408d-b159-398769f3ada8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465154915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.465154915
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2804721900
Short name T976
Test name
Test status
Simulation time 32234754 ps
CPU time 0.79 seconds
Started Jun 13 01:47:53 PM PDT 24
Finished Jun 13 01:47:56 PM PDT 24
Peak memory 204196 kb
Host smart-ff3c8823-d276-4b44-8683-0d181346a5dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804721900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2804721900
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1977202227
Short name T1010
Test name
Test status
Simulation time 65061366 ps
CPU time 0.7 seconds
Started Jun 13 01:47:55 PM PDT 24
Finished Jun 13 01:47:57 PM PDT 24
Peak memory 204204 kb
Host smart-fee49b9e-8769-49fa-91dd-5545e75851c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977202227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1977202227
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.47921908
Short name T986
Test name
Test status
Simulation time 12148987 ps
CPU time 0.78 seconds
Started Jun 13 01:47:54 PM PDT 24
Finished Jun 13 01:47:56 PM PDT 24
Peak memory 204004 kb
Host smart-3550615d-8397-4605-9659-24681da9d676
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47921908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.47921908
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1302433418
Short name T1001
Test name
Test status
Simulation time 43955901 ps
CPU time 0.67 seconds
Started Jun 13 01:47:50 PM PDT 24
Finished Jun 13 01:47:51 PM PDT 24
Peak memory 203844 kb
Host smart-ab15f6db-bbb4-44ee-99d3-5afdb563d159
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302433418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1302433418
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2389649061
Short name T981
Test name
Test status
Simulation time 17334072 ps
CPU time 0.77 seconds
Started Jun 13 01:47:54 PM PDT 24
Finished Jun 13 01:47:56 PM PDT 24
Peak memory 204220 kb
Host smart-5c0a8691-3d8e-4d27-8f53-1a963897fdd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389649061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2389649061
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.444146030
Short name T1007
Test name
Test status
Simulation time 10694683 ps
CPU time 0.72 seconds
Started Jun 13 01:47:52 PM PDT 24
Finished Jun 13 01:47:54 PM PDT 24
Peak memory 203904 kb
Host smart-4962b88e-c72c-4a81-aac7-cf49d13e19bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444146030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.444146030
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2212906946
Short name T961
Test name
Test status
Simulation time 30619763 ps
CPU time 0.74 seconds
Started Jun 13 01:48:00 PM PDT 24
Finished Jun 13 01:48:01 PM PDT 24
Peak memory 203904 kb
Host smart-b8d2b7ec-b41b-4a02-87be-c0e9cce252a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212906946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2212906946
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2893727370
Short name T116
Test name
Test status
Simulation time 1829321582 ps
CPU time 8.24 seconds
Started Jun 13 01:47:29 PM PDT 24
Finished Jun 13 01:47:38 PM PDT 24
Peak memory 207104 kb
Host smart-52b51f37-f59d-4275-87fe-6e53989e448f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893727370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2893727370
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1525137053
Short name T1044
Test name
Test status
Simulation time 2445448204 ps
CPU time 37.27 seconds
Started Jun 13 01:47:31 PM PDT 24
Finished Jun 13 01:48:09 PM PDT 24
Peak memory 215356 kb
Host smart-ab9e8cbd-eebb-4065-87e4-798ecf16e897
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525137053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1525137053
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2530035640
Short name T90
Test name
Test status
Simulation time 22726563 ps
CPU time 1.01 seconds
Started Jun 13 01:47:30 PM PDT 24
Finished Jun 13 01:47:32 PM PDT 24
Peak memory 206972 kb
Host smart-155afce4-509c-4cf1-804e-67b0a43208e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530035640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2530035640
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3275110994
Short name T983
Test name
Test status
Simulation time 107467565 ps
CPU time 3.71 seconds
Started Jun 13 01:47:30 PM PDT 24
Finished Jun 13 01:47:34 PM PDT 24
Peak memory 216524 kb
Host smart-fc548ee5-9bdd-42f1-ac3b-eaac02274dc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275110994 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3275110994
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2425166131
Short name T124
Test name
Test status
Simulation time 225135878 ps
CPU time 2.82 seconds
Started Jun 13 01:47:30 PM PDT 24
Finished Jun 13 01:47:34 PM PDT 24
Peak memory 215308 kb
Host smart-8f9d8d94-2fff-4ab6-9907-359640567e1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425166131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
425166131
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3733402702
Short name T1067
Test name
Test status
Simulation time 22019292 ps
CPU time 0.72 seconds
Started Jun 13 01:47:32 PM PDT 24
Finished Jun 13 01:47:33 PM PDT 24
Peak memory 203948 kb
Host smart-3d4e3f0e-c624-45e8-853b-e7af27ce396a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733402702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
733402702
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.404580908
Short name T1036
Test name
Test status
Simulation time 25369654 ps
CPU time 2.09 seconds
Started Jun 13 01:47:31 PM PDT 24
Finished Jun 13 01:47:34 PM PDT 24
Peak memory 215460 kb
Host smart-d16fa703-fadc-4883-b2ac-7d6ccccd017e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404580908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.404580908
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2877496274
Short name T1066
Test name
Test status
Simulation time 33046435 ps
CPU time 0.7 seconds
Started Jun 13 01:47:30 PM PDT 24
Finished Jun 13 01:47:32 PM PDT 24
Peak memory 203796 kb
Host smart-300726d7-9e3b-4e8d-882f-caf7c53cd88d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877496274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2877496274
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3023981939
Short name T137
Test name
Test status
Simulation time 240605062 ps
CPU time 4.09 seconds
Started Jun 13 01:47:34 PM PDT 24
Finished Jun 13 01:47:39 PM PDT 24
Peak memory 215404 kb
Host smart-5a66224a-2f09-443b-bba0-de07de6cc08d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023981939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3023981939
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2247806229
Short name T106
Test name
Test status
Simulation time 1811556963 ps
CPU time 4.43 seconds
Started Jun 13 01:47:23 PM PDT 24
Finished Jun 13 01:47:28 PM PDT 24
Peak memory 215524 kb
Host smart-515fec33-4db7-43ce-9343-b5699797bdfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247806229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
247806229
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.47717425
Short name T242
Test name
Test status
Simulation time 11009579889 ps
CPU time 24.04 seconds
Started Jun 13 01:47:24 PM PDT 24
Finished Jun 13 01:47:49 PM PDT 24
Peak memory 216172 kb
Host smart-cb5ddfd3-1c38-4925-8c81-66d0704befd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47717425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_t
l_intg_err.47717425
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2401106623
Short name T973
Test name
Test status
Simulation time 46226690 ps
CPU time 0.74 seconds
Started Jun 13 01:48:01 PM PDT 24
Finished Jun 13 01:48:02 PM PDT 24
Peak memory 203912 kb
Host smart-5fc074f6-f20d-4707-a000-974e5dfe50d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401106623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2401106623
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.4132030596
Short name T997
Test name
Test status
Simulation time 12035822 ps
CPU time 0.74 seconds
Started Jun 13 01:48:01 PM PDT 24
Finished Jun 13 01:48:02 PM PDT 24
Peak memory 203916 kb
Host smart-eb1c2718-1eb4-48b8-97c1-3d26fb2a369b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132030596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
4132030596
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2958033457
Short name T1075
Test name
Test status
Simulation time 40561266 ps
CPU time 0.71 seconds
Started Jun 13 01:48:00 PM PDT 24
Finished Jun 13 01:48:01 PM PDT 24
Peak memory 203900 kb
Host smart-30ff4d78-5b28-40e9-b366-2cd21aa2afcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958033457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2958033457
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.857939307
Short name T967
Test name
Test status
Simulation time 39602614 ps
CPU time 0.8 seconds
Started Jun 13 01:48:02 PM PDT 24
Finished Jun 13 01:48:03 PM PDT 24
Peak memory 203908 kb
Host smart-85cfb605-0783-4d07-8603-884f678cd53f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857939307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.857939307
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.4250411878
Short name T1004
Test name
Test status
Simulation time 43391081 ps
CPU time 0.75 seconds
Started Jun 13 01:48:02 PM PDT 24
Finished Jun 13 01:48:04 PM PDT 24
Peak memory 204204 kb
Host smart-41fcb00b-793b-4d43-9d8e-53985e565029
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250411878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
4250411878
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2833757221
Short name T969
Test name
Test status
Simulation time 29548379 ps
CPU time 0.77 seconds
Started Jun 13 01:48:02 PM PDT 24
Finished Jun 13 01:48:04 PM PDT 24
Peak memory 204200 kb
Host smart-cc08f691-cd8c-4845-8fab-c17e8ba06d23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833757221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2833757221
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4097706266
Short name T972
Test name
Test status
Simulation time 47145362 ps
CPU time 0.76 seconds
Started Jun 13 01:48:01 PM PDT 24
Finished Jun 13 01:48:02 PM PDT 24
Peak memory 203944 kb
Host smart-b67eb46a-3990-402d-9121-39445d49f062
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097706266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
4097706266
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2881847923
Short name T987
Test name
Test status
Simulation time 12930208 ps
CPU time 0.79 seconds
Started Jun 13 01:48:02 PM PDT 24
Finished Jun 13 01:48:03 PM PDT 24
Peak memory 203948 kb
Host smart-3ab3cf7b-5175-4fe8-8f02-10e6c12be1be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881847923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2881847923
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1551634528
Short name T991
Test name
Test status
Simulation time 53656609 ps
CPU time 0.73 seconds
Started Jun 13 01:48:00 PM PDT 24
Finished Jun 13 01:48:01 PM PDT 24
Peak memory 204176 kb
Host smart-182e77ff-08ee-42ea-a5da-e23cc51d9c32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551634528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1551634528
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2531404883
Short name T1002
Test name
Test status
Simulation time 42194552 ps
CPU time 0.77 seconds
Started Jun 13 01:47:59 PM PDT 24
Finished Jun 13 01:48:00 PM PDT 24
Peak memory 203924 kb
Host smart-6c86d1c2-c960-4b19-bd4c-5ffd2dd8a0cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531404883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2531404883
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1827193231
Short name T968
Test name
Test status
Simulation time 78710736 ps
CPU time 2.82 seconds
Started Jun 13 01:47:30 PM PDT 24
Finished Jun 13 01:47:33 PM PDT 24
Peak memory 217832 kb
Host smart-a79ae8cf-13ba-4b3a-a8cb-3c04e486f18c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827193231 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1827193231
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.181133960
Short name T118
Test name
Test status
Simulation time 39609410 ps
CPU time 2.59 seconds
Started Jun 13 01:47:33 PM PDT 24
Finished Jun 13 01:47:36 PM PDT 24
Peak memory 215372 kb
Host smart-ada80027-1ea6-4415-81e6-04e9c2bae28a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181133960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.181133960
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.142416203
Short name T954
Test name
Test status
Simulation time 43147673 ps
CPU time 0.74 seconds
Started Jun 13 01:47:31 PM PDT 24
Finished Jun 13 01:47:33 PM PDT 24
Peak memory 204244 kb
Host smart-b571853e-97ff-4398-b956-6bb7f5c92c91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142416203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.142416203
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1862753700
Short name T149
Test name
Test status
Simulation time 198629651 ps
CPU time 2.09 seconds
Started Jun 13 01:47:33 PM PDT 24
Finished Jun 13 01:47:36 PM PDT 24
Peak memory 215404 kb
Host smart-4745eee0-c7b2-4a7b-b0a0-d58f28c81a45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862753700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1862753700
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1955966626
Short name T103
Test name
Test status
Simulation time 535536801 ps
CPU time 3.13 seconds
Started Jun 13 01:47:34 PM PDT 24
Finished Jun 13 01:47:38 PM PDT 24
Peak memory 215724 kb
Host smart-d45aa19b-4df0-413c-a74c-ae02651d1c16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955966626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
955966626
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2058204482
Short name T146
Test name
Test status
Simulation time 3540035732 ps
CPU time 17.42 seconds
Started Jun 13 01:47:31 PM PDT 24
Finished Jun 13 01:47:49 PM PDT 24
Peak memory 216860 kb
Host smart-cba6fd03-8464-4221-9a79-1c847dbedbe0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058204482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2058204482
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.874756479
Short name T1014
Test name
Test status
Simulation time 168564408 ps
CPU time 3.6 seconds
Started Jun 13 01:47:37 PM PDT 24
Finished Jun 13 01:47:42 PM PDT 24
Peak memory 215900 kb
Host smart-4a5e0893-69a4-485d-ae47-1c29440f7665
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874756479 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.874756479
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2038512567
Short name T1037
Test name
Test status
Simulation time 359006592 ps
CPU time 2.92 seconds
Started Jun 13 01:47:36 PM PDT 24
Finished Jun 13 01:47:40 PM PDT 24
Peak memory 215408 kb
Host smart-fabb78b9-ac11-4758-9898-2a659ca51f5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038512567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
038512567
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.199125581
Short name T1011
Test name
Test status
Simulation time 86364077 ps
CPU time 0.76 seconds
Started Jun 13 01:47:38 PM PDT 24
Finished Jun 13 01:47:42 PM PDT 24
Peak memory 204256 kb
Host smart-5b7820d3-e771-41fe-b99a-2b836194d962
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199125581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.199125581
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1714015061
Short name T988
Test name
Test status
Simulation time 27520774 ps
CPU time 1.8 seconds
Started Jun 13 01:47:39 PM PDT 24
Finished Jun 13 01:47:43 PM PDT 24
Peak memory 215424 kb
Host smart-957b4dc1-5464-4284-911d-bc40a68ef0d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714015061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1714015061
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.82799163
Short name T107
Test name
Test status
Simulation time 328910042 ps
CPU time 3.72 seconds
Started Jun 13 01:47:31 PM PDT 24
Finished Jun 13 01:47:36 PM PDT 24
Peak memory 215676 kb
Host smart-9f7a799a-6614-4c0c-a51a-b5d0921b9518
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82799163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.82799163
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.798923575
Short name T1012
Test name
Test status
Simulation time 295016565 ps
CPU time 19.86 seconds
Started Jun 13 01:47:31 PM PDT 24
Finished Jun 13 01:47:52 PM PDT 24
Peak memory 215408 kb
Host smart-3144671f-2dd8-4631-aa8b-ea92cd2cf824
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798923575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.798923575
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3226240430
Short name T964
Test name
Test status
Simulation time 613209563 ps
CPU time 1.73 seconds
Started Jun 13 01:47:37 PM PDT 24
Finished Jun 13 01:47:41 PM PDT 24
Peak memory 216616 kb
Host smart-b04e421d-ec02-4c72-a3ff-09fff9ecba27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226240430 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3226240430
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3373447522
Short name T1006
Test name
Test status
Simulation time 171294419 ps
CPU time 2.54 seconds
Started Jun 13 01:47:37 PM PDT 24
Finished Jun 13 01:47:42 PM PDT 24
Peak memory 215300 kb
Host smart-ca81c797-2203-43b9-8d6f-c62fcf4036f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373447522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
373447522
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1561640872
Short name T959
Test name
Test status
Simulation time 11554164 ps
CPU time 0.77 seconds
Started Jun 13 01:47:36 PM PDT 24
Finished Jun 13 01:47:39 PM PDT 24
Peak memory 203952 kb
Host smart-34bf227c-482e-440b-bc88-442e4c5ab856
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561640872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
561640872
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3255829202
Short name T1015
Test name
Test status
Simulation time 149847541 ps
CPU time 1.81 seconds
Started Jun 13 01:47:36 PM PDT 24
Finished Jun 13 01:47:39 PM PDT 24
Peak memory 215316 kb
Host smart-c5d109a9-0cd0-47d2-b930-cd242bc5d1ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255829202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3255829202
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2353640215
Short name T1013
Test name
Test status
Simulation time 64261696 ps
CPU time 1.88 seconds
Started Jun 13 01:47:36 PM PDT 24
Finished Jun 13 01:47:38 PM PDT 24
Peak memory 215700 kb
Host smart-759f0fe9-a151-43f9-bfe9-3d8409d8e3d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353640215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
353640215
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4169512582
Short name T1071
Test name
Test status
Simulation time 4664721166 ps
CPU time 8.11 seconds
Started Jun 13 01:47:38 PM PDT 24
Finished Jun 13 01:47:49 PM PDT 24
Peak memory 215624 kb
Host smart-5dc1d9c1-8fb1-4f68-bf22-4499a4736b2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169512582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.4169512582
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3205216696
Short name T68
Test name
Test status
Simulation time 38869169 ps
CPU time 2.48 seconds
Started Jun 13 01:47:38 PM PDT 24
Finished Jun 13 01:47:43 PM PDT 24
Peak memory 217016 kb
Host smart-fc43d326-c4f8-47ff-9cf1-50958f434ee7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205216696 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3205216696
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.875650458
Short name T122
Test name
Test status
Simulation time 29890068 ps
CPU time 1.79 seconds
Started Jun 13 01:47:40 PM PDT 24
Finished Jun 13 01:47:44 PM PDT 24
Peak memory 207112 kb
Host smart-3564769b-005d-479e-b6eb-5d2869590e04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875650458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.875650458
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3678692844
Short name T998
Test name
Test status
Simulation time 14807061 ps
CPU time 0.75 seconds
Started Jun 13 01:47:36 PM PDT 24
Finished Jun 13 01:47:38 PM PDT 24
Peak memory 204180 kb
Host smart-efba2e66-2663-4a66-b854-2fc2208c5bc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678692844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
678692844
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.378068975
Short name T1061
Test name
Test status
Simulation time 60099196 ps
CPU time 3.84 seconds
Started Jun 13 01:47:36 PM PDT 24
Finished Jun 13 01:47:41 PM PDT 24
Peak memory 215260 kb
Host smart-2226922f-06b0-4ded-ba2a-d042d0f4283c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378068975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.378068975
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2245397657
Short name T109
Test name
Test status
Simulation time 157633237 ps
CPU time 3.65 seconds
Started Jun 13 01:47:38 PM PDT 24
Finished Jun 13 01:47:44 PM PDT 24
Peak memory 216584 kb
Host smart-8c57ea93-26f9-499e-b265-75b6bbf8a9cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245397657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
245397657
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1121864939
Short name T1076
Test name
Test status
Simulation time 4484040357 ps
CPU time 21.7 seconds
Started Jun 13 01:47:39 PM PDT 24
Finished Jun 13 01:48:03 PM PDT 24
Peak memory 223424 kb
Host smart-dff70f20-b506-46dc-8f5c-92e567fa6364
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121864939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1121864939
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.121225801
Short name T989
Test name
Test status
Simulation time 99923691 ps
CPU time 1.88 seconds
Started Jun 13 01:47:39 PM PDT 24
Finished Jun 13 01:47:43 PM PDT 24
Peak memory 216500 kb
Host smart-22d291fa-357d-4c33-b2ac-9a1676689940
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121225801 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.121225801
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3403171208
Short name T1057
Test name
Test status
Simulation time 153769867 ps
CPU time 2.63 seconds
Started Jun 13 01:47:39 PM PDT 24
Finished Jun 13 01:47:44 PM PDT 24
Peak memory 215332 kb
Host smart-bf2b872f-5dfa-4546-bd34-a63be14faf6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403171208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
403171208
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2197355226
Short name T966
Test name
Test status
Simulation time 100720959 ps
CPU time 0.76 seconds
Started Jun 13 01:47:38 PM PDT 24
Finished Jun 13 01:47:42 PM PDT 24
Peak memory 203960 kb
Host smart-1346c8b4-73bc-479d-9637-dadbb947ed75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197355226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
197355226
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3902740782
Short name T1069
Test name
Test status
Simulation time 81687571 ps
CPU time 2.84 seconds
Started Jun 13 01:47:36 PM PDT 24
Finished Jun 13 01:47:40 PM PDT 24
Peak memory 215324 kb
Host smart-64319b04-bcce-4cf3-9c08-b6fd4fb4451d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902740782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3902740782
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2347486388
Short name T1055
Test name
Test status
Simulation time 69610814 ps
CPU time 1.5 seconds
Started Jun 13 01:47:38 PM PDT 24
Finished Jun 13 01:47:42 PM PDT 24
Peak memory 215796 kb
Host smart-7a6dd502-1f02-47d8-8ef4-84f2a34b44c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347486388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
347486388
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.120994441
Short name T244
Test name
Test status
Simulation time 4128278080 ps
CPU time 21.57 seconds
Started Jun 13 01:47:35 PM PDT 24
Finished Jun 13 01:47:58 PM PDT 24
Peak memory 215604 kb
Host smart-2ca2cf19-4fd2-43c0-961a-474d9cc34387
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120994441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.120994441
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3479606923
Short name T854
Test name
Test status
Simulation time 21545130 ps
CPU time 0.72 seconds
Started Jun 13 12:32:46 PM PDT 24
Finished Jun 13 12:32:48 PM PDT 24
Peak memory 205996 kb
Host smart-ed24559d-3a32-4ab3-be8e-a314c8823b1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479606923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
479606923
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2775936781
Short name T771
Test name
Test status
Simulation time 284467393 ps
CPU time 2.53 seconds
Started Jun 13 12:32:00 PM PDT 24
Finished Jun 13 12:32:04 PM PDT 24
Peak memory 233284 kb
Host smart-ac94eba6-0f70-4598-bc50-df533677f6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775936781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2775936781
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.4266131026
Short name T572
Test name
Test status
Simulation time 61629621 ps
CPU time 0.78 seconds
Started Jun 13 12:32:25 PM PDT 24
Finished Jun 13 12:32:28 PM PDT 24
Peak memory 207092 kb
Host smart-0627639f-247f-4dac-9228-5adc88f0bd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266131026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.4266131026
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.732769411
Short name T391
Test name
Test status
Simulation time 5453929165 ps
CPU time 70.69 seconds
Started Jun 13 12:32:14 PM PDT 24
Finished Jun 13 12:33:27 PM PDT 24
Peak memory 256192 kb
Host smart-6dce69c6-4baf-4003-82fa-d2b68c1989a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732769411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.732769411
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.412561789
Short name T835
Test name
Test status
Simulation time 45858676421 ps
CPU time 126.02 seconds
Started Jun 13 12:32:19 PM PDT 24
Finished Jun 13 12:34:28 PM PDT 24
Peak memory 249760 kb
Host smart-7bfb1a1f-586b-41b4-8ba0-2c2d9a34ae00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412561789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
412561789
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3427965946
Short name T938
Test name
Test status
Simulation time 6154501814 ps
CPU time 15.4 seconds
Started Jun 13 12:32:40 PM PDT 24
Finished Jun 13 12:32:58 PM PDT 24
Peak memory 233364 kb
Host smart-e7068940-1d7c-42a4-91aa-cfa81fee3133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427965946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3427965946
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1242724585
Short name T562
Test name
Test status
Simulation time 682181192 ps
CPU time 2.6 seconds
Started Jun 13 12:32:09 PM PDT 24
Finished Jun 13 12:32:14 PM PDT 24
Peak memory 224112 kb
Host smart-c932e7e7-fab2-4e40-9010-6c47d7ac9fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242724585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1242724585
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2072072545
Short name T656
Test name
Test status
Simulation time 4915973405 ps
CPU time 7.99 seconds
Started Jun 13 12:32:15 PM PDT 24
Finished Jun 13 12:32:25 PM PDT 24
Peak memory 233320 kb
Host smart-cba77b75-2ff5-4121-9a9f-48db70e9e7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072072545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2072072545
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1493501900
Short name T551
Test name
Test status
Simulation time 18189069343 ps
CPU time 13.79 seconds
Started Jun 13 12:32:22 PM PDT 24
Finished Jun 13 12:32:39 PM PDT 24
Peak memory 220980 kb
Host smart-0f2402c8-c39d-416f-91f0-2f7601e678f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1493501900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1493501900
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2334877626
Short name T471
Test name
Test status
Simulation time 17518179628 ps
CPU time 17.13 seconds
Started Jun 13 12:32:17 PM PDT 24
Finished Jun 13 12:32:36 PM PDT 24
Peak memory 216868 kb
Host smart-5d30464e-45f3-4660-a75e-3db39b7d6930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334877626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2334877626
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3294266121
Short name T828
Test name
Test status
Simulation time 38630646379 ps
CPU time 25.48 seconds
Started Jun 13 12:32:20 PM PDT 24
Finished Jun 13 12:32:48 PM PDT 24
Peak memory 216892 kb
Host smart-37ff3bf0-ca3d-4ce9-9cea-a56f63690f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294266121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3294266121
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3530542140
Short name T240
Test name
Test status
Simulation time 82461383 ps
CPU time 4.16 seconds
Started Jun 13 12:32:49 PM PDT 24
Finished Jun 13 12:32:54 PM PDT 24
Peak memory 216860 kb
Host smart-88b5ce4a-9481-4b89-bd5e-6d7a2b2f0305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530542140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3530542140
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1423843405
Short name T639
Test name
Test status
Simulation time 212725150 ps
CPU time 0.86 seconds
Started Jun 13 12:32:18 PM PDT 24
Finished Jun 13 12:32:21 PM PDT 24
Peak memory 206440 kb
Host smart-a6e81b2f-4ed6-4692-a5ff-2fcd34a52d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423843405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1423843405
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3630558516
Short name T538
Test name
Test status
Simulation time 76086851 ps
CPU time 2.13 seconds
Started Jun 13 12:32:10 PM PDT 24
Finished Jun 13 12:32:15 PM PDT 24
Peak memory 224688 kb
Host smart-382a2f19-8f89-48b4-89aa-f7afccca7934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630558516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3630558516
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1888106904
Short name T431
Test name
Test status
Simulation time 11271285 ps
CPU time 0.72 seconds
Started Jun 13 12:32:43 PM PDT 24
Finished Jun 13 12:32:45 PM PDT 24
Peak memory 205404 kb
Host smart-6e230900-a866-4b1b-832b-7523969edd14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888106904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
888106904
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3156432387
Short name T373
Test name
Test status
Simulation time 341162124 ps
CPU time 3.38 seconds
Started Jun 13 12:32:19 PM PDT 24
Finished Jun 13 12:32:24 PM PDT 24
Peak memory 224992 kb
Host smart-b06b41ff-8c90-48a7-bffc-2ff3e332630e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156432387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3156432387
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.499137767
Short name T846
Test name
Test status
Simulation time 28503383 ps
CPU time 0.81 seconds
Started Jun 13 12:32:05 PM PDT 24
Finished Jun 13 12:32:07 PM PDT 24
Peak memory 206420 kb
Host smart-21571916-dc4e-430d-9976-a089b8c62ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499137767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.499137767
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3560680337
Short name T56
Test name
Test status
Simulation time 143127035887 ps
CPU time 138.7 seconds
Started Jun 13 12:32:39 PM PDT 24
Finished Jun 13 12:35:00 PM PDT 24
Peak memory 257932 kb
Host smart-7bd5637d-3c1b-4809-94ce-d2c36e578066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560680337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3560680337
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1704354228
Short name T697
Test name
Test status
Simulation time 95707144 ps
CPU time 2.6 seconds
Started Jun 13 12:32:42 PM PDT 24
Finished Jun 13 12:32:46 PM PDT 24
Peak memory 233276 kb
Host smart-42d8a721-e4ec-4fad-a719-f5fa3d06eb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704354228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1704354228
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.4117596922
Short name T190
Test name
Test status
Simulation time 10413198438 ps
CPU time 40.09 seconds
Started Jun 13 12:32:21 PM PDT 24
Finished Jun 13 12:33:04 PM PDT 24
Peak memory 230084 kb
Host smart-5e1626eb-5d9a-43a9-be6d-02dc21a47124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117596922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.4117596922
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1490811375
Short name T766
Test name
Test status
Simulation time 103929144 ps
CPU time 2.06 seconds
Started Jun 13 12:32:16 PM PDT 24
Finished Jun 13 12:32:20 PM PDT 24
Peak memory 223416 kb
Host smart-909dd6c7-c68e-443b-b0e4-69bce0bc1bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490811375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1490811375
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.928319253
Short name T455
Test name
Test status
Simulation time 721378335 ps
CPU time 3.9 seconds
Started Jun 13 12:32:09 PM PDT 24
Finished Jun 13 12:32:16 PM PDT 24
Peak memory 225036 kb
Host smart-787fa136-244f-4fc1-9348-4015f4aa3cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928319253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.928319253
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2801801362
Short name T855
Test name
Test status
Simulation time 160999535 ps
CPU time 3.91 seconds
Started Jun 13 12:32:22 PM PDT 24
Finished Jun 13 12:32:29 PM PDT 24
Peak memory 223128 kb
Host smart-45c6a205-4d26-4789-8159-1d684e2b84de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2801801362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2801801362
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1444153667
Short name T70
Test name
Test status
Simulation time 77741304 ps
CPU time 1.15 seconds
Started Jun 13 12:32:19 PM PDT 24
Finished Jun 13 12:32:23 PM PDT 24
Peak memory 236412 kb
Host smart-902d19bb-030c-41d8-8b2c-81b6e8399cbb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444153667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1444153667
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3170023968
Short name T464
Test name
Test status
Simulation time 663901527 ps
CPU time 7.61 seconds
Started Jun 13 12:32:23 PM PDT 24
Finished Jun 13 12:32:33 PM PDT 24
Peak memory 216976 kb
Host smart-1f20a188-6b7a-4075-b60d-9ec9e1e61de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170023968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3170023968
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.764233515
Short name T630
Test name
Test status
Simulation time 273711045 ps
CPU time 2.17 seconds
Started Jun 13 12:32:27 PM PDT 24
Finished Jun 13 12:32:32 PM PDT 24
Peak memory 216612 kb
Host smart-68c3ae3a-8364-46f0-920a-ec31a808ef07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764233515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.764233515
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3375061706
Short name T685
Test name
Test status
Simulation time 11444539 ps
CPU time 0.68 seconds
Started Jun 13 12:32:22 PM PDT 24
Finished Jun 13 12:32:25 PM PDT 24
Peak memory 206172 kb
Host smart-4f357648-3e11-4121-8700-89602f657c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375061706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3375061706
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3535654530
Short name T321
Test name
Test status
Simulation time 50305868 ps
CPU time 0.83 seconds
Started Jun 13 12:32:25 PM PDT 24
Finished Jun 13 12:32:28 PM PDT 24
Peak memory 206432 kb
Host smart-82493a52-a2d8-4732-95f9-c36e8376cfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535654530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3535654530
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.541039906
Short name T831
Test name
Test status
Simulation time 1196205413 ps
CPU time 6.92 seconds
Started Jun 13 12:32:09 PM PDT 24
Finished Jun 13 12:32:19 PM PDT 24
Peak memory 249368 kb
Host smart-8f4e2d76-db47-406a-a719-827158a7331f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541039906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.541039906
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3447022270
Short name T417
Test name
Test status
Simulation time 24852059 ps
CPU time 0.76 seconds
Started Jun 13 12:32:24 PM PDT 24
Finished Jun 13 12:32:27 PM PDT 24
Peak memory 205480 kb
Host smart-8f308a41-352a-4eaf-9fb5-2b59322e43ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447022270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3447022270
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1324761394
Short name T853
Test name
Test status
Simulation time 3248333010 ps
CPU time 26.9 seconds
Started Jun 13 12:32:57 PM PDT 24
Finished Jun 13 12:33:25 PM PDT 24
Peak memory 233256 kb
Host smart-77fea749-36ef-49d9-8429-f9ca19e175ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324761394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1324761394
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3367219107
Short name T461
Test name
Test status
Simulation time 69662260 ps
CPU time 0.8 seconds
Started Jun 13 12:32:24 PM PDT 24
Finished Jun 13 12:32:28 PM PDT 24
Peak memory 207480 kb
Host smart-078f62e0-6459-4df2-be0c-2d4254d96945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367219107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3367219107
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1829049123
Short name T518
Test name
Test status
Simulation time 17337826296 ps
CPU time 59.03 seconds
Started Jun 13 12:32:25 PM PDT 24
Finished Jun 13 12:33:26 PM PDT 24
Peak memory 249740 kb
Host smart-37e3a0b6-98c2-4f50-8913-f5144b71b03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829049123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1829049123
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2462823438
Short name T760
Test name
Test status
Simulation time 3715309047 ps
CPU time 11.2 seconds
Started Jun 13 12:32:31 PM PDT 24
Finished Jun 13 12:32:44 PM PDT 24
Peak memory 225160 kb
Host smart-1219c8db-42b9-47ef-a189-2103f4863aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462823438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2462823438
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1811149825
Short name T83
Test name
Test status
Simulation time 33973934 ps
CPU time 2.48 seconds
Started Jun 13 12:32:41 PM PDT 24
Finished Jun 13 12:32:46 PM PDT 24
Peak memory 233092 kb
Host smart-e28477ea-1170-486e-837d-13eaafdf1918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811149825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1811149825
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2177412220
Short name T653
Test name
Test status
Simulation time 5926698286 ps
CPU time 17.99 seconds
Started Jun 13 12:32:31 PM PDT 24
Finished Jun 13 12:32:51 PM PDT 24
Peak memory 225060 kb
Host smart-771a9d9a-fdd5-494a-a443-e01d8f54d9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177412220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2177412220
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.975460421
Short name T542
Test name
Test status
Simulation time 31382598 ps
CPU time 2.07 seconds
Started Jun 13 12:33:15 PM PDT 24
Finished Jun 13 12:33:21 PM PDT 24
Peak memory 223676 kb
Host smart-e4c285f8-ffd6-4b35-9b27-36c06e420caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975460421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.975460421
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3929348525
Short name T262
Test name
Test status
Simulation time 143903359 ps
CPU time 3.21 seconds
Started Jun 13 12:32:37 PM PDT 24
Finished Jun 13 12:32:42 PM PDT 24
Peak memory 233252 kb
Host smart-92e50987-c4ad-4b69-a8d0-3894af22d9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929348525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3929348525
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2740025306
Short name T474
Test name
Test status
Simulation time 749134383 ps
CPU time 10.57 seconds
Started Jun 13 12:32:49 PM PDT 24
Finished Jun 13 12:33:00 PM PDT 24
Peak memory 223188 kb
Host smart-64180e2d-d3e0-42b2-ba5c-1bae257b3bd0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2740025306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2740025306
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3134781664
Short name T526
Test name
Test status
Simulation time 61579509 ps
CPU time 0.89 seconds
Started Jun 13 12:32:43 PM PDT 24
Finished Jun 13 12:32:45 PM PDT 24
Peak memory 207160 kb
Host smart-bec4e71f-6359-415c-8e6e-33c6c2be149a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134781664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3134781664
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2535854448
Short name T939
Test name
Test status
Simulation time 1240000306 ps
CPU time 20.96 seconds
Started Jun 13 12:32:29 PM PDT 24
Finished Jun 13 12:32:51 PM PDT 24
Peak memory 216888 kb
Host smart-0a4da835-59d9-4333-9d23-44bf9a7c894b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535854448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2535854448
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1363250119
Short name T732
Test name
Test status
Simulation time 2354986301 ps
CPU time 10.78 seconds
Started Jun 13 12:32:26 PM PDT 24
Finished Jun 13 12:32:39 PM PDT 24
Peak memory 216932 kb
Host smart-35ae48c4-e358-4556-be41-417e747aee06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363250119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1363250119
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2113415603
Short name T703
Test name
Test status
Simulation time 98252449 ps
CPU time 1.95 seconds
Started Jun 13 12:32:34 PM PDT 24
Finished Jun 13 12:32:38 PM PDT 24
Peak memory 216772 kb
Host smart-217833ab-fde6-44db-9521-a63ba9fc7a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113415603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2113415603
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.763033718
Short name T92
Test name
Test status
Simulation time 43476445 ps
CPU time 0.72 seconds
Started Jun 13 12:32:38 PM PDT 24
Finished Jun 13 12:32:41 PM PDT 24
Peak memory 206520 kb
Host smart-1f303c3b-2c77-4e95-b062-b455db0743c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763033718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.763033718
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.59032014
Short name T613
Test name
Test status
Simulation time 2879695816 ps
CPU time 10.3 seconds
Started Jun 13 12:32:55 PM PDT 24
Finished Jun 13 12:33:07 PM PDT 24
Peak memory 233304 kb
Host smart-39a1d530-d8bf-40e4-92aa-8b8faa9dc1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59032014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.59032014
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3277653375
Short name T368
Test name
Test status
Simulation time 11655343 ps
CPU time 0.71 seconds
Started Jun 13 12:33:07 PM PDT 24
Finished Jun 13 12:33:09 PM PDT 24
Peak memory 205424 kb
Host smart-f6fafbc6-4615-41fb-93c6-04b19b845532
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277653375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3277653375
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.4101232220
Short name T529
Test name
Test status
Simulation time 858547474 ps
CPU time 4.49 seconds
Started Jun 13 12:32:30 PM PDT 24
Finished Jun 13 12:32:37 PM PDT 24
Peak memory 233308 kb
Host smart-42d13987-c6a8-40ae-929e-fec668f67ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101232220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.4101232220
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2067029977
Short name T678
Test name
Test status
Simulation time 16755710 ps
CPU time 0.77 seconds
Started Jun 13 12:32:41 PM PDT 24
Finished Jun 13 12:32:44 PM PDT 24
Peak memory 207160 kb
Host smart-bd2cd359-1c3c-4e4c-b454-50f5e2e2a63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067029977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2067029977
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.849863418
Short name T719
Test name
Test status
Simulation time 43156218162 ps
CPU time 94.76 seconds
Started Jun 13 12:32:44 PM PDT 24
Finished Jun 13 12:34:20 PM PDT 24
Peak memory 238404 kb
Host smart-78f76e5f-34b7-49b0-b855-d7f0536b9202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849863418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.849863418
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2953211132
Short name T309
Test name
Test status
Simulation time 2625388743 ps
CPU time 24.79 seconds
Started Jun 13 12:32:59 PM PDT 24
Finished Jun 13 12:33:25 PM PDT 24
Peak memory 225164 kb
Host smart-5f2a51f0-638b-4e4b-bd1f-e2e774dbee9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953211132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2953211132
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1173744260
Short name T897
Test name
Test status
Simulation time 17156585678 ps
CPU time 81.95 seconds
Started Jun 13 12:32:34 PM PDT 24
Finished Jun 13 12:33:58 PM PDT 24
Peak memory 253572 kb
Host smart-3c3dc063-9915-4ee4-aa1a-8e6bfa37b9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173744260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1173744260
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.38519126
Short name T400
Test name
Test status
Simulation time 15344612216 ps
CPU time 35.21 seconds
Started Jun 13 12:32:44 PM PDT 24
Finished Jun 13 12:33:26 PM PDT 24
Peak memory 233356 kb
Host smart-823a1e2a-83e3-49e4-a4f6-57cc183d56fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38519126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.38519126
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.759105804
Short name T104
Test name
Test status
Simulation time 13985050120 ps
CPU time 13.91 seconds
Started Jun 13 12:32:49 PM PDT 24
Finished Jun 13 12:33:05 PM PDT 24
Peak memory 233320 kb
Host smart-1a65e03d-ffc6-49f6-a029-52b0d75aa374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759105804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.759105804
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3427602760
Short name T750
Test name
Test status
Simulation time 901740619 ps
CPU time 6.46 seconds
Started Jun 13 12:33:00 PM PDT 24
Finished Jun 13 12:33:08 PM PDT 24
Peak memory 225032 kb
Host smart-ea312f67-c3da-4de7-b92b-a7708eeb0e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427602760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3427602760
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.850923699
Short name T38
Test name
Test status
Simulation time 315685704 ps
CPU time 3.83 seconds
Started Jun 13 12:32:40 PM PDT 24
Finished Jun 13 12:32:47 PM PDT 24
Peak memory 225044 kb
Host smart-39cc5691-20c1-45b9-9478-c0976a0892d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850923699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.850923699
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2285237004
Short name T508
Test name
Test status
Simulation time 157376936 ps
CPU time 2.72 seconds
Started Jun 13 12:32:41 PM PDT 24
Finished Jun 13 12:32:46 PM PDT 24
Peak memory 233268 kb
Host smart-42904377-f9d1-4b88-92e0-72622828c1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285237004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2285237004
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1176835169
Short name T575
Test name
Test status
Simulation time 391290514 ps
CPU time 5.4 seconds
Started Jun 13 12:32:30 PM PDT 24
Finished Jun 13 12:32:36 PM PDT 24
Peak memory 223584 kb
Host smart-195e6de4-eafc-423d-905c-6a05c41a3af7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1176835169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1176835169
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2528457614
Short name T554
Test name
Test status
Simulation time 6622939184 ps
CPU time 34.36 seconds
Started Jun 13 12:32:35 PM PDT 24
Finished Jun 13 12:33:11 PM PDT 24
Peak memory 241600 kb
Host smart-b6266755-fecd-4d35-8c3c-7ce3e8a7b617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528457614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2528457614
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.32740607
Short name T586
Test name
Test status
Simulation time 3216211039 ps
CPU time 25.09 seconds
Started Jun 13 12:32:32 PM PDT 24
Finished Jun 13 12:33:00 PM PDT 24
Peak memory 216840 kb
Host smart-aa6614b3-050a-475f-9359-c2bc448c05a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32740607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.32740607
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3954372670
Short name T916
Test name
Test status
Simulation time 777834998 ps
CPU time 5.79 seconds
Started Jun 13 12:32:49 PM PDT 24
Finished Jun 13 12:32:56 PM PDT 24
Peak memory 216792 kb
Host smart-b2fc4eda-cb46-4f5f-b523-4daca0854c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954372670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3954372670
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1473461374
Short name T65
Test name
Test status
Simulation time 32448588 ps
CPU time 0.7 seconds
Started Jun 13 12:32:35 PM PDT 24
Finished Jun 13 12:32:42 PM PDT 24
Peak memory 206176 kb
Host smart-334efa15-8975-4788-9580-644188f74b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473461374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1473461374
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2981839039
Short name T576
Test name
Test status
Simulation time 44156314 ps
CPU time 0.78 seconds
Started Jun 13 12:32:43 PM PDT 24
Finished Jun 13 12:32:46 PM PDT 24
Peak memory 206464 kb
Host smart-91d1ac83-eb54-43e0-8a79-ecda4e7e331a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981839039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2981839039
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3858247818
Short name T814
Test name
Test status
Simulation time 8454610435 ps
CPU time 8.16 seconds
Started Jun 13 12:32:58 PM PDT 24
Finished Jun 13 12:33:08 PM PDT 24
Peak memory 225112 kb
Host smart-75d415c3-32fe-41bc-aa6d-9fbef4471bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858247818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3858247818
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2627854122
Short name T64
Test name
Test status
Simulation time 14688839 ps
CPU time 0.72 seconds
Started Jun 13 12:32:53 PM PDT 24
Finished Jun 13 12:32:54 PM PDT 24
Peak memory 205996 kb
Host smart-f66c6ae4-6215-4e1e-ad6e-6de6fe377dcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627854122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2627854122
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1128582919
Short name T930
Test name
Test status
Simulation time 19948955 ps
CPU time 0.81 seconds
Started Jun 13 12:32:45 PM PDT 24
Finished Jun 13 12:32:48 PM PDT 24
Peak memory 207548 kb
Host smart-b7810240-383a-4a80-9d9b-b022c4e62faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128582919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1128582919
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2522520276
Short name T175
Test name
Test status
Simulation time 45364821344 ps
CPU time 313.87 seconds
Started Jun 13 12:32:58 PM PDT 24
Finished Jun 13 12:38:14 PM PDT 24
Peak memory 255552 kb
Host smart-5d9c7395-a360-4c66-bbc4-2ebb1a2dffe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522520276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2522520276
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.445588739
Short name T596
Test name
Test status
Simulation time 5071676380 ps
CPU time 11.31 seconds
Started Jun 13 12:32:48 PM PDT 24
Finished Jun 13 12:33:00 PM PDT 24
Peak memory 218056 kb
Host smart-57a1f90e-b7e2-43ca-b119-777f51cd3461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445588739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.445588739
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1728098242
Short name T39
Test name
Test status
Simulation time 12663048074 ps
CPU time 83.23 seconds
Started Jun 13 12:32:39 PM PDT 24
Finished Jun 13 12:34:04 PM PDT 24
Peak memory 241552 kb
Host smart-073927ec-86e6-4514-9c89-1f6e5f85ed6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728098242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1728098242
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.807447900
Short name T560
Test name
Test status
Simulation time 2445377454 ps
CPU time 7.14 seconds
Started Jun 13 12:33:01 PM PDT 24
Finished Jun 13 12:33:09 PM PDT 24
Peak memory 225136 kb
Host smart-c009209f-5cf4-4910-a576-bee4644f39b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807447900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.807447900
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2495454069
Short name T598
Test name
Test status
Simulation time 519799135 ps
CPU time 7.23 seconds
Started Jun 13 12:32:49 PM PDT 24
Finished Jun 13 12:32:58 PM PDT 24
Peak memory 225028 kb
Host smart-f1e0cc8f-9e26-42a7-b554-7daba9117fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495454069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2495454069
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2377351952
Short name T778
Test name
Test status
Simulation time 10684639808 ps
CPU time 97.67 seconds
Started Jun 13 12:32:58 PM PDT 24
Finished Jun 13 12:34:42 PM PDT 24
Peak memory 241236 kb
Host smart-7e24dfdc-c612-45f5-996f-635db6424deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377351952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2377351952
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1485853681
Short name T718
Test name
Test status
Simulation time 108084779 ps
CPU time 2.81 seconds
Started Jun 13 12:32:50 PM PDT 24
Finished Jun 13 12:32:54 PM PDT 24
Peak memory 233280 kb
Host smart-293e80ce-28a9-4313-9c27-b997215abdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485853681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1485853681
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1542299317
Short name T601
Test name
Test status
Simulation time 6179265544 ps
CPU time 3.16 seconds
Started Jun 13 12:32:40 PM PDT 24
Finished Jun 13 12:32:45 PM PDT 24
Peak memory 225128 kb
Host smart-c3f449f8-6a01-4056-b7cb-d08472e3e29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542299317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1542299317
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3448944003
Short name T375
Test name
Test status
Simulation time 286782872 ps
CPU time 5.03 seconds
Started Jun 13 12:32:51 PM PDT 24
Finished Jun 13 12:32:57 PM PDT 24
Peak memory 221096 kb
Host smart-4fef58a0-aa39-471e-9576-a1c4962d0f42
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3448944003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3448944003
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3724273748
Short name T489
Test name
Test status
Simulation time 50749343 ps
CPU time 1.12 seconds
Started Jun 13 12:32:56 PM PDT 24
Finished Jun 13 12:32:58 PM PDT 24
Peak memory 208448 kb
Host smart-2f00649e-3f4d-4f40-8025-d85f3117a793
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724273748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3724273748
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.958132045
Short name T691
Test name
Test status
Simulation time 1856661504 ps
CPU time 22.04 seconds
Started Jun 13 12:32:56 PM PDT 24
Finished Jun 13 12:33:19 PM PDT 24
Peak memory 220328 kb
Host smart-3c214595-d67e-4846-95e3-0aead09baa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958132045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.958132045
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.113867378
Short name T772
Test name
Test status
Simulation time 570243879 ps
CPU time 1.54 seconds
Started Jun 13 12:32:43 PM PDT 24
Finished Jun 13 12:32:46 PM PDT 24
Peak memory 208432 kb
Host smart-2306024e-66c9-45d8-9dbd-c84e5816ff6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113867378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.113867378
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3622655388
Short name T751
Test name
Test status
Simulation time 66088006 ps
CPU time 1.47 seconds
Started Jun 13 12:32:33 PM PDT 24
Finished Jun 13 12:32:47 PM PDT 24
Peak memory 216888 kb
Host smart-060e1cf0-2a60-47d2-85a0-76d72bec8f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622655388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3622655388
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.835338223
Short name T419
Test name
Test status
Simulation time 68738451 ps
CPU time 0.8 seconds
Started Jun 13 12:33:02 PM PDT 24
Finished Jun 13 12:33:04 PM PDT 24
Peak memory 206360 kb
Host smart-5ae73cf9-4b28-45ee-b76b-30d8ab16a554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835338223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.835338223
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3348460880
Short name T541
Test name
Test status
Simulation time 1466926466 ps
CPU time 7.13 seconds
Started Jun 13 12:33:08 PM PDT 24
Finished Jun 13 12:33:18 PM PDT 24
Peak memory 225020 kb
Host smart-362d38b2-3ec8-41bd-87c3-e686260b0d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348460880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3348460880
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3385058596
Short name T281
Test name
Test status
Simulation time 1145478013 ps
CPU time 4.69 seconds
Started Jun 13 12:33:06 PM PDT 24
Finished Jun 13 12:33:11 PM PDT 24
Peak memory 233220 kb
Host smart-c5b42744-d063-43a8-98c5-58b8ad71f550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385058596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3385058596
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.233862015
Short name T315
Test name
Test status
Simulation time 14875719 ps
CPU time 0.81 seconds
Started Jun 13 12:32:45 PM PDT 24
Finished Jun 13 12:32:48 PM PDT 24
Peak memory 207172 kb
Host smart-bd16b519-e37d-4cd7-ac3b-f4d77d936dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233862015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.233862015
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.806723758
Short name T456
Test name
Test status
Simulation time 172474677069 ps
CPU time 105.94 seconds
Started Jun 13 12:33:04 PM PDT 24
Finished Jun 13 12:34:52 PM PDT 24
Peak memory 249788 kb
Host smart-d468d538-586f-4b93-9d1e-9f3730c9e0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806723758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.806723758
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2096396005
Short name T268
Test name
Test status
Simulation time 7599052284 ps
CPU time 45.53 seconds
Started Jun 13 12:32:50 PM PDT 24
Finished Jun 13 12:33:37 PM PDT 24
Peak memory 249656 kb
Host smart-3914db0e-3431-4a51-9680-4b43d97b6150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096396005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2096396005
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3906103265
Short name T136
Test name
Test status
Simulation time 43097486896 ps
CPU time 195.99 seconds
Started Jun 13 12:32:33 PM PDT 24
Finished Jun 13 12:35:51 PM PDT 24
Peak memory 251500 kb
Host smart-80c89a20-56d7-4dbe-a36f-b48e899f8623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906103265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3906103265
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2459851932
Short name T372
Test name
Test status
Simulation time 66607154 ps
CPU time 2.51 seconds
Started Jun 13 12:32:52 PM PDT 24
Finished Jun 13 12:32:56 PM PDT 24
Peak memory 233220 kb
Host smart-334c36d2-ea52-49fa-843a-90edbb7c89cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459851932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2459851932
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2634452870
Short name T786
Test name
Test status
Simulation time 950482121 ps
CPU time 9.94 seconds
Started Jun 13 12:32:56 PM PDT 24
Finished Jun 13 12:33:07 PM PDT 24
Peak memory 233268 kb
Host smart-a0eaa43b-8a6e-47e8-9fe8-289336c1789e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634452870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2634452870
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1623157842
Short name T195
Test name
Test status
Simulation time 644104698 ps
CPU time 8.49 seconds
Started Jun 13 12:32:39 PM PDT 24
Finished Jun 13 12:32:50 PM PDT 24
Peak memory 249572 kb
Host smart-83bb051f-04c2-408e-976c-fcf944f07816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623157842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1623157842
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1141173435
Short name T226
Test name
Test status
Simulation time 763528255 ps
CPU time 4.65 seconds
Started Jun 13 12:32:50 PM PDT 24
Finished Jun 13 12:32:56 PM PDT 24
Peak memory 241204 kb
Host smart-5683b994-d9f6-4b87-8283-3df78af8fb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141173435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1141173435
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.576196727
Short name T546
Test name
Test status
Simulation time 2394763929 ps
CPU time 9.53 seconds
Started Jun 13 12:32:46 PM PDT 24
Finished Jun 13 12:32:57 PM PDT 24
Peak memory 241192 kb
Host smart-f99a4eda-adad-4e6c-9ecc-1577daa1b0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576196727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.576196727
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1166290896
Short name T353
Test name
Test status
Simulation time 3286486965 ps
CPU time 10.1 seconds
Started Jun 13 12:32:54 PM PDT 24
Finished Jun 13 12:33:06 PM PDT 24
Peak memory 221444 kb
Host smart-f65e7c13-7885-4e00-a1ac-c7a3f7744851
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1166290896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1166290896
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1114383104
Short name T304
Test name
Test status
Simulation time 5264839007 ps
CPU time 31.95 seconds
Started Jun 13 12:32:48 PM PDT 24
Finished Jun 13 12:33:21 PM PDT 24
Peak memory 216872 kb
Host smart-36c6ce57-0725-47c6-8f0a-d3299fc09a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114383104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1114383104
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3150639795
Short name T860
Test name
Test status
Simulation time 7614521493 ps
CPU time 5.49 seconds
Started Jun 13 12:32:45 PM PDT 24
Finished Jun 13 12:32:52 PM PDT 24
Peak memory 216936 kb
Host smart-8eac37b3-c594-4d4f-b04d-e268ffe31633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150639795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3150639795
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1076265099
Short name T347
Test name
Test status
Simulation time 268424250 ps
CPU time 1.75 seconds
Started Jun 13 12:32:52 PM PDT 24
Finished Jun 13 12:32:55 PM PDT 24
Peak memory 216808 kb
Host smart-8aa4cd1c-c852-4585-bc9a-8bde598df903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076265099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1076265099
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1187692855
Short name T735
Test name
Test status
Simulation time 152285596 ps
CPU time 0.78 seconds
Started Jun 13 12:32:57 PM PDT 24
Finished Jun 13 12:32:59 PM PDT 24
Peak memory 206452 kb
Host smart-7eb8574a-a22e-4e10-92df-95a2c99c6978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187692855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1187692855
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1830550655
Short name T928
Test name
Test status
Simulation time 9107258764 ps
CPU time 8.9 seconds
Started Jun 13 12:32:49 PM PDT 24
Finished Jun 13 12:33:00 PM PDT 24
Peak memory 225080 kb
Host smart-5b5292e8-327d-4bff-aee3-4a01f4dcb408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830550655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1830550655
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.4271654598
Short name T388
Test name
Test status
Simulation time 12029252 ps
CPU time 0.74 seconds
Started Jun 13 12:32:40 PM PDT 24
Finished Jun 13 12:32:43 PM PDT 24
Peak memory 205412 kb
Host smart-22ac031e-e76f-469b-8390-74a61427df9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271654598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
4271654598
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1654490145
Short name T282
Test name
Test status
Simulation time 1208220827 ps
CPU time 16.33 seconds
Started Jun 13 12:32:57 PM PDT 24
Finished Jun 13 12:33:14 PM PDT 24
Peak memory 225036 kb
Host smart-89c9e858-a911-4e0e-b877-94e7532be241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654490145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1654490145
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1423175637
Short name T655
Test name
Test status
Simulation time 259260466 ps
CPU time 0.78 seconds
Started Jun 13 12:32:54 PM PDT 24
Finished Jun 13 12:32:56 PM PDT 24
Peak memory 207168 kb
Host smart-256ebf6a-a614-4207-a7b0-5f9649a4beef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423175637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1423175637
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.452656738
Short name T211
Test name
Test status
Simulation time 15473040094 ps
CPU time 37 seconds
Started Jun 13 12:32:56 PM PDT 24
Finished Jun 13 12:33:34 PM PDT 24
Peak memory 249680 kb
Host smart-4377c6c2-ecdf-4f47-a26f-9f8e23bb8834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452656738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.452656738
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3414477595
Short name T900
Test name
Test status
Simulation time 6054916519 ps
CPU time 49.71 seconds
Started Jun 13 12:32:43 PM PDT 24
Finished Jun 13 12:33:35 PM PDT 24
Peak memory 241528 kb
Host smart-b5696f85-8fff-475d-9809-a40e23255694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414477595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3414477595
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3955379805
Short name T561
Test name
Test status
Simulation time 8278092395 ps
CPU time 45.05 seconds
Started Jun 13 12:33:06 PM PDT 24
Finished Jun 13 12:33:52 PM PDT 24
Peak memory 251916 kb
Host smart-93a75c82-6ef2-4655-b9ca-9e0009ce2b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955379805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3955379805
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1224232419
Short name T261
Test name
Test status
Simulation time 71915084 ps
CPU time 2.88 seconds
Started Jun 13 12:33:12 PM PDT 24
Finished Jun 13 12:33:24 PM PDT 24
Peak memory 233252 kb
Host smart-97fb2b7c-39bf-4d60-8ac5-761f28406fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224232419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1224232419
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2188689024
Short name T178
Test name
Test status
Simulation time 1337994683 ps
CPU time 5.33 seconds
Started Jun 13 12:32:52 PM PDT 24
Finished Jun 13 12:32:58 PM PDT 24
Peak memory 233304 kb
Host smart-db39e6e3-cb2f-44f1-9b45-31f2ddc84a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188689024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2188689024
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.229667651
Short name T160
Test name
Test status
Simulation time 632311404 ps
CPU time 4.26 seconds
Started Jun 13 12:33:00 PM PDT 24
Finished Jun 13 12:33:05 PM PDT 24
Peak memory 233184 kb
Host smart-80c430c9-63b6-4030-9e0e-725eb820fee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229667651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.229667651
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2212424219
Short name T213
Test name
Test status
Simulation time 6185938491 ps
CPU time 17.39 seconds
Started Jun 13 12:32:54 PM PDT 24
Finished Jun 13 12:33:13 PM PDT 24
Peak memory 225052 kb
Host smart-a7fe626e-8fad-4c51-b9e2-dc9227b0abda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212424219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2212424219
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3708922266
Short name T350
Test name
Test status
Simulation time 317202812 ps
CPU time 3.01 seconds
Started Jun 13 12:32:37 PM PDT 24
Finished Jun 13 12:32:42 PM PDT 24
Peak memory 224968 kb
Host smart-d0b99ddd-e036-45ac-be66-9dd7c6801fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708922266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3708922266
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2570619425
Short name T857
Test name
Test status
Simulation time 803434190 ps
CPU time 7.38 seconds
Started Jun 13 12:33:00 PM PDT 24
Finished Jun 13 12:33:08 PM PDT 24
Peak memory 223072 kb
Host smart-185d9559-e922-4c16-bedc-213894c91fcf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2570619425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2570619425
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.154764547
Short name T172
Test name
Test status
Simulation time 13471694078 ps
CPU time 104.22 seconds
Started Jun 13 12:33:01 PM PDT 24
Finished Jun 13 12:34:46 PM PDT 24
Peak memory 266160 kb
Host smart-29d9e8f8-7972-4fe9-b08d-2388900105c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154764547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.154764547
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.260193182
Short name T748
Test name
Test status
Simulation time 7113023284 ps
CPU time 19.47 seconds
Started Jun 13 12:32:45 PM PDT 24
Finished Jun 13 12:33:06 PM PDT 24
Peak memory 217128 kb
Host smart-0f531974-e967-4122-bb05-b3db21558b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260193182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.260193182
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3016364743
Short name T332
Test name
Test status
Simulation time 9900239528 ps
CPU time 11.97 seconds
Started Jun 13 12:32:42 PM PDT 24
Finished Jun 13 12:32:56 PM PDT 24
Peak memory 216892 kb
Host smart-d25e4480-ad35-4f55-af20-0380a207aa64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016364743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3016364743
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3095070865
Short name T361
Test name
Test status
Simulation time 72916350 ps
CPU time 1.27 seconds
Started Jun 13 12:33:15 PM PDT 24
Finished Jun 13 12:33:20 PM PDT 24
Peak memory 208516 kb
Host smart-d768a1b3-d7ea-4972-b94f-cdb9ffc9c0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095070865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3095070865
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2032668174
Short name T414
Test name
Test status
Simulation time 29870645 ps
CPU time 0.87 seconds
Started Jun 13 12:32:59 PM PDT 24
Finished Jun 13 12:33:02 PM PDT 24
Peak memory 206516 kb
Host smart-f6869813-ce47-4d1e-ac91-014d2485942e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032668174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2032668174
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3194155729
Short name T862
Test name
Test status
Simulation time 73128852 ps
CPU time 2.51 seconds
Started Jun 13 12:32:56 PM PDT 24
Finished Jun 13 12:33:00 PM PDT 24
Peak memory 233032 kb
Host smart-b3178893-16d7-4e4f-95a9-1d33bd8a02ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194155729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3194155729
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3104912070
Short name T378
Test name
Test status
Simulation time 14405148 ps
CPU time 0.71 seconds
Started Jun 13 12:33:05 PM PDT 24
Finished Jun 13 12:33:07 PM PDT 24
Peak memory 205384 kb
Host smart-67b19244-2820-4c45-84fe-ae455465c135
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104912070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3104912070
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3074524548
Short name T784
Test name
Test status
Simulation time 392682321 ps
CPU time 4.93 seconds
Started Jun 13 12:33:09 PM PDT 24
Finished Jun 13 12:33:16 PM PDT 24
Peak memory 225036 kb
Host smart-2f4125af-39f2-4500-b1ad-268c0217f1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074524548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3074524548
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.4156649805
Short name T536
Test name
Test status
Simulation time 64110625 ps
CPU time 0.75 seconds
Started Jun 13 12:32:43 PM PDT 24
Finished Jun 13 12:32:45 PM PDT 24
Peak memory 207168 kb
Host smart-6e341bf2-1449-429c-a638-dc110115b4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156649805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.4156649805
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.295663804
Short name T912
Test name
Test status
Simulation time 7089610580 ps
CPU time 48.06 seconds
Started Jun 13 12:32:41 PM PDT 24
Finished Jun 13 12:33:31 PM PDT 24
Peak memory 241264 kb
Host smart-fcf44b70-4ca5-4daa-b3df-833bda30d4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295663804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.295663804
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.248891369
Short name T87
Test name
Test status
Simulation time 6512601912 ps
CPU time 84.6 seconds
Started Jun 13 12:32:51 PM PDT 24
Finished Jun 13 12:34:17 PM PDT 24
Peak memory 251520 kb
Host smart-61fd5e48-f0a0-4308-9f47-35957cc49878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248891369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.248891369
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.542749627
Short name T515
Test name
Test status
Simulation time 281371716 ps
CPU time 3.8 seconds
Started Jun 13 12:32:52 PM PDT 24
Finished Jun 13 12:32:57 PM PDT 24
Peak memory 225064 kb
Host smart-9b891561-1532-4d76-9c8d-6e3d6dc6e266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542749627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.542749627
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2648049053
Short name T951
Test name
Test status
Simulation time 33206574 ps
CPU time 2.12 seconds
Started Jun 13 12:33:05 PM PDT 24
Finished Jun 13 12:33:08 PM PDT 24
Peak memory 225024 kb
Host smart-26255909-ac03-411f-8769-e62bc168f74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648049053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2648049053
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2993520687
Short name T713
Test name
Test status
Simulation time 14408466015 ps
CPU time 49.32 seconds
Started Jun 13 12:32:49 PM PDT 24
Finished Jun 13 12:33:40 PM PDT 24
Peak memory 241056 kb
Host smart-ab6411cb-ce28-49d5-bcdb-44dc2a42caa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993520687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2993520687
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2758090491
Short name T235
Test name
Test status
Simulation time 9519502568 ps
CPU time 11.46 seconds
Started Jun 13 12:33:07 PM PDT 24
Finished Jun 13 12:33:19 PM PDT 24
Peak memory 241440 kb
Host smart-ea25f3c0-7ca5-4367-8bc4-7205910a1e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758090491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2758090491
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3928633405
Short name T796
Test name
Test status
Simulation time 1081058225 ps
CPU time 4.62 seconds
Started Jun 13 12:32:59 PM PDT 24
Finished Jun 13 12:33:05 PM PDT 24
Peak memory 233272 kb
Host smart-4cc65ed0-a540-44f4-9d52-9f1b732d8592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928633405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3928633405
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.4147407880
Short name T924
Test name
Test status
Simulation time 242832795 ps
CPU time 3.93 seconds
Started Jun 13 12:32:41 PM PDT 24
Finished Jun 13 12:32:47 PM PDT 24
Peak memory 221252 kb
Host smart-8c09a4cd-a3b8-4665-8596-a9ebfa6a6d3c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4147407880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.4147407880
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.455547428
Short name T840
Test name
Test status
Simulation time 40260686440 ps
CPU time 449.79 seconds
Started Jun 13 12:32:48 PM PDT 24
Finished Jun 13 12:40:19 PM PDT 24
Peak memory 267468 kb
Host smart-d4a4105f-fdb2-4bbe-98ad-74ceefe02320
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455547428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.455547428
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.437160142
Short name T747
Test name
Test status
Simulation time 5016764961 ps
CPU time 15.94 seconds
Started Jun 13 12:32:46 PM PDT 24
Finished Jun 13 12:33:03 PM PDT 24
Peak memory 216952 kb
Host smart-378e4961-3c4f-4efb-9db7-e12cfb36b038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437160142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.437160142
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2290961596
Short name T334
Test name
Test status
Simulation time 3633564362 ps
CPU time 12.32 seconds
Started Jun 13 12:32:55 PM PDT 24
Finished Jun 13 12:33:09 PM PDT 24
Peak memory 216840 kb
Host smart-024523ce-a505-400f-b987-46c77554ed9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290961596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2290961596
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1544109255
Short name T742
Test name
Test status
Simulation time 2019023813 ps
CPU time 4.03 seconds
Started Jun 13 12:33:10 PM PDT 24
Finished Jun 13 12:33:16 PM PDT 24
Peak memory 216880 kb
Host smart-21d4554e-2585-400f-9ede-be05318e4569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544109255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1544109255
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.855205982
Short name T621
Test name
Test status
Simulation time 286326490 ps
CPU time 0.89 seconds
Started Jun 13 12:32:54 PM PDT 24
Finished Jun 13 12:32:55 PM PDT 24
Peak memory 206464 kb
Host smart-c6600ac3-2ac9-47fa-baaf-1ef9e225787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855205982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.855205982
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1868329916
Short name T666
Test name
Test status
Simulation time 12419084707 ps
CPU time 15.6 seconds
Started Jun 13 12:33:08 PM PDT 24
Finished Jun 13 12:33:25 PM PDT 24
Peak memory 233448 kb
Host smart-5a10fc7d-8c52-4b20-9d72-2fad88210623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868329916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1868329916
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2765380680
Short name T333
Test name
Test status
Simulation time 16789095 ps
CPU time 0.76 seconds
Started Jun 13 12:33:02 PM PDT 24
Finished Jun 13 12:33:04 PM PDT 24
Peak memory 205976 kb
Host smart-6c75356e-a0f5-4ede-bd48-e33cee7b0317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765380680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2765380680
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3944403062
Short name T351
Test name
Test status
Simulation time 261610031 ps
CPU time 4.47 seconds
Started Jun 13 12:32:51 PM PDT 24
Finished Jun 13 12:32:56 PM PDT 24
Peak memory 233244 kb
Host smart-5cf5dadf-4ef2-4886-becb-43112d20e548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944403062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3944403062
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3486211989
Short name T730
Test name
Test status
Simulation time 39808265 ps
CPU time 0.77 seconds
Started Jun 13 12:32:56 PM PDT 24
Finished Jun 13 12:32:58 PM PDT 24
Peak memory 207208 kb
Host smart-2e4f662e-37b0-4da3-8cdd-c289176e0d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486211989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3486211989
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1921699757
Short name T519
Test name
Test status
Simulation time 11929292141 ps
CPU time 118.4 seconds
Started Jun 13 12:32:54 PM PDT 24
Finished Jun 13 12:34:53 PM PDT 24
Peak memory 253892 kb
Host smart-e812a826-ed25-4f03-8318-b6d07686b5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921699757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1921699757
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3884320371
Short name T473
Test name
Test status
Simulation time 3418810275 ps
CPU time 66.23 seconds
Started Jun 13 12:32:48 PM PDT 24
Finished Jun 13 12:33:56 PM PDT 24
Peak memory 250160 kb
Host smart-095c06c8-7ed4-43d0-96de-8d5c50a25810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884320371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3884320371
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3634689668
Short name T297
Test name
Test status
Simulation time 2172217462 ps
CPU time 32.76 seconds
Started Jun 13 12:33:01 PM PDT 24
Finished Jun 13 12:33:35 PM PDT 24
Peak memory 233280 kb
Host smart-33858461-8585-4856-a263-46c6b33713b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634689668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3634689668
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2298276247
Short name T468
Test name
Test status
Simulation time 492979584 ps
CPU time 3.88 seconds
Started Jun 13 12:33:12 PM PDT 24
Finished Jun 13 12:33:18 PM PDT 24
Peak memory 225036 kb
Host smart-ce229e38-e72b-47df-ab51-17d5b62ee1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298276247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2298276247
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.767506787
Short name T96
Test name
Test status
Simulation time 2949922191 ps
CPU time 46.36 seconds
Started Jun 13 12:32:40 PM PDT 24
Finished Jun 13 12:33:29 PM PDT 24
Peak memory 233284 kb
Host smart-83d65691-59a1-4d9e-9604-36061defde22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767506787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.767506787
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1875035950
Short name T837
Test name
Test status
Simulation time 130237508 ps
CPU time 2.5 seconds
Started Jun 13 12:32:43 PM PDT 24
Finished Jun 13 12:32:47 PM PDT 24
Peak memory 224956 kb
Host smart-76713681-5aa9-4131-a190-8a37fb504733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875035950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1875035950
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2765573553
Short name T548
Test name
Test status
Simulation time 27762144026 ps
CPU time 16.01 seconds
Started Jun 13 12:33:07 PM PDT 24
Finished Jun 13 12:33:25 PM PDT 24
Peak memory 223844 kb
Host smart-1d1a0479-3ae4-4971-9184-979b225213b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765573553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2765573553
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1490264704
Short name T342
Test name
Test status
Simulation time 453096523 ps
CPU time 3.99 seconds
Started Jun 13 12:32:57 PM PDT 24
Finished Jun 13 12:33:02 PM PDT 24
Peak memory 220708 kb
Host smart-dc72dc94-ac84-4c5c-806e-9f5c538d5534
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1490264704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1490264704
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3058966328
Short name T650
Test name
Test status
Simulation time 6120568402 ps
CPU time 8.21 seconds
Started Jun 13 12:32:38 PM PDT 24
Finished Jun 13 12:32:47 PM PDT 24
Peak memory 216944 kb
Host smart-331fb678-15d1-47de-94fd-4a9c8a487cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058966328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3058966328
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1976453492
Short name T911
Test name
Test status
Simulation time 1516890285 ps
CPU time 2.83 seconds
Started Jun 13 12:32:50 PM PDT 24
Finished Jun 13 12:32:54 PM PDT 24
Peak memory 208432 kb
Host smart-caa9da1c-d961-4302-977c-4cfe366e0ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976453492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1976453492
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.4235475776
Short name T323
Test name
Test status
Simulation time 58036287 ps
CPU time 0.86 seconds
Started Jun 13 12:33:10 PM PDT 24
Finished Jun 13 12:33:13 PM PDT 24
Peak memory 206440 kb
Host smart-4575185c-facb-436a-bc4b-3c6d8631c598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235475776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.4235475776
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3083760604
Short name T943
Test name
Test status
Simulation time 57261842 ps
CPU time 0.82 seconds
Started Jun 13 12:32:55 PM PDT 24
Finished Jun 13 12:32:57 PM PDT 24
Peak memory 206456 kb
Host smart-e6030219-1353-4fe6-a0e1-f4fc673c0e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083760604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3083760604
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1751601304
Short name T865
Test name
Test status
Simulation time 1736730627 ps
CPU time 6.59 seconds
Started Jun 13 12:33:09 PM PDT 24
Finished Jun 13 12:33:18 PM PDT 24
Peak memory 232428 kb
Host smart-096d1a8c-082b-4f58-976d-5b86dc4eac55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751601304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1751601304
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1875090761
Short name T876
Test name
Test status
Simulation time 69215474 ps
CPU time 0.75 seconds
Started Jun 13 12:32:51 PM PDT 24
Finished Jun 13 12:32:53 PM PDT 24
Peak memory 205936 kb
Host smart-e061465b-e3f1-4dec-a41d-4a38944f87f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875090761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1875090761
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1806014176
Short name T184
Test name
Test status
Simulation time 1131763261 ps
CPU time 11.76 seconds
Started Jun 13 12:33:09 PM PDT 24
Finished Jun 13 12:33:22 PM PDT 24
Peak memory 225100 kb
Host smart-31e68f1c-84a3-46b9-8d1b-e6325a7bb615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806014176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1806014176
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1091642340
Short name T441
Test name
Test status
Simulation time 75570632 ps
CPU time 0.78 seconds
Started Jun 13 12:32:58 PM PDT 24
Finished Jun 13 12:33:00 PM PDT 24
Peak memory 207464 kb
Host smart-4ab38b31-b8da-4f68-bfb1-e169a014dc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091642340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1091642340
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1682551709
Short name T76
Test name
Test status
Simulation time 25441727744 ps
CPU time 47.26 seconds
Started Jun 13 12:32:59 PM PDT 24
Finished Jun 13 12:33:48 PM PDT 24
Peak memory 225112 kb
Host smart-a196fa78-3dd4-4f54-99ea-e02efa01e80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682551709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1682551709
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2849724032
Short name T301
Test name
Test status
Simulation time 5825453368 ps
CPU time 42.01 seconds
Started Jun 13 12:33:06 PM PDT 24
Finished Jun 13 12:33:49 PM PDT 24
Peak memory 251392 kb
Host smart-9db1cf16-552c-4f0e-99f5-fb4ea3caa997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849724032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2849724032
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1144572038
Short name T625
Test name
Test status
Simulation time 714527873 ps
CPU time 5.22 seconds
Started Jun 13 12:33:05 PM PDT 24
Finished Jun 13 12:33:12 PM PDT 24
Peak memory 233280 kb
Host smart-6b980b48-9e6a-4087-8903-c081bbfade04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144572038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1144572038
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2913050208
Short name T185
Test name
Test status
Simulation time 168141559 ps
CPU time 3.5 seconds
Started Jun 13 12:33:12 PM PDT 24
Finished Jun 13 12:33:24 PM PDT 24
Peak memory 225004 kb
Host smart-7098f632-9e1a-4287-9354-88d19c3fc183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913050208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2913050208
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.4170553931
Short name T131
Test name
Test status
Simulation time 1009354864 ps
CPU time 5.3 seconds
Started Jun 13 12:33:11 PM PDT 24
Finished Jun 13 12:33:18 PM PDT 24
Peak memory 233192 kb
Host smart-cc8483cd-055a-49b9-a5ff-f9422e9a85f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170553931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.4170553931
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2152428547
Short name T654
Test name
Test status
Simulation time 13734125411 ps
CPU time 11.04 seconds
Started Jun 13 12:33:07 PM PDT 24
Finished Jun 13 12:33:19 PM PDT 24
Peak memory 233332 kb
Host smart-5056385f-b905-48ce-bcf1-da640409820f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152428547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2152428547
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1404175409
Short name T366
Test name
Test status
Simulation time 4478263036 ps
CPU time 6.14 seconds
Started Jun 13 12:33:05 PM PDT 24
Finished Jun 13 12:33:12 PM PDT 24
Peak memory 223584 kb
Host smart-cd1fde9f-8290-4fbb-9dde-c0cf9f9975b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1404175409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1404175409
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.451863184
Short name T462
Test name
Test status
Simulation time 248742680 ps
CPU time 2.68 seconds
Started Jun 13 12:33:19 PM PDT 24
Finished Jun 13 12:33:27 PM PDT 24
Peak memory 216888 kb
Host smart-5516d3f7-1399-4a72-89c4-c6e96a6be83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451863184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.451863184
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3213573043
Short name T509
Test name
Test status
Simulation time 1361936535 ps
CPU time 8.18 seconds
Started Jun 13 12:32:59 PM PDT 24
Finished Jun 13 12:33:09 PM PDT 24
Peak memory 216868 kb
Host smart-827b4fab-6e29-47cb-971b-c739db222b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213573043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3213573043
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1978300379
Short name T488
Test name
Test status
Simulation time 26238626 ps
CPU time 1.47 seconds
Started Jun 13 12:33:08 PM PDT 24
Finished Jun 13 12:33:11 PM PDT 24
Peak memory 216872 kb
Host smart-9daf04c0-00d4-4ceb-8923-abc69d69ab9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978300379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1978300379
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1248104043
Short name T727
Test name
Test status
Simulation time 50558761 ps
CPU time 0.81 seconds
Started Jun 13 12:32:56 PM PDT 24
Finished Jun 13 12:32:58 PM PDT 24
Peak memory 206472 kb
Host smart-8fc4df3d-dad0-4616-8dc5-a93eb7758b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248104043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1248104043
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1839360096
Short name T724
Test name
Test status
Simulation time 1888466354 ps
CPU time 3.99 seconds
Started Jun 13 12:33:11 PM PDT 24
Finished Jun 13 12:33:18 PM PDT 24
Peak memory 225148 kb
Host smart-b04233e3-5382-458f-8b49-dac2761f21df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839360096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1839360096
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3740409428
Short name T741
Test name
Test status
Simulation time 15944743 ps
CPU time 0.73 seconds
Started Jun 13 12:32:43 PM PDT 24
Finished Jun 13 12:32:46 PM PDT 24
Peak memory 205952 kb
Host smart-3cfce6a1-3a54-4dd9-8f9e-2278a4fad5e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740409428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3740409428
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3701468037
Short name T358
Test name
Test status
Simulation time 1180106071 ps
CPU time 4.52 seconds
Started Jun 13 12:32:53 PM PDT 24
Finished Jun 13 12:32:58 PM PDT 24
Peak memory 225076 kb
Host smart-cc363bd4-7843-42c0-949e-c224a53bfde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701468037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3701468037
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1523093935
Short name T130
Test name
Test status
Simulation time 25459915 ps
CPU time 0.74 seconds
Started Jun 13 12:33:08 PM PDT 24
Finished Jun 13 12:33:10 PM PDT 24
Peak memory 206440 kb
Host smart-d086f59a-02b0-4692-8058-aeb20ae7d4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523093935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1523093935
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.700683108
Short name T44
Test name
Test status
Simulation time 21542010767 ps
CPU time 49.17 seconds
Started Jun 13 12:33:11 PM PDT 24
Finished Jun 13 12:34:03 PM PDT 24
Peak memory 239712 kb
Host smart-d775541f-a756-4c43-b9f5-84dd117e08ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700683108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.700683108
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3696601297
Short name T181
Test name
Test status
Simulation time 11395518092 ps
CPU time 82.43 seconds
Started Jun 13 12:32:57 PM PDT 24
Finished Jun 13 12:34:21 PM PDT 24
Peak memory 253724 kb
Host smart-1a72a9a6-899d-463c-83d7-945fdd701d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696601297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3696601297
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2288452169
Short name T688
Test name
Test status
Simulation time 329918246 ps
CPU time 8 seconds
Started Jun 13 12:33:11 PM PDT 24
Finished Jun 13 12:33:22 PM PDT 24
Peak memory 233300 kb
Host smart-98d67929-7608-45fa-a316-a63a8949aaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288452169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2288452169
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2408323728
Short name T948
Test name
Test status
Simulation time 968531149 ps
CPU time 5.88 seconds
Started Jun 13 12:32:58 PM PDT 24
Finished Jun 13 12:33:06 PM PDT 24
Peak memory 225020 kb
Host smart-c19602ad-2835-4910-bd07-0b40ba06fc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408323728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2408323728
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2220639475
Short name T532
Test name
Test status
Simulation time 104837968 ps
CPU time 2.06 seconds
Started Jun 13 12:32:55 PM PDT 24
Finished Jun 13 12:32:58 PM PDT 24
Peak memory 224524 kb
Host smart-672e29f6-665e-409f-abc1-6c3f99aa6554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220639475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2220639475
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3552849471
Short name T712
Test name
Test status
Simulation time 27494222650 ps
CPU time 18.41 seconds
Started Jun 13 12:32:56 PM PDT 24
Finished Jun 13 12:33:16 PM PDT 24
Peak memory 225084 kb
Host smart-cbca4979-dffc-4bfa-a6ea-18920e01c56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552849471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3552849471
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1458231351
Short name T669
Test name
Test status
Simulation time 699649944 ps
CPU time 5.56 seconds
Started Jun 13 12:32:59 PM PDT 24
Finished Jun 13 12:33:06 PM PDT 24
Peak memory 225004 kb
Host smart-88641f7f-8c90-45b6-b1ce-28cb4a5e76c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458231351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1458231351
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2746244652
Short name T450
Test name
Test status
Simulation time 1745855288 ps
CPU time 14.06 seconds
Started Jun 13 12:33:15 PM PDT 24
Finished Jun 13 12:33:32 PM PDT 24
Peak memory 219296 kb
Host smart-dff4995c-699b-4f69-8385-d434dbf166b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2746244652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2746244652
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1325210746
Short name T592
Test name
Test status
Simulation time 21153518529 ps
CPU time 140.94 seconds
Started Jun 13 12:33:27 PM PDT 24
Finished Jun 13 12:35:50 PM PDT 24
Peak memory 249784 kb
Host smart-b853f7ec-dd32-41f0-ae77-c4cd9d0259d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325210746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1325210746
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.743988417
Short name T425
Test name
Test status
Simulation time 4802058284 ps
CPU time 31.26 seconds
Started Jun 13 12:32:47 PM PDT 24
Finished Jun 13 12:33:19 PM PDT 24
Peak memory 216880 kb
Host smart-04792565-9abe-4e23-acbf-b4f0efd23e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743988417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.743988417
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3005565506
Short name T791
Test name
Test status
Simulation time 2543393628 ps
CPU time 9.44 seconds
Started Jun 13 12:33:00 PM PDT 24
Finished Jun 13 12:33:11 PM PDT 24
Peak memory 216932 kb
Host smart-0641a845-5075-4022-b09e-3a83494fde23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005565506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3005565506
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2022420123
Short name T889
Test name
Test status
Simulation time 16058782 ps
CPU time 0.86 seconds
Started Jun 13 12:33:10 PM PDT 24
Finished Jun 13 12:33:19 PM PDT 24
Peak memory 207468 kb
Host smart-bbc40f22-48a6-45e8-b235-21d72d1baa89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022420123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2022420123
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.269245964
Short name T893
Test name
Test status
Simulation time 28493711 ps
CPU time 0.86 seconds
Started Jun 13 12:32:58 PM PDT 24
Finished Jun 13 12:33:00 PM PDT 24
Peak memory 206376 kb
Host smart-9fd3f5eb-3e1f-494c-a4e4-888f8062da9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269245964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.269245964
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3120141485
Short name T194
Test name
Test status
Simulation time 179686697 ps
CPU time 2.23 seconds
Started Jun 13 12:33:00 PM PDT 24
Finished Jun 13 12:33:04 PM PDT 24
Peak memory 233288 kb
Host smart-15ff7fe7-d8aa-49c3-a1c7-c62671b63615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120141485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3120141485
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3727074866
Short name T558
Test name
Test status
Simulation time 58151723 ps
CPU time 0.77 seconds
Started Jun 13 12:32:46 PM PDT 24
Finished Jun 13 12:32:48 PM PDT 24
Peak memory 206320 kb
Host smart-c134f398-d016-49fc-9d79-edf936fc62cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727074866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3727074866
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1790639239
Short name T360
Test name
Test status
Simulation time 295826471 ps
CPU time 5.81 seconds
Started Jun 13 12:32:57 PM PDT 24
Finished Jun 13 12:33:04 PM PDT 24
Peak memory 233200 kb
Host smart-5176127c-2340-4621-8b5c-fef01929a958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790639239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1790639239
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1293428420
Short name T500
Test name
Test status
Simulation time 18637299 ps
CPU time 0.84 seconds
Started Jun 13 12:32:57 PM PDT 24
Finished Jun 13 12:32:59 PM PDT 24
Peak memory 207472 kb
Host smart-b5baf9ed-7516-42ba-b13c-1a6df0ab2a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293428420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1293428420
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.714424842
Short name T196
Test name
Test status
Simulation time 5561093169 ps
CPU time 65.49 seconds
Started Jun 13 12:32:54 PM PDT 24
Finished Jun 13 12:34:00 PM PDT 24
Peak memory 251588 kb
Host smart-c8ef0b5b-0092-454f-954d-266fa892243a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714424842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.714424842
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3920634954
Short name T199
Test name
Test status
Simulation time 41448177439 ps
CPU time 91.17 seconds
Started Jun 13 12:32:54 PM PDT 24
Finished Jun 13 12:34:27 PM PDT 24
Peak memory 257804 kb
Host smart-063a23f6-c4f6-4288-b21f-b5115ae5b7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920634954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3920634954
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1459764806
Short name T435
Test name
Test status
Simulation time 98044765 ps
CPU time 4.68 seconds
Started Jun 13 12:32:50 PM PDT 24
Finished Jun 13 12:32:56 PM PDT 24
Peak memory 233232 kb
Host smart-77892154-dd7f-4f46-9ac3-72be34dd8a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459764806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1459764806
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3439027316
Short name T191
Test name
Test status
Simulation time 13812997056 ps
CPU time 30.74 seconds
Started Jun 13 12:32:58 PM PDT 24
Finished Jun 13 12:33:30 PM PDT 24
Peak memory 233332 kb
Host smart-99c19ce4-5618-4724-8a6f-1b4c14cbd37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439027316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3439027316
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.264988791
Short name T34
Test name
Test status
Simulation time 11539069038 ps
CPU time 45.52 seconds
Started Jun 13 12:33:14 PM PDT 24
Finished Jun 13 12:34:02 PM PDT 24
Peak memory 236480 kb
Host smart-6008ea55-b07f-4e55-bc65-645a3f0bfe77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264988791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.264988791
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1651739079
Short name T481
Test name
Test status
Simulation time 1906344308 ps
CPU time 11.08 seconds
Started Jun 13 12:32:55 PM PDT 24
Finished Jun 13 12:33:07 PM PDT 24
Peak memory 233192 kb
Host smart-60e9d651-36ba-4506-8c2e-082a84088080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651739079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1651739079
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2594317017
Short name T437
Test name
Test status
Simulation time 19361218733 ps
CPU time 17.48 seconds
Started Jun 13 12:33:14 PM PDT 24
Finished Jun 13 12:33:35 PM PDT 24
Peak memory 241480 kb
Host smart-d999cdcd-5522-4372-9a16-a2ca8ccefc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594317017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2594317017
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.993229582
Short name T626
Test name
Test status
Simulation time 12091739942 ps
CPU time 9.51 seconds
Started Jun 13 12:33:15 PM PDT 24
Finished Jun 13 12:33:28 PM PDT 24
Peak memory 219764 kb
Host smart-09bd8ccc-931b-40fe-890f-c0b043900d8b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=993229582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.993229582
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2837412965
Short name T581
Test name
Test status
Simulation time 168384807 ps
CPU time 0.95 seconds
Started Jun 13 12:32:49 PM PDT 24
Finished Jun 13 12:32:51 PM PDT 24
Peak memory 207216 kb
Host smart-423e8938-3ed9-4c00-b91e-c03c099d3eb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837412965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2837412965
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.190502318
Short name T609
Test name
Test status
Simulation time 2171115182 ps
CPU time 23.2 seconds
Started Jun 13 12:32:58 PM PDT 24
Finished Jun 13 12:33:22 PM PDT 24
Peak memory 216852 kb
Host smart-e06da3e8-8cde-4ed5-a772-b5f8f7b3120b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190502318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.190502318
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.331470831
Short name T370
Test name
Test status
Simulation time 2096082477 ps
CPU time 4.67 seconds
Started Jun 13 12:33:04 PM PDT 24
Finished Jun 13 12:33:10 PM PDT 24
Peak memory 216812 kb
Host smart-3036b549-bae4-43cb-b670-41ac5163f580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331470831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.331470831
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2432557947
Short name T768
Test name
Test status
Simulation time 50512701 ps
CPU time 1.42 seconds
Started Jun 13 12:32:57 PM PDT 24
Finished Jun 13 12:32:59 PM PDT 24
Peak memory 216884 kb
Host smart-757835a5-6615-4abc-a38e-5037f6d24444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432557947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2432557947
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.466193766
Short name T341
Test name
Test status
Simulation time 120887377 ps
CPU time 0.83 seconds
Started Jun 13 12:33:10 PM PDT 24
Finished Jun 13 12:33:13 PM PDT 24
Peak memory 206476 kb
Host smart-5cf3272f-e4e9-4138-8b02-ad62071a4853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466193766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.466193766
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3281209880
Short name T582
Test name
Test status
Simulation time 1010528677 ps
CPU time 9.53 seconds
Started Jun 13 12:33:11 PM PDT 24
Finished Jun 13 12:33:23 PM PDT 24
Peak memory 239144 kb
Host smart-a0463cf3-c77d-465a-bf0e-bce11ea5b589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281209880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3281209880
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.4034194898
Short name T446
Test name
Test status
Simulation time 32366943 ps
CPU time 0.73 seconds
Started Jun 13 12:32:37 PM PDT 24
Finished Jun 13 12:32:42 PM PDT 24
Peak memory 205960 kb
Host smart-492dcc19-26da-4647-b384-152a2688e07d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034194898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.4
034194898
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1574639411
Short name T929
Test name
Test status
Simulation time 929009058 ps
CPU time 3.85 seconds
Started Jun 13 12:32:14 PM PDT 24
Finished Jun 13 12:32:20 PM PDT 24
Peak memory 224968 kb
Host smart-675e960a-e848-40e7-a9c9-4fe157791201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574639411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1574639411
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3483716249
Short name T671
Test name
Test status
Simulation time 35685984 ps
CPU time 0.77 seconds
Started Jun 13 12:32:38 PM PDT 24
Finished Jun 13 12:32:40 PM PDT 24
Peak memory 207160 kb
Host smart-057ae77f-ed54-460b-9d76-a6cfead4ca68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483716249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3483716249
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2742627327
Short name T413
Test name
Test status
Simulation time 12215643836 ps
CPU time 44.77 seconds
Started Jun 13 12:32:19 PM PDT 24
Finished Jun 13 12:33:06 PM PDT 24
Peak memory 241056 kb
Host smart-8cc708f5-c13d-460c-bd8d-51b02b82f532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742627327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2742627327
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2264827688
Short name T557
Test name
Test status
Simulation time 3290838333 ps
CPU time 56.29 seconds
Started Jun 13 12:32:28 PM PDT 24
Finished Jun 13 12:33:26 PM PDT 24
Peak memory 249780 kb
Host smart-86312af5-e2ff-4ed5-b86f-59787d281c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264827688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2264827688
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2679255614
Short name T232
Test name
Test status
Simulation time 9749787433 ps
CPU time 96.72 seconds
Started Jun 13 12:32:29 PM PDT 24
Finished Jun 13 12:34:07 PM PDT 24
Peak memory 251392 kb
Host smart-dd29dfc6-469f-4276-b5e4-c3f78b005e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679255614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2679255614
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2428414365
Short name T649
Test name
Test status
Simulation time 446608218 ps
CPU time 6.7 seconds
Started Jun 13 12:32:12 PM PDT 24
Finished Jun 13 12:32:21 PM PDT 24
Peak memory 224988 kb
Host smart-a2549e60-57ea-4107-82b7-982a97a2967d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428414365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2428414365
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2813670802
Short name T369
Test name
Test status
Simulation time 145096203 ps
CPU time 2.32 seconds
Started Jun 13 12:32:15 PM PDT 24
Finished Jun 13 12:32:19 PM PDT 24
Peak memory 233232 kb
Host smart-a909377b-1911-4f12-a6dc-7fa6975ffbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813670802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2813670802
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2343597409
Short name T314
Test name
Test status
Simulation time 34177129 ps
CPU time 2.44 seconds
Started Jun 13 12:32:23 PM PDT 24
Finished Jun 13 12:32:28 PM PDT 24
Peak memory 233336 kb
Host smart-66f8a606-2aba-48cf-a185-60da4deda55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343597409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2343597409
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3177483290
Short name T591
Test name
Test status
Simulation time 448103620 ps
CPU time 3.49 seconds
Started Jun 13 12:32:26 PM PDT 24
Finished Jun 13 12:32:31 PM PDT 24
Peak memory 225080 kb
Host smart-f6d7b3f2-e999-4efe-9f7f-9c36b92429cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177483290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3177483290
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.35832222
Short name T279
Test name
Test status
Simulation time 1454785215 ps
CPU time 5.78 seconds
Started Jun 13 12:32:22 PM PDT 24
Finished Jun 13 12:32:31 PM PDT 24
Peak memory 225012 kb
Host smart-c51905f5-5ae6-4afc-b8d8-0dcd344207d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35832222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.35832222
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.4229519892
Short name T143
Test name
Test status
Simulation time 1496407041 ps
CPU time 10.1 seconds
Started Jun 13 12:32:11 PM PDT 24
Finished Jun 13 12:32:24 PM PDT 24
Peak memory 219760 kb
Host smart-614c01a2-d781-4340-b037-e1be70fe553f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4229519892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.4229519892
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.810597088
Short name T73
Test name
Test status
Simulation time 3162547754 ps
CPU time 1.41 seconds
Started Jun 13 12:32:55 PM PDT 24
Finished Jun 13 12:32:58 PM PDT 24
Peak memory 237088 kb
Host smart-e8501626-0bb0-43a8-95d7-2a851582baa3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810597088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.810597088
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.4167278110
Short name T936
Test name
Test status
Simulation time 13397810629 ps
CPU time 156.04 seconds
Started Jun 13 12:32:39 PM PDT 24
Finished Jun 13 12:35:17 PM PDT 24
Peak memory 270996 kb
Host smart-9eab9618-2fe0-4026-94b6-c993acef8c41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167278110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.4167278110
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2424095555
Short name T623
Test name
Test status
Simulation time 4539128076 ps
CPU time 6.12 seconds
Started Jun 13 12:32:27 PM PDT 24
Finished Jun 13 12:32:35 PM PDT 24
Peak memory 217168 kb
Host smart-d11df950-1829-4d25-9633-f7b69754e099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424095555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2424095555
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2102017912
Short name T460
Test name
Test status
Simulation time 968152549 ps
CPU time 1.99 seconds
Started Jun 13 12:32:16 PM PDT 24
Finished Jun 13 12:32:20 PM PDT 24
Peak memory 216620 kb
Host smart-22846776-94da-4b0f-a59e-935612cf6a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102017912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2102017912
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2491258853
Short name T318
Test name
Test status
Simulation time 386825354 ps
CPU time 2.54 seconds
Started Jun 13 12:32:29 PM PDT 24
Finished Jun 13 12:32:33 PM PDT 24
Peak memory 216816 kb
Host smart-d7a0645b-af03-4c89-a7d1-61c79668fe93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491258853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2491258853
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1415491722
Short name T878
Test name
Test status
Simulation time 35551605 ps
CPU time 0.83 seconds
Started Jun 13 12:32:26 PM PDT 24
Finished Jun 13 12:32:29 PM PDT 24
Peak memory 206408 kb
Host smart-6b48c52a-d8fc-40bc-8fa8-138176a7f82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415491722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1415491722
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3221044508
Short name T863
Test name
Test status
Simulation time 9653570636 ps
CPU time 29.99 seconds
Started Jun 13 12:32:18 PM PDT 24
Finished Jun 13 12:32:51 PM PDT 24
Peak memory 233300 kb
Host smart-63bfcbad-c48f-4218-a581-2b86b43f8eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221044508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3221044508
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3087670738
Short name T452
Test name
Test status
Simulation time 22976234 ps
CPU time 0.72 seconds
Started Jun 13 12:33:10 PM PDT 24
Finished Jun 13 12:33:13 PM PDT 24
Peak memory 206328 kb
Host smart-923bd10d-1d90-4b1b-8939-a421c3cf5a73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087670738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3087670738
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.4225220639
Short name T829
Test name
Test status
Simulation time 168891899 ps
CPU time 2.64 seconds
Started Jun 13 12:33:16 PM PDT 24
Finished Jun 13 12:33:24 PM PDT 24
Peak memory 233208 kb
Host smart-95e6adeb-9026-4f09-8dfa-61b1d19eeefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225220639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.4225220639
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.997565419
Short name T665
Test name
Test status
Simulation time 29930105 ps
CPU time 0.77 seconds
Started Jun 13 12:33:14 PM PDT 24
Finished Jun 13 12:33:18 PM PDT 24
Peak memory 206088 kb
Host smart-292d29bc-3e77-431a-90a0-b41e12b86b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997565419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.997565419
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1508567298
Short name T158
Test name
Test status
Simulation time 163173453 ps
CPU time 0.75 seconds
Started Jun 13 12:33:08 PM PDT 24
Finished Jun 13 12:33:11 PM PDT 24
Peak memory 216372 kb
Host smart-2ce505dc-5a2b-40ad-963a-c7c40a6b87d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508567298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1508567298
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.408959583
Short name T716
Test name
Test status
Simulation time 11925670557 ps
CPU time 30.92 seconds
Started Jun 13 12:33:15 PM PDT 24
Finished Jun 13 12:33:50 PM PDT 24
Peak memory 237988 kb
Host smart-22d161a1-1202-4497-b4a6-8655f32f6139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408959583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.408959583
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3897289667
Short name T233
Test name
Test status
Simulation time 7430747606 ps
CPU time 44.74 seconds
Started Jun 13 12:32:58 PM PDT 24
Finished Jun 13 12:33:44 PM PDT 24
Peak memory 237480 kb
Host smart-9aaf47f4-26ea-4b10-97e7-669187dc447c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897289667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3897289667
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2717704649
Short name T339
Test name
Test status
Simulation time 5830579444 ps
CPU time 16.09 seconds
Started Jun 13 12:33:12 PM PDT 24
Finished Jun 13 12:33:30 PM PDT 24
Peak memory 225136 kb
Host smart-82b252ef-fdda-49e6-a211-fb74fed1d1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717704649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2717704649
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3778841882
Short name T800
Test name
Test status
Simulation time 171966377 ps
CPU time 3.57 seconds
Started Jun 13 12:33:10 PM PDT 24
Finished Jun 13 12:33:15 PM PDT 24
Peak memory 233264 kb
Host smart-4b7249bb-dc86-476a-ae17-3138f28f0eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778841882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3778841882
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.194573969
Short name T695
Test name
Test status
Simulation time 2604009282 ps
CPU time 22.39 seconds
Started Jun 13 12:33:02 PM PDT 24
Finished Jun 13 12:33:26 PM PDT 24
Peak memory 233308 kb
Host smart-5bab4270-d2b6-4250-bbe6-aedf8d05181c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194573969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.194573969
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3260413809
Short name T818
Test name
Test status
Simulation time 56473334 ps
CPU time 2.39 seconds
Started Jun 13 12:33:02 PM PDT 24
Finished Jun 13 12:33:05 PM PDT 24
Peak memory 233028 kb
Host smart-9012a96e-25c5-46f6-b860-801cebfbdbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260413809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3260413809
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3404683033
Short name T35
Test name
Test status
Simulation time 9276245011 ps
CPU time 21.94 seconds
Started Jun 13 12:33:09 PM PDT 24
Finished Jun 13 12:33:33 PM PDT 24
Peak memory 233304 kb
Host smart-f1e81bc3-91bd-4eb4-bf62-ca31fa704fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404683033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3404683033
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.977451766
Short name T459
Test name
Test status
Simulation time 151274497 ps
CPU time 3.78 seconds
Started Jun 13 12:33:22 PM PDT 24
Finished Jun 13 12:33:30 PM PDT 24
Peak memory 219920 kb
Host smart-e0cdc3c3-f3c7-465a-aebd-d5b9673745d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=977451766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.977451766
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2066484321
Short name T308
Test name
Test status
Simulation time 1248346791 ps
CPU time 15.23 seconds
Started Jun 13 12:33:02 PM PDT 24
Finished Jun 13 12:33:18 PM PDT 24
Peak memory 216996 kb
Host smart-e8b2c2de-0322-49f9-b7e4-d710e1ebd316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066484321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2066484321
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1569686140
Short name T810
Test name
Test status
Simulation time 10525613118 ps
CPU time 9.55 seconds
Started Jun 13 12:33:00 PM PDT 24
Finished Jun 13 12:33:10 PM PDT 24
Peak memory 216896 kb
Host smart-7387da45-e8a4-46c5-9d32-4624996894ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569686140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1569686140
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2115471793
Short name T544
Test name
Test status
Simulation time 592385456 ps
CPU time 2.03 seconds
Started Jun 13 12:33:11 PM PDT 24
Finished Jun 13 12:33:15 PM PDT 24
Peak memory 216864 kb
Host smart-054a4a63-255e-4853-9234-5e87df2448e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115471793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2115471793
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2254953958
Short name T128
Test name
Test status
Simulation time 54049922 ps
CPU time 0.73 seconds
Started Jun 13 12:33:24 PM PDT 24
Finished Jun 13 12:33:28 PM PDT 24
Peak memory 206464 kb
Host smart-fdec3df1-4b58-416c-83f6-6ac856b0e5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254953958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2254953958
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.854934995
Short name T249
Test name
Test status
Simulation time 312032520 ps
CPU time 3.64 seconds
Started Jun 13 12:33:16 PM PDT 24
Finished Jun 13 12:33:24 PM PDT 24
Peak memory 225052 kb
Host smart-08fcf278-12ee-4fb0-85cb-a0c3709ac3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854934995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.854934995
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.35319595
Short name T327
Test name
Test status
Simulation time 40302438 ps
CPU time 0.73 seconds
Started Jun 13 12:33:02 PM PDT 24
Finished Jun 13 12:33:04 PM PDT 24
Peak memory 206024 kb
Host smart-aebb332d-52ea-410a-81b3-04da4220ac93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35319595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.35319595
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.504016429
Short name T516
Test name
Test status
Simulation time 360057137 ps
CPU time 2.77 seconds
Started Jun 13 12:33:13 PM PDT 24
Finished Jun 13 12:33:19 PM PDT 24
Peak memory 233240 kb
Host smart-ac7517d0-ac74-4650-966f-aa082adf2cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504016429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.504016429
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3092073483
Short name T866
Test name
Test status
Simulation time 20688752 ps
CPU time 0.8 seconds
Started Jun 13 12:33:07 PM PDT 24
Finished Jun 13 12:33:09 PM PDT 24
Peak memory 207172 kb
Host smart-ef2dc11b-d69f-4900-9f2f-9fa3f75eca61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092073483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3092073483
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3109584622
Short name T169
Test name
Test status
Simulation time 653886751 ps
CPU time 7.6 seconds
Started Jun 13 12:32:52 PM PDT 24
Finished Jun 13 12:33:01 PM PDT 24
Peak memory 234720 kb
Host smart-416b0d6d-ad0f-4f12-96d7-90b647789f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109584622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3109584622
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2005000590
Short name T259
Test name
Test status
Simulation time 68727166001 ps
CPU time 128.59 seconds
Started Jun 13 12:32:58 PM PDT 24
Finished Jun 13 12:35:08 PM PDT 24
Peak memory 255968 kb
Host smart-1be217ff-1d92-4f1f-9176-80493c140ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005000590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2005000590
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1748344844
Short name T302
Test name
Test status
Simulation time 10949613933 ps
CPU time 39.7 seconds
Started Jun 13 12:33:09 PM PDT 24
Finished Jun 13 12:33:51 PM PDT 24
Peak memory 233336 kb
Host smart-5a8ffc2c-39ed-4da9-b6ab-09622df2220a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748344844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1748344844
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.4095610397
Short name T12
Test name
Test status
Simulation time 115134635 ps
CPU time 3.24 seconds
Started Jun 13 12:33:14 PM PDT 24
Finished Jun 13 12:33:20 PM PDT 24
Peak memory 233352 kb
Host smart-9655b100-05b1-4170-97c8-f9a2137826b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095610397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.4095610397
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3701647453
Short name T616
Test name
Test status
Simulation time 841601481 ps
CPU time 6.71 seconds
Started Jun 13 12:33:00 PM PDT 24
Finished Jun 13 12:33:08 PM PDT 24
Peak memory 241436 kb
Host smart-28a35b2a-4b12-4f43-ba75-1b12022bd85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701647453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3701647453
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.35762259
Short name T794
Test name
Test status
Simulation time 107780045 ps
CPU time 2.23 seconds
Started Jun 13 12:33:11 PM PDT 24
Finished Jun 13 12:33:16 PM PDT 24
Peak memory 233092 kb
Host smart-72514362-6e2b-4010-98d1-a72a2bc525f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35762259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.35762259
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.416423408
Short name T377
Test name
Test status
Simulation time 1263908613 ps
CPU time 3.37 seconds
Started Jun 13 12:33:06 PM PDT 24
Finished Jun 13 12:33:10 PM PDT 24
Peak memory 225040 kb
Host smart-081cdf65-237b-406a-a4d0-4b52b21137e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416423408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.416423408
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2521277451
Short name T433
Test name
Test status
Simulation time 5577637082 ps
CPU time 18.87 seconds
Started Jun 13 12:33:08 PM PDT 24
Finished Jun 13 12:33:29 PM PDT 24
Peak memory 219520 kb
Host smart-73a4859b-2b81-4eef-9cd5-f60ec575709d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2521277451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2521277451
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2162036169
Short name T86
Test name
Test status
Simulation time 151936268870 ps
CPU time 377.58 seconds
Started Jun 13 12:32:57 PM PDT 24
Finished Jun 13 12:39:16 PM PDT 24
Peak memory 290276 kb
Host smart-f953e3f0-961c-486d-92cf-d08ae4a29309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162036169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2162036169
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3400292646
Short name T682
Test name
Test status
Simulation time 2383189315 ps
CPU time 15.92 seconds
Started Jun 13 12:33:04 PM PDT 24
Finished Jun 13 12:33:21 PM PDT 24
Peak memory 216924 kb
Host smart-43ceafda-54c2-44e8-bbb4-bbd4baa464f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400292646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3400292646
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2837249816
Short name T820
Test name
Test status
Simulation time 906684512 ps
CPU time 10.87 seconds
Started Jun 13 12:33:08 PM PDT 24
Finished Jun 13 12:33:20 PM PDT 24
Peak memory 216824 kb
Host smart-e464cfe4-1f75-4f41-94a7-736b5472d214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837249816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2837249816
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1383149575
Short name T833
Test name
Test status
Simulation time 73369393 ps
CPU time 0.85 seconds
Started Jun 13 12:33:06 PM PDT 24
Finished Jun 13 12:33:07 PM PDT 24
Peak memory 206464 kb
Host smart-ed62c7fc-32d2-429b-9e17-ec7c4581cd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383149575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1383149575
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3565156658
Short name T825
Test name
Test status
Simulation time 6223628385 ps
CPU time 21.21 seconds
Started Jun 13 12:33:16 PM PDT 24
Finished Jun 13 12:33:41 PM PDT 24
Peak memory 225140 kb
Host smart-77280aac-a605-43dc-b20b-f85bd8904946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565156658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3565156658
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.632262697
Short name T469
Test name
Test status
Simulation time 32732131 ps
CPU time 0.74 seconds
Started Jun 13 12:33:09 PM PDT 24
Finished Jun 13 12:33:12 PM PDT 24
Peak memory 205996 kb
Host smart-2c631e6d-7f4d-4af5-8789-8ab19c9060f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632262697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.632262697
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3507438853
Short name T781
Test name
Test status
Simulation time 3590596222 ps
CPU time 19.53 seconds
Started Jun 13 12:32:58 PM PDT 24
Finished Jun 13 12:33:19 PM PDT 24
Peak memory 225112 kb
Host smart-a27b21be-1811-49a3-94cf-d5d40471fc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507438853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3507438853
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1214448690
Short name T324
Test name
Test status
Simulation time 49084560 ps
CPU time 0.74 seconds
Started Jun 13 12:33:08 PM PDT 24
Finished Jun 13 12:33:10 PM PDT 24
Peak memory 207480 kb
Host smart-379872af-2c23-474a-8ccf-23223dfe3904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214448690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1214448690
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2474939515
Short name T197
Test name
Test status
Simulation time 83707082032 ps
CPU time 181.37 seconds
Started Jun 13 12:33:16 PM PDT 24
Finished Jun 13 12:36:22 PM PDT 24
Peak memory 249760 kb
Host smart-c487ff68-8212-4048-8238-5e8fe98ed6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474939515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2474939515
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2305156897
Short name T257
Test name
Test status
Simulation time 21930414005 ps
CPU time 59.63 seconds
Started Jun 13 12:33:08 PM PDT 24
Finished Jun 13 12:34:10 PM PDT 24
Peak memory 254940 kb
Host smart-83ef86d5-a0af-49cd-9fe0-28e4ce06f4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305156897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2305156897
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.793660485
Short name T805
Test name
Test status
Simulation time 18117589787 ps
CPU time 173.52 seconds
Started Jun 13 12:33:07 PM PDT 24
Finished Jun 13 12:36:02 PM PDT 24
Peak memory 254324 kb
Host smart-0f963501-b96f-4dee-b2f2-d6f4377fe236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793660485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.793660485
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2966212619
Short name T534
Test name
Test status
Simulation time 1108777497 ps
CPU time 8.67 seconds
Started Jun 13 12:33:13 PM PDT 24
Finished Jun 13 12:33:24 PM PDT 24
Peak memory 243420 kb
Host smart-ef561147-8094-4c09-9280-7936ea16cb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966212619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2966212619
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3804220885
Short name T885
Test name
Test status
Simulation time 264450551 ps
CPU time 4.71 seconds
Started Jun 13 12:33:06 PM PDT 24
Finished Jun 13 12:33:12 PM PDT 24
Peak memory 225004 kb
Host smart-4d769e48-0f86-4b82-aec3-e944420edd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804220885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3804220885
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.731451950
Short name T54
Test name
Test status
Simulation time 241306775 ps
CPU time 7.15 seconds
Started Jun 13 12:33:12 PM PDT 24
Finished Jun 13 12:33:21 PM PDT 24
Peak memory 233220 kb
Host smart-a61c86f0-fb15-4c52-be24-42e6f4ac4019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731451950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.731451950
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1520037899
Short name T8
Test name
Test status
Simulation time 2231161599 ps
CPU time 9.19 seconds
Started Jun 13 12:33:12 PM PDT 24
Finished Jun 13 12:33:23 PM PDT 24
Peak memory 233372 kb
Host smart-a67590cf-9d6e-4f26-9651-2bcac543975d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520037899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1520037899
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3503752594
Short name T823
Test name
Test status
Simulation time 6300375307 ps
CPU time 10.69 seconds
Started Jun 13 12:33:18 PM PDT 24
Finished Jun 13 12:33:34 PM PDT 24
Peak memory 225152 kb
Host smart-3de7a3e6-f92b-4cdb-93d4-28e162067fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503752594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3503752594
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2617225779
Short name T798
Test name
Test status
Simulation time 705585842 ps
CPU time 8.79 seconds
Started Jun 13 12:33:02 PM PDT 24
Finished Jun 13 12:33:12 PM PDT 24
Peak memory 223604 kb
Host smart-d5d7ee8d-7d27-4a23-b03f-19f578cc6318
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2617225779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2617225779
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1557388385
Short name T155
Test name
Test status
Simulation time 419802253 ps
CPU time 1.17 seconds
Started Jun 13 12:33:05 PM PDT 24
Finished Jun 13 12:33:07 PM PDT 24
Peak memory 207588 kb
Host smart-87ed674a-9d8f-447f-b57c-d215c46f45d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557388385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1557388385
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3638724965
Short name T790
Test name
Test status
Simulation time 3431745715 ps
CPU time 15.52 seconds
Started Jun 13 12:33:10 PM PDT 24
Finished Jun 13 12:33:28 PM PDT 24
Peak memory 217124 kb
Host smart-5bff6cab-65c0-4deb-82e2-8eae001faae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638724965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3638724965
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2817360671
Short name T392
Test name
Test status
Simulation time 6635577854 ps
CPU time 15.61 seconds
Started Jun 13 12:33:21 PM PDT 24
Finished Jun 13 12:33:41 PM PDT 24
Peak memory 216852 kb
Host smart-b1299cfd-a603-4e4a-838f-c611e5150994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817360671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2817360671
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3352717482
Short name T393
Test name
Test status
Simulation time 25452037 ps
CPU time 0.94 seconds
Started Jun 13 12:33:11 PM PDT 24
Finished Jun 13 12:33:14 PM PDT 24
Peak memory 207928 kb
Host smart-ddbba41d-fc93-465e-8958-12bbf94fed30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352717482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3352717482
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1911107741
Short name T537
Test name
Test status
Simulation time 743492112 ps
CPU time 0.94 seconds
Started Jun 13 12:33:11 PM PDT 24
Finished Jun 13 12:33:14 PM PDT 24
Peak memory 206680 kb
Host smart-7e8c75fb-fbbe-460d-bf6f-2e9583cf932f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911107741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1911107741
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1768701310
Short name T447
Test name
Test status
Simulation time 1787267364 ps
CPU time 7.5 seconds
Started Jun 13 12:33:06 PM PDT 24
Finished Jun 13 12:33:15 PM PDT 24
Peak memory 225012 kb
Host smart-7683c60c-cec8-4cd6-8d24-f8aa30e05e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768701310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1768701310
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1075980424
Short name T510
Test name
Test status
Simulation time 18627057 ps
CPU time 0.73 seconds
Started Jun 13 12:33:18 PM PDT 24
Finished Jun 13 12:33:24 PM PDT 24
Peak memory 205940 kb
Host smart-487564ea-5cee-4489-aa59-5ad46c564dc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075980424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1075980424
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2744736365
Short name T479
Test name
Test status
Simulation time 530265468 ps
CPU time 5.09 seconds
Started Jun 13 12:33:08 PM PDT 24
Finished Jun 13 12:33:15 PM PDT 24
Peak memory 225032 kb
Host smart-632b4f3f-1f9e-486d-afd8-083e2a0aea6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744736365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2744736365
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.44682136
Short name T827
Test name
Test status
Simulation time 24563512 ps
CPU time 0.73 seconds
Started Jun 13 12:33:16 PM PDT 24
Finished Jun 13 12:33:22 PM PDT 24
Peak memory 206420 kb
Host smart-a61f8e71-08ad-4c33-b521-80fe34d31dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44682136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.44682136
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1605312315
Short name T159
Test name
Test status
Simulation time 16771655845 ps
CPU time 32.95 seconds
Started Jun 13 12:33:12 PM PDT 24
Finished Jun 13 12:33:48 PM PDT 24
Peak memory 237376 kb
Host smart-4fadca8b-98b4-4928-bde7-59c724656ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605312315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1605312315
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1678700737
Short name T759
Test name
Test status
Simulation time 46080786042 ps
CPU time 205.91 seconds
Started Jun 13 12:33:15 PM PDT 24
Finished Jun 13 12:36:45 PM PDT 24
Peak memory 249852 kb
Host smart-b109d4a9-190f-4567-bbe9-71c3ced6bbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678700737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1678700737
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2303753162
Short name T171
Test name
Test status
Simulation time 6626194001 ps
CPU time 72.52 seconds
Started Jun 13 12:33:09 PM PDT 24
Finished Jun 13 12:34:24 PM PDT 24
Peak memory 241556 kb
Host smart-ab0b0fbc-6847-4543-87a9-730926ab5f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303753162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2303753162
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3449477948
Short name T858
Test name
Test status
Simulation time 275404966 ps
CPU time 5.7 seconds
Started Jun 13 12:33:17 PM PDT 24
Finished Jun 13 12:33:28 PM PDT 24
Peak memory 225056 kb
Host smart-34851319-0688-4edb-aecc-7c1b774aaf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449477948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3449477948
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3657942135
Short name T815
Test name
Test status
Simulation time 725432515 ps
CPU time 7.69 seconds
Started Jun 13 12:33:19 PM PDT 24
Finished Jun 13 12:33:31 PM PDT 24
Peak memory 233268 kb
Host smart-4886836f-bf8d-49e6-a1fe-068eccaa5462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657942135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3657942135
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1741074642
Short name T36
Test name
Test status
Simulation time 5659864066 ps
CPU time 52.46 seconds
Started Jun 13 12:33:00 PM PDT 24
Finished Jun 13 12:33:54 PM PDT 24
Peak memory 236312 kb
Host smart-07d9922a-29a1-4070-92ab-c56ca478870b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741074642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1741074642
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.127131747
Short name T633
Test name
Test status
Simulation time 865661980 ps
CPU time 4.71 seconds
Started Jun 13 12:33:12 PM PDT 24
Finished Jun 13 12:33:19 PM PDT 24
Peak memory 233260 kb
Host smart-684873a7-bd44-45fb-8d44-05ac366d08e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127131747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.127131747
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.221697651
Short name T401
Test name
Test status
Simulation time 1589529062 ps
CPU time 6.28 seconds
Started Jun 13 12:33:15 PM PDT 24
Finished Jun 13 12:33:26 PM PDT 24
Peak memory 224968 kb
Host smart-b695ecac-a90a-459f-8f87-04614f5f56eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221697651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.221697651
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3373404767
Short name T550
Test name
Test status
Simulation time 3321460809 ps
CPU time 16.25 seconds
Started Jun 13 12:33:12 PM PDT 24
Finished Jun 13 12:33:30 PM PDT 24
Peak memory 221196 kb
Host smart-db6aa4a2-a24a-4a5d-a55d-910ad64f651d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3373404767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3373404767
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3208727675
Short name T17
Test name
Test status
Simulation time 417079614 ps
CPU time 0.99 seconds
Started Jun 13 12:33:18 PM PDT 24
Finished Jun 13 12:33:24 PM PDT 24
Peak memory 208180 kb
Host smart-a7e39ed3-e628-483a-b219-9d643fdfce56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208727675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3208727675
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1238858669
Short name T643
Test name
Test status
Simulation time 1006869078 ps
CPU time 10.07 seconds
Started Jun 13 12:33:22 PM PDT 24
Finished Jun 13 12:33:37 PM PDT 24
Peak memory 216928 kb
Host smart-ddfce654-d6b9-4f01-8a02-6d5c3f7db6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238858669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1238858669
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.452069715
Short name T746
Test name
Test status
Simulation time 4793150728 ps
CPU time 14.28 seconds
Started Jun 13 12:33:19 PM PDT 24
Finished Jun 13 12:33:38 PM PDT 24
Peak memory 216876 kb
Host smart-ae4948ed-7f92-4a57-97a4-6f25655bbe6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452069715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.452069715
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3100032020
Short name T381
Test name
Test status
Simulation time 207334839 ps
CPU time 1.32 seconds
Started Jun 13 12:33:20 PM PDT 24
Finished Jun 13 12:33:26 PM PDT 24
Peak memory 208612 kb
Host smart-7baa3ecb-c84b-47df-9b24-55408e510ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100032020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3100032020
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2094615196
Short name T839
Test name
Test status
Simulation time 59571417 ps
CPU time 0.83 seconds
Started Jun 13 12:33:11 PM PDT 24
Finished Jun 13 12:33:14 PM PDT 24
Peak memory 206188 kb
Host smart-dba26052-8a6d-4c21-85dc-940efd322eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094615196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2094615196
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.260484237
Short name T416
Test name
Test status
Simulation time 2796758800 ps
CPU time 10.4 seconds
Started Jun 13 12:32:58 PM PDT 24
Finished Jun 13 12:33:10 PM PDT 24
Peak memory 233312 kb
Host smart-81f0913d-df5f-45e9-8574-9ccf40f1789b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260484237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.260484237
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3691084645
Short name T371
Test name
Test status
Simulation time 15280109 ps
CPU time 0.74 seconds
Started Jun 13 12:33:15 PM PDT 24
Finished Jun 13 12:33:19 PM PDT 24
Peak memory 204576 kb
Host smart-1becaca3-f489-4a6c-8e9d-ca9ec6683965
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691084645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3691084645
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3750731773
Short name T699
Test name
Test status
Simulation time 283828921 ps
CPU time 2.6 seconds
Started Jun 13 12:33:11 PM PDT 24
Finished Jun 13 12:33:28 PM PDT 24
Peak memory 233076 kb
Host smart-716fd405-b701-4c92-acf5-cc7f5126656e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750731773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3750731773
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3281323153
Short name T331
Test name
Test status
Simulation time 17706567 ps
CPU time 0.79 seconds
Started Jun 13 12:33:12 PM PDT 24
Finished Jun 13 12:33:15 PM PDT 24
Peak memory 207000 kb
Host smart-1772441a-ad8a-4849-aec9-97a70af95ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281323153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3281323153
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3314176651
Short name T595
Test name
Test status
Simulation time 1907269946 ps
CPU time 38.23 seconds
Started Jun 13 12:33:16 PM PDT 24
Finished Jun 13 12:33:58 PM PDT 24
Peak memory 249712 kb
Host smart-efb0ab9f-888a-433f-a0bc-f1dd98748a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314176651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3314176651
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3600371585
Short name T156
Test name
Test status
Simulation time 185794377606 ps
CPU time 461.34 seconds
Started Jun 13 12:33:05 PM PDT 24
Finished Jun 13 12:40:48 PM PDT 24
Peak memory 257964 kb
Host smart-351c1935-ca38-44b0-b51b-0f2aa1ca7310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600371585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3600371585
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2004730407
Short name T42
Test name
Test status
Simulation time 12500234388 ps
CPU time 116.95 seconds
Started Jun 13 12:33:16 PM PDT 24
Finished Jun 13 12:35:18 PM PDT 24
Peak memory 240652 kb
Host smart-1fd4a170-baa5-4e8d-a766-ef269e8a4e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004730407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2004730407
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1768308525
Short name T312
Test name
Test status
Simulation time 12145108185 ps
CPU time 30.11 seconds
Started Jun 13 12:33:31 PM PDT 24
Finished Jun 13 12:34:02 PM PDT 24
Peak memory 233352 kb
Host smart-eccfe549-bbbb-4da0-bf78-61dc86434f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768308525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1768308525
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2256205358
Short name T448
Test name
Test status
Simulation time 16161300515 ps
CPU time 15.68 seconds
Started Jun 13 12:33:14 PM PDT 24
Finished Jun 13 12:33:32 PM PDT 24
Peak memory 233264 kb
Host smart-f06889b2-65a5-4c5c-a620-437d96a4c5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256205358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2256205358
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3992790329
Short name T263
Test name
Test status
Simulation time 3008635983 ps
CPU time 25.94 seconds
Started Jun 13 12:33:14 PM PDT 24
Finished Jun 13 12:33:44 PM PDT 24
Peak memory 229468 kb
Host smart-6bfe6e8f-9dfe-48c2-9a9c-585492af066e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992790329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3992790329
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1748286576
Short name T290
Test name
Test status
Simulation time 13195316956 ps
CPU time 11.31 seconds
Started Jun 13 12:33:12 PM PDT 24
Finished Jun 13 12:33:26 PM PDT 24
Peak memory 225056 kb
Host smart-2fbc65ed-bed7-4d7e-b657-dfcb59d76e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748286576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1748286576
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3465769609
Short name T139
Test name
Test status
Simulation time 1904758414 ps
CPU time 9.03 seconds
Started Jun 13 12:33:09 PM PDT 24
Finished Jun 13 12:33:21 PM PDT 24
Peak memory 233268 kb
Host smart-6422ef36-cc1d-493e-9a07-bb326660fcfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465769609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3465769609
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2039674983
Short name T504
Test name
Test status
Simulation time 530760901 ps
CPU time 3.86 seconds
Started Jun 13 12:33:09 PM PDT 24
Finished Jun 13 12:33:15 PM PDT 24
Peak memory 219064 kb
Host smart-57fa12b8-8990-48ed-ad5a-88bb9df76616
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2039674983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2039674983
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3016757688
Short name T161
Test name
Test status
Simulation time 13411388769 ps
CPU time 21.65 seconds
Started Jun 13 12:33:11 PM PDT 24
Finished Jun 13 12:33:35 PM PDT 24
Peak memory 217152 kb
Host smart-9d8651f3-6230-483b-ba2e-e39d0e8c3c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016757688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3016757688
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.41123135
Short name T842
Test name
Test status
Simulation time 892922511 ps
CPU time 6.18 seconds
Started Jun 13 12:33:00 PM PDT 24
Finished Jun 13 12:33:08 PM PDT 24
Peak memory 216788 kb
Host smart-2e4a0f1f-9c4b-4dd6-a8d2-2b71ec12fd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41123135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.41123135
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.609254919
Short name T624
Test name
Test status
Simulation time 25712973 ps
CPU time 0.72 seconds
Started Jun 13 12:33:19 PM PDT 24
Finished Jun 13 12:33:25 PM PDT 24
Peak memory 206420 kb
Host smart-4d83b24f-20da-4311-9f00-3c1086cda558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609254919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.609254919
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.4158592453
Short name T512
Test name
Test status
Simulation time 25533800 ps
CPU time 0.82 seconds
Started Jun 13 12:33:08 PM PDT 24
Finished Jun 13 12:33:12 PM PDT 24
Peak memory 205612 kb
Host smart-4a2c1b59-249e-4822-b466-0f1b7a0b160d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158592453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.4158592453
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1605306674
Short name T567
Test name
Test status
Simulation time 68622354948 ps
CPU time 41.58 seconds
Started Jun 13 12:33:15 PM PDT 24
Finished Jun 13 12:34:00 PM PDT 24
Peak memory 233616 kb
Host smart-42479536-8014-48d2-9bf0-4d097924c4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605306674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1605306674
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1271554297
Short name T384
Test name
Test status
Simulation time 26561682 ps
CPU time 0.67 seconds
Started Jun 13 12:33:23 PM PDT 24
Finished Jun 13 12:33:28 PM PDT 24
Peak memory 205976 kb
Host smart-0e01b84c-8bbd-4f0f-9286-7d35cc669028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271554297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1271554297
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2139655916
Short name T186
Test name
Test status
Simulation time 5254065077 ps
CPU time 18.29 seconds
Started Jun 13 12:33:21 PM PDT 24
Finished Jun 13 12:33:44 PM PDT 24
Peak memory 225152 kb
Host smart-c7b80ac8-41dc-436a-b8a5-d5cd9b69feca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139655916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2139655916
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1814675220
Short name T773
Test name
Test status
Simulation time 49716702 ps
CPU time 0.86 seconds
Started Jun 13 12:33:16 PM PDT 24
Finished Jun 13 12:33:21 PM PDT 24
Peak memory 207136 kb
Host smart-3be21199-bf4c-4615-98eb-0f89b89eb2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814675220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1814675220
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1826671606
Short name T214
Test name
Test status
Simulation time 120505822871 ps
CPU time 227.52 seconds
Started Jun 13 12:33:02 PM PDT 24
Finished Jun 13 12:36:50 PM PDT 24
Peak memory 254556 kb
Host smart-b90afd35-5875-4447-939a-a18f3db699b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826671606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1826671606
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1138619302
Short name T176
Test name
Test status
Simulation time 43963477044 ps
CPU time 189.72 seconds
Started Jun 13 12:33:09 PM PDT 24
Finished Jun 13 12:36:21 PM PDT 24
Peak memory 251120 kb
Host smart-38ddb2b6-9dbd-4b9f-8af3-da80a325ae70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138619302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1138619302
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2244166242
Short name T849
Test name
Test status
Simulation time 475309661 ps
CPU time 6.76 seconds
Started Jun 13 12:33:28 PM PDT 24
Finished Jun 13 12:33:37 PM PDT 24
Peak memory 225080 kb
Host smart-9e9d8ac0-eb78-4056-94d8-c83c7df4fffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244166242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2244166242
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1151566368
Short name T764
Test name
Test status
Simulation time 7525720037 ps
CPU time 35.76 seconds
Started Jun 13 12:33:16 PM PDT 24
Finished Jun 13 12:33:56 PM PDT 24
Peak memory 233308 kb
Host smart-e854d232-f682-4b9a-bba9-0a34442a9e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151566368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1151566368
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1682521076
Short name T629
Test name
Test status
Simulation time 201296513 ps
CPU time 4.89 seconds
Started Jun 13 12:33:16 PM PDT 24
Finished Jun 13 12:33:25 PM PDT 24
Peak memory 225040 kb
Host smart-d0958eed-39ec-4883-bd6d-4fdb9787cb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682521076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1682521076
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1172881851
Short name T946
Test name
Test status
Simulation time 2420218390 ps
CPU time 9.89 seconds
Started Jun 13 12:33:19 PM PDT 24
Finished Jun 13 12:33:34 PM PDT 24
Peak memory 224296 kb
Host smart-3fa11017-7097-4677-87fa-569e20e3889d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172881851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1172881851
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3761964050
Short name T658
Test name
Test status
Simulation time 46299047749 ps
CPU time 33.2 seconds
Started Jun 13 12:33:15 PM PDT 24
Finished Jun 13 12:33:53 PM PDT 24
Peak memory 249268 kb
Host smart-e15839b3-2329-4dfa-b43b-2d5f6047a1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761964050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3761964050
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3216992539
Short name T651
Test name
Test status
Simulation time 1075567037 ps
CPU time 5.45 seconds
Started Jun 13 12:33:20 PM PDT 24
Finished Jun 13 12:33:30 PM PDT 24
Peak memory 223500 kb
Host smart-d2180b76-493f-482c-a999-a463490a0071
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3216992539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3216992539
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1998094655
Short name T154
Test name
Test status
Simulation time 34737371970 ps
CPU time 115.07 seconds
Started Jun 13 12:33:28 PM PDT 24
Finished Jun 13 12:35:25 PM PDT 24
Peak memory 253912 kb
Host smart-e9852cea-b2e1-486f-921e-e130de7a8090
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998094655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1998094655
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2098593232
Short name T838
Test name
Test status
Simulation time 1436904882 ps
CPU time 11.7 seconds
Started Jun 13 12:33:17 PM PDT 24
Finished Jun 13 12:33:34 PM PDT 24
Peak memory 216832 kb
Host smart-159364c0-0fe7-459e-a88c-8b588054dcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098593232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2098593232
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3986226010
Short name T680
Test name
Test status
Simulation time 6193493625 ps
CPU time 17.97 seconds
Started Jun 13 12:33:10 PM PDT 24
Finished Jun 13 12:33:30 PM PDT 24
Peak memory 216692 kb
Host smart-6027d350-d75c-4ea9-a5e8-16d4639a8cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986226010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3986226010
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3153403565
Short name T729
Test name
Test status
Simulation time 59655454 ps
CPU time 1.46 seconds
Started Jun 13 12:33:15 PM PDT 24
Finished Jun 13 12:33:21 PM PDT 24
Peak memory 216788 kb
Host smart-b3f5da7a-5790-442b-85bb-d4dbdce70e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153403565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3153403565
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.925578860
Short name T757
Test name
Test status
Simulation time 30486466 ps
CPU time 0.78 seconds
Started Jun 13 12:33:10 PM PDT 24
Finished Jun 13 12:33:13 PM PDT 24
Peak memory 206452 kb
Host smart-19cfbc63-b85d-47a3-ad82-1ca0229034cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925578860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.925578860
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.4223592904
Short name T769
Test name
Test status
Simulation time 16067532960 ps
CPU time 21.29 seconds
Started Jun 13 12:33:21 PM PDT 24
Finished Jun 13 12:33:46 PM PDT 24
Peak memory 241500 kb
Host smart-f3850007-4fae-484c-bca4-0519ca5efa06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223592904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.4223592904
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.967686257
Short name T63
Test name
Test status
Simulation time 22310397 ps
CPU time 0.69 seconds
Started Jun 13 12:33:22 PM PDT 24
Finished Jun 13 12:33:27 PM PDT 24
Peak memory 206312 kb
Host smart-b255aaa4-8d44-4007-9d8e-c1367645c22e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967686257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.967686257
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1607563935
Short name T917
Test name
Test status
Simulation time 2076122377 ps
CPU time 6.11 seconds
Started Jun 13 12:33:28 PM PDT 24
Finished Jun 13 12:33:36 PM PDT 24
Peak memory 225048 kb
Host smart-a4d237c5-a74a-4c10-99cb-48a20e0e941b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607563935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1607563935
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.4266871061
Short name T449
Test name
Test status
Simulation time 20086921 ps
CPU time 0.83 seconds
Started Jun 13 12:33:32 PM PDT 24
Finished Jun 13 12:33:34 PM PDT 24
Peak memory 207148 kb
Host smart-8123fa40-252e-4ade-ac5a-cebc09a09677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266871061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.4266871061
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.944772222
Short name T660
Test name
Test status
Simulation time 5748865379 ps
CPU time 77.44 seconds
Started Jun 13 12:33:20 PM PDT 24
Finished Jun 13 12:34:42 PM PDT 24
Peak memory 257660 kb
Host smart-b8dc0166-e05b-4c73-a23f-49c54ea5e022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944772222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.944772222
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3709304805
Short name T947
Test name
Test status
Simulation time 22093186249 ps
CPU time 87.47 seconds
Started Jun 13 12:33:43 PM PDT 24
Finished Jun 13 12:35:11 PM PDT 24
Peak memory 262812 kb
Host smart-71aa6c4c-1cef-4a8b-9244-ba6ed265b4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709304805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3709304805
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.882577457
Short name T217
Test name
Test status
Simulation time 25261036735 ps
CPU time 249.51 seconds
Started Jun 13 12:33:16 PM PDT 24
Finished Jun 13 12:37:29 PM PDT 24
Peak memory 249916 kb
Host smart-242646a6-038a-411b-83ab-dfa424a244f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882577457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.882577457
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2319892297
Short name T82
Test name
Test status
Simulation time 32053493 ps
CPU time 2.33 seconds
Started Jun 13 12:33:06 PM PDT 24
Finished Jun 13 12:33:09 PM PDT 24
Peak memory 233256 kb
Host smart-32a7bc9f-626a-4a63-a5a8-966145368d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319892297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2319892297
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.404844870
Short name T661
Test name
Test status
Simulation time 11151204266 ps
CPU time 22.05 seconds
Started Jun 13 12:33:19 PM PDT 24
Finished Jun 13 12:33:46 PM PDT 24
Peak memory 233352 kb
Host smart-617b584b-5b52-46a1-b669-1e40702f0ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404844870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.404844870
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3119155387
Short name T880
Test name
Test status
Simulation time 207798575 ps
CPU time 3.87 seconds
Started Jun 13 12:33:17 PM PDT 24
Finished Jun 13 12:33:26 PM PDT 24
Peak memory 219240 kb
Host smart-108ce04b-eba2-4698-9531-c9b845f340a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119155387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3119155387
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2218036132
Short name T852
Test name
Test status
Simulation time 411717917 ps
CPU time 3.44 seconds
Started Jun 13 12:33:09 PM PDT 24
Finished Jun 13 12:33:15 PM PDT 24
Peak memory 233260 kb
Host smart-de5586a0-b237-41a5-85a8-2bb535029770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218036132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2218036132
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3133081088
Short name T602
Test name
Test status
Simulation time 1222879961 ps
CPU time 5.3 seconds
Started Jun 13 12:33:12 PM PDT 24
Finished Jun 13 12:33:19 PM PDT 24
Peak memory 224856 kb
Host smart-fe4bbc3c-9a30-4965-9511-784b76236c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133081088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3133081088
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1980060155
Short name T754
Test name
Test status
Simulation time 8734692399 ps
CPU time 16.31 seconds
Started Jun 13 12:33:13 PM PDT 24
Finished Jun 13 12:33:31 PM PDT 24
Peak memory 220436 kb
Host smart-d612a95c-ce83-4653-ae46-7a3fa0ee6eb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1980060155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1980060155
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1011339040
Short name T949
Test name
Test status
Simulation time 15926887194 ps
CPU time 58.81 seconds
Started Jun 13 12:33:12 PM PDT 24
Finished Jun 13 12:34:13 PM PDT 24
Peak memory 254688 kb
Host smart-67ac5778-b7e1-4f91-8b25-b617c0cf8935
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011339040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1011339040
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2761775550
Short name T578
Test name
Test status
Simulation time 5716463741 ps
CPU time 33.07 seconds
Started Jun 13 12:33:22 PM PDT 24
Finished Jun 13 12:33:59 PM PDT 24
Peak memory 220828 kb
Host smart-be1fa796-4d73-4e2b-ab79-dd4533a62404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761775550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2761775550
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2541467541
Short name T356
Test name
Test status
Simulation time 24312045 ps
CPU time 0.7 seconds
Started Jun 13 12:33:15 PM PDT 24
Finished Jun 13 12:33:19 PM PDT 24
Peak memory 206224 kb
Host smart-2c3c2b04-6dc4-473e-b217-774e6dfc1bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541467541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2541467541
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2426590860
Short name T497
Test name
Test status
Simulation time 205451634 ps
CPU time 2.66 seconds
Started Jun 13 12:33:15 PM PDT 24
Finished Jun 13 12:33:22 PM PDT 24
Peak memory 216792 kb
Host smart-15cf92f5-a972-4af9-b6c3-79c8fe5b595b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426590860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2426590860
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2663419178
Short name T348
Test name
Test status
Simulation time 113175754 ps
CPU time 0.81 seconds
Started Jun 13 12:33:42 PM PDT 24
Finished Jun 13 12:33:44 PM PDT 24
Peak memory 206452 kb
Host smart-2412047a-ca3c-45a1-9760-510dbba5b947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663419178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2663419178
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1806761097
Short name T871
Test name
Test status
Simulation time 138545063 ps
CPU time 2.41 seconds
Started Jun 13 12:33:18 PM PDT 24
Finished Jun 13 12:33:25 PM PDT 24
Peak memory 233068 kb
Host smart-553953c8-89a4-4e55-b13a-c044c3743327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806761097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1806761097
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2265975597
Short name T525
Test name
Test status
Simulation time 15641162 ps
CPU time 0.74 seconds
Started Jun 13 12:33:17 PM PDT 24
Finished Jun 13 12:33:22 PM PDT 24
Peak memory 206412 kb
Host smart-b86da6df-1bd9-4fee-9fdc-10a06ffb1585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265975597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2265975597
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3501292940
Short name T276
Test name
Test status
Simulation time 5036599134 ps
CPU time 19.87 seconds
Started Jun 13 12:33:14 PM PDT 24
Finished Jun 13 12:33:37 PM PDT 24
Peak memory 233336 kb
Host smart-ec14073f-de4f-4e77-84bf-0fe167a50128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501292940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3501292940
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2135158568
Short name T657
Test name
Test status
Simulation time 72175880 ps
CPU time 0.79 seconds
Started Jun 13 12:33:05 PM PDT 24
Finished Jun 13 12:33:07 PM PDT 24
Peak memory 207144 kb
Host smart-c210fd56-284a-45de-8996-ac0947b45430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135158568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2135158568
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.31287216
Short name T470
Test name
Test status
Simulation time 88172918 ps
CPU time 0.87 seconds
Started Jun 13 12:33:19 PM PDT 24
Finished Jun 13 12:33:25 PM PDT 24
Peak memory 216416 kb
Host smart-615bc9eb-e985-46a4-8cae-2b914de930ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31287216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.31287216
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3809776177
Short name T177
Test name
Test status
Simulation time 6899947147 ps
CPU time 93.72 seconds
Started Jun 13 12:33:29 PM PDT 24
Finished Jun 13 12:35:04 PM PDT 24
Peak memory 253624 kb
Host smart-fc7695a8-435a-4414-b927-35b67ce41003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809776177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3809776177
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.4120560826
Short name T230
Test name
Test status
Simulation time 15292829441 ps
CPU time 106.04 seconds
Started Jun 13 12:33:15 PM PDT 24
Finished Jun 13 12:35:04 PM PDT 24
Peak memory 264388 kb
Host smart-c9f1ed9e-11ad-4af7-bf67-ea41fd9b213d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120560826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.4120560826
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2483665235
Short name T296
Test name
Test status
Simulation time 279689112 ps
CPU time 9.54 seconds
Started Jun 13 12:33:16 PM PDT 24
Finished Jun 13 12:33:30 PM PDT 24
Peak memory 241548 kb
Host smart-7db105a6-3234-4d0f-8fc7-eabba00d9e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483665235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2483665235
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.4171733590
Short name T251
Test name
Test status
Simulation time 3209591394 ps
CPU time 9.24 seconds
Started Jun 13 12:33:19 PM PDT 24
Finished Jun 13 12:33:33 PM PDT 24
Peak memory 229500 kb
Host smart-c469140d-166c-4a48-8fad-0a6c38c4a57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171733590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.4171733590
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2584030332
Short name T295
Test name
Test status
Simulation time 406019728 ps
CPU time 3.66 seconds
Started Jun 13 12:33:15 PM PDT 24
Finished Jun 13 12:33:22 PM PDT 24
Peak memory 225032 kb
Host smart-226e963f-4a33-44ec-b647-892fc7ca54d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584030332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2584030332
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.978049882
Short name T777
Test name
Test status
Simulation time 4120872241 ps
CPU time 7.05 seconds
Started Jun 13 12:33:15 PM PDT 24
Finished Jun 13 12:33:26 PM PDT 24
Peak memory 225140 kb
Host smart-9cfe668f-ddfb-41c8-b4b0-6b2be9e453ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978049882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.978049882
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.367485309
Short name T376
Test name
Test status
Simulation time 3613815484 ps
CPU time 6.98 seconds
Started Jun 13 12:33:09 PM PDT 24
Finished Jun 13 12:33:18 PM PDT 24
Peak memory 233340 kb
Host smart-c72679db-713f-4201-9cc4-950334ecf94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367485309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.367485309
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3342885517
Short name T926
Test name
Test status
Simulation time 2728222749 ps
CPU time 3.94 seconds
Started Jun 13 12:33:18 PM PDT 24
Finished Jun 13 12:33:27 PM PDT 24
Peak memory 221228 kb
Host smart-7edf4627-2ad6-49ef-bfa6-28413fb206c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3342885517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3342885517
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1553567270
Short name T32
Test name
Test status
Simulation time 43953408090 ps
CPU time 150.13 seconds
Started Jun 13 12:33:19 PM PDT 24
Finished Jun 13 12:35:54 PM PDT 24
Peak memory 254248 kb
Host smart-f6c516be-ba28-4e4d-90d5-a9afb5e419f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553567270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1553567270
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1211496694
Short name T43
Test name
Test status
Simulation time 5307747989 ps
CPU time 37.63 seconds
Started Jun 13 12:33:18 PM PDT 24
Finished Jun 13 12:34:01 PM PDT 24
Peak memory 216920 kb
Host smart-75b3726e-b19b-4271-8958-1eb044b1a064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211496694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1211496694
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.178032359
Short name T482
Test name
Test status
Simulation time 1944484618 ps
CPU time 4.28 seconds
Started Jun 13 12:33:12 PM PDT 24
Finished Jun 13 12:33:18 PM PDT 24
Peak memory 216876 kb
Host smart-b0d60a92-f34d-4456-85b5-5f25d59cf9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178032359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.178032359
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3472415734
Short name T439
Test name
Test status
Simulation time 27334090 ps
CPU time 0.82 seconds
Started Jun 13 12:33:24 PM PDT 24
Finished Jun 13 12:33:28 PM PDT 24
Peak memory 207108 kb
Host smart-0aafd61c-caae-4eab-b500-6836af296497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472415734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3472415734
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.415835342
Short name T383
Test name
Test status
Simulation time 24431125 ps
CPU time 0.76 seconds
Started Jun 13 12:33:09 PM PDT 24
Finished Jun 13 12:33:12 PM PDT 24
Peak memory 206188 kb
Host smart-70bf14b2-2894-4de8-908c-f3b627a0b7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415835342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.415835342
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.973274175
Short name T690
Test name
Test status
Simulation time 171411262 ps
CPU time 2.33 seconds
Started Jun 13 12:33:25 PM PDT 24
Finished Jun 13 12:33:31 PM PDT 24
Peak memory 224360 kb
Host smart-8df43644-7f31-408b-b582-fdf6d6f4b574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973274175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.973274175
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.824436997
Short name T583
Test name
Test status
Simulation time 12667024 ps
CPU time 0.74 seconds
Started Jun 13 12:33:09 PM PDT 24
Finished Jun 13 12:33:12 PM PDT 24
Peak memory 206360 kb
Host smart-8bc3b272-0c49-4642-b17f-ad103b838d79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824436997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.824436997
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2869856861
Short name T689
Test name
Test status
Simulation time 166571945 ps
CPU time 3.92 seconds
Started Jun 13 12:33:17 PM PDT 24
Finished Jun 13 12:33:27 PM PDT 24
Peak memory 233200 kb
Host smart-195f8dad-bdcf-4387-b16a-39980fe97b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869856861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2869856861
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3069357615
Short name T26
Test name
Test status
Simulation time 21853605 ps
CPU time 0.79 seconds
Started Jun 13 12:33:16 PM PDT 24
Finished Jun 13 12:33:21 PM PDT 24
Peak memory 207168 kb
Host smart-e0ec8c11-ca39-4521-9456-851c12136ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069357615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3069357615
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.648564477
Short name T628
Test name
Test status
Simulation time 5274187010 ps
CPU time 23.67 seconds
Started Jun 13 12:33:20 PM PDT 24
Finished Jun 13 12:33:49 PM PDT 24
Peak memory 241572 kb
Host smart-00abe36b-4de1-4f90-8eb5-0c5bfe260066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648564477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.648564477
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1158613949
Short name T631
Test name
Test status
Simulation time 2504224796 ps
CPU time 24 seconds
Started Jun 13 12:33:14 PM PDT 24
Finished Jun 13 12:33:42 PM PDT 24
Peak memory 236424 kb
Host smart-ed6c39d5-47c4-44d8-b432-5a7779d49cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158613949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1158613949
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3904888212
Short name T708
Test name
Test status
Simulation time 9548184128 ps
CPU time 14.8 seconds
Started Jun 13 12:33:22 PM PDT 24
Finished Jun 13 12:33:41 PM PDT 24
Peak memory 233328 kb
Host smart-c9e19f94-8ec5-486a-b3a9-b99de53171eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904888212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3904888212
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.4278786707
Short name T645
Test name
Test status
Simulation time 77815453 ps
CPU time 2.21 seconds
Started Jun 13 12:33:14 PM PDT 24
Finished Jun 13 12:33:19 PM PDT 24
Peak memory 223736 kb
Host smart-cab935cb-3232-459d-8496-7a732ec47f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278786707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.4278786707
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3052180791
Short name T675
Test name
Test status
Simulation time 3194076619 ps
CPU time 15.69 seconds
Started Jun 13 12:33:11 PM PDT 24
Finished Jun 13 12:33:36 PM PDT 24
Peak memory 233288 kb
Host smart-84982563-fb1e-440f-8efa-87e83caac398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052180791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3052180791
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.968635548
Short name T637
Test name
Test status
Simulation time 715073243 ps
CPU time 4.11 seconds
Started Jun 13 12:33:24 PM PDT 24
Finished Jun 13 12:33:32 PM PDT 24
Peak memory 233256 kb
Host smart-6c8ef3af-6168-4ccf-aff0-d735d881ec70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968635548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.968635548
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.361253103
Short name T927
Test name
Test status
Simulation time 115463100 ps
CPU time 2.52 seconds
Started Jun 13 12:33:14 PM PDT 24
Finished Jun 13 12:33:20 PM PDT 24
Peak memory 233104 kb
Host smart-cd96d534-e941-4e9d-8015-7b9e6daba481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361253103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.361253103
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2083782848
Short name T345
Test name
Test status
Simulation time 688116245 ps
CPU time 6.01 seconds
Started Jun 13 12:33:17 PM PDT 24
Finished Jun 13 12:33:29 PM PDT 24
Peak memory 223608 kb
Host smart-8ad2a8e0-e777-4949-9541-a8842d3b4970
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2083782848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2083782848
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.51745834
Short name T168
Test name
Test status
Simulation time 200608590919 ps
CPU time 397.48 seconds
Started Jun 13 12:33:23 PM PDT 24
Finished Jun 13 12:40:05 PM PDT 24
Peak memory 266188 kb
Host smart-9fff265a-0666-46d2-b215-ef4326255108
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51745834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress
_all.51745834
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.738211391
Short name T427
Test name
Test status
Simulation time 4674214819 ps
CPU time 8.62 seconds
Started Jun 13 12:33:21 PM PDT 24
Finished Jun 13 12:33:34 PM PDT 24
Peak memory 216852 kb
Host smart-4a3a7bfe-0c3c-4e50-b253-6828617cf227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738211391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.738211391
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.4210115476
Short name T1
Test name
Test status
Simulation time 6057086425 ps
CPU time 16.22 seconds
Started Jun 13 12:33:34 PM PDT 24
Finished Jun 13 12:33:51 PM PDT 24
Peak memory 216956 kb
Host smart-ed0a65af-4e44-441e-a601-88c93f2e0261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210115476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.4210115476
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.905454335
Short name T387
Test name
Test status
Simulation time 49494208 ps
CPU time 1.02 seconds
Started Jun 13 12:33:17 PM PDT 24
Finished Jun 13 12:33:23 PM PDT 24
Peak memory 207512 kb
Host smart-3e18f617-eff8-40be-9dff-d4fb704ec9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905454335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.905454335
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2252533084
Short name T389
Test name
Test status
Simulation time 22794979 ps
CPU time 0.78 seconds
Started Jun 13 12:33:33 PM PDT 24
Finished Jun 13 12:33:35 PM PDT 24
Peak memory 206456 kb
Host smart-8af7a822-e4ef-4fe7-99a5-48e660d501b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252533084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2252533084
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.979683731
Short name T77
Test name
Test status
Simulation time 255437700 ps
CPU time 3.02 seconds
Started Jun 13 12:33:19 PM PDT 24
Finished Jun 13 12:33:27 PM PDT 24
Peak memory 233268 kb
Host smart-de1809c9-6adf-467d-8d6a-852c2c2b7970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979683731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.979683731
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3361418852
Short name T811
Test name
Test status
Simulation time 62683351 ps
CPU time 0.74 seconds
Started Jun 13 12:33:30 PM PDT 24
Finished Jun 13 12:33:32 PM PDT 24
Peak memory 206308 kb
Host smart-63980c24-5cc1-4fa0-aa61-bbc46da5fadd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361418852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3361418852
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.764915122
Short name T193
Test name
Test status
Simulation time 142355823 ps
CPU time 2.21 seconds
Started Jun 13 12:33:25 PM PDT 24
Finished Jun 13 12:33:30 PM PDT 24
Peak memory 224984 kb
Host smart-84153ed0-3723-4c81-86f2-22789048899a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764915122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.764915122
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2331675427
Short name T728
Test name
Test status
Simulation time 15454010 ps
CPU time 0.8 seconds
Started Jun 13 12:33:14 PM PDT 24
Finished Jun 13 12:33:18 PM PDT 24
Peak memory 207172 kb
Host smart-8e0bd16e-38a8-4014-9faf-89d2471ad77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331675427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2331675427
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1661087061
Short name T5
Test name
Test status
Simulation time 6638778874 ps
CPU time 97.89 seconds
Started Jun 13 12:33:31 PM PDT 24
Finished Jun 13 12:35:09 PM PDT 24
Peak memory 249772 kb
Host smart-c7761dc7-e7a4-454f-a6e3-60c0e2be999e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661087061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1661087061
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3700492760
Short name T409
Test name
Test status
Simulation time 229871172 ps
CPU time 7.48 seconds
Started Jun 13 12:33:35 PM PDT 24
Finished Jun 13 12:33:43 PM PDT 24
Peak memory 233260 kb
Host smart-8b297e91-88fa-4129-8cce-eb0b67c7bf52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700492760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3700492760
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2639589079
Short name T594
Test name
Test status
Simulation time 102487382 ps
CPU time 2.41 seconds
Started Jun 13 12:33:39 PM PDT 24
Finished Jun 13 12:33:42 PM PDT 24
Peak memory 233040 kb
Host smart-04ab1e4f-5e07-44a0-8bf2-487098ee6e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639589079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2639589079
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2818069301
Short name T311
Test name
Test status
Simulation time 1186831105 ps
CPU time 14.44 seconds
Started Jun 13 12:33:22 PM PDT 24
Finished Jun 13 12:33:41 PM PDT 24
Peak memory 225048 kb
Host smart-1dfdbeff-565c-4db5-ae34-fa70ccd68c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818069301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2818069301
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1646416102
Short name T267
Test name
Test status
Simulation time 81234027 ps
CPU time 2.22 seconds
Started Jun 13 12:33:28 PM PDT 24
Finished Jun 13 12:33:32 PM PDT 24
Peak memory 233284 kb
Host smart-f9529e50-11b3-493c-bba2-6d21d3272c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646416102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1646416102
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.364073305
Short name T283
Test name
Test status
Simulation time 627548802 ps
CPU time 5.38 seconds
Started Jun 13 12:33:31 PM PDT 24
Finished Jun 13 12:33:38 PM PDT 24
Peak memory 225096 kb
Host smart-5ed0b69f-b190-41d7-a492-37b40980ffe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364073305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.364073305
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.486825372
Short name T698
Test name
Test status
Simulation time 944235776 ps
CPU time 11.88 seconds
Started Jun 13 12:33:34 PM PDT 24
Finished Jun 13 12:33:47 PM PDT 24
Peak memory 223480 kb
Host smart-c795ed50-8c13-4ffa-8e68-c8023219cb99
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=486825372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.486825372
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3133152902
Short name T875
Test name
Test status
Simulation time 134387279028 ps
CPU time 269.38 seconds
Started Jun 13 12:33:26 PM PDT 24
Finished Jun 13 12:37:59 PM PDT 24
Peak memory 250212 kb
Host smart-8bd0a043-a1a1-456b-a0a1-2b9648043d68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133152902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3133152902
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.127150314
Short name T434
Test name
Test status
Simulation time 7105761362 ps
CPU time 41.47 seconds
Started Jun 13 12:33:22 PM PDT 24
Finished Jun 13 12:34:08 PM PDT 24
Peak memory 216868 kb
Host smart-dfd710ff-bd1a-4077-b503-dc09d36b3778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127150314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.127150314
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3917584551
Short name T11
Test name
Test status
Simulation time 607056778 ps
CPU time 2.99 seconds
Started Jun 13 12:33:16 PM PDT 24
Finished Jun 13 12:33:23 PM PDT 24
Peak memory 216804 kb
Host smart-603fdb57-a7af-4e91-8027-9dabb4c45867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917584551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3917584551
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2096636065
Short name T922
Test name
Test status
Simulation time 1236467917 ps
CPU time 6.15 seconds
Started Jun 13 12:33:19 PM PDT 24
Finished Jun 13 12:33:31 PM PDT 24
Peak memory 216872 kb
Host smart-79154a62-0d5e-4e52-a28b-d093aea939e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096636065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2096636065
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.178214134
Short name T320
Test name
Test status
Simulation time 227461574 ps
CPU time 0.93 seconds
Started Jun 13 12:33:18 PM PDT 24
Finished Jun 13 12:33:24 PM PDT 24
Peak memory 206472 kb
Host smart-a0f83bca-f6e8-4e86-897e-1e1bec5f6a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178214134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.178214134
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.4282511536
Short name T934
Test name
Test status
Simulation time 2592098741 ps
CPU time 13.19 seconds
Started Jun 13 12:33:20 PM PDT 24
Finished Jun 13 12:33:38 PM PDT 24
Peak memory 241216 kb
Host smart-391f796e-9ebd-4793-9820-d57bd72a7784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282511536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.4282511536
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2298234692
Short name T856
Test name
Test status
Simulation time 15554939 ps
CPU time 0.74 seconds
Started Jun 13 12:32:39 PM PDT 24
Finished Jun 13 12:32:42 PM PDT 24
Peak memory 205984 kb
Host smart-b8d16bad-4a81-4398-9d03-c113f773b9ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298234692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
298234692
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.4214636757
Short name T438
Test name
Test status
Simulation time 135387394 ps
CPU time 2.36 seconds
Started Jun 13 12:32:26 PM PDT 24
Finished Jun 13 12:32:31 PM PDT 24
Peak memory 225024 kb
Host smart-62db4ff5-5734-444e-8266-1b1af59588f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214636757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.4214636757
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3851483299
Short name T522
Test name
Test status
Simulation time 63110024 ps
CPU time 0.77 seconds
Started Jun 13 12:32:14 PM PDT 24
Finished Jun 13 12:32:17 PM PDT 24
Peak memory 207160 kb
Host smart-d78be312-445f-4a69-a51d-e21b3b1da91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851483299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3851483299
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.860508372
Short name T215
Test name
Test status
Simulation time 16863154584 ps
CPU time 79.83 seconds
Started Jun 13 12:32:18 PM PDT 24
Finished Jun 13 12:33:40 PM PDT 24
Peak memory 254460 kb
Host smart-6b934954-f978-4927-83fc-8298e4c38244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860508372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.860508372
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1765167301
Short name T803
Test name
Test status
Simulation time 85136757966 ps
CPU time 194.61 seconds
Started Jun 13 12:32:22 PM PDT 24
Finished Jun 13 12:35:39 PM PDT 24
Peak memory 251336 kb
Host smart-26fe3cec-e0af-4983-af94-8d021e1d4fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765167301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1765167301
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1276658569
Short name T539
Test name
Test status
Simulation time 5417269415 ps
CPU time 23.25 seconds
Started Jun 13 12:32:13 PM PDT 24
Finished Jun 13 12:32:38 PM PDT 24
Peak memory 251876 kb
Host smart-f49f47c8-9e6b-4f21-bf55-6e53c372b09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276658569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1276658569
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3019489071
Short name T909
Test name
Test status
Simulation time 3245909815 ps
CPU time 7.6 seconds
Started Jun 13 12:32:29 PM PDT 24
Finished Jun 13 12:32:38 PM PDT 24
Peak memory 225128 kb
Host smart-1b2cd3bb-cc7d-4152-868a-fe6eadbd4f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019489071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3019489071
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3605561900
Short name T273
Test name
Test status
Simulation time 2420054727 ps
CPU time 12.87 seconds
Started Jun 13 12:32:11 PM PDT 24
Finished Jun 13 12:32:27 PM PDT 24
Peak memory 233288 kb
Host smart-9cc8ca38-930a-4940-a2bc-b097de443d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605561900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3605561900
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.449700855
Short name T496
Test name
Test status
Simulation time 22762246894 ps
CPU time 107.21 seconds
Started Jun 13 12:32:20 PM PDT 24
Finished Jun 13 12:34:10 PM PDT 24
Peak memory 252844 kb
Host smart-aa01080e-dcb5-4834-a515-0dd86103db0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449700855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.449700855
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2627603635
Short name T740
Test name
Test status
Simulation time 141896625 ps
CPU time 3.23 seconds
Started Jun 13 12:32:22 PM PDT 24
Finished Jun 13 12:32:28 PM PDT 24
Peak memory 233236 kb
Host smart-09590249-f0b5-448e-882a-49943479cba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627603635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2627603635
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.881183267
Short name T622
Test name
Test status
Simulation time 399573993 ps
CPU time 5.08 seconds
Started Jun 13 12:32:12 PM PDT 24
Finished Jun 13 12:32:19 PM PDT 24
Peak memory 233244 kb
Host smart-e7d149ab-f59b-43ae-a136-fdab0727d093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881183267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.881183267
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1490365209
Short name T114
Test name
Test status
Simulation time 4129501863 ps
CPU time 13.46 seconds
Started Jun 13 12:32:22 PM PDT 24
Finished Jun 13 12:32:38 PM PDT 24
Peak memory 223124 kb
Host smart-ffc282d3-761b-4073-8127-47015db22728
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1490365209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1490365209
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3050825191
Short name T72
Test name
Test status
Simulation time 474826469 ps
CPU time 1.02 seconds
Started Jun 13 12:32:05 PM PDT 24
Finished Jun 13 12:32:07 PM PDT 24
Peak memory 235992 kb
Host smart-51dcfb74-576d-4880-bb1b-dc6d7983fad1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050825191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3050825191
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2060738653
Short name T153
Test name
Test status
Simulation time 41102849160 ps
CPU time 313.91 seconds
Started Jun 13 12:32:35 PM PDT 24
Finished Jun 13 12:37:55 PM PDT 24
Peak memory 249744 kb
Host smart-ebde7d28-583f-42d8-8a3c-84af5a06cc68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060738653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2060738653
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1229679527
Short name T547
Test name
Test status
Simulation time 2632278928 ps
CPU time 10.51 seconds
Started Jun 13 12:32:12 PM PDT 24
Finished Jun 13 12:32:25 PM PDT 24
Peak memory 216920 kb
Host smart-eb86fab8-eff2-42d6-b878-dd545e216f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229679527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1229679527
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1147818548
Short name T6
Test name
Test status
Simulation time 29183568837 ps
CPU time 19.32 seconds
Started Jun 13 12:32:39 PM PDT 24
Finished Jun 13 12:33:05 PM PDT 24
Peak memory 216864 kb
Host smart-defd0966-4ff0-4a8b-9830-0675c85bc7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147818548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1147818548
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1926451613
Short name T380
Test name
Test status
Simulation time 126756342 ps
CPU time 2.09 seconds
Started Jun 13 12:32:17 PM PDT 24
Finished Jun 13 12:32:22 PM PDT 24
Peak memory 216728 kb
Host smart-ee611eed-4880-488d-b796-0592419fbb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926451613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1926451613
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.285734060
Short name T907
Test name
Test status
Simulation time 336411703 ps
CPU time 0.97 seconds
Started Jun 13 12:32:22 PM PDT 24
Finished Jun 13 12:32:26 PM PDT 24
Peak memory 206672 kb
Host smart-e8842082-beea-47a4-a623-e2515156ac3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285734060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.285734060
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3916040354
Short name T765
Test name
Test status
Simulation time 1270604688 ps
CPU time 6.5 seconds
Started Jun 13 12:32:18 PM PDT 24
Finished Jun 13 12:32:27 PM PDT 24
Peak memory 224968 kb
Host smart-1f0ed43d-3a2e-46c7-a88c-3e0bb31f07e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916040354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3916040354
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1282262656
Short name T662
Test name
Test status
Simulation time 66334095 ps
CPU time 0.71 seconds
Started Jun 13 12:33:26 PM PDT 24
Finished Jun 13 12:33:30 PM PDT 24
Peak memory 205808 kb
Host smart-dfbc9c3d-672a-4ca4-96a9-e5ca8c15a589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282262656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1282262656
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.835510984
Short name T494
Test name
Test status
Simulation time 4099496261 ps
CPU time 14.76 seconds
Started Jun 13 12:33:25 PM PDT 24
Finished Jun 13 12:33:43 PM PDT 24
Peak memory 225156 kb
Host smart-f1f4502b-83b6-488c-8ee8-08c6d14be8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835510984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.835510984
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2917685650
Short name T322
Test name
Test status
Simulation time 16887482 ps
CPU time 0.77 seconds
Started Jun 13 12:33:17 PM PDT 24
Finished Jun 13 12:33:23 PM PDT 24
Peak memory 207472 kb
Host smart-ae8d977f-0b33-48d3-90a7-34adf47c2594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917685650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2917685650
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3817654044
Short name T252
Test name
Test status
Simulation time 27535283808 ps
CPU time 92.19 seconds
Started Jun 13 12:33:14 PM PDT 24
Finished Jun 13 12:34:49 PM PDT 24
Peak memory 241500 kb
Host smart-bafd3b3d-2c8f-45fb-ae2d-fdefcb5a6d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817654044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3817654044
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3346720085
Short name T205
Test name
Test status
Simulation time 48845129128 ps
CPU time 192.01 seconds
Started Jun 13 12:33:15 PM PDT 24
Finished Jun 13 12:36:31 PM PDT 24
Peak memory 256112 kb
Host smart-297f678a-7a3b-4b6c-832f-2a6e57bba0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346720085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3346720085
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1402865769
Short name T608
Test name
Test status
Simulation time 2981407566 ps
CPU time 43.77 seconds
Started Jun 13 12:33:38 PM PDT 24
Finished Jun 13 12:34:23 PM PDT 24
Peak memory 237100 kb
Host smart-49bad367-461f-4447-bc68-3d3e84c79a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402865769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1402865769
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3269991221
Short name T896
Test name
Test status
Simulation time 779782052 ps
CPU time 6.27 seconds
Started Jun 13 12:33:23 PM PDT 24
Finished Jun 13 12:33:33 PM PDT 24
Peak memory 233308 kb
Host smart-3ba70dff-25d5-4329-a1f1-43f7d3bcd747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269991221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3269991221
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3807664263
Short name T710
Test name
Test status
Simulation time 4079227385 ps
CPU time 3.99 seconds
Started Jun 13 12:33:34 PM PDT 24
Finished Jun 13 12:33:40 PM PDT 24
Peak memory 225156 kb
Host smart-7ceedde0-7c9b-4243-980d-17d0767f6f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807664263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3807664263
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3669236931
Short name T886
Test name
Test status
Simulation time 46165732245 ps
CPU time 69.23 seconds
Started Jun 13 12:33:31 PM PDT 24
Finished Jun 13 12:34:41 PM PDT 24
Peak memory 253336 kb
Host smart-1c1a2f7e-05ab-49b7-9b5e-cf516bec16b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669236931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3669236931
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1060683717
Short name T182
Test name
Test status
Simulation time 5129050772 ps
CPU time 13.96 seconds
Started Jun 13 12:33:23 PM PDT 24
Finished Jun 13 12:33:41 PM PDT 24
Peak memory 233348 kb
Host smart-fda0bc8f-e955-4d15-8993-317721ed130f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060683717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1060683717
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3071933827
Short name T410
Test name
Test status
Simulation time 2012991605 ps
CPU time 7.41 seconds
Started Jun 13 12:33:32 PM PDT 24
Finished Jun 13 12:33:40 PM PDT 24
Peak memory 233264 kb
Host smart-a94e2332-5113-4162-ba8a-c635b62ce117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071933827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3071933827
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.429321406
Short name T142
Test name
Test status
Simulation time 1199085832 ps
CPU time 3.23 seconds
Started Jun 13 12:33:32 PM PDT 24
Finished Jun 13 12:33:36 PM PDT 24
Peak memory 220552 kb
Host smart-4ae242fa-9ec8-461e-b06d-3a9c0bbc9645
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=429321406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.429321406
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.328640506
Short name T545
Test name
Test status
Simulation time 71657746 ps
CPU time 1.13 seconds
Started Jun 13 12:33:23 PM PDT 24
Finished Jun 13 12:33:29 PM PDT 24
Peak memory 208192 kb
Host smart-75d642ef-1f79-410a-81be-b8d464d33dec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328640506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.328640506
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.4162047002
Short name T51
Test name
Test status
Simulation time 501375715 ps
CPU time 1.95 seconds
Started Jun 13 12:33:23 PM PDT 24
Finished Jun 13 12:33:29 PM PDT 24
Peak memory 216784 kb
Host smart-5375f554-04c8-4193-97a0-6b82538cd841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162047002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.4162047002
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2243408102
Short name T571
Test name
Test status
Simulation time 3142905717 ps
CPU time 6.93 seconds
Started Jun 13 12:33:19 PM PDT 24
Finished Jun 13 12:33:31 PM PDT 24
Peak memory 216852 kb
Host smart-d023d6dc-1ee7-4b56-b536-a01e5ec26eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243408102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2243408102
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.188966391
Short name T873
Test name
Test status
Simulation time 22450032 ps
CPU time 0.82 seconds
Started Jun 13 12:33:34 PM PDT 24
Finished Jun 13 12:33:36 PM PDT 24
Peak memory 206524 kb
Host smart-c160fd20-66bc-4f92-8b3c-77eeb6f7137f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188966391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.188966391
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1739742640
Short name T552
Test name
Test status
Simulation time 23437561 ps
CPU time 0.83 seconds
Started Jun 13 12:33:34 PM PDT 24
Finished Jun 13 12:33:36 PM PDT 24
Peak memory 206432 kb
Host smart-57bf0b61-0439-4071-8d33-5fad3f1c7f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739742640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1739742640
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3532106096
Short name T614
Test name
Test status
Simulation time 21517515204 ps
CPU time 37.39 seconds
Started Jun 13 12:33:19 PM PDT 24
Finished Jun 13 12:34:02 PM PDT 24
Peak memory 249720 kb
Host smart-bbc45e63-bb62-4eae-9bb1-ca54f88277b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532106096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3532106096
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3475432854
Short name T920
Test name
Test status
Simulation time 13259611 ps
CPU time 0.76 seconds
Started Jun 13 12:33:28 PM PDT 24
Finished Jun 13 12:33:35 PM PDT 24
Peak memory 205960 kb
Host smart-556d05bb-65e8-403b-b232-f086529a2ff1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475432854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3475432854
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1896707541
Short name T480
Test name
Test status
Simulation time 258474844 ps
CPU time 2.87 seconds
Started Jun 13 12:33:20 PM PDT 24
Finished Jun 13 12:33:28 PM PDT 24
Peak memory 224652 kb
Host smart-1130a989-8e96-40f3-8614-aa6ca175d287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896707541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1896707541
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3245821577
Short name T502
Test name
Test status
Simulation time 79631506 ps
CPU time 0.86 seconds
Started Jun 13 12:33:40 PM PDT 24
Finished Jun 13 12:33:42 PM PDT 24
Peak memory 206236 kb
Host smart-4e88cecd-8913-4c71-a143-9be0e3bd40a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245821577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3245821577
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3719709837
Short name T206
Test name
Test status
Simulation time 4911646044 ps
CPU time 62.29 seconds
Started Jun 13 12:33:28 PM PDT 24
Finished Jun 13 12:34:32 PM PDT 24
Peak memory 249712 kb
Host smart-76faa167-3729-4032-9fdc-01f8f2a45d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719709837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3719709837
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3533166118
Short name T294
Test name
Test status
Simulation time 9492847032 ps
CPU time 68.72 seconds
Started Jun 13 12:33:31 PM PDT 24
Finished Jun 13 12:34:41 PM PDT 24
Peak memory 225312 kb
Host smart-81d9b71f-4861-42af-baae-021b556c2e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533166118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3533166118
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.219458669
Short name T524
Test name
Test status
Simulation time 15356164007 ps
CPU time 130.16 seconds
Started Jun 13 12:33:37 PM PDT 24
Finished Jun 13 12:35:48 PM PDT 24
Peak memory 249868 kb
Host smart-a5cecedc-f200-4415-94ff-63ce739c49b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219458669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.219458669
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2649897439
Short name T883
Test name
Test status
Simulation time 2505241455 ps
CPU time 46.41 seconds
Started Jun 13 12:33:25 PM PDT 24
Finished Jun 13 12:34:14 PM PDT 24
Peak memory 233396 kb
Host smart-dc4fe56f-ce8e-4ca8-a232-5b1477eb04b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649897439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2649897439
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.576878138
Short name T250
Test name
Test status
Simulation time 534549459 ps
CPU time 7.99 seconds
Started Jun 13 12:33:26 PM PDT 24
Finished Jun 13 12:33:37 PM PDT 24
Peak memory 225112 kb
Host smart-1587cf50-3f75-4d8f-98e5-d2300fe40cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576878138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.576878138
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.4216054908
Short name T105
Test name
Test status
Simulation time 172490118 ps
CPU time 2.46 seconds
Started Jun 13 12:33:16 PM PDT 24
Finished Jun 13 12:33:23 PM PDT 24
Peak memory 233240 kb
Host smart-e841ecfe-6366-4230-9bde-7fc4f4b1fba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216054908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.4216054908
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2867232549
Short name T527
Test name
Test status
Simulation time 625690091 ps
CPU time 2.51 seconds
Started Jun 13 12:33:17 PM PDT 24
Finished Jun 13 12:33:24 PM PDT 24
Peak memory 224916 kb
Host smart-e127168e-28e1-49db-9ec3-8233b401b235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867232549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2867232549
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.94242437
Short name T475
Test name
Test status
Simulation time 1157272748 ps
CPU time 8.28 seconds
Started Jun 13 12:33:36 PM PDT 24
Finished Jun 13 12:33:46 PM PDT 24
Peak memory 233332 kb
Host smart-788801e4-d463-4f6a-87cb-9d933015e37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94242437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.94242437
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.198169501
Short name T61
Test name
Test status
Simulation time 156587736 ps
CPU time 4.23 seconds
Started Jun 13 12:33:38 PM PDT 24
Finished Jun 13 12:33:43 PM PDT 24
Peak memory 223680 kb
Host smart-cf331b94-5e0f-4900-8e7d-fa4eff3ee22a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=198169501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.198169501
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.769488075
Short name T779
Test name
Test status
Simulation time 30585528266 ps
CPU time 35.1 seconds
Started Jun 13 12:33:14 PM PDT 24
Finished Jun 13 12:33:52 PM PDT 24
Peak memory 216800 kb
Host smart-ea9780ec-3ca1-4856-a0e1-d6abf247ff4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769488075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.769488075
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2011982727
Short name T478
Test name
Test status
Simulation time 3718152795 ps
CPU time 7.84 seconds
Started Jun 13 12:33:20 PM PDT 24
Finished Jun 13 12:33:33 PM PDT 24
Peak memory 216836 kb
Host smart-b6ef0642-e990-4c11-b401-6f35dda3d174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011982727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2011982727
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3241239990
Short name T46
Test name
Test status
Simulation time 427665175 ps
CPU time 8.12 seconds
Started Jun 13 12:33:25 PM PDT 24
Finished Jun 13 12:33:37 PM PDT 24
Peak memory 216820 kb
Host smart-f66eda7d-2ba8-41d5-b47b-408d5318954e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241239990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3241239990
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2919793329
Short name T679
Test name
Test status
Simulation time 46559207 ps
CPU time 0.88 seconds
Started Jun 13 12:33:29 PM PDT 24
Finished Jun 13 12:33:31 PM PDT 24
Peak memory 206456 kb
Host smart-18998144-8b10-4cba-89b2-755dcd386c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919793329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2919793329
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3782500812
Short name T477
Test name
Test status
Simulation time 618090023 ps
CPU time 2.74 seconds
Started Jun 13 12:33:27 PM PDT 24
Finished Jun 13 12:33:32 PM PDT 24
Peak memory 218564 kb
Host smart-32afb058-0f5f-4f21-87c4-43e4725d4985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782500812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3782500812
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3779294459
Short name T513
Test name
Test status
Simulation time 28981055 ps
CPU time 0.7 seconds
Started Jun 13 12:33:36 PM PDT 24
Finished Jun 13 12:33:38 PM PDT 24
Peak memory 205976 kb
Host smart-d7b663a6-e698-4630-ba3f-e8ac6bd78fdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779294459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3779294459
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3662528677
Short name T795
Test name
Test status
Simulation time 174521645 ps
CPU time 3.52 seconds
Started Jun 13 12:33:41 PM PDT 24
Finished Jun 13 12:33:45 PM PDT 24
Peak memory 225012 kb
Host smart-71ca6bb3-c067-46ac-98e4-7a4f885705f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662528677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3662528677
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.514377233
Short name T847
Test name
Test status
Simulation time 32864147 ps
CPU time 0.79 seconds
Started Jun 13 12:33:37 PM PDT 24
Finished Jun 13 12:33:38 PM PDT 24
Peak memory 207152 kb
Host smart-3213b43c-0f43-4bb7-86ec-94313ed5e8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514377233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.514377233
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.933978459
Short name T396
Test name
Test status
Simulation time 9507434060 ps
CPU time 74.8 seconds
Started Jun 13 12:33:24 PM PDT 24
Finished Jun 13 12:34:43 PM PDT 24
Peak memory 237552 kb
Host smart-c7f7cd15-7513-4f1d-8c36-7a0a0f02ccaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933978459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.933978459
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3538233143
Short name T676
Test name
Test status
Simulation time 30234131857 ps
CPU time 52.64 seconds
Started Jun 13 12:33:48 PM PDT 24
Finished Jun 13 12:34:42 PM PDT 24
Peak memory 249784 kb
Host smart-d4cc307a-a198-4eb4-af5d-39bfc6a21c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538233143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3538233143
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1396074416
Short name T722
Test name
Test status
Simulation time 46189544 ps
CPU time 3.28 seconds
Started Jun 13 12:33:36 PM PDT 24
Finished Jun 13 12:33:41 PM PDT 24
Peak memory 233292 kb
Host smart-8d6e20fa-8630-4a04-b349-8ac956fd0258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396074416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1396074416
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1272134760
Short name T465
Test name
Test status
Simulation time 331308544 ps
CPU time 5.43 seconds
Started Jun 13 12:33:45 PM PDT 24
Finished Jun 13 12:33:51 PM PDT 24
Peak memory 233236 kb
Host smart-b72e2aed-c38f-451e-be28-5bb9e03643c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272134760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1272134760
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.4246547680
Short name T610
Test name
Test status
Simulation time 646260442 ps
CPU time 8.93 seconds
Started Jun 13 12:33:38 PM PDT 24
Finished Jun 13 12:33:48 PM PDT 24
Peak memory 225008 kb
Host smart-75d1b856-ac80-46cd-8017-49db79a69ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246547680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.4246547680
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.629118748
Short name T877
Test name
Test status
Simulation time 107622384 ps
CPU time 3.06 seconds
Started Jun 13 12:33:43 PM PDT 24
Finished Jun 13 12:33:47 PM PDT 24
Peak memory 233300 kb
Host smart-d3f5a69b-395e-4e7e-8ffb-013a10d2d056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629118748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.629118748
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3430063137
Short name T255
Test name
Test status
Simulation time 2644470816 ps
CPU time 13.06 seconds
Started Jun 13 12:33:23 PM PDT 24
Finished Jun 13 12:33:40 PM PDT 24
Peak memory 228936 kb
Host smart-341b63b2-75c9-47dc-8533-5a68e70e7ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430063137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3430063137
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4096499030
Short name T705
Test name
Test status
Simulation time 1448692427 ps
CPU time 3.85 seconds
Started Jun 13 12:33:35 PM PDT 24
Finished Jun 13 12:33:40 PM PDT 24
Peak memory 223600 kb
Host smart-67a3c6a8-91ea-4aca-89c2-c6ff4e11cd99
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4096499030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4096499030
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2065418582
Short name T29
Test name
Test status
Simulation time 68892142 ps
CPU time 1.14 seconds
Started Jun 13 12:33:25 PM PDT 24
Finished Jun 13 12:33:30 PM PDT 24
Peak memory 207512 kb
Host smart-3d50c9b7-7b22-47f2-877b-b475819eed69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065418582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2065418582
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.651918817
Short name T753
Test name
Test status
Simulation time 12548830661 ps
CPU time 25.88 seconds
Started Jun 13 12:33:33 PM PDT 24
Finished Jun 13 12:34:00 PM PDT 24
Peak memory 217016 kb
Host smart-f369fa76-b577-4e9a-84e5-0ac3ee0224d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651918817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.651918817
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3936741346
Short name T10
Test name
Test status
Simulation time 3419748587 ps
CPU time 12.69 seconds
Started Jun 13 12:33:43 PM PDT 24
Finished Jun 13 12:33:57 PM PDT 24
Peak memory 216864 kb
Host smart-12b593c5-9663-43bc-9ec2-5715216d1012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936741346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3936741346
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1455061846
Short name T307
Test name
Test status
Simulation time 30238923 ps
CPU time 1.16 seconds
Started Jun 13 12:33:42 PM PDT 24
Finished Jun 13 12:33:45 PM PDT 24
Peak memory 216832 kb
Host smart-cb652ec8-bd8f-42d1-a43d-21f89bbce4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455061846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1455061846
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.476855751
Short name T841
Test name
Test status
Simulation time 88156212 ps
CPU time 0.82 seconds
Started Jun 13 12:33:30 PM PDT 24
Finished Jun 13 12:33:32 PM PDT 24
Peak memory 206456 kb
Host smart-a0cb6fae-339a-4579-b2c9-f838dc747d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476855751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.476855751
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3541408335
Short name T287
Test name
Test status
Simulation time 4024495136 ps
CPU time 14.67 seconds
Started Jun 13 12:33:26 PM PDT 24
Finished Jun 13 12:33:44 PM PDT 24
Peak memory 249700 kb
Host smart-4d6be33d-49d6-4940-8962-ff5e6fb6243f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541408335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3541408335
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1623518752
Short name T694
Test name
Test status
Simulation time 16339446 ps
CPU time 0.73 seconds
Started Jun 13 01:37:30 PM PDT 24
Finished Jun 13 01:37:31 PM PDT 24
Peak memory 206080 kb
Host smart-530b5e85-7f01-454d-8bc5-14a78bff8f3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623518752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1623518752
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1975868982
Short name T570
Test name
Test status
Simulation time 589736626 ps
CPU time 5.82 seconds
Started Jun 13 01:21:16 PM PDT 24
Finished Jun 13 01:21:22 PM PDT 24
Peak memory 233376 kb
Host smart-b55cfb24-ca31-4306-8041-93ff3cf21deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975868982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1975868982
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1302287598
Short name T664
Test name
Test status
Simulation time 16158797 ps
CPU time 0.84 seconds
Started Jun 13 12:33:34 PM PDT 24
Finished Jun 13 12:33:36 PM PDT 24
Peak memory 207188 kb
Host smart-2bfa34b6-c148-48eb-bc10-a95eafe8b32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302287598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1302287598
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3340353199
Short name T599
Test name
Test status
Simulation time 553022812 ps
CPU time 4.35 seconds
Started Jun 13 01:48:59 PM PDT 24
Finished Jun 13 01:49:05 PM PDT 24
Peak memory 225236 kb
Host smart-3813b2e7-92aa-4e22-b096-69bdb98dcd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340353199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3340353199
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3692730939
Short name T404
Test name
Test status
Simulation time 6654550636 ps
CPU time 26.19 seconds
Started Jun 13 12:53:49 PM PDT 24
Finished Jun 13 12:54:16 PM PDT 24
Peak memory 225220 kb
Host smart-494e114a-a085-4df9-afc8-79c18b37c610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692730939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3692730939
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2996673142
Short name T411
Test name
Test status
Simulation time 5174565494 ps
CPU time 15.57 seconds
Started Jun 13 01:00:00 PM PDT 24
Finished Jun 13 01:00:17 PM PDT 24
Peak memory 225248 kb
Host smart-6c2b1b63-c62d-499c-bc1a-da151e1bc20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996673142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2996673142
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1608533091
Short name T692
Test name
Test status
Simulation time 78700638 ps
CPU time 3.06 seconds
Started Jun 13 02:39:49 PM PDT 24
Finished Jun 13 02:40:00 PM PDT 24
Peak memory 233436 kb
Host smart-033b19c5-8b16-4660-9a56-65e7d6532a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608533091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1608533091
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1691280085
Short name T278
Test name
Test status
Simulation time 1676613649 ps
CPU time 19.79 seconds
Started Jun 13 01:35:16 PM PDT 24
Finished Jun 13 01:35:36 PM PDT 24
Peak memory 233400 kb
Host smart-eecd3744-3f66-445e-8dd6-d130116cb3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691280085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1691280085
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3517191712
Short name T640
Test name
Test status
Simulation time 340929232 ps
CPU time 4.2 seconds
Started Jun 13 12:33:26 PM PDT 24
Finished Jun 13 12:33:33 PM PDT 24
Peak memory 233212 kb
Host smart-d4568340-11a6-4fb7-bcc2-2c680a0e327d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517191712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3517191712
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.235829711
Short name T612
Test name
Test status
Simulation time 6138303976 ps
CPU time 18.08 seconds
Started Jun 13 12:33:43 PM PDT 24
Finished Jun 13 12:34:03 PM PDT 24
Peak memory 233316 kb
Host smart-6a73eea8-46fd-4976-a0e0-6e6a985d1251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235829711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.235829711
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.4064693145
Short name T714
Test name
Test status
Simulation time 2761048525 ps
CPU time 11.13 seconds
Started Jun 13 01:39:00 PM PDT 24
Finished Jun 13 01:39:13 PM PDT 24
Peak memory 221164 kb
Host smart-fa567747-e6cc-4d25-97b1-d8cb31bd5189
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4064693145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.4064693145
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3665133503
Short name T884
Test name
Test status
Simulation time 1125626094 ps
CPU time 4.1 seconds
Started Jun 13 12:33:35 PM PDT 24
Finished Jun 13 12:33:40 PM PDT 24
Peak memory 216900 kb
Host smart-6d95c51b-e548-4b94-95f5-8deb988e9e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665133503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3665133503
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3058194530
Short name T535
Test name
Test status
Simulation time 1416396998 ps
CPU time 3.87 seconds
Started Jun 13 12:33:38 PM PDT 24
Finished Jun 13 12:33:43 PM PDT 24
Peak memory 216868 kb
Host smart-51b97abf-1342-4970-8efa-f87217d9b8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058194530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3058194530
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.230419147
Short name T47
Test name
Test status
Simulation time 47115942 ps
CPU time 1.42 seconds
Started Jun 13 12:33:39 PM PDT 24
Finished Jun 13 12:33:42 PM PDT 24
Peak memory 216788 kb
Host smart-56d9bbdd-72bb-46f8-9bdb-d898ff38f936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230419147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.230419147
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.4227383502
Short name T632
Test name
Test status
Simulation time 28255669 ps
CPU time 0.78 seconds
Started Jun 13 12:33:41 PM PDT 24
Finished Jun 13 12:33:43 PM PDT 24
Peak memory 206456 kb
Host smart-e9847dcf-f636-4b07-8882-35439197a03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227383502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.4227383502
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2692874693
Short name T188
Test name
Test status
Simulation time 1787469865 ps
CPU time 5.06 seconds
Started Jun 13 02:00:00 PM PDT 24
Finished Jun 13 02:00:07 PM PDT 24
Peak memory 233436 kb
Host smart-c84bfeca-de72-40f0-a39a-4cdf4a8a086e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692874693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2692874693
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.260456517
Short name T346
Test name
Test status
Simulation time 29519142 ps
CPU time 0.75 seconds
Started Jun 13 01:38:30 PM PDT 24
Finished Jun 13 01:38:32 PM PDT 24
Peak memory 206480 kb
Host smart-6e035fd6-2d6f-45c0-910a-726a9f43c972
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260456517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.260456517
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.588112481
Short name T819
Test name
Test status
Simulation time 152545710 ps
CPU time 3.01 seconds
Started Jun 13 01:25:44 PM PDT 24
Finished Jun 13 01:25:48 PM PDT 24
Peak memory 225192 kb
Host smart-7fc39118-ec3c-4f9e-89eb-1f59e7200fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588112481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.588112481
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1790373490
Short name T328
Test name
Test status
Simulation time 143821809 ps
CPU time 0.75 seconds
Started Jun 13 02:44:48 PM PDT 24
Finished Jun 13 02:44:59 PM PDT 24
Peak memory 206328 kb
Host smart-dc3dfc64-6255-4490-9a72-4cc707e23e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790373490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1790373490
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2766202034
Short name T564
Test name
Test status
Simulation time 3153003280 ps
CPU time 34.64 seconds
Started Jun 13 02:43:05 PM PDT 24
Finished Jun 13 02:43:42 PM PDT 24
Peak memory 249916 kb
Host smart-edbd08c3-7d64-415e-b23d-c34c32f21e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766202034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2766202034
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2090606105
Short name T204
Test name
Test status
Simulation time 35264176631 ps
CPU time 341.64 seconds
Started Jun 13 01:02:05 PM PDT 24
Finished Jun 13 01:07:48 PM PDT 24
Peak memory 250172 kb
Host smart-3c7a605c-6597-4a37-aaea-aa9d3e162c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090606105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2090606105
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3009587101
Short name T950
Test name
Test status
Simulation time 42937775406 ps
CPU time 218.56 seconds
Started Jun 13 02:20:08 PM PDT 24
Finished Jun 13 02:23:55 PM PDT 24
Peak memory 258324 kb
Host smart-9c697c51-3390-41d7-95a6-4ea780a55c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009587101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3009587101
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1876194886
Short name T788
Test name
Test status
Simulation time 349019595 ps
CPU time 7.23 seconds
Started Jun 13 01:35:52 PM PDT 24
Finished Jun 13 01:36:00 PM PDT 24
Peak memory 225172 kb
Host smart-86f8235f-da4b-4d25-b35c-0e9c7599ad74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876194886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1876194886
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.42071906
Short name T677
Test name
Test status
Simulation time 37902713680 ps
CPU time 34.93 seconds
Started Jun 13 12:57:04 PM PDT 24
Finished Jun 13 12:57:40 PM PDT 24
Peak memory 225216 kb
Host smart-a669be1b-ccb8-4c95-b0a3-1c2560306521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42071906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.42071906
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.940126094
Short name T453
Test name
Test status
Simulation time 2923442492 ps
CPU time 5.87 seconds
Started Jun 13 01:14:03 PM PDT 24
Finished Jun 13 01:14:10 PM PDT 24
Peak memory 225440 kb
Host smart-f54f785e-95f9-473b-883b-a0f9e800d5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940126094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.940126094
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2531784779
Short name T941
Test name
Test status
Simulation time 294565695 ps
CPU time 3.1 seconds
Started Jun 13 02:49:42 PM PDT 24
Finished Jun 13 02:50:03 PM PDT 24
Peak memory 233436 kb
Host smart-6bfe8da2-6027-4804-83b6-a72518785c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531784779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2531784779
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.422439276
Short name T357
Test name
Test status
Simulation time 171706410221 ps
CPU time 28.75 seconds
Started Jun 13 12:44:28 PM PDT 24
Finished Jun 13 12:44:57 PM PDT 24
Peak memory 249564 kb
Host smart-68c8743c-3751-493d-8a41-f48b5ebeef55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422439276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.422439276
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3186361830
Short name T913
Test name
Test status
Simulation time 4873317358 ps
CPU time 14.77 seconds
Started Jun 13 12:33:45 PM PDT 24
Finished Jun 13 12:34:01 PM PDT 24
Peak memory 223696 kb
Host smart-52d8d051-6e9c-4cf0-ab06-ca141dcb16f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3186361830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3186361830
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1032379711
Short name T253
Test name
Test status
Simulation time 5710917156 ps
CPU time 65.47 seconds
Started Jun 13 02:13:58 PM PDT 24
Finished Jun 13 02:15:04 PM PDT 24
Peak memory 241764 kb
Host smart-5e2dda79-aa82-4f66-bd63-c5eb9ad21bb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032379711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1032379711
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.4238059771
Short name T914
Test name
Test status
Simulation time 8139896879 ps
CPU time 11.91 seconds
Started Jun 13 01:29:32 PM PDT 24
Finished Jun 13 01:29:44 PM PDT 24
Peak memory 220540 kb
Host smart-5e638738-ccc7-4012-89f5-f20b2dfb030a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238059771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.4238059771
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2971117221
Short name T701
Test name
Test status
Simulation time 15663270071 ps
CPU time 10.61 seconds
Started Jun 13 12:44:08 PM PDT 24
Finished Jun 13 12:44:19 PM PDT 24
Peak memory 216932 kb
Host smart-4f604c2d-9b73-4533-aab8-7462a46db760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971117221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2971117221
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2524088957
Short name T915
Test name
Test status
Simulation time 50232971 ps
CPU time 0.78 seconds
Started Jun 13 12:33:48 PM PDT 24
Finished Jun 13 12:33:50 PM PDT 24
Peak memory 206448 kb
Host smart-7c393149-cacb-4ccb-8937-e479bdef5161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524088957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2524088957
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1447078485
Short name T762
Test name
Test status
Simulation time 348937045 ps
CPU time 0.91 seconds
Started Jun 13 01:19:44 PM PDT 24
Finished Jun 13 01:19:45 PM PDT 24
Peak memory 207636 kb
Host smart-42e92900-04fb-4dba-81f5-575f725589ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447078485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1447078485
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2596909390
Short name T723
Test name
Test status
Simulation time 8278098876 ps
CPU time 12.18 seconds
Started Jun 13 02:01:21 PM PDT 24
Finished Jun 13 02:01:35 PM PDT 24
Peak memory 240924 kb
Host smart-118896aa-a001-4dd6-a996-56b7670a61da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596909390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2596909390
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3472713164
Short name T627
Test name
Test status
Simulation time 13350048 ps
CPU time 0.74 seconds
Started Jun 13 01:29:35 PM PDT 24
Finished Jun 13 01:29:37 PM PDT 24
Peak memory 205568 kb
Host smart-164efaa1-8249-46a1-9194-1bf6de6115e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472713164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3472713164
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2393627714
Short name T870
Test name
Test status
Simulation time 1222041665 ps
CPU time 8.51 seconds
Started Jun 13 01:47:17 PM PDT 24
Finished Jun 13 01:47:26 PM PDT 24
Peak memory 233408 kb
Host smart-64b0f454-5033-42ad-8446-89be0fb67541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393627714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2393627714
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.655074562
Short name T484
Test name
Test status
Simulation time 90244001 ps
CPU time 0.83 seconds
Started Jun 13 12:44:39 PM PDT 24
Finished Jun 13 12:44:40 PM PDT 24
Peak memory 207592 kb
Host smart-6a24ee52-8a20-4779-945e-3e75fe1d2f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655074562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.655074562
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.779994471
Short name T210
Test name
Test status
Simulation time 30175854153 ps
CPU time 87.69 seconds
Started Jun 13 01:34:14 PM PDT 24
Finished Jun 13 01:35:42 PM PDT 24
Peak memory 258100 kb
Host smart-5a432ce4-4959-444a-9cf4-d8d60011da04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779994471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.779994471
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.364566192
Short name T310
Test name
Test status
Simulation time 4222714197 ps
CPU time 27.68 seconds
Started Jun 13 12:57:00 PM PDT 24
Finished Jun 13 12:57:29 PM PDT 24
Peak memory 224288 kb
Host smart-0a8248b2-507e-4823-a67c-85664e510afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364566192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.364566192
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2867556918
Short name T140
Test name
Test status
Simulation time 815786141 ps
CPU time 9.92 seconds
Started Jun 13 01:18:02 PM PDT 24
Finished Jun 13 01:18:13 PM PDT 24
Peak memory 250028 kb
Host smart-df9ab731-6c46-4474-87d6-8ac0ed793ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867556918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2867556918
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2027293885
Short name T133
Test name
Test status
Simulation time 384170706 ps
CPU time 3.75 seconds
Started Jun 13 12:39:20 PM PDT 24
Finished Jun 13 12:39:24 PM PDT 24
Peak memory 225120 kb
Host smart-d95e3b6c-352d-4949-b953-7d85c536a1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027293885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2027293885
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1457187159
Short name T902
Test name
Test status
Simulation time 12055511609 ps
CPU time 27.21 seconds
Started Jun 13 02:13:32 PM PDT 24
Finished Jun 13 02:14:01 PM PDT 24
Peak memory 233456 kb
Host smart-08d5091e-6042-40e0-99d2-cca116b583d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457187159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1457187159
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3596505703
Short name T923
Test name
Test status
Simulation time 121594819 ps
CPU time 2.34 seconds
Started Jun 13 01:09:30 PM PDT 24
Finished Jun 13 01:09:33 PM PDT 24
Peak memory 225180 kb
Host smart-4adaa17c-017f-4eda-adbb-676f73e786f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596505703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3596505703
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2227225901
Short name T316
Test name
Test status
Simulation time 5068271967 ps
CPU time 16.45 seconds
Started Jun 13 12:42:39 PM PDT 24
Finished Jun 13 12:42:57 PM PDT 24
Peak memory 241508 kb
Host smart-4a5ca896-a5bf-473d-a386-28b05f5a9df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227225901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2227225901
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2339700918
Short name T845
Test name
Test status
Simulation time 1110111539 ps
CPU time 8.08 seconds
Started Jun 13 01:37:05 PM PDT 24
Finished Jun 13 01:37:14 PM PDT 24
Peak memory 220692 kb
Host smart-1fa9cc02-b3e2-432e-818c-8f63a4872dcc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2339700918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2339700918
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1990056646
Short name T41
Test name
Test status
Simulation time 793640832865 ps
CPU time 416.08 seconds
Started Jun 13 01:04:10 PM PDT 24
Finished Jun 13 01:11:07 PM PDT 24
Peak memory 271060 kb
Host smart-f8b8cba4-4f9d-42c5-aa80-3fbb1668eb49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990056646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1990056646
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3987302777
Short name T910
Test name
Test status
Simulation time 15428212930 ps
CPU time 39.65 seconds
Started Jun 13 01:16:54 PM PDT 24
Finished Jun 13 01:17:34 PM PDT 24
Peak memory 217128 kb
Host smart-98823572-3b0e-4bd8-9ea8-0e5b1136a60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987302777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3987302777
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.4190208699
Short name T817
Test name
Test status
Simulation time 46213303 ps
CPU time 0.74 seconds
Started Jun 13 01:36:24 PM PDT 24
Finished Jun 13 01:36:26 PM PDT 24
Peak memory 206364 kb
Host smart-3b93a3c8-0a2b-49d6-b0b3-2b71aa4c6bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190208699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.4190208699
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.418206771
Short name T813
Test name
Test status
Simulation time 34950938 ps
CPU time 1.98 seconds
Started Jun 13 01:09:25 PM PDT 24
Finished Jun 13 01:09:28 PM PDT 24
Peak memory 217000 kb
Host smart-71399c8d-d9f1-4b1a-ae82-9b48b209ea32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418206771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.418206771
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2904653505
Short name T652
Test name
Test status
Simulation time 136281757 ps
CPU time 0.83 seconds
Started Jun 13 01:17:47 PM PDT 24
Finished Jun 13 01:17:48 PM PDT 24
Peak memory 207644 kb
Host smart-4040471c-a5a4-4bb8-88fb-144c7927841d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904653505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2904653505
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.202907163
Short name T879
Test name
Test status
Simulation time 104163443 ps
CPU time 2.96 seconds
Started Jun 13 01:59:25 PM PDT 24
Finished Jun 13 01:59:29 PM PDT 24
Peak memory 233396 kb
Host smart-27e453c6-6cb9-49b9-bcaf-4e2e3ff6710e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202907163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.202907163
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2489793193
Short name T329
Test name
Test status
Simulation time 14369074 ps
CPU time 0.74 seconds
Started Jun 13 02:19:09 PM PDT 24
Finished Jun 13 02:19:19 PM PDT 24
Peak memory 205540 kb
Host smart-c23e2351-14f8-4b2f-b0d1-c1c1b96de2e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489793193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2489793193
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.641812841
Short name T702
Test name
Test status
Simulation time 545753011 ps
CPU time 2.57 seconds
Started Jun 13 01:54:50 PM PDT 24
Finished Jun 13 01:54:57 PM PDT 24
Peak memory 225232 kb
Host smart-18890bf6-ac15-444f-b1b5-841e9b12413f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641812841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.641812841
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2879055487
Short name T891
Test name
Test status
Simulation time 40997405 ps
CPU time 0.77 seconds
Started Jun 13 02:48:45 PM PDT 24
Finished Jun 13 02:49:02 PM PDT 24
Peak memory 206612 kb
Host smart-46ee5bb3-0a27-42ac-9787-89c4846f80c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879055487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2879055487
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1857206734
Short name T641
Test name
Test status
Simulation time 381024384 ps
CPU time 7.16 seconds
Started Jun 13 01:33:22 PM PDT 24
Finished Jun 13 01:33:30 PM PDT 24
Peak memory 225244 kb
Host smart-695d26cc-e143-4ebd-93f7-98d8d78cd672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857206734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1857206734
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.4234494410
Short name T868
Test name
Test status
Simulation time 2380551348 ps
CPU time 27.65 seconds
Started Jun 13 01:41:02 PM PDT 24
Finished Jun 13 01:41:31 PM PDT 24
Peak memory 241676 kb
Host smart-bb004080-82cf-4e28-af73-52e94b9465e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234494410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.4234494410
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1342689022
Short name T848
Test name
Test status
Simulation time 22024641695 ps
CPU time 221.19 seconds
Started Jun 13 02:31:21 PM PDT 24
Finished Jun 13 02:35:05 PM PDT 24
Peak memory 250356 kb
Host smart-5700c075-e581-4cf5-a361-1a08e7003c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342689022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1342689022
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_intercept.193563520
Short name T280
Test name
Test status
Simulation time 862031229 ps
CPU time 7.85 seconds
Started Jun 13 12:38:41 PM PDT 24
Finished Jun 13 12:38:49 PM PDT 24
Peak memory 233400 kb
Host smart-86da7f50-cef1-4e2d-b037-4c24e39d725d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193563520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.193563520
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.696817540
Short name T424
Test name
Test status
Simulation time 755540055 ps
CPU time 16.25 seconds
Started Jun 13 01:17:13 PM PDT 24
Finished Jun 13 01:17:30 PM PDT 24
Peak memory 235040 kb
Host smart-5ea3d5d2-669f-4b2d-8075-f774e17d6035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696817540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.696817540
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.19862052
Short name T606
Test name
Test status
Simulation time 1025454375 ps
CPU time 4.7 seconds
Started Jun 13 01:37:38 PM PDT 24
Finished Jun 13 01:37:43 PM PDT 24
Peak memory 225224 kb
Host smart-89cb1965-83c9-407d-867a-8eab18e320fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19862052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.19862052
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.306148153
Short name T867
Test name
Test status
Simulation time 3974733687 ps
CPU time 12.82 seconds
Started Jun 13 01:34:15 PM PDT 24
Finished Jun 13 01:34:29 PM PDT 24
Peak memory 233492 kb
Host smart-270e26ce-93ff-4098-ae42-a05ab43d3c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306148153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.306148153
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1781670162
Short name T2
Test name
Test status
Simulation time 327854697 ps
CPU time 4.23 seconds
Started Jun 13 12:33:30 PM PDT 24
Finished Jun 13 12:33:35 PM PDT 24
Peak memory 219788 kb
Host smart-9cf83df7-e95b-47c6-b167-4a14b5c8400c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1781670162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1781670162
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2304658284
Short name T834
Test name
Test status
Simulation time 44153113 ps
CPU time 1.02 seconds
Started Jun 13 01:20:50 PM PDT 24
Finished Jun 13 01:20:52 PM PDT 24
Peak memory 207636 kb
Host smart-21f24831-ce2a-4c30-99a7-c22e9de4c200
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304658284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2304658284
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2460337405
Short name T618
Test name
Test status
Simulation time 14255823529 ps
CPU time 38.3 seconds
Started Jun 13 01:38:55 PM PDT 24
Finished Jun 13 01:39:35 PM PDT 24
Peak memory 217044 kb
Host smart-d1fa0e04-5b97-46b1-acfe-5be92823ca64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460337405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2460337405
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1260329420
Short name T932
Test name
Test status
Simulation time 1331753577 ps
CPU time 5.38 seconds
Started Jun 13 12:59:57 PM PDT 24
Finished Jun 13 01:00:04 PM PDT 24
Peak memory 217224 kb
Host smart-61429a65-a12b-483e-9173-5db60db26621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260329420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1260329420
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1190863749
Short name T559
Test name
Test status
Simulation time 23541594 ps
CPU time 0.75 seconds
Started Jun 13 01:36:03 PM PDT 24
Finished Jun 13 01:36:04 PM PDT 24
Peak memory 206636 kb
Host smart-81c3ae98-d178-455a-ab98-ec1d728561bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190863749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1190863749
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2435059105
Short name T933
Test name
Test status
Simulation time 19164613 ps
CPU time 0.79 seconds
Started Jun 13 02:23:32 PM PDT 24
Finished Jun 13 02:23:33 PM PDT 24
Peak memory 206608 kb
Host smart-9ee6c086-bb4f-4b23-a9b8-86db06f1e15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435059105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2435059105
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3670991675
Short name T826
Test name
Test status
Simulation time 959181209 ps
CPU time 2.33 seconds
Started Jun 13 01:36:11 PM PDT 24
Finished Jun 13 01:36:14 PM PDT 24
Peak memory 225184 kb
Host smart-32055296-d18d-44d2-bfa8-842f67e9e60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670991675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3670991675
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.775893261
Short name T523
Test name
Test status
Simulation time 31037965 ps
CPU time 0.74 seconds
Started Jun 13 01:40:38 PM PDT 24
Finished Jun 13 01:40:39 PM PDT 24
Peak memory 206148 kb
Host smart-90a6ba0b-4c56-4acb-b959-3eebd29553d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775893261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.775893261
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2990987159
Short name T556
Test name
Test status
Simulation time 350852039 ps
CPU time 4.58 seconds
Started Jun 13 12:39:04 PM PDT 24
Finished Jun 13 12:39:09 PM PDT 24
Peak memory 233308 kb
Host smart-08a114b4-834c-471a-a07d-b5bf1ca1c398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990987159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2990987159
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.4291913651
Short name T440
Test name
Test status
Simulation time 53049902 ps
CPU time 0.78 seconds
Started Jun 13 02:08:38 PM PDT 24
Finished Jun 13 02:08:40 PM PDT 24
Peak memory 207324 kb
Host smart-790e4bde-73b1-4e08-943f-7dfe73570529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291913651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.4291913651
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.946809343
Short name T597
Test name
Test status
Simulation time 8349118613 ps
CPU time 72.63 seconds
Started Jun 13 01:23:37 PM PDT 24
Finished Jun 13 01:24:50 PM PDT 24
Peak memory 241684 kb
Host smart-e74e7856-7d19-4d24-bbb3-17cb23b47021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946809343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.946809343
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2533688962
Short name T670
Test name
Test status
Simulation time 12097823417 ps
CPU time 60.26 seconds
Started Jun 13 12:55:41 PM PDT 24
Finished Jun 13 12:56:42 PM PDT 24
Peak memory 255628 kb
Host smart-23cbb81a-9c30-4e5a-b479-51bf262002e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533688962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2533688962
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.4047129915
Short name T229
Test name
Test status
Simulation time 505898026266 ps
CPU time 554.01 seconds
Started Jun 13 01:31:43 PM PDT 24
Finished Jun 13 01:40:58 PM PDT 24
Peak memory 257276 kb
Host smart-5e037665-e4d0-4e47-b4b4-e801bb8db165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047129915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.4047129915
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2632950924
Short name T144
Test name
Test status
Simulation time 466660221 ps
CPU time 5.57 seconds
Started Jun 13 12:44:43 PM PDT 24
Finished Jun 13 12:44:50 PM PDT 24
Peak memory 236184 kb
Host smart-4e8952be-c49b-4913-ac61-1b3771c29096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632950924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2632950924
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3401309898
Short name T364
Test name
Test status
Simulation time 2743115658 ps
CPU time 3.99 seconds
Started Jun 13 01:47:02 PM PDT 24
Finished Jun 13 01:47:08 PM PDT 24
Peak memory 225256 kb
Host smart-944b3261-512d-4453-bf71-c40a3fce92b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401309898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3401309898
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.865499966
Short name T619
Test name
Test status
Simulation time 195706926 ps
CPU time 6.75 seconds
Started Jun 13 01:18:22 PM PDT 24
Finished Jun 13 01:18:29 PM PDT 24
Peak memory 241556 kb
Host smart-be540a72-1339-4509-a146-b3951e828af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865499966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.865499966
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2007168715
Short name T24
Test name
Test status
Simulation time 432315266 ps
CPU time 2.36 seconds
Started Jun 13 01:44:33 PM PDT 24
Finished Jun 13 01:44:37 PM PDT 24
Peak memory 223864 kb
Host smart-e27d1da2-383d-4dac-b958-bc1101d05544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007168715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2007168715
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3904638566
Short name T442
Test name
Test status
Simulation time 33197999056 ps
CPU time 25.64 seconds
Started Jun 13 01:59:39 PM PDT 24
Finished Jun 13 02:00:07 PM PDT 24
Peak memory 240144 kb
Host smart-6d1f7195-f064-4afe-bc60-55436c3a9c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904638566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3904638566
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.788252185
Short name T789
Test name
Test status
Simulation time 83391535 ps
CPU time 3.82 seconds
Started Jun 13 01:37:11 PM PDT 24
Finished Jun 13 01:37:16 PM PDT 24
Peak memory 219964 kb
Host smart-d940bded-c1ca-4c3b-a16b-a9c57bb54b51
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=788252185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.788252185
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.382684370
Short name T386
Test name
Test status
Simulation time 70303139 ps
CPU time 0.9 seconds
Started Jun 13 02:10:27 PM PDT 24
Finished Jun 13 02:10:29 PM PDT 24
Peak memory 207612 kb
Host smart-5abb3216-dbd8-41c8-ab9d-c102d5e85627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382684370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.382684370
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2231051712
Short name T394
Test name
Test status
Simulation time 3964357624 ps
CPU time 20.21 seconds
Started Jun 13 01:44:44 PM PDT 24
Finished Jun 13 01:45:04 PM PDT 24
Peak memory 217236 kb
Host smart-aece3ac4-6460-48e0-aa16-76b0e740625f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231051712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2231051712
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3068439777
Short name T382
Test name
Test status
Simulation time 14303698 ps
CPU time 0.78 seconds
Started Jun 13 02:23:15 PM PDT 24
Finished Jun 13 02:23:16 PM PDT 24
Peak memory 206404 kb
Host smart-f8e62c0d-0d7f-44bf-8e45-86e669251b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068439777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3068439777
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3645983088
Short name T731
Test name
Test status
Simulation time 971698268 ps
CPU time 5.41 seconds
Started Jun 13 02:12:03 PM PDT 24
Finished Jun 13 02:12:09 PM PDT 24
Peak memory 217016 kb
Host smart-ee6a8800-cc57-4e37-91cf-2699a46b32a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645983088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3645983088
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2417723416
Short name T406
Test name
Test status
Simulation time 66676595 ps
CPU time 0.78 seconds
Started Jun 13 12:33:28 PM PDT 24
Finished Jun 13 12:33:30 PM PDT 24
Peak memory 206432 kb
Host smart-0b418fa5-d9c1-4a46-ad00-3f6071630eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417723416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2417723416
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.811205460
Short name T52
Test name
Test status
Simulation time 24790320528 ps
CPU time 39.56 seconds
Started Jun 13 12:44:36 PM PDT 24
Finished Jun 13 12:45:16 PM PDT 24
Peak memory 225172 kb
Host smart-58ba8654-957c-461d-b5b9-c5abf9134364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811205460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.811205460
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.180888077
Short name T776
Test name
Test status
Simulation time 57215563 ps
CPU time 0.77 seconds
Started Jun 13 01:16:02 PM PDT 24
Finished Jun 13 01:16:04 PM PDT 24
Peak memory 206496 kb
Host smart-6c1c1e71-a75d-47ca-a7a4-ba12251909a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180888077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.180888077
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3178958268
Short name T736
Test name
Test status
Simulation time 116703607 ps
CPU time 2.13 seconds
Started Jun 13 12:37:20 PM PDT 24
Finished Jun 13 12:37:25 PM PDT 24
Peak memory 225036 kb
Host smart-5763a732-2dde-4544-9bbb-30ad2df23ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178958268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3178958268
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3867415729
Short name T668
Test name
Test status
Simulation time 32106443 ps
CPU time 0.79 seconds
Started Jun 13 01:26:00 PM PDT 24
Finished Jun 13 01:26:04 PM PDT 24
Peak memory 207340 kb
Host smart-6f854fa5-4a49-423e-b195-9e393d2c8bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867415729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3867415729
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.4079596728
Short name T587
Test name
Test status
Simulation time 10006876161 ps
CPU time 19.78 seconds
Started Jun 13 01:32:03 PM PDT 24
Finished Jun 13 01:32:23 PM PDT 24
Peak memory 237644 kb
Host smart-5e7c050e-dfed-4d7f-a6e9-8a42d3efae4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079596728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.4079596728
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3727807644
Short name T212
Test name
Test status
Simulation time 90784927987 ps
CPU time 296.45 seconds
Started Jun 13 01:19:58 PM PDT 24
Finished Jun 13 01:24:56 PM PDT 24
Peak memory 266360 kb
Host smart-fcf7f0a5-cba0-44af-b858-ef20549c7e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727807644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3727807644
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3344297207
Short name T271
Test name
Test status
Simulation time 2264860113 ps
CPU time 28.49 seconds
Started Jun 13 01:57:30 PM PDT 24
Finished Jun 13 01:58:00 PM PDT 24
Peak memory 233456 kb
Host smart-655470d5-ed44-4785-b69a-9c4a5905874d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344297207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3344297207
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2688603102
Short name T264
Test name
Test status
Simulation time 110328919 ps
CPU time 4.24 seconds
Started Jun 13 01:41:08 PM PDT 24
Finished Jun 13 01:41:14 PM PDT 24
Peak memory 225244 kb
Host smart-3af7697e-99ac-4448-a1ae-f99c341cd1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688603102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2688603102
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3476031345
Short name T588
Test name
Test status
Simulation time 9064610119 ps
CPU time 25.02 seconds
Started Jun 13 01:24:33 PM PDT 24
Finished Jun 13 01:24:59 PM PDT 24
Peak memory 234632 kb
Host smart-5bd80589-7d49-439a-88c5-a425d0a12133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476031345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3476031345
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1129475517
Short name T292
Test name
Test status
Simulation time 1427949651 ps
CPU time 4.34 seconds
Started Jun 13 12:43:30 PM PDT 24
Finished Jun 13 12:43:34 PM PDT 24
Peak memory 225192 kb
Host smart-9b9055c9-b460-442e-a3c9-51f00457c708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129475517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1129475517
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2282388365
Short name T872
Test name
Test status
Simulation time 59312848534 ps
CPU time 12.61 seconds
Started Jun 13 01:40:42 PM PDT 24
Finished Jun 13 01:40:56 PM PDT 24
Peak memory 241564 kb
Host smart-337dbc47-a3d3-47ea-9eb6-8eb3c3dc1faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282388365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2282388365
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3947979975
Short name T338
Test name
Test status
Simulation time 3541580755 ps
CPU time 10.96 seconds
Started Jun 13 02:03:40 PM PDT 24
Finished Jun 13 02:03:52 PM PDT 24
Peak memory 221380 kb
Host smart-a6b2356d-1cb2-4984-9ec6-110c22b96863
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3947979975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3947979975
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3725427419
Short name T115
Test name
Test status
Simulation time 1691948411 ps
CPU time 6.7 seconds
Started Jun 13 01:11:06 PM PDT 24
Finished Jun 13 01:11:18 PM PDT 24
Peak memory 217100 kb
Host smart-48acc778-2324-406d-bd7d-14b2cf0dbbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725427419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3725427419
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1044324017
Short name T365
Test name
Test status
Simulation time 4972382047 ps
CPU time 4.75 seconds
Started Jun 13 12:41:30 PM PDT 24
Finished Jun 13 12:41:35 PM PDT 24
Peak memory 216868 kb
Host smart-c6cdcd3c-f5e9-4d0a-9222-dd479d2236ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044324017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1044324017
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1148256025
Short name T607
Test name
Test status
Simulation time 19376711 ps
CPU time 0.86 seconds
Started Jun 13 01:21:10 PM PDT 24
Finished Jun 13 01:21:12 PM PDT 24
Peak memory 207516 kb
Host smart-5c02ba7c-3344-455c-bd9d-1c52b2d41b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148256025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1148256025
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.887773206
Short name T585
Test name
Test status
Simulation time 23493854 ps
CPU time 0.81 seconds
Started Jun 13 01:55:26 PM PDT 24
Finished Jun 13 01:55:28 PM PDT 24
Peak memory 206528 kb
Host smart-975ec384-2af8-4edc-8af0-a029c3ad92dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887773206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.887773206
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3082711276
Short name T272
Test name
Test status
Simulation time 249109404 ps
CPU time 5.2 seconds
Started Jun 13 01:17:09 PM PDT 24
Finished Jun 13 01:17:15 PM PDT 24
Peak memory 233412 kb
Host smart-0c844317-3138-461c-9255-4a61563c71fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082711276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3082711276
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1511073487
Short name T363
Test name
Test status
Simulation time 48116912 ps
CPU time 0.72 seconds
Started Jun 13 01:14:43 PM PDT 24
Finished Jun 13 01:14:45 PM PDT 24
Peak memory 205568 kb
Host smart-a6a9a948-a053-4ef9-a727-c5fbfdcb5bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511073487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1511073487
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1953215595
Short name T830
Test name
Test status
Simulation time 364746634 ps
CPU time 3.67 seconds
Started Jun 13 01:36:17 PM PDT 24
Finished Jun 13 01:36:21 PM PDT 24
Peak memory 233408 kb
Host smart-4822767f-312c-45fd-b354-9116a5821a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953215595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1953215595
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3904761331
Short name T890
Test name
Test status
Simulation time 67201521 ps
CPU time 0.76 seconds
Started Jun 13 01:05:01 PM PDT 24
Finished Jun 13 01:05:05 PM PDT 24
Peak memory 206200 kb
Host smart-2de41532-c226-4a51-9f8a-622414641d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904761331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3904761331
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2254035552
Short name T84
Test name
Test status
Simulation time 18784162422 ps
CPU time 62.48 seconds
Started Jun 13 02:18:00 PM PDT 24
Finished Jun 13 02:19:10 PM PDT 24
Peak memory 253640 kb
Host smart-dcef5d28-72b5-4674-a781-224eba69993d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254035552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2254035552
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2727821608
Short name T445
Test name
Test status
Simulation time 99807497267 ps
CPU time 140.7 seconds
Started Jun 13 01:31:34 PM PDT 24
Finished Jun 13 01:33:56 PM PDT 24
Peak memory 250320 kb
Host smart-65e827f3-28c0-45b5-aab1-f77c6d6faa8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727821608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2727821608
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3868323236
Short name T604
Test name
Test status
Simulation time 209922851 ps
CPU time 3.1 seconds
Started Jun 13 02:34:14 PM PDT 24
Finished Jun 13 02:34:19 PM PDT 24
Peak memory 233404 kb
Host smart-00bd8a3c-6581-466d-a139-1fc3ef6c7b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868323236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3868323236
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.390307698
Short name T454
Test name
Test status
Simulation time 235119319 ps
CPU time 3.6 seconds
Started Jun 13 12:33:42 PM PDT 24
Finished Jun 13 12:33:46 PM PDT 24
Peak memory 225024 kb
Host smart-16654b66-15e9-45ae-8bc5-d211b9478d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390307698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.390307698
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2544406467
Short name T385
Test name
Test status
Simulation time 2209673986 ps
CPU time 22.3 seconds
Started Jun 13 01:32:18 PM PDT 24
Finished Jun 13 01:32:41 PM PDT 24
Peak memory 233520 kb
Host smart-bd960c53-e7d4-488f-80d5-7d8f8e64835c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544406467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2544406467
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1235113856
Short name T921
Test name
Test status
Simulation time 652904676 ps
CPU time 3.55 seconds
Started Jun 13 12:41:24 PM PDT 24
Finished Jun 13 12:41:28 PM PDT 24
Peak memory 225160 kb
Host smart-d09fcc3e-9d69-4203-824c-77394d356caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235113856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1235113856
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1690837152
Short name T275
Test name
Test status
Simulation time 10256425735 ps
CPU time 6.61 seconds
Started Jun 13 02:17:29 PM PDT 24
Finished Jun 13 02:17:39 PM PDT 24
Peak memory 225200 kb
Host smart-090180d9-fc5c-47ad-84be-560b812ae628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690837152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1690837152
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3430042539
Short name T758
Test name
Test status
Simulation time 252696712 ps
CPU time 4.19 seconds
Started Jun 13 01:50:21 PM PDT 24
Finished Jun 13 01:50:27 PM PDT 24
Peak memory 219592 kb
Host smart-a7dcf1c3-9d93-4b06-a90a-4a3571675a76
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3430042539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3430042539
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3378569461
Short name T151
Test name
Test status
Simulation time 171628149 ps
CPU time 0.94 seconds
Started Jun 13 12:55:31 PM PDT 24
Finished Jun 13 12:55:33 PM PDT 24
Peak memory 208272 kb
Host smart-da32c173-037e-4b50-8aac-4bbaedc0a6aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378569461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3378569461
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.131491297
Short name T767
Test name
Test status
Simulation time 567835708 ps
CPU time 8.22 seconds
Started Jun 13 01:55:06 PM PDT 24
Finished Jun 13 01:55:15 PM PDT 24
Peak memory 217032 kb
Host smart-cd03b79a-5584-4759-ba4e-55c65d1c0131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131491297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.131491297
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.408785676
Short name T367
Test name
Test status
Simulation time 554682568 ps
CPU time 3.55 seconds
Started Jun 13 02:07:16 PM PDT 24
Finished Jun 13 02:07:21 PM PDT 24
Peak memory 217008 kb
Host smart-6c622d56-fe04-4531-b27a-4b635b8d2772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408785676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.408785676
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.156282451
Short name T362
Test name
Test status
Simulation time 415216321 ps
CPU time 2.73 seconds
Started Jun 13 12:43:28 PM PDT 24
Finished Jun 13 12:43:31 PM PDT 24
Peak memory 216820 kb
Host smart-e862f1da-481f-4044-9769-9fd37e7e2761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156282451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.156282451
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2568059852
Short name T793
Test name
Test status
Simulation time 34326521 ps
CPU time 0.84 seconds
Started Jun 13 01:32:02 PM PDT 24
Finished Jun 13 01:32:03 PM PDT 24
Peak memory 206592 kb
Host smart-d64ffd4d-07ed-49f5-9dfb-0a828bb4d12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568059852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2568059852
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2511148793
Short name T129
Test name
Test status
Simulation time 81705692 ps
CPU time 2.3 seconds
Started Jun 13 02:12:29 PM PDT 24
Finished Jun 13 02:12:32 PM PDT 24
Peak memory 233204 kb
Host smart-e5cfe00d-a519-498a-a3bc-f2a08b865c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511148793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2511148793
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.4274938292
Short name T864
Test name
Test status
Simulation time 43328331 ps
CPU time 0.72 seconds
Started Jun 13 12:32:31 PM PDT 24
Finished Jun 13 12:32:34 PM PDT 24
Peak memory 205412 kb
Host smart-17bcd7ce-f1d8-4041-9c42-85feab550708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274938292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.4
274938292
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.619460505
Short name T75
Test name
Test status
Simulation time 639523476 ps
CPU time 4.46 seconds
Started Jun 13 12:32:17 PM PDT 24
Finished Jun 13 12:32:24 PM PDT 24
Peak memory 233224 kb
Host smart-4c8ced55-be7a-4d2c-8082-5005d7150998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619460505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.619460505
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3328804939
Short name T355
Test name
Test status
Simulation time 14811081 ps
CPU time 0.78 seconds
Started Jun 13 12:32:37 PM PDT 24
Finished Jun 13 12:32:39 PM PDT 24
Peak memory 206156 kb
Host smart-0fef2ec7-81b6-49a4-9483-60d2a7c60930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328804939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3328804939
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2063968757
Short name T851
Test name
Test status
Simulation time 146717844 ps
CPU time 0.77 seconds
Started Jun 13 12:32:37 PM PDT 24
Finished Jun 13 12:32:39 PM PDT 24
Peak memory 216364 kb
Host smart-76443776-114f-4f8c-9c06-031dd44509a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063968757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2063968757
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3551561287
Short name T174
Test name
Test status
Simulation time 39373186842 ps
CPU time 182.01 seconds
Started Jun 13 12:33:11 PM PDT 24
Finished Jun 13 12:36:16 PM PDT 24
Peak memory 255860 kb
Host smart-9e66425b-4f7c-4249-8482-195eecf7d8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551561287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3551561287
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3632943362
Short name T869
Test name
Test status
Simulation time 2996299346 ps
CPU time 61.66 seconds
Started Jun 13 12:32:35 PM PDT 24
Finished Jun 13 12:33:38 PM PDT 24
Peak memory 241464 kb
Host smart-92dbe6d9-f347-4109-9b62-0bdb31fe594e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632943362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3632943362
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.588444347
Short name T483
Test name
Test status
Simulation time 565601528 ps
CPU time 3.69 seconds
Started Jun 13 12:32:27 PM PDT 24
Finished Jun 13 12:32:33 PM PDT 24
Peak memory 225064 kb
Host smart-a7264d1b-8d15-4e53-9a65-806e0af8646d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588444347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.588444347
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3154301645
Short name T892
Test name
Test status
Simulation time 797741118 ps
CPU time 5.48 seconds
Started Jun 13 12:32:20 PM PDT 24
Finished Jun 13 12:32:28 PM PDT 24
Peak memory 233296 kb
Host smart-20795737-6fa8-4448-b69b-e88119e33d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154301645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3154301645
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3837901276
Short name T952
Test name
Test status
Simulation time 17399078162 ps
CPU time 84.45 seconds
Started Jun 13 12:32:35 PM PDT 24
Finished Jun 13 12:34:01 PM PDT 24
Peak memory 240756 kb
Host smart-6b472ed9-e0be-43a0-8fdb-ba5a9f37d2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837901276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3837901276
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3086322171
Short name T663
Test name
Test status
Simulation time 17608581478 ps
CPU time 24.07 seconds
Started Jun 13 12:32:15 PM PDT 24
Finished Jun 13 12:32:41 PM PDT 24
Peak memory 233296 kb
Host smart-2cd60ad8-bda5-4fac-93d6-cbb024251ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086322171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3086322171
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2879445150
Short name T432
Test name
Test status
Simulation time 6241883519 ps
CPU time 16.07 seconds
Started Jun 13 12:32:20 PM PDT 24
Finished Jun 13 12:32:39 PM PDT 24
Peak memory 233388 kb
Host smart-0a9d24f8-cf5f-4368-9a07-f200224a8a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879445150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2879445150
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1853633446
Short name T579
Test name
Test status
Simulation time 664466354 ps
CPU time 9.27 seconds
Started Jun 13 12:32:43 PM PDT 24
Finished Jun 13 12:32:55 PM PDT 24
Peak memory 223612 kb
Host smart-94ac91ae-8b28-4675-a40e-4f3de32c69d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1853633446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1853633446
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.492958228
Short name T74
Test name
Test status
Simulation time 544235873 ps
CPU time 1.2 seconds
Started Jun 13 12:32:25 PM PDT 24
Finished Jun 13 12:32:29 PM PDT 24
Peak memory 237504 kb
Host smart-3062af6a-f9d0-43b5-b4a6-0b9c50fc856b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492958228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.492958228
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2268307858
Short name T225
Test name
Test status
Simulation time 34814399510 ps
CPU time 343.06 seconds
Started Jun 13 12:32:22 PM PDT 24
Finished Jun 13 12:38:08 PM PDT 24
Peak memory 266144 kb
Host smart-499da47b-ff82-4a41-9194-296a3a979df2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268307858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2268307858
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.912488188
Short name T81
Test name
Test status
Simulation time 671770573 ps
CPU time 4.01 seconds
Started Jun 13 12:32:36 PM PDT 24
Finished Jun 13 12:32:44 PM PDT 24
Peak memory 216976 kb
Host smart-f82414f5-7dba-46cd-88e4-284e71ef5633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912488188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.912488188
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2605053270
Short name T589
Test name
Test status
Simulation time 263102549 ps
CPU time 2.12 seconds
Started Jun 13 12:32:52 PM PDT 24
Finished Jun 13 12:32:55 PM PDT 24
Peak memory 216840 kb
Host smart-4b537a9c-6773-4b45-8262-639916087d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605053270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2605053270
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.868153676
Short name T335
Test name
Test status
Simulation time 129064536 ps
CPU time 2.65 seconds
Started Jun 13 12:32:22 PM PDT 24
Finished Jun 13 12:32:28 PM PDT 24
Peak memory 216880 kb
Host smart-0f531eb9-a5ce-4178-8537-7d864a692e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868153676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.868153676
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3278711790
Short name T755
Test name
Test status
Simulation time 14390959 ps
CPU time 0.72 seconds
Started Jun 13 12:32:22 PM PDT 24
Finished Jun 13 12:32:25 PM PDT 24
Peak memory 206408 kb
Host smart-064efa6c-fd23-4f89-a915-6772b443de1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278711790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3278711790
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2016952979
Short name T506
Test name
Test status
Simulation time 96899935 ps
CPU time 2.46 seconds
Started Jun 13 12:32:15 PM PDT 24
Finished Jun 13 12:32:19 PM PDT 24
Peak memory 227836 kb
Host smart-406b9c4c-c4c0-4efd-a33d-522f6361a33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016952979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2016952979
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.796226275
Short name T507
Test name
Test status
Simulation time 40420891 ps
CPU time 0.79 seconds
Started Jun 13 12:39:44 PM PDT 24
Finished Jun 13 12:39:45 PM PDT 24
Peak memory 206132 kb
Host smart-4733b469-52ec-4bc4-b904-9c3ad1c677cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796226275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.796226275
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.141522144
Short name T720
Test name
Test status
Simulation time 284172088 ps
CPU time 4.95 seconds
Started Jun 13 12:37:25 PM PDT 24
Finished Jun 13 12:37:31 PM PDT 24
Peak memory 225120 kb
Host smart-9827bcf9-4024-497f-9dd6-8eef5e315361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141522144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.141522144
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1197816600
Short name T806
Test name
Test status
Simulation time 47410635 ps
CPU time 0.76 seconds
Started Jun 13 12:58:45 PM PDT 24
Finished Jun 13 12:58:47 PM PDT 24
Peak memory 207296 kb
Host smart-25d00ffe-16fb-4519-ba16-173c01f67834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197816600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1197816600
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.696035969
Short name T166
Test name
Test status
Simulation time 64816715720 ps
CPU time 114.05 seconds
Started Jun 13 02:20:15 PM PDT 24
Finished Jun 13 02:22:20 PM PDT 24
Peak memory 241700 kb
Host smart-bcb1c287-9865-49be-8146-0a1480458d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696035969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.696035969
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2792704954
Short name T23
Test name
Test status
Simulation time 632070659 ps
CPU time 13.04 seconds
Started Jun 13 02:26:55 PM PDT 24
Finished Jun 13 02:27:09 PM PDT 24
Peak memory 236136 kb
Host smart-66ccd965-f691-4aa5-8be8-bc921c7c0c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792704954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2792704954
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1220804954
Short name T167
Test name
Test status
Simulation time 116054166348 ps
CPU time 231.53 seconds
Started Jun 13 02:10:14 PM PDT 24
Finished Jun 13 02:14:07 PM PDT 24
Peak memory 249940 kb
Host smart-43df4621-a4b5-4ede-986c-7fd846d20666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220804954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1220804954
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3034878847
Short name T299
Test name
Test status
Simulation time 2184357854 ps
CPU time 7.76 seconds
Started Jun 13 02:02:55 PM PDT 24
Finished Jun 13 02:03:03 PM PDT 24
Peak memory 225312 kb
Host smart-ba0fbcef-cdbb-4b2f-ad70-782bcbb04ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034878847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3034878847
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3702899349
Short name T284
Test name
Test status
Simulation time 37866250204 ps
CPU time 19.49 seconds
Started Jun 13 01:55:35 PM PDT 24
Finished Jun 13 01:55:55 PM PDT 24
Peak memory 233492 kb
Host smart-8ce510aa-3dcc-4f6a-b991-919319511e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702899349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3702899349
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2336172681
Short name T274
Test name
Test status
Simulation time 1377227163 ps
CPU time 8.39 seconds
Started Jun 13 01:10:49 PM PDT 24
Finished Jun 13 01:10:58 PM PDT 24
Peak memory 241584 kb
Host smart-9a9a7b63-9d8f-4daa-adc5-f148912d6ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336172681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2336172681
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1893151722
Short name T291
Test name
Test status
Simulation time 11167686000 ps
CPU time 11.43 seconds
Started Jun 13 01:44:08 PM PDT 24
Finished Jun 13 01:44:21 PM PDT 24
Peak memory 233500 kb
Host smart-0800934c-5837-49b6-b26b-e82a743c487c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893151722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1893151722
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.4222965029
Short name T635
Test name
Test status
Simulation time 2175929861 ps
CPU time 7.75 seconds
Started Jun 13 02:29:34 PM PDT 24
Finished Jun 13 02:29:43 PM PDT 24
Peak memory 241592 kb
Host smart-e513982a-2ae1-4b39-8014-264478ab913d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222965029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4222965029
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3190202057
Short name T141
Test name
Test status
Simulation time 3820573233 ps
CPU time 19.35 seconds
Started Jun 13 01:23:07 PM PDT 24
Finished Jun 13 01:23:27 PM PDT 24
Peak memory 221424 kb
Host smart-d2ba1409-3445-4031-b37a-f28695d1de02
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3190202057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3190202057
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2477996637
Short name T22
Test name
Test status
Simulation time 15685433063 ps
CPU time 66.24 seconds
Started Jun 13 01:24:47 PM PDT 24
Finished Jun 13 01:25:54 PM PDT 24
Peak memory 250348 kb
Host smart-a84070e4-4adc-4d6b-9bf6-877b4b8784fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477996637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2477996637
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2140679909
Short name T306
Test name
Test status
Simulation time 22878568602 ps
CPU time 56.87 seconds
Started Jun 13 02:12:48 PM PDT 24
Finished Jun 13 02:13:45 PM PDT 24
Peak memory 217052 kb
Host smart-1a357a9c-7019-4bf5-a97c-9becd2b87dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140679909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2140679909
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3419352368
Short name T573
Test name
Test status
Simulation time 1465570664 ps
CPU time 3.03 seconds
Started Jun 13 01:07:05 PM PDT 24
Finished Jun 13 01:07:09 PM PDT 24
Peak memory 216972 kb
Host smart-e405d7e6-ba31-4b6c-90e5-606636945a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419352368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3419352368
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.4181769604
Short name T418
Test name
Test status
Simulation time 146335306 ps
CPU time 1.32 seconds
Started Jun 13 01:45:00 PM PDT 24
Finished Jun 13 01:45:02 PM PDT 24
Peak memory 217032 kb
Host smart-03a160e8-6e9b-460b-9eb8-c76ec01441a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181769604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.4181769604
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.4084735127
Short name T942
Test name
Test status
Simulation time 121570393 ps
CPU time 0.84 seconds
Started Jun 13 01:06:49 PM PDT 24
Finished Jun 13 01:06:51 PM PDT 24
Peak memory 206576 kb
Host smart-6e486dae-fe36-45f1-9389-2bd830b566e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084735127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.4084735127
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1988191165
Short name T326
Test name
Test status
Simulation time 407449293 ps
CPU time 5.98 seconds
Started Jun 13 02:00:15 PM PDT 24
Finished Jun 13 02:00:22 PM PDT 24
Peak memory 233392 kb
Host smart-02cb53f8-6f16-4ad9-b2f4-bfd426681af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988191165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1988191165
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.4001567288
Short name T717
Test name
Test status
Simulation time 56252668 ps
CPU time 0.73 seconds
Started Jun 13 01:21:12 PM PDT 24
Finished Jun 13 01:21:15 PM PDT 24
Peak memory 206124 kb
Host smart-a589e721-3706-435a-94ed-462988984757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001567288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
4001567288
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3161572288
Short name T733
Test name
Test status
Simulation time 312730358 ps
CPU time 4.58 seconds
Started Jun 13 01:41:15 PM PDT 24
Finished Jun 13 01:41:23 PM PDT 24
Peak memory 233384 kb
Host smart-253682dc-a364-4d4a-8302-4a21acb6d181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161572288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3161572288
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2015107653
Short name T686
Test name
Test status
Simulation time 19598369 ps
CPU time 0.81 seconds
Started Jun 13 01:37:04 PM PDT 24
Finished Jun 13 01:37:05 PM PDT 24
Peak memory 207640 kb
Host smart-332ddb5b-2561-4601-9e48-7b76f10f324e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015107653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2015107653
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1571003626
Short name T16
Test name
Test status
Simulation time 8686336358 ps
CPU time 119.14 seconds
Started Jun 13 01:47:24 PM PDT 24
Finished Jun 13 01:49:24 PM PDT 24
Peak memory 258064 kb
Host smart-77f235af-8418-4b72-9958-d61cc49bf5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571003626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1571003626
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1595997618
Short name T935
Test name
Test status
Simulation time 5025183375 ps
CPU time 48.18 seconds
Started Jun 13 02:23:08 PM PDT 24
Finished Jun 13 02:23:57 PM PDT 24
Peak memory 225376 kb
Host smart-d92c732b-5d43-47c4-9261-7ba579168937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595997618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1595997618
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2257664838
Short name T646
Test name
Test status
Simulation time 93991203395 ps
CPU time 185.92 seconds
Started Jun 13 01:53:24 PM PDT 24
Finished Jun 13 01:56:31 PM PDT 24
Peak memory 251848 kb
Host smart-c338e210-7a91-4d2a-96b1-90d703f55329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257664838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2257664838
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3267677546
Short name T145
Test name
Test status
Simulation time 8044814815 ps
CPU time 56.96 seconds
Started Jun 13 01:46:34 PM PDT 24
Finished Jun 13 01:47:32 PM PDT 24
Peak memory 233512 kb
Host smart-c677f220-68c9-48c7-850c-50e20a8c3636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267677546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3267677546
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.665517940
Short name T485
Test name
Test status
Simulation time 2382583044 ps
CPU time 28.27 seconds
Started Jun 13 02:45:38 PM PDT 24
Finished Jun 13 02:46:18 PM PDT 24
Peak memory 225232 kb
Host smart-0eac4704-5607-4fa5-b692-72cca3d96ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665517940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.665517940
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1523727446
Short name T906
Test name
Test status
Simulation time 8194795840 ps
CPU time 34.82 seconds
Started Jun 13 01:16:53 PM PDT 24
Finished Jun 13 01:17:28 PM PDT 24
Peak memory 249384 kb
Host smart-aaaea807-6718-426b-ae55-45c4525e7811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523727446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1523727446
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3229300973
Short name T265
Test name
Test status
Simulation time 4507614261 ps
CPU time 12.06 seconds
Started Jun 13 12:51:31 PM PDT 24
Finished Jun 13 12:51:43 PM PDT 24
Peak memory 225256 kb
Host smart-75f29609-4c9a-4706-bbfd-3b4407e1ff63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229300973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3229300973
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.610358997
Short name T187
Test name
Test status
Simulation time 1373125772 ps
CPU time 5.75 seconds
Started Jun 13 02:05:09 PM PDT 24
Finished Jun 13 02:05:15 PM PDT 24
Peak memory 233420 kb
Host smart-7cc002c2-09b7-422f-9a96-5af47fc3a9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610358997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.610358997
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1182277462
Short name T648
Test name
Test status
Simulation time 4359549899 ps
CPU time 6.16 seconds
Started Jun 13 01:37:01 PM PDT 24
Finished Jun 13 01:37:07 PM PDT 24
Peak memory 220716 kb
Host smart-8f2a0085-0eed-44c1-833a-a05042fad4c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1182277462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1182277462
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3802972430
Short name T563
Test name
Test status
Simulation time 2496697350 ps
CPU time 33.99 seconds
Started Jun 13 01:03:27 PM PDT 24
Finished Jun 13 01:04:02 PM PDT 24
Peak memory 251080 kb
Host smart-ddaa4fe1-e53e-4296-810d-ffb82e71f1b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802972430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3802972430
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2636564231
Short name T305
Test name
Test status
Simulation time 6963744575 ps
CPU time 24.63 seconds
Started Jun 13 02:28:38 PM PDT 24
Finished Jun 13 02:29:03 PM PDT 24
Peak memory 217036 kb
Host smart-f036fc18-e2b6-4183-afbb-2754cedb0621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636564231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2636564231
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1270798728
Short name T681
Test name
Test status
Simulation time 829228680 ps
CPU time 2.78 seconds
Started Jun 13 01:57:46 PM PDT 24
Finished Jun 13 01:57:50 PM PDT 24
Peak memory 217008 kb
Host smart-4736d5e6-1390-4eca-b8a8-ecb3f6711164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270798728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1270798728
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3760490266
Short name T476
Test name
Test status
Simulation time 22208741 ps
CPU time 0.68 seconds
Started Jun 13 01:45:44 PM PDT 24
Finished Jun 13 01:45:46 PM PDT 24
Peak memory 206308 kb
Host smart-85b17f92-f204-4b95-9508-9c2e97030a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760490266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3760490266
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1701411309
Short name T715
Test name
Test status
Simulation time 85640131 ps
CPU time 0.87 seconds
Started Jun 13 02:00:30 PM PDT 24
Finished Jun 13 02:00:31 PM PDT 24
Peak memory 206616 kb
Host smart-21a12559-216a-4e82-9e40-17b7caeed388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701411309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1701411309
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2147386855
Short name T763
Test name
Test status
Simulation time 432268768 ps
CPU time 6.41 seconds
Started Jun 13 02:29:43 PM PDT 24
Finished Jun 13 02:29:51 PM PDT 24
Peak memory 233400 kb
Host smart-b5fb2611-dd5e-4eea-9706-0928f12ad7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147386855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2147386855
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3574136636
Short name T379
Test name
Test status
Simulation time 50892963 ps
CPU time 0.73 seconds
Started Jun 13 01:01:33 PM PDT 24
Finished Jun 13 01:01:34 PM PDT 24
Peak memory 205524 kb
Host smart-345cd85a-6a10-471e-bbc2-7b35d7f59b15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574136636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3574136636
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.4221606382
Short name T555
Test name
Test status
Simulation time 135759163 ps
CPU time 2.25 seconds
Started Jun 13 01:56:08 PM PDT 24
Finished Jun 13 01:56:14 PM PDT 24
Peak memory 223720 kb
Host smart-e0d74a6f-40a4-4464-a5d6-32550b27ac37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221606382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.4221606382
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1281709131
Short name T590
Test name
Test status
Simulation time 20203796 ps
CPU time 0.79 seconds
Started Jun 13 01:57:35 PM PDT 24
Finished Jun 13 01:57:37 PM PDT 24
Peak memory 207344 kb
Host smart-c13966f9-9607-4779-8af3-ac542a6489aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281709131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1281709131
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1999748912
Short name T749
Test name
Test status
Simulation time 20444929901 ps
CPU time 92.84 seconds
Started Jun 13 01:32:31 PM PDT 24
Finished Jun 13 01:34:05 PM PDT 24
Peak memory 254416 kb
Host smart-44d2c42f-ee65-423e-b928-de1848c58dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999748912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1999748912
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3713051447
Short name T9
Test name
Test status
Simulation time 33210273826 ps
CPU time 336.08 seconds
Started Jun 13 01:39:35 PM PDT 24
Finished Jun 13 01:45:12 PM PDT 24
Peak memory 253976 kb
Host smart-bf879bad-05d7-493c-854c-7539b0edc6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713051447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3713051447
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3806279294
Short name T566
Test name
Test status
Simulation time 133740242082 ps
CPU time 252.88 seconds
Started Jun 13 02:25:38 PM PDT 24
Finished Jun 13 02:29:52 PM PDT 24
Peak memory 241748 kb
Host smart-3bca5c50-cc00-4888-b369-2013aa673b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806279294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3806279294
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2849202646
Short name T904
Test name
Test status
Simulation time 911823494 ps
CPU time 6.06 seconds
Started Jun 13 01:27:35 PM PDT 24
Finished Jun 13 01:27:43 PM PDT 24
Peak memory 225216 kb
Host smart-d67dbfe0-ae18-483f-af5f-51aeac6f0af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849202646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2849202646
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1512617720
Short name T457
Test name
Test status
Simulation time 147284898 ps
CPU time 5.43 seconds
Started Jun 13 12:58:41 PM PDT 24
Finished Jun 13 12:58:48 PM PDT 24
Peak memory 233352 kb
Host smart-d37c8056-b3e3-4703-afb6-50c15f15a10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512617720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1512617720
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2837720240
Short name T337
Test name
Test status
Simulation time 13139205246 ps
CPU time 19.27 seconds
Started Jun 13 01:26:31 PM PDT 24
Finished Jun 13 01:26:51 PM PDT 24
Peak memory 225260 kb
Host smart-eac8bc4b-2e9b-4f13-aff6-76cb190cd392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837720240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2837720240
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.4289890435
Short name T859
Test name
Test status
Simulation time 9708209053 ps
CPU time 23.86 seconds
Started Jun 13 02:34:10 PM PDT 24
Finished Jun 13 02:34:35 PM PDT 24
Peak memory 225232 kb
Host smart-569dca2d-253d-4e3a-9714-3798d3dbfd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289890435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.4289890435
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.361573455
Short name T543
Test name
Test status
Simulation time 24043919041 ps
CPU time 14.92 seconds
Started Jun 13 12:35:26 PM PDT 24
Finished Jun 13 12:35:42 PM PDT 24
Peak memory 225132 kb
Host smart-bc886374-58c0-4842-ae54-2ec63d149194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361573455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.361573455
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3234900747
Short name T792
Test name
Test status
Simulation time 1429472800 ps
CPU time 10.39 seconds
Started Jun 13 01:52:25 PM PDT 24
Finished Jun 13 01:52:37 PM PDT 24
Peak memory 223108 kb
Host smart-d28b1f79-b325-45a0-a15e-dfa975c7cf5d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3234900747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3234900747
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2887105594
Short name T531
Test name
Test status
Simulation time 66553429 ps
CPU time 0.93 seconds
Started Jun 13 01:52:18 PM PDT 24
Finished Jun 13 01:52:21 PM PDT 24
Peak memory 207324 kb
Host smart-4c3e0f59-f26e-44fe-9111-4d84cfd9e9f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887105594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2887105594
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3254988489
Short name T580
Test name
Test status
Simulation time 9735501657 ps
CPU time 25.41 seconds
Started Jun 13 02:24:17 PM PDT 24
Finished Jun 13 02:24:43 PM PDT 24
Peak memory 217020 kb
Host smart-e5a43658-787f-49b9-8464-2ec6dc272385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254988489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3254988489
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2396732457
Short name T343
Test name
Test status
Simulation time 979751529 ps
CPU time 4.17 seconds
Started Jun 13 01:27:17 PM PDT 24
Finished Jun 13 01:27:23 PM PDT 24
Peak memory 216936 kb
Host smart-ef09bc70-1902-4950-90d2-a8971a44ab2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396732457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2396732457
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1708412257
Short name T354
Test name
Test status
Simulation time 54168436 ps
CPU time 1.29 seconds
Started Jun 13 12:37:51 PM PDT 24
Finished Jun 13 12:37:54 PM PDT 24
Peak memory 208768 kb
Host smart-e3c6cc79-d06b-496d-837b-827c69adcbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708412257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1708412257
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.4211836237
Short name T824
Test name
Test status
Simulation time 121976567 ps
CPU time 0.79 seconds
Started Jun 13 12:42:01 PM PDT 24
Finished Jun 13 12:42:03 PM PDT 24
Peak memory 206524 kb
Host smart-55fddd77-57fb-4505-8bc0-81fc8055f637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211836237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.4211836237
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.765610300
Short name T179
Test name
Test status
Simulation time 13343454884 ps
CPU time 14.86 seconds
Started Jun 13 01:30:45 PM PDT 24
Finished Jun 13 01:31:00 PM PDT 24
Peak memory 249716 kb
Host smart-f4cc715b-d38a-484b-b43e-26ab0a0f987b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765610300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.765610300
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3202967530
Short name T390
Test name
Test status
Simulation time 43658147 ps
CPU time 0.77 seconds
Started Jun 13 12:49:26 PM PDT 24
Finished Jun 13 12:49:29 PM PDT 24
Peak memory 205524 kb
Host smart-83e2439c-ed36-47a1-ae60-64b112108dd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202967530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3202967530
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1607114644
Short name T492
Test name
Test status
Simulation time 772579829 ps
CPU time 9.01 seconds
Started Jun 13 01:41:51 PM PDT 24
Finished Jun 13 01:42:01 PM PDT 24
Peak memory 233268 kb
Host smart-cb5bc97a-848e-4327-813b-9c0f623ed94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607114644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1607114644
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.547185607
Short name T905
Test name
Test status
Simulation time 40833070 ps
CPU time 0.82 seconds
Started Jun 13 02:14:45 PM PDT 24
Finished Jun 13 02:14:47 PM PDT 24
Peak memory 207360 kb
Host smart-22e236c5-b783-4006-9830-e8746a1ec082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547185607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.547185607
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2579057805
Short name T706
Test name
Test status
Simulation time 1350033055 ps
CPU time 18.25 seconds
Started Jun 13 02:04:23 PM PDT 24
Finished Jun 13 02:04:43 PM PDT 24
Peak memory 241608 kb
Host smart-ac1c2973-0ee2-430b-9b52-a1f516e9c020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579057805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2579057805
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1632260209
Short name T770
Test name
Test status
Simulation time 25953758403 ps
CPU time 165.11 seconds
Started Jun 13 12:33:34 PM PDT 24
Finished Jun 13 12:36:21 PM PDT 24
Peak memory 266168 kb
Host smart-98026aef-db49-4b03-a779-a029deb460bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632260209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1632260209
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2147454466
Short name T636
Test name
Test status
Simulation time 69286939577 ps
CPU time 158.8 seconds
Started Jun 13 01:27:22 PM PDT 24
Finished Jun 13 01:30:02 PM PDT 24
Peak memory 250404 kb
Host smart-c322b2a4-626e-4d1e-a46b-f175d1f1fb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147454466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2147454466
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2313403857
Short name T783
Test name
Test status
Simulation time 220586394 ps
CPU time 6.83 seconds
Started Jun 13 01:59:31 PM PDT 24
Finished Jun 13 01:59:39 PM PDT 24
Peak memory 225264 kb
Host smart-b947d70c-c4ef-423d-8321-29a104378e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313403857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2313403857
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2416257092
Short name T895
Test name
Test status
Simulation time 799465521 ps
CPU time 5.62 seconds
Started Jun 13 01:55:42 PM PDT 24
Finished Jun 13 01:55:49 PM PDT 24
Peak memory 225180 kb
Host smart-7c0eb035-6aca-48fc-9ef1-d00cc22603b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416257092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2416257092
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3264314991
Short name T850
Test name
Test status
Simulation time 10355483627 ps
CPU time 19.5 seconds
Started Jun 13 01:53:24 PM PDT 24
Finished Jun 13 01:53:44 PM PDT 24
Peak memory 233440 kb
Host smart-1ac32692-2902-4c41-9bc7-eb46ecf3450f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264314991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3264314991
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3423340007
Short name T157
Test name
Test status
Simulation time 8061452994 ps
CPU time 9.4 seconds
Started Jun 13 01:18:46 PM PDT 24
Finished Jun 13 01:18:56 PM PDT 24
Peak memory 233440 kb
Host smart-3fde12a7-773b-4d83-af0f-23d89a171f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423340007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3423340007
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2169067900
Short name T540
Test name
Test status
Simulation time 485378175 ps
CPU time 3.76 seconds
Started Jun 13 01:25:30 PM PDT 24
Finished Jun 13 01:25:34 PM PDT 24
Peak memory 225256 kb
Host smart-5160bb92-2df3-4f5c-b075-fe56fbb7cce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169067900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2169067900
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1906874380
Short name T898
Test name
Test status
Simulation time 6995173610 ps
CPU time 14.93 seconds
Started Jun 13 01:47:03 PM PDT 24
Finished Jun 13 01:47:20 PM PDT 24
Peak memory 221236 kb
Host smart-1c347418-c7a1-4f60-a935-e5b00a5d0735
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1906874380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1906874380
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3134307956
Short name T30
Test name
Test status
Simulation time 13234832373 ps
CPU time 54.2 seconds
Started Jun 13 01:54:42 PM PDT 24
Finished Jun 13 01:55:43 PM PDT 24
Peak memory 249956 kb
Host smart-d64c063f-506c-4db6-ad0d-ec8baf5ea4f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134307956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3134307956
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1414115600
Short name T644
Test name
Test status
Simulation time 3916348097 ps
CPU time 22.75 seconds
Started Jun 13 01:21:04 PM PDT 24
Finished Jun 13 01:21:28 PM PDT 24
Peak memory 217076 kb
Host smart-da3dcdc0-00b1-45a5-8afe-016370d61205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414115600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1414115600
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.35175203
Short name T27
Test name
Test status
Simulation time 854986642 ps
CPU time 5.14 seconds
Started Jun 13 02:41:27 PM PDT 24
Finished Jun 13 02:41:37 PM PDT 24
Peak memory 217008 kb
Host smart-73ba7264-ed75-47e0-a0fa-b8e6126f97d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35175203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.35175203
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3495744712
Short name T761
Test name
Test status
Simulation time 350987727 ps
CPU time 1.05 seconds
Started Jun 13 12:36:33 PM PDT 24
Finished Jun 13 12:36:35 PM PDT 24
Peak memory 207636 kb
Host smart-281f4205-7b0b-4533-bb26-a5ae49848a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495744712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3495744712
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2965937953
Short name T693
Test name
Test status
Simulation time 91551195 ps
CPU time 0.79 seconds
Started Jun 13 01:33:02 PM PDT 24
Finished Jun 13 01:33:04 PM PDT 24
Peak memory 206616 kb
Host smart-2f42603c-917d-48c0-a192-74b609b988ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965937953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2965937953
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1156851738
Short name T472
Test name
Test status
Simulation time 512735179 ps
CPU time 7.72 seconds
Started Jun 13 01:40:12 PM PDT 24
Finished Jun 13 01:40:21 PM PDT 24
Peak memory 241368 kb
Host smart-d00bcb70-d2ed-4dfa-8a13-4ff75341fd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156851738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1156851738
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.4073783916
Short name T501
Test name
Test status
Simulation time 69061794 ps
CPU time 0.74 seconds
Started Jun 13 12:52:05 PM PDT 24
Finished Jun 13 12:52:06 PM PDT 24
Peak memory 205524 kb
Host smart-19259df6-63b1-4bcd-812f-4e1223e89f05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073783916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
4073783916
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1089573739
Short name T549
Test name
Test status
Simulation time 4598574571 ps
CPU time 13.47 seconds
Started Jun 13 01:47:23 PM PDT 24
Finished Jun 13 01:47:38 PM PDT 24
Peak memory 233480 kb
Host smart-1a485ad0-3dfb-462d-af82-64215eff431b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089573739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1089573739
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.745738946
Short name T611
Test name
Test status
Simulation time 75827440 ps
CPU time 0.84 seconds
Started Jun 13 01:26:45 PM PDT 24
Finished Jun 13 01:26:46 PM PDT 24
Peak memory 207288 kb
Host smart-e5a9b659-4296-45db-b68d-511e71cbbaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745738946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.745738946
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1295136661
Short name T200
Test name
Test status
Simulation time 6204626997 ps
CPU time 106.01 seconds
Started Jun 13 01:32:00 PM PDT 24
Finished Jun 13 01:33:47 PM PDT 24
Peak memory 249940 kb
Host smart-c1fb304c-404f-4901-b261-7c7bfea8ea4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295136661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1295136661
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2886977278
Short name T203
Test name
Test status
Simulation time 7957888219 ps
CPU time 54.45 seconds
Started Jun 13 02:15:33 PM PDT 24
Finished Jun 13 02:16:29 PM PDT 24
Peak memory 225376 kb
Host smart-fdcf5f2a-da9b-4748-9b62-5b0d2b3733b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886977278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2886977278
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.149041883
Short name T289
Test name
Test status
Simulation time 28162425048 ps
CPU time 246.58 seconds
Started Jun 13 02:24:38 PM PDT 24
Finished Jun 13 02:28:46 PM PDT 24
Peak memory 249964 kb
Host smart-122e26e6-2f38-424b-958f-3c1b145289b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149041883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.149041883
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.978572679
Short name T605
Test name
Test status
Simulation time 1286150497 ps
CPU time 15.28 seconds
Started Jun 13 02:02:53 PM PDT 24
Finished Jun 13 02:03:08 PM PDT 24
Peak memory 225260 kb
Host smart-ae3c9504-ce83-4467-a669-fc57850b3fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978572679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.978572679
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.4105505403
Short name T726
Test name
Test status
Simulation time 866309343 ps
CPU time 4.55 seconds
Started Jun 13 01:23:21 PM PDT 24
Finished Jun 13 01:23:28 PM PDT 24
Peak memory 225192 kb
Host smart-2718fa48-15b2-40a4-95d3-6850b15fa6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105505403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.4105505403
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3839493761
Short name T782
Test name
Test status
Simulation time 29483827703 ps
CPU time 33.02 seconds
Started Jun 13 01:03:15 PM PDT 24
Finished Jun 13 01:03:49 PM PDT 24
Peak memory 225160 kb
Host smart-70e05888-a252-494d-8a6b-7ed4599a1be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839493761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3839493761
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2761161536
Short name T816
Test name
Test status
Simulation time 676585721 ps
CPU time 6.48 seconds
Started Jun 13 01:14:23 PM PDT 24
Finished Jun 13 01:14:31 PM PDT 24
Peak memory 233412 kb
Host smart-8027d61f-442d-4870-aff3-3068f80d7956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761161536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2761161536
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1356763730
Short name T25
Test name
Test status
Simulation time 144009423 ps
CPU time 2.86 seconds
Started Jun 13 01:34:58 PM PDT 24
Finished Jun 13 01:35:01 PM PDT 24
Peak memory 233468 kb
Host smart-9d2be5b8-36dd-4abe-971b-5c93fd33b8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356763730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1356763730
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2180213004
Short name T403
Test name
Test status
Simulation time 508417394 ps
CPU time 5.15 seconds
Started Jun 13 01:22:29 PM PDT 24
Finished Jun 13 01:22:35 PM PDT 24
Peak memory 223864 kb
Host smart-8bf05c60-2831-4656-8f43-ed4f999bd023
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2180213004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2180213004
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3654580342
Short name T674
Test name
Test status
Simulation time 164454373 ps
CPU time 1.06 seconds
Started Jun 13 12:33:38 PM PDT 24
Finished Jun 13 12:33:40 PM PDT 24
Peak memory 207672 kb
Host smart-8de896b6-0f7d-42c7-8d59-76dc06607c5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654580342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3654580342
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2271150437
Short name T836
Test name
Test status
Simulation time 5286093349 ps
CPU time 22.38 seconds
Started Jun 13 12:54:28 PM PDT 24
Finished Jun 13 12:54:51 PM PDT 24
Peak memory 217048 kb
Host smart-a8afdf76-37b3-4696-8a80-6ba79de9e5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271150437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2271150437
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1323660969
Short name T843
Test name
Test status
Simulation time 7504204221 ps
CPU time 19.62 seconds
Started Jun 13 01:34:06 PM PDT 24
Finished Jun 13 01:34:27 PM PDT 24
Peak memory 217040 kb
Host smart-871d4847-f3a6-4c00-bd1a-8d0a2e2ee557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323660969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1323660969
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.184493044
Short name T881
Test name
Test status
Simulation time 33637194 ps
CPU time 0.92 seconds
Started Jun 13 01:50:57 PM PDT 24
Finished Jun 13 01:51:01 PM PDT 24
Peak memory 207580 kb
Host smart-cf8e2603-a823-4e84-990b-a882ad4fd15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184493044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.184493044
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.4175576888
Short name T931
Test name
Test status
Simulation time 999024922 ps
CPU time 0.86 seconds
Started Jun 13 02:04:45 PM PDT 24
Finished Jun 13 02:04:47 PM PDT 24
Peak memory 206620 kb
Host smart-268dbfbf-0bfa-4bcb-82ed-3317f552b2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175576888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4175576888
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.4166251106
Short name T503
Test name
Test status
Simulation time 121018266 ps
CPU time 2.48 seconds
Started Jun 13 02:26:46 PM PDT 24
Finished Jun 13 02:26:49 PM PDT 24
Peak memory 219404 kb
Host smart-d7757331-be95-4243-b1f7-77df1e6fdc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166251106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.4166251106
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.232828019
Short name T808
Test name
Test status
Simulation time 92534390 ps
CPU time 0.7 seconds
Started Jun 13 01:56:07 PM PDT 24
Finished Jun 13 01:56:10 PM PDT 24
Peak memory 206180 kb
Host smart-725feef6-f997-4b76-bb9b-e329c47f6bf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232828019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.232828019
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3779965318
Short name T94
Test name
Test status
Simulation time 3585187370 ps
CPU time 6.77 seconds
Started Jun 13 12:46:30 PM PDT 24
Finished Jun 13 12:46:38 PM PDT 24
Peak memory 233404 kb
Host smart-4f6efdcc-90de-4622-86b8-95620919b785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779965318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3779965318
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3231016027
Short name T430
Test name
Test status
Simulation time 18821432 ps
CPU time 0.83 seconds
Started Jun 13 01:02:29 PM PDT 24
Finished Jun 13 01:02:31 PM PDT 24
Peak memory 207272 kb
Host smart-dfa59fec-48a9-4383-821a-e1ad9149bc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231016027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3231016027
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.642876006
Short name T165
Test name
Test status
Simulation time 20048672014 ps
CPU time 50.82 seconds
Started Jun 13 01:00:05 PM PDT 24
Finished Jun 13 01:00:57 PM PDT 24
Peak memory 249852 kb
Host smart-08be739f-580f-4f5d-9b21-b4c82b0c047a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642876006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.642876006
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3730332851
Short name T812
Test name
Test status
Simulation time 2387984880 ps
CPU time 64.13 seconds
Started Jun 13 01:55:45 PM PDT 24
Finished Jun 13 01:56:50 PM PDT 24
Peak memory 258060 kb
Host smart-ffa7b993-3408-4359-9873-1cbfb76de1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730332851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3730332851
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.692736850
Short name T780
Test name
Test status
Simulation time 9598850862 ps
CPU time 31.15 seconds
Started Jun 13 01:42:28 PM PDT 24
Finished Jun 13 01:43:00 PM PDT 24
Peak memory 218212 kb
Host smart-d13868ed-757a-4c38-b9a4-99c23d11b17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692736850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.692736850
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1194213465
Short name T422
Test name
Test status
Simulation time 297190834 ps
CPU time 6.23 seconds
Started Jun 13 01:25:03 PM PDT 24
Finished Jun 13 01:25:10 PM PDT 24
Peak memory 225244 kb
Host smart-b31e994a-d2a5-49f1-bc00-ae8b11a482cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194213465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1194213465
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1162105158
Short name T775
Test name
Test status
Simulation time 756962457 ps
CPU time 3.88 seconds
Started Jun 13 02:42:29 PM PDT 24
Finished Jun 13 02:42:41 PM PDT 24
Peak memory 225132 kb
Host smart-c0c823b3-c681-406e-b337-6756efe0fc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162105158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1162105158
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.509009933
Short name T254
Test name
Test status
Simulation time 5457974360 ps
CPU time 15.46 seconds
Started Jun 13 02:17:16 PM PDT 24
Finished Jun 13 02:17:36 PM PDT 24
Peak memory 241640 kb
Host smart-e8bca5b7-e960-41ca-8580-a623b237a0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509009933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.509009933
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3168996655
Short name T407
Test name
Test status
Simulation time 471233492 ps
CPU time 3.49 seconds
Started Jun 13 02:20:02 PM PDT 24
Finished Jun 13 02:20:14 PM PDT 24
Peak memory 233404 kb
Host smart-53efc7db-3e1d-44df-961e-7095e970ea69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168996655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3168996655
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.4014618418
Short name T944
Test name
Test status
Simulation time 473862407 ps
CPU time 4.39 seconds
Started Jun 13 12:37:16 PM PDT 24
Finished Jun 13 12:37:24 PM PDT 24
Peak memory 225172 kb
Host smart-fab9279e-6fa6-4885-8353-d6363f03ce0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014618418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.4014618418
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.633982100
Short name T565
Test name
Test status
Simulation time 264272279 ps
CPU time 3.82 seconds
Started Jun 13 02:07:08 PM PDT 24
Finished Jun 13 02:07:13 PM PDT 24
Peak memory 220028 kb
Host smart-1a87b6c6-ef64-4560-97c3-a5b05a13b719
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=633982100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.633982100
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.147051787
Short name T152
Test name
Test status
Simulation time 53966256402 ps
CPU time 171.53 seconds
Started Jun 13 01:30:02 PM PDT 24
Finished Jun 13 01:32:54 PM PDT 24
Peak memory 265476 kb
Host smart-d310a4e4-8727-4cca-98a0-ab010bf4edc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147051787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.147051787
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3283254890
Short name T861
Test name
Test status
Simulation time 4405442460 ps
CPU time 23.97 seconds
Started Jun 13 12:36:26 PM PDT 24
Finished Jun 13 12:36:53 PM PDT 24
Peak memory 221024 kb
Host smart-03855206-57a5-454f-9a7c-dc367a41c196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283254890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3283254890
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3369939811
Short name T493
Test name
Test status
Simulation time 13364602947 ps
CPU time 10.51 seconds
Started Jun 13 02:22:49 PM PDT 24
Finished Jun 13 02:23:00 PM PDT 24
Peak memory 217092 kb
Host smart-3133ffb4-b3bf-476e-8ba8-b0ca3051d7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369939811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3369939811
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3884995
Short name T600
Test name
Test status
Simulation time 331323251 ps
CPU time 1.79 seconds
Started Jun 13 12:49:07 PM PDT 24
Finished Jun 13 12:49:10 PM PDT 24
Peak memory 216952 kb
Host smart-a2e29e2b-b4e6-4746-9d03-285b8dd906cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3884995
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1560879610
Short name T774
Test name
Test status
Simulation time 149034247 ps
CPU time 0.76 seconds
Started Jun 13 01:34:57 PM PDT 24
Finished Jun 13 01:34:58 PM PDT 24
Peak memory 206624 kb
Host smart-248f91be-903a-4652-9d7e-e7460a81a936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560879610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1560879610
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.223387448
Short name T707
Test name
Test status
Simulation time 16518525096 ps
CPU time 6.93 seconds
Started Jun 13 01:58:33 PM PDT 24
Finished Jun 13 01:58:41 PM PDT 24
Peak memory 233512 kb
Host smart-dec8c1e0-e114-4131-9667-bb3ea2952400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223387448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.223387448
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3719882741
Short name T7
Test name
Test status
Simulation time 13311769 ps
CPU time 0.75 seconds
Started Jun 13 02:13:43 PM PDT 24
Finished Jun 13 02:13:45 PM PDT 24
Peak memory 205572 kb
Host smart-9caf8ef0-c7e8-4408-8b3e-88d68813e49d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719882741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3719882741
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2342109353
Short name T937
Test name
Test status
Simulation time 1113375445 ps
CPU time 7.51 seconds
Started Jun 13 01:15:46 PM PDT 24
Finished Jun 13 01:15:54 PM PDT 24
Peak memory 233344 kb
Host smart-8ffbbf11-d255-47bc-b4b3-1ff52c7bb1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342109353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2342109353
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.365187885
Short name T874
Test name
Test status
Simulation time 36770530 ps
CPU time 0.78 seconds
Started Jun 13 01:37:26 PM PDT 24
Finished Jun 13 01:37:27 PM PDT 24
Peak memory 207580 kb
Host smart-468145a9-6cda-4f60-9e4c-ddf3809972a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365187885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.365187885
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1457212237
Short name T48
Test name
Test status
Simulation time 9297375651 ps
CPU time 23.76 seconds
Started Jun 13 12:52:20 PM PDT 24
Finished Jun 13 12:52:45 PM PDT 24
Peak memory 241564 kb
Host smart-3ba720ea-5623-42ba-8e1c-9c40fa709d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457212237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1457212237
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2255701408
Short name T882
Test name
Test status
Simulation time 8066001956 ps
CPU time 32.31 seconds
Started Jun 13 01:29:29 PM PDT 24
Finished Jun 13 01:30:02 PM PDT 24
Peak memory 225348 kb
Host smart-4948415d-54f9-4d48-a143-9eb3693824cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255701408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2255701408
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3563142880
Short name T802
Test name
Test status
Simulation time 1746384526 ps
CPU time 25.14 seconds
Started Jun 13 12:33:37 PM PDT 24
Finished Jun 13 12:34:03 PM PDT 24
Peak memory 233308 kb
Host smart-72930447-480f-4b6a-8fd0-f50b8d565fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563142880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3563142880
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.908437364
Short name T593
Test name
Test status
Simulation time 227257498 ps
CPU time 2.88 seconds
Started Jun 13 02:46:42 PM PDT 24
Finished Jun 13 02:46:54 PM PDT 24
Peak memory 233432 kb
Host smart-4009495c-5b97-4a6e-91ef-5d6f9025a3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908437364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.908437364
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1654464119
Short name T286
Test name
Test status
Simulation time 53351913137 ps
CPU time 104.32 seconds
Started Jun 13 02:21:25 PM PDT 24
Finished Jun 13 02:23:10 PM PDT 24
Peak memory 235092 kb
Host smart-733b9858-5d16-4533-90fb-b0aca5096249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654464119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1654464119
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1644247524
Short name T208
Test name
Test status
Simulation time 2500704075 ps
CPU time 5.71 seconds
Started Jun 13 01:11:52 PM PDT 24
Finished Jun 13 01:11:58 PM PDT 24
Peak memory 233472 kb
Host smart-deccb351-e42a-40a4-96df-dfc8e325eede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644247524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1644247524
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2110189795
Short name T684
Test name
Test status
Simulation time 329824414 ps
CPU time 2.93 seconds
Started Jun 13 12:57:48 PM PDT 24
Finished Jun 13 12:57:53 PM PDT 24
Peak memory 225216 kb
Host smart-21372d4b-4297-407a-94fb-15201d5ed526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110189795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2110189795
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2195799133
Short name T13
Test name
Test status
Simulation time 8289755407 ps
CPU time 14 seconds
Started Jun 13 01:57:54 PM PDT 24
Finished Jun 13 01:58:11 PM PDT 24
Peak memory 221264 kb
Host smart-6d595672-8df5-434a-af45-bcae8ab2eed9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2195799133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2195799133
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2405957993
Short name T359
Test name
Test status
Simulation time 110525792 ps
CPU time 1.04 seconds
Started Jun 13 01:08:09 PM PDT 24
Finished Jun 13 01:08:11 PM PDT 24
Peak memory 208276 kb
Host smart-487267cc-623e-4adb-aeb3-b2980842f8ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405957993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2405957993
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2274525688
Short name T58
Test name
Test status
Simulation time 1227541722 ps
CPU time 7.14 seconds
Started Jun 13 01:37:54 PM PDT 24
Finished Jun 13 01:38:02 PM PDT 24
Peak memory 219652 kb
Host smart-8bb5121b-0af7-4a91-afd7-00f39901febc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274525688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2274525688
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2035528068
Short name T667
Test name
Test status
Simulation time 1171940475 ps
CPU time 5.88 seconds
Started Jun 13 12:41:43 PM PDT 24
Finished Jun 13 12:41:50 PM PDT 24
Peak memory 216948 kb
Host smart-42d3fdd0-f480-43e3-bf88-4ebaf73922d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035528068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2035528068
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.77244159
Short name T28
Test name
Test status
Simulation time 30053451 ps
CPU time 0.78 seconds
Started Jun 13 01:18:23 PM PDT 24
Finished Jun 13 01:18:24 PM PDT 24
Peak memory 206568 kb
Host smart-8f401f76-b5f9-4095-bcdd-ea5c87b17789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77244159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.77244159
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3669458507
Short name T420
Test name
Test status
Simulation time 21313534 ps
CPU time 0.75 seconds
Started Jun 13 01:45:26 PM PDT 24
Finished Jun 13 01:45:28 PM PDT 24
Peak memory 206616 kb
Host smart-44d7b5bf-5caa-4675-8c8a-1560f24e88e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669458507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3669458507
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1007519653
Short name T37
Test name
Test status
Simulation time 1535597593 ps
CPU time 4.68 seconds
Started Jun 13 01:43:46 PM PDT 24
Finished Jun 13 01:43:52 PM PDT 24
Peak memory 225144 kb
Host smart-c482686d-ed40-4a08-83b4-675f57574cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007519653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1007519653
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2459000261
Short name T423
Test name
Test status
Simulation time 11798317 ps
CPU time 0.75 seconds
Started Jun 13 01:34:08 PM PDT 24
Finished Jun 13 01:34:10 PM PDT 24
Peak memory 206496 kb
Host smart-2ec11754-bd8b-40dc-8bf3-de028d2e38d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459000261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2459000261
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3974706753
Short name T248
Test name
Test status
Simulation time 1111546133 ps
CPU time 5.28 seconds
Started Jun 13 01:36:31 PM PDT 24
Finished Jun 13 01:36:37 PM PDT 24
Peak memory 233412 kb
Host smart-0a131e93-0e81-45f0-9c2e-e145e1130d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974706753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3974706753
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.862534626
Short name T349
Test name
Test status
Simulation time 27389764 ps
CPU time 0.79 seconds
Started Jun 13 02:05:08 PM PDT 24
Finished Jun 13 02:05:10 PM PDT 24
Peak memory 207304 kb
Host smart-83b2a407-e28c-4405-9b1d-1deca9b876a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862534626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.862534626
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2744251556
Short name T223
Test name
Test status
Simulation time 10584162762 ps
CPU time 62.2 seconds
Started Jun 13 02:14:48 PM PDT 24
Finished Jun 13 02:15:51 PM PDT 24
Peak memory 251268 kb
Host smart-7c1710ba-883d-4b42-8305-8575d1211b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744251556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2744251556
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1710096854
Short name T495
Test name
Test status
Simulation time 5457147510 ps
CPU time 11.87 seconds
Started Jun 13 01:26:09 PM PDT 24
Finished Jun 13 01:26:22 PM PDT 24
Peak memory 218632 kb
Host smart-3c06b2df-6040-4d1c-8038-c33f7ee79ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710096854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1710096854
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1411762791
Short name T298
Test name
Test status
Simulation time 1540280391 ps
CPU time 18.82 seconds
Started Jun 13 02:00:56 PM PDT 24
Finished Jun 13 02:01:16 PM PDT 24
Peak memory 225260 kb
Host smart-0e1dc2fb-8e5c-4cd8-a719-1a3c7d366243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411762791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1411762791
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3464418647
Short name T374
Test name
Test status
Simulation time 119767146 ps
CPU time 2.31 seconds
Started Jun 13 12:33:38 PM PDT 24
Finished Jun 13 12:33:41 PM PDT 24
Peak memory 233160 kb
Host smart-d9e76784-1c72-4365-8987-65f26a49cc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464418647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3464418647
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.700578276
Short name T260
Test name
Test status
Simulation time 3221425429 ps
CPU time 13.45 seconds
Started Jun 13 02:20:39 PM PDT 24
Finished Jun 13 02:20:58 PM PDT 24
Peak memory 233460 kb
Host smart-37946e1c-54e9-4502-b25c-3d3cf28a481a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700578276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.700578276
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1792505204
Short name T799
Test name
Test status
Simulation time 11195915610 ps
CPU time 8.66 seconds
Started Jun 13 02:18:56 PM PDT 24
Finished Jun 13 02:19:15 PM PDT 24
Peak memory 225312 kb
Host smart-246be778-c6bf-49f4-af84-b853df17c9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792505204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1792505204
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.277855058
Short name T887
Test name
Test status
Simulation time 2316053196 ps
CPU time 13.2 seconds
Started Jun 13 02:21:12 PM PDT 24
Finished Jun 13 02:21:26 PM PDT 24
Peak memory 233420 kb
Host smart-20dc2e65-eb68-4458-9225-d6335e858daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277855058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.277855058
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.679189665
Short name T330
Test name
Test status
Simulation time 3309685474 ps
CPU time 9.71 seconds
Started Jun 13 02:17:15 PM PDT 24
Finished Jun 13 02:17:30 PM PDT 24
Peak memory 223896 kb
Host smart-aec08857-8faf-4b44-b461-bfc06aebb4ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=679189665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.679189665
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2942240801
Short name T568
Test name
Test status
Simulation time 4713635428 ps
CPU time 46.48 seconds
Started Jun 13 01:29:10 PM PDT 24
Finished Jun 13 01:29:57 PM PDT 24
Peak memory 236224 kb
Host smart-beda19e8-e6f6-48f6-9fce-da0b4c6df6cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942240801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2942240801
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.271361195
Short name T709
Test name
Test status
Simulation time 6787488022 ps
CPU time 21.85 seconds
Started Jun 13 02:21:23 PM PDT 24
Finished Jun 13 02:21:45 PM PDT 24
Peak memory 217212 kb
Host smart-01a539d0-e5a5-490f-9274-a6b73c6aa9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271361195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.271361195
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3478406904
Short name T451
Test name
Test status
Simulation time 31422578179 ps
CPU time 23.1 seconds
Started Jun 13 01:30:06 PM PDT 24
Finished Jun 13 01:30:29 PM PDT 24
Peak memory 217168 kb
Host smart-2d8a6514-2ad4-4d54-8c85-14fa09fc5fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478406904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3478406904
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2840074331
Short name T325
Test name
Test status
Simulation time 91756967 ps
CPU time 2.4 seconds
Started Jun 13 01:24:33 PM PDT 24
Finished Jun 13 01:24:36 PM PDT 24
Peak memory 216980 kb
Host smart-520073fb-4ae2-442d-a5af-5f38ad05972d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840074331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2840074331
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1314738627
Short name T801
Test name
Test status
Simulation time 17940487 ps
CPU time 0.74 seconds
Started Jun 13 12:48:18 PM PDT 24
Finished Jun 13 12:48:19 PM PDT 24
Peak memory 206456 kb
Host smart-a4e36168-ba3f-4733-aa73-d3104291f5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314738627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1314738627
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3857422026
Short name T498
Test name
Test status
Simulation time 1108783308 ps
CPU time 10.4 seconds
Started Jun 13 12:46:21 PM PDT 24
Finished Jun 13 12:46:32 PM PDT 24
Peak memory 241516 kb
Host smart-41e80586-e227-43cc-b022-793d8e03ad8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857422026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3857422026
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1906598725
Short name T520
Test name
Test status
Simulation time 18839990 ps
CPU time 0.73 seconds
Started Jun 13 12:52:28 PM PDT 24
Finished Jun 13 12:52:29 PM PDT 24
Peak memory 206412 kb
Host smart-6a69e22e-cf4a-4eef-8336-51b5c9357452
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906598725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1906598725
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2429902096
Short name T700
Test name
Test status
Simulation time 269893563 ps
CPU time 4.97 seconds
Started Jun 13 02:00:06 PM PDT 24
Finished Jun 13 02:00:12 PM PDT 24
Peak memory 233412 kb
Host smart-8c4a2798-bf06-472c-a69a-859213bb2644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429902096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2429902096
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2218388669
Short name T659
Test name
Test status
Simulation time 12678919 ps
CPU time 0.74 seconds
Started Jun 13 02:02:27 PM PDT 24
Finished Jun 13 02:02:28 PM PDT 24
Peak memory 207224 kb
Host smart-5211fe86-f3a6-4590-8497-a28ee32c3404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218388669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2218388669
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.170890998
Short name T60
Test name
Test status
Simulation time 1375710781 ps
CPU time 18.34 seconds
Started Jun 13 12:52:54 PM PDT 24
Finished Jun 13 12:53:13 PM PDT 24
Peak memory 239592 kb
Host smart-26428d5d-8277-4eeb-b1c6-9fc41d441108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170890998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.170890998
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.499458992
Short name T135
Test name
Test status
Simulation time 8190312558 ps
CPU time 175.54 seconds
Started Jun 13 02:09:38 PM PDT 24
Finished Jun 13 02:12:34 PM PDT 24
Peak memory 255380 kb
Host smart-62b232d1-eea2-4a93-ab24-7d43a067798f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499458992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.499458992
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2726977011
Short name T270
Test name
Test status
Simulation time 63736142546 ps
CPU time 575.8 seconds
Started Jun 13 01:49:44 PM PDT 24
Finished Jun 13 01:59:21 PM PDT 24
Peak memory 266592 kb
Host smart-a83d2051-0f95-47f7-b88c-dedbdfc2510f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726977011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2726977011
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.992321439
Short name T313
Test name
Test status
Simulation time 6105505298 ps
CPU time 16.85 seconds
Started Jun 13 01:45:24 PM PDT 24
Finished Jun 13 01:45:41 PM PDT 24
Peak memory 233472 kb
Host smart-781eadbd-339a-4dd5-ac3e-5757d3cdca81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992321439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.992321439
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3044391979
Short name T620
Test name
Test status
Simulation time 583627420 ps
CPU time 3.64 seconds
Started Jun 13 12:51:25 PM PDT 24
Finished Jun 13 12:51:29 PM PDT 24
Peak memory 233400 kb
Host smart-6ced4a2d-b369-41c0-9188-21619642b126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044391979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3044391979
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1633919966
Short name T285
Test name
Test status
Simulation time 3580556509 ps
CPU time 27.12 seconds
Started Jun 13 02:08:25 PM PDT 24
Finished Jun 13 02:08:53 PM PDT 24
Peak memory 238568 kb
Host smart-9ead3da0-5b79-4261-8e50-84a06833e86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633919966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1633919966
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2703757566
Short name T293
Test name
Test status
Simulation time 6237377184 ps
CPU time 10.71 seconds
Started Jun 13 01:25:44 PM PDT 24
Finished Jun 13 01:25:56 PM PDT 24
Peak memory 233444 kb
Host smart-a9c29457-a92e-4f36-b3a3-42c43de34428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703757566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2703757566
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.173269753
Short name T487
Test name
Test status
Simulation time 2402197117 ps
CPU time 3.45 seconds
Started Jun 13 01:37:46 PM PDT 24
Finished Jun 13 01:37:50 PM PDT 24
Peak memory 225264 kb
Host smart-a432aa68-63ea-431e-977d-9bdf1a0d8435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173269753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.173269753
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3016780000
Short name T804
Test name
Test status
Simulation time 533826492 ps
CPU time 4.46 seconds
Started Jun 13 02:25:05 PM PDT 24
Finished Jun 13 02:25:10 PM PDT 24
Peak memory 223772 kb
Host smart-138a5bc3-49dc-4219-a0d8-ff87821a4088
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3016780000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3016780000
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.4157353226
Short name T687
Test name
Test status
Simulation time 5043290096 ps
CPU time 9.45 seconds
Started Jun 13 02:20:38 PM PDT 24
Finished Jun 13 02:20:53 PM PDT 24
Peak memory 217104 kb
Host smart-7aec02ce-cf01-4ccc-81b3-3ced113ca975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157353226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.4157353226
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1075857965
Short name T908
Test name
Test status
Simulation time 1233345717 ps
CPU time 3.05 seconds
Started Jun 13 01:42:35 PM PDT 24
Finished Jun 13 01:42:39 PM PDT 24
Peak memory 216972 kb
Host smart-bd1e6ad6-e9ec-4e80-b0fe-90a01d714c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075857965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1075857965
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2148751907
Short name T405
Test name
Test status
Simulation time 37644476 ps
CPU time 0.87 seconds
Started Jun 13 01:02:55 PM PDT 24
Finished Jun 13 01:02:57 PM PDT 24
Peak memory 207152 kb
Host smart-b82af47f-c186-40a7-b695-643afaad8ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148751907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2148751907
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.772305700
Short name T832
Test name
Test status
Simulation time 80884238 ps
CPU time 1.01 seconds
Started Jun 13 02:24:10 PM PDT 24
Finished Jun 13 02:24:11 PM PDT 24
Peak memory 206620 kb
Host smart-f20a5b27-0dae-450d-84bd-1c6750d7c182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772305700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.772305700
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2929721099
Short name T189
Test name
Test status
Simulation time 316316768 ps
CPU time 4.54 seconds
Started Jun 13 12:57:20 PM PDT 24
Finished Jun 13 12:57:25 PM PDT 24
Peak memory 225112 kb
Host smart-66120f6f-215e-4e29-8934-7c37cf378900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929721099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2929721099
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1840397098
Short name T737
Test name
Test status
Simulation time 48826067 ps
CPU time 0.75 seconds
Started Jun 13 02:11:17 PM PDT 24
Finished Jun 13 02:11:19 PM PDT 24
Peak memory 206128 kb
Host smart-5602a199-30bd-4612-8a7b-a9e33e230014
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840397098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1840397098
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3337583713
Short name T617
Test name
Test status
Simulation time 848576528 ps
CPU time 2.55 seconds
Started Jun 13 02:07:42 PM PDT 24
Finished Jun 13 02:07:46 PM PDT 24
Peak memory 225128 kb
Host smart-a5764223-a801-4c12-980c-bd466d63fea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337583713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3337583713
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.4248363209
Short name T533
Test name
Test status
Simulation time 41800825 ps
CPU time 0.77 seconds
Started Jun 13 02:24:10 PM PDT 24
Finished Jun 13 02:24:12 PM PDT 24
Peak memory 206628 kb
Host smart-78125ef3-1a5f-4fb1-91fc-73f99a9f2d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248363209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.4248363209
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1363278767
Short name T198
Test name
Test status
Simulation time 6852765284 ps
CPU time 80.66 seconds
Started Jun 13 01:27:51 PM PDT 24
Finished Jun 13 01:29:13 PM PDT 24
Peak memory 254776 kb
Host smart-bab7d5cf-0a5c-4e52-83c1-5d39c0c1525f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363278767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1363278767
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1299199431
Short name T756
Test name
Test status
Simulation time 14111515792 ps
CPU time 175.78 seconds
Started Jun 13 12:46:45 PM PDT 24
Finished Jun 13 12:49:42 PM PDT 24
Peak memory 255144 kb
Host smart-b412f4f3-f3e6-427c-ba30-c6ee48f0df21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299199431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1299199431
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.740098603
Short name T236
Test name
Test status
Simulation time 58416473848 ps
CPU time 123.33 seconds
Started Jun 13 02:51:34 PM PDT 24
Finished Jun 13 02:53:48 PM PDT 24
Peak memory 257196 kb
Host smart-a685598f-f4d9-4691-8ebd-b4e48940c3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740098603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.740098603
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.906643266
Short name T443
Test name
Test status
Simulation time 420938841 ps
CPU time 3.69 seconds
Started Jun 13 12:57:13 PM PDT 24
Finished Jun 13 12:57:17 PM PDT 24
Peak memory 233276 kb
Host smart-9f73ed90-ffc1-4f3b-be20-af4e1a095b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906643266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.906643266
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2875934468
Short name T785
Test name
Test status
Simulation time 524588219 ps
CPU time 4.9 seconds
Started Jun 13 01:32:57 PM PDT 24
Finished Jun 13 01:33:03 PM PDT 24
Peak memory 225136 kb
Host smart-0d251cd9-2a62-4229-af29-11034398f621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875934468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2875934468
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3791002143
Short name T615
Test name
Test status
Simulation time 20882004786 ps
CPU time 90.79 seconds
Started Jun 13 01:57:18 PM PDT 24
Finished Jun 13 01:58:52 PM PDT 24
Peak memory 249896 kb
Host smart-5bfe97ce-c04f-4343-8723-e3a67ec97a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791002143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3791002143
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.4118443892
Short name T634
Test name
Test status
Simulation time 148526248 ps
CPU time 2.99 seconds
Started Jun 13 12:33:43 PM PDT 24
Finished Jun 13 12:33:48 PM PDT 24
Peak memory 233256 kb
Host smart-a4036faf-f9d3-4763-8a12-9d50393ea016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118443892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.4118443892
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2963408333
Short name T352
Test name
Test status
Simulation time 725601087 ps
CPU time 4.45 seconds
Started Jun 13 01:17:25 PM PDT 24
Finished Jun 13 01:17:30 PM PDT 24
Peak memory 233436 kb
Host smart-ac165d5d-a8ac-497a-9aa8-e7ec42fd99a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963408333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2963408333
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2022808430
Short name T603
Test name
Test status
Simulation time 2680430369 ps
CPU time 10.18 seconds
Started Jun 13 01:55:43 PM PDT 24
Finished Jun 13 01:55:54 PM PDT 24
Peak memory 223848 kb
Host smart-52b228d3-5412-43b9-aaf5-ecf260568cce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2022808430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2022808430
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.634353862
Short name T220
Test name
Test status
Simulation time 57860423459 ps
CPU time 227.11 seconds
Started Jun 13 12:59:53 PM PDT 24
Finished Jun 13 01:03:41 PM PDT 24
Peak memory 258064 kb
Host smart-2d584776-34bd-469c-8bb5-a2548264daf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634353862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.634353862
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3884522248
Short name T647
Test name
Test status
Simulation time 21946909 ps
CPU time 0.74 seconds
Started Jun 13 01:49:24 PM PDT 24
Finished Jun 13 01:49:25 PM PDT 24
Peak memory 206420 kb
Host smart-cff31030-9e52-4371-a44f-6151d513ff92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884522248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3884522248
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.963830597
Short name T317
Test name
Test status
Simulation time 1800364510 ps
CPU time 2.98 seconds
Started Jun 13 12:37:43 PM PDT 24
Finished Jun 13 12:37:48 PM PDT 24
Peak memory 216696 kb
Host smart-5bc57841-b648-4631-a802-94280f7bc8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963830597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.963830597
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2195440656
Short name T574
Test name
Test status
Simulation time 188397883 ps
CPU time 1.7 seconds
Started Jun 13 12:46:37 PM PDT 24
Finished Jun 13 12:46:39 PM PDT 24
Peak memory 216952 kb
Host smart-827264b1-fb8e-41fa-9631-9b611407e76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195440656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2195440656
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3162889557
Short name T683
Test name
Test status
Simulation time 66072508 ps
CPU time 0.8 seconds
Started Jun 13 12:44:38 PM PDT 24
Finished Jun 13 12:44:39 PM PDT 24
Peak memory 206512 kb
Host smart-53abd215-17ca-4478-a54a-7c32c2a53ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162889557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3162889557
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1675170881
Short name T918
Test name
Test status
Simulation time 17181210257 ps
CPU time 7.2 seconds
Started Jun 13 02:06:46 PM PDT 24
Finished Jun 13 02:06:54 PM PDT 24
Peak memory 225320 kb
Host smart-91fff19d-3a56-496e-baf5-295238f60dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675170881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1675170881
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3686938596
Short name T62
Test name
Test status
Simulation time 11328013 ps
CPU time 0.73 seconds
Started Jun 13 12:32:25 PM PDT 24
Finished Jun 13 12:32:28 PM PDT 24
Peak memory 205404 kb
Host smart-4c93312c-f460-4fb7-9905-7ffff0f0b8c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686938596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
686938596
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.568061431
Short name T412
Test name
Test status
Simulation time 4640952757 ps
CPU time 5.02 seconds
Started Jun 13 12:32:45 PM PDT 24
Finished Jun 13 12:32:52 PM PDT 24
Peak memory 233300 kb
Host smart-adcc18fe-0c82-4b73-ae9e-53b7343ed1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568061431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.568061431
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.146917851
Short name T490
Test name
Test status
Simulation time 77481349 ps
CPU time 0.83 seconds
Started Jun 13 12:32:28 PM PDT 24
Finished Jun 13 12:32:30 PM PDT 24
Peak memory 207132 kb
Host smart-ccd43475-9c34-4d60-9f4d-79c7cff90be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146917851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.146917851
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2756138818
Short name T505
Test name
Test status
Simulation time 47757167068 ps
CPU time 86.27 seconds
Started Jun 13 12:32:21 PM PDT 24
Finished Jun 13 12:33:50 PM PDT 24
Peak memory 240336 kb
Host smart-a3607b35-c8cb-4b18-9852-de887eac31b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756138818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2756138818
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1148822980
Short name T164
Test name
Test status
Simulation time 17298852825 ps
CPU time 153.14 seconds
Started Jun 13 12:32:27 PM PDT 24
Finished Jun 13 12:35:02 PM PDT 24
Peak memory 252436 kb
Host smart-2380df31-38ee-4783-ac72-d93c49a7b2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148822980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1148822980
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2400000451
Short name T528
Test name
Test status
Simulation time 269583271 ps
CPU time 6.09 seconds
Started Jun 13 12:32:21 PM PDT 24
Finished Jun 13 12:32:29 PM PDT 24
Peak memory 233256 kb
Host smart-328069bc-21fe-4627-af27-d73a175192b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400000451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2400000451
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3200906825
Short name T925
Test name
Test status
Simulation time 9247862412 ps
CPU time 23.86 seconds
Started Jun 13 12:32:50 PM PDT 24
Finished Jun 13 12:33:15 PM PDT 24
Peak memory 225084 kb
Host smart-a8719be3-f02a-4675-b1fd-df804273d995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200906825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3200906825
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2103836802
Short name T398
Test name
Test status
Simulation time 7808036731 ps
CPU time 22.62 seconds
Started Jun 13 12:32:19 PM PDT 24
Finished Jun 13 12:32:44 PM PDT 24
Peak memory 239076 kb
Host smart-45bd1cf6-67d4-4a02-b969-dea4a80c9305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103836802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2103836802
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3256600281
Short name T183
Test name
Test status
Simulation time 4244847879 ps
CPU time 13.15 seconds
Started Jun 13 12:32:21 PM PDT 24
Finished Jun 13 12:32:37 PM PDT 24
Peak memory 225056 kb
Host smart-9eb16d79-751a-4098-b9cb-373ea749d4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256600281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3256600281
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.795994264
Short name T888
Test name
Test status
Simulation time 8411857830 ps
CPU time 11.5 seconds
Started Jun 13 12:32:33 PM PDT 24
Finished Jun 13 12:32:47 PM PDT 24
Peak memory 233348 kb
Host smart-cef7f975-76e3-4b99-8d42-7d80dcdd3460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795994264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.795994264
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2285804305
Short name T344
Test name
Test status
Simulation time 329797858 ps
CPU time 3.94 seconds
Started Jun 13 12:32:21 PM PDT 24
Finished Jun 13 12:32:27 PM PDT 24
Peak memory 223588 kb
Host smart-27a43230-d1eb-49a3-aa41-bcb57471766f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2285804305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2285804305
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.794739702
Short name T415
Test name
Test status
Simulation time 34775469 ps
CPU time 0.88 seconds
Started Jun 13 12:32:38 PM PDT 24
Finished Jun 13 12:32:41 PM PDT 24
Peak memory 207476 kb
Host smart-40eda995-9d23-43d3-a76c-30bcb085405d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794739702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.794739702
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1587357081
Short name T486
Test name
Test status
Simulation time 14256345172 ps
CPU time 29.3 seconds
Started Jun 13 12:32:22 PM PDT 24
Finished Jun 13 12:32:54 PM PDT 24
Peak memory 216912 kb
Host smart-d99f9936-23e9-4bd1-a17d-6b720ff2218a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587357081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1587357081
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2598529432
Short name T499
Test name
Test status
Simulation time 23317966522 ps
CPU time 19.85 seconds
Started Jun 13 12:32:43 PM PDT 24
Finished Jun 13 12:33:04 PM PDT 24
Peak memory 216868 kb
Host smart-4240e610-c6a0-4226-90e1-e7a815983e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598529432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2598529432
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2715836045
Short name T399
Test name
Test status
Simulation time 81789105 ps
CPU time 1.06 seconds
Started Jun 13 12:32:17 PM PDT 24
Finished Jun 13 12:32:20 PM PDT 24
Peak memory 208420 kb
Host smart-ee89fd08-3613-4e1d-acd9-543c5f5d14eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715836045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2715836045
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3124523944
Short name T436
Test name
Test status
Simulation time 49008890 ps
CPU time 0.76 seconds
Started Jun 13 12:32:22 PM PDT 24
Finished Jun 13 12:32:26 PM PDT 24
Peak memory 206456 kb
Host smart-0015efc5-574b-4b9a-abb4-184e6520ed9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124523944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3124523944
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2895301837
Short name T919
Test name
Test status
Simulation time 212740817 ps
CPU time 2.94 seconds
Started Jun 13 12:32:38 PM PDT 24
Finished Jun 13 12:32:43 PM PDT 24
Peak memory 225024 kb
Host smart-b29b2b5b-8cf6-4576-9517-ce02af75caa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895301837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2895301837
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2180377165
Short name T945
Test name
Test status
Simulation time 16797163 ps
CPU time 0.71 seconds
Started Jun 13 12:32:29 PM PDT 24
Finished Jun 13 12:32:31 PM PDT 24
Peak memory 205972 kb
Host smart-6763757c-c632-422c-acad-7fc301fed5cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180377165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
180377165
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.511895613
Short name T940
Test name
Test status
Simulation time 205095095 ps
CPU time 2.38 seconds
Started Jun 13 12:32:31 PM PDT 24
Finished Jun 13 12:32:36 PM PDT 24
Peak memory 225088 kb
Host smart-e53dd28e-f403-4a96-9871-bfe305a0fe7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511895613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.511895613
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3098876148
Short name T809
Test name
Test status
Simulation time 15945327 ps
CPU time 0.78 seconds
Started Jun 13 12:32:31 PM PDT 24
Finished Jun 13 12:32:34 PM PDT 24
Peak memory 206132 kb
Host smart-1700af97-2f0f-4698-9e6e-4bc5228c92e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098876148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3098876148
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.4166282495
Short name T50
Test name
Test status
Simulation time 27061788713 ps
CPU time 125.9 seconds
Started Jun 13 12:32:21 PM PDT 24
Finished Jun 13 12:34:30 PM PDT 24
Peak memory 249776 kb
Host smart-85638850-f1c0-4d8b-b0ee-c1c6a2c3a817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166282495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.4166282495
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.4087306002
Short name T426
Test name
Test status
Simulation time 4302078485 ps
CPU time 6.5 seconds
Started Jun 13 12:32:40 PM PDT 24
Finished Jun 13 12:32:49 PM PDT 24
Peak memory 225112 kb
Host smart-759355bd-1cac-489f-b654-b4c0e35f40bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087306002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.4087306002
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.690604874
Short name T95
Test name
Test status
Simulation time 327202207 ps
CPU time 4.33 seconds
Started Jun 13 12:32:36 PM PDT 24
Finished Jun 13 12:32:46 PM PDT 24
Peak memory 225080 kb
Host smart-ceb338b7-565a-491e-89cd-3396afde517e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690604874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.690604874
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1324059894
Short name T79
Test name
Test status
Simulation time 238722248 ps
CPU time 4.07 seconds
Started Jun 13 12:32:54 PM PDT 24
Finished Jun 13 12:32:59 PM PDT 24
Peak memory 225016 kb
Host smart-1c7ace64-7e5b-405b-aad5-f0e3d2fa8ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324059894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1324059894
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1046501171
Short name T744
Test name
Test status
Simulation time 13074375993 ps
CPU time 9.84 seconds
Started Jun 13 12:32:26 PM PDT 24
Finished Jun 13 12:32:39 PM PDT 24
Peak memory 225084 kb
Host smart-0de32a70-d00f-4b0b-aaba-a72db3fc630a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046501171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1046501171
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2065753387
Short name T752
Test name
Test status
Simulation time 6149196357 ps
CPU time 12.11 seconds
Started Jun 13 12:32:49 PM PDT 24
Finished Jun 13 12:33:03 PM PDT 24
Peak memory 233396 kb
Host smart-f9d65056-83ce-4824-88cc-2371b0830b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065753387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2065753387
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1754549216
Short name T93
Test name
Test status
Simulation time 9054144162 ps
CPU time 9.92 seconds
Started Jun 13 12:32:23 PM PDT 24
Finished Jun 13 12:32:36 PM PDT 24
Peak memory 223696 kb
Host smart-5e060da2-b049-49f9-b1f0-b8e6c72f2d59
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1754549216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1754549216
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3899952092
Short name T521
Test name
Test status
Simulation time 41279240 ps
CPU time 1.04 seconds
Started Jun 13 12:32:33 PM PDT 24
Finished Jun 13 12:32:36 PM PDT 24
Peak memory 207588 kb
Host smart-2617724c-59c8-493e-a1f0-37f306921fd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899952092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3899952092
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3498059518
Short name T807
Test name
Test status
Simulation time 808219811 ps
CPU time 2.78 seconds
Started Jun 13 12:32:49 PM PDT 24
Finished Jun 13 12:32:53 PM PDT 24
Peak memory 216804 kb
Host smart-cef16b75-af2a-4070-9d16-f06c55834ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498059518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3498059518
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.198041771
Short name T821
Test name
Test status
Simulation time 2563591539 ps
CPU time 4.74 seconds
Started Jun 13 12:32:29 PM PDT 24
Finished Jun 13 12:32:35 PM PDT 24
Peak memory 216880 kb
Host smart-06f835a1-9e0c-4681-8844-1801391dded1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198041771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.198041771
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.900427005
Short name T696
Test name
Test status
Simulation time 47005977 ps
CPU time 0.86 seconds
Started Jun 13 12:32:22 PM PDT 24
Finished Jun 13 12:32:26 PM PDT 24
Peak memory 207136 kb
Host smart-cb292aff-5f2b-4d14-9c97-d01757a47f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900427005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.900427005
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.4105930751
Short name T797
Test name
Test status
Simulation time 48941824 ps
CPU time 0.87 seconds
Started Jun 13 12:32:17 PM PDT 24
Finished Jun 13 12:32:20 PM PDT 24
Peak memory 206444 kb
Host smart-eecad717-5acb-424e-91a3-1430f6fc59d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105930751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.4105930751
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2732208430
Short name T517
Test name
Test status
Simulation time 220528006 ps
CPU time 3.76 seconds
Started Jun 13 12:32:19 PM PDT 24
Finished Jun 13 12:32:26 PM PDT 24
Peak memory 233200 kb
Host smart-c99184bb-ce59-49de-a6ed-bc317a096e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732208430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2732208430
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.697428967
Short name T428
Test name
Test status
Simulation time 52862384 ps
CPU time 0.7 seconds
Started Jun 13 12:32:28 PM PDT 24
Finished Jun 13 12:32:30 PM PDT 24
Peak memory 206304 kb
Host smart-2cb5dbbf-ae38-493e-b3fc-7edec82a2d9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697428967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.697428967
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1298026062
Short name T704
Test name
Test status
Simulation time 32693057 ps
CPU time 2.48 seconds
Started Jun 13 12:32:36 PM PDT 24
Finished Jun 13 12:32:40 PM PDT 24
Peak memory 233032 kb
Host smart-1249af6d-f99f-4356-9658-9dbb89b98e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298026062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1298026062
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2085158384
Short name T55
Test name
Test status
Simulation time 11850732 ps
CPU time 0.76 seconds
Started Jun 13 12:32:27 PM PDT 24
Finished Jun 13 12:32:30 PM PDT 24
Peak memory 206096 kb
Host smart-58aa1aa3-f36a-46cd-8c40-4ef6c8c455a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085158384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2085158384
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.238333628
Short name T787
Test name
Test status
Simulation time 17995989843 ps
CPU time 55.99 seconds
Started Jun 13 12:32:27 PM PDT 24
Finished Jun 13 12:33:25 PM PDT 24
Peak memory 249740 kb
Host smart-c2d48185-5ed0-4245-be9f-d1f5487c163c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238333628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.238333628
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2302965808
Short name T844
Test name
Test status
Simulation time 8582994713 ps
CPU time 70.9 seconds
Started Jun 13 12:32:23 PM PDT 24
Finished Jun 13 12:33:36 PM PDT 24
Peak memory 256596 kb
Host smart-d7b77cf5-91db-43ea-a01c-71d1450a00fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302965808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2302965808
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.237653662
Short name T266
Test name
Test status
Simulation time 1735933588 ps
CPU time 9.39 seconds
Started Jun 13 12:32:23 PM PDT 24
Finished Jun 13 12:32:35 PM PDT 24
Peak memory 233288 kb
Host smart-504be9e5-cdd5-4985-a4e9-c612c5988b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237653662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.237653662
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1711076687
Short name T530
Test name
Test status
Simulation time 5047415509 ps
CPU time 9.79 seconds
Started Jun 13 12:32:24 PM PDT 24
Finished Jun 13 12:32:36 PM PDT 24
Peak memory 225140 kb
Host smart-b7ec21fd-5401-4291-b819-c4d7b55c5e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711076687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1711076687
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3401292453
Short name T319
Test name
Test status
Simulation time 8681515021 ps
CPU time 79.35 seconds
Started Jun 13 12:32:28 PM PDT 24
Finished Jun 13 12:33:49 PM PDT 24
Peak memory 233252 kb
Host smart-84b27754-83fb-4419-a8eb-9be9ddeb4eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401292453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3401292453
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.4178620644
Short name T256
Test name
Test status
Simulation time 7179910407 ps
CPU time 9.74 seconds
Started Jun 13 12:32:51 PM PDT 24
Finished Jun 13 12:33:07 PM PDT 24
Peak memory 233352 kb
Host smart-81762ee9-fbda-4b38-a819-1d44dbde0a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178620644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.4178620644
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3756648558
Short name T577
Test name
Test status
Simulation time 189770117 ps
CPU time 3.42 seconds
Started Jun 13 12:32:39 PM PDT 24
Finished Jun 13 12:32:45 PM PDT 24
Peak memory 233260 kb
Host smart-53b89292-1a0f-4d97-b787-5ed22542f0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756648558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3756648558
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3726853227
Short name T903
Test name
Test status
Simulation time 353386626 ps
CPU time 4.09 seconds
Started Jun 13 12:32:22 PM PDT 24
Finished Jun 13 12:32:29 PM PDT 24
Peak memory 223556 kb
Host smart-417bfa6e-9c54-4c46-a482-e1897e344fac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3726853227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3726853227
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3988585647
Short name T80
Test name
Test status
Simulation time 9787271687 ps
CPU time 15.89 seconds
Started Jun 13 12:32:32 PM PDT 24
Finished Jun 13 12:32:50 PM PDT 24
Peak memory 223904 kb
Host smart-57144d8d-8e41-45e6-bdab-379ff1100497
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988585647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3988585647
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1784392480
Short name T303
Test name
Test status
Simulation time 5573785304 ps
CPU time 15.98 seconds
Started Jun 13 12:32:31 PM PDT 24
Finished Jun 13 12:32:49 PM PDT 24
Peak memory 220556 kb
Host smart-56c597fb-a9e3-4a26-bd83-49e0a2a6f5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784392480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1784392480
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2954808920
Short name T421
Test name
Test status
Simulation time 5789284371 ps
CPU time 16.87 seconds
Started Jun 13 12:32:41 PM PDT 24
Finished Jun 13 12:33:01 PM PDT 24
Peak memory 216924 kb
Host smart-fa14c917-92e2-41ac-9642-ca5fa17d444b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954808920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2954808920
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.840543547
Short name T514
Test name
Test status
Simulation time 13769590 ps
CPU time 0.74 seconds
Started Jun 13 12:32:33 PM PDT 24
Finished Jun 13 12:32:36 PM PDT 24
Peak memory 206440 kb
Host smart-872787e4-0da7-4afe-808e-2915014b4631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840543547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.840543547
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.4153209163
Short name T444
Test name
Test status
Simulation time 62049316 ps
CPU time 0.82 seconds
Started Jun 13 12:32:23 PM PDT 24
Finished Jun 13 12:32:26 PM PDT 24
Peak memory 206496 kb
Host smart-07daae53-aa69-4a49-bdab-f97b12f1a954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153209163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.4153209163
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3364109424
Short name T491
Test name
Test status
Simulation time 77545072 ps
CPU time 2.73 seconds
Started Jun 13 12:32:21 PM PDT 24
Finished Jun 13 12:32:26 PM PDT 24
Peak memory 241412 kb
Host smart-33da0272-aead-4003-9ef9-6c1f27cddc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364109424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3364109424
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.646634401
Short name T734
Test name
Test status
Simulation time 23268319 ps
CPU time 0.76 seconds
Started Jun 13 12:32:35 PM PDT 24
Finished Jun 13 12:32:37 PM PDT 24
Peak memory 205984 kb
Host smart-dc69e682-f712-47c8-a3e2-e6dbb7c59f34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646634401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.646634401
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2606655019
Short name T33
Test name
Test status
Simulation time 890304691 ps
CPU time 4.98 seconds
Started Jun 13 12:32:38 PM PDT 24
Finished Jun 13 12:32:45 PM PDT 24
Peak memory 233232 kb
Host smart-bcae4254-cfdc-40eb-a89d-b02a2a2cc6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606655019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2606655019
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.427710718
Short name T511
Test name
Test status
Simulation time 47610099 ps
CPU time 0.76 seconds
Started Jun 13 12:32:40 PM PDT 24
Finished Jun 13 12:32:43 PM PDT 24
Peak memory 206404 kb
Host smart-34314d18-e87b-4095-b3f2-fcdd3fb45677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427710718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.427710718
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1254080304
Short name T466
Test name
Test status
Simulation time 14305402 ps
CPU time 0.78 seconds
Started Jun 13 12:32:37 PM PDT 24
Finished Jun 13 12:32:39 PM PDT 24
Peak memory 216388 kb
Host smart-b8cf9bfc-30f0-4b82-a474-e48b49d0b122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254080304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1254080304
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3062707102
Short name T234
Test name
Test status
Simulation time 9120281624 ps
CPU time 94.05 seconds
Started Jun 13 12:32:54 PM PDT 24
Finished Jun 13 12:34:28 PM PDT 24
Peak memory 251052 kb
Host smart-6b2c62e6-1a8a-4dc7-8477-bbf22e07775e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062707102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3062707102
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2277248921
Short name T277
Test name
Test status
Simulation time 19687850966 ps
CPU time 194.75 seconds
Started Jun 13 12:32:31 PM PDT 24
Finished Jun 13 12:35:48 PM PDT 24
Peak memory 249840 kb
Host smart-fcfd57c1-46a2-4d37-82d3-f437225b6c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277248921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2277248921
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2657147430
Short name T745
Test name
Test status
Simulation time 1535046773 ps
CPU time 14.04 seconds
Started Jun 13 12:32:26 PM PDT 24
Finished Jun 13 12:32:43 PM PDT 24
Peak memory 225076 kb
Host smart-a1e5a63a-419d-462c-acb2-390ab8158873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657147430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2657147430
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1013022695
Short name T673
Test name
Test status
Simulation time 3676888127 ps
CPU time 7.95 seconds
Started Jun 13 12:32:23 PM PDT 24
Finished Jun 13 12:32:34 PM PDT 24
Peak memory 233384 kb
Host smart-605dd31f-cbd9-45d4-ac90-94833d2bbe7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013022695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1013022695
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.171211981
Short name T397
Test name
Test status
Simulation time 8360184825 ps
CPU time 55.48 seconds
Started Jun 13 12:32:40 PM PDT 24
Finished Jun 13 12:33:38 PM PDT 24
Peak memory 219328 kb
Host smart-a5247c71-102b-43fd-a1a4-c82cd97a8a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171211981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.171211981
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.316813734
Short name T288
Test name
Test status
Simulation time 1064901240 ps
CPU time 3.87 seconds
Started Jun 13 12:32:29 PM PDT 24
Finished Jun 13 12:32:34 PM PDT 24
Peak memory 233264 kb
Host smart-568004b0-65d9-4f8a-9376-7af86dcd66dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316813734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
316813734
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.189863905
Short name T899
Test name
Test status
Simulation time 2235060979 ps
CPU time 9.83 seconds
Started Jun 13 12:32:38 PM PDT 24
Finished Jun 13 12:32:50 PM PDT 24
Peak memory 241616 kb
Host smart-8e6eeb06-40c6-4900-820b-46174c6ae922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189863905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.189863905
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2341056406
Short name T569
Test name
Test status
Simulation time 632573355 ps
CPU time 3.95 seconds
Started Jun 13 12:32:40 PM PDT 24
Finished Jun 13 12:32:46 PM PDT 24
Peak memory 220896 kb
Host smart-56da5988-b5d1-49d0-bf0b-9fbe7c23db21
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2341056406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2341056406
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.4099934594
Short name T408
Test name
Test status
Simulation time 163619990 ps
CPU time 0.99 seconds
Started Jun 13 12:32:38 PM PDT 24
Finished Jun 13 12:32:42 PM PDT 24
Peak memory 207636 kb
Host smart-89254b74-412c-469c-a2fe-7fa635b83e73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099934594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.4099934594
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3025196153
Short name T738
Test name
Test status
Simulation time 2570049748 ps
CPU time 20.49 seconds
Started Jun 13 12:32:55 PM PDT 24
Finished Jun 13 12:33:17 PM PDT 24
Peak memory 216972 kb
Host smart-1780f7bd-13b9-4f36-9910-adf951d0e145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025196153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3025196153
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.624579589
Short name T458
Test name
Test status
Simulation time 2723162776 ps
CPU time 3.66 seconds
Started Jun 13 12:32:25 PM PDT 24
Finished Jun 13 12:32:31 PM PDT 24
Peak memory 216868 kb
Host smart-af193ec2-4a07-48d7-83a1-05facb96fdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624579589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.624579589
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3347454763
Short name T429
Test name
Test status
Simulation time 373119496 ps
CPU time 3.38 seconds
Started Jun 13 12:32:23 PM PDT 24
Finished Jun 13 12:32:29 PM PDT 24
Peak memory 216824 kb
Host smart-26fe5df2-09e3-4f70-a756-b134127d9e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347454763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3347454763
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3586381783
Short name T672
Test name
Test status
Simulation time 14179690 ps
CPU time 0.71 seconds
Started Jun 13 12:32:38 PM PDT 24
Finished Jun 13 12:32:40 PM PDT 24
Peak memory 206416 kb
Host smart-32290ebe-0e19-4089-903c-a58ee70d52bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586381783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3586381783
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.323947586
Short name T642
Test name
Test status
Simulation time 14304455202 ps
CPU time 11.13 seconds
Started Jun 13 12:32:19 PM PDT 24
Finished Jun 13 12:32:32 PM PDT 24
Peak memory 243904 kb
Host smart-c529b9f1-0b59-4b25-8986-59dd2b4d1880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323947586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.323947586
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.301458377
Short name T395
Test name
Test status
Simulation time 14293958 ps
CPU time 0.72 seconds
Started Jun 13 12:32:26 PM PDT 24
Finished Jun 13 12:32:29 PM PDT 24
Peak memory 205408 kb
Host smart-e7a29014-ebbe-4450-ad60-b5fe2959d1e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301458377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.301458377
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1370409343
Short name T57
Test name
Test status
Simulation time 178369582 ps
CPU time 2.77 seconds
Started Jun 13 12:32:28 PM PDT 24
Finished Jun 13 12:32:33 PM PDT 24
Peak memory 233224 kb
Host smart-8c689ebf-85cd-4312-ab7f-4757830902a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370409343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1370409343
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2167882354
Short name T336
Test name
Test status
Simulation time 142587498 ps
CPU time 0.74 seconds
Started Jun 13 12:32:40 PM PDT 24
Finished Jun 13 12:32:43 PM PDT 24
Peak memory 206096 kb
Host smart-7ffdbee4-2d5f-4438-af94-7b2e8476008f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167882354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2167882354
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.263984829
Short name T231
Test name
Test status
Simulation time 53769258179 ps
CPU time 190.12 seconds
Started Jun 13 12:32:44 PM PDT 24
Finished Jun 13 12:35:56 PM PDT 24
Peak memory 253696 kb
Host smart-9904a22f-820d-4b2f-8729-9e13b5bd07f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263984829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.263984829
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2188055934
Short name T239
Test name
Test status
Simulation time 25163246780 ps
CPU time 104.85 seconds
Started Jun 13 12:32:55 PM PDT 24
Finished Jun 13 12:34:41 PM PDT 24
Peak memory 253900 kb
Host smart-5cbb48a5-dcda-46ab-9c05-16835f217546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188055934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2188055934
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.260224413
Short name T721
Test name
Test status
Simulation time 10151545508 ps
CPU time 109.29 seconds
Started Jun 13 12:32:31 PM PDT 24
Finished Jun 13 12:34:22 PM PDT 24
Peak memory 249784 kb
Host smart-92b18b5a-0269-4884-8061-de819552ee41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260224413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
260224413
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.236505547
Short name T467
Test name
Test status
Simulation time 167307718 ps
CPU time 3.78 seconds
Started Jun 13 12:32:26 PM PDT 24
Finished Jun 13 12:32:32 PM PDT 24
Peak memory 225032 kb
Host smart-1f1e2e8b-04ad-4fcd-bbd3-e5bffd7384fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236505547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.236505547
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.574912599
Short name T402
Test name
Test status
Simulation time 231697892 ps
CPU time 3.82 seconds
Started Jun 13 12:32:56 PM PDT 24
Finished Jun 13 12:33:01 PM PDT 24
Peak memory 225040 kb
Host smart-b2107fcb-304f-4ea2-8c85-9b813b5c5284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574912599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.574912599
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2545526386
Short name T463
Test name
Test status
Simulation time 210681286 ps
CPU time 3.77 seconds
Started Jun 13 12:32:24 PM PDT 24
Finished Jun 13 12:32:31 PM PDT 24
Peak memory 224992 kb
Host smart-fa4385fe-bf81-45cb-ae50-fe38dd0d8f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545526386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2545526386
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3217824704
Short name T584
Test name
Test status
Simulation time 961322750 ps
CPU time 6.88 seconds
Started Jun 13 12:32:24 PM PDT 24
Finished Jun 13 12:32:34 PM PDT 24
Peak memory 233180 kb
Host smart-04eb7661-a6b1-4107-9937-021b8bad091a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217824704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3217824704
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.609255881
Short name T739
Test name
Test status
Simulation time 277003557 ps
CPU time 3.96 seconds
Started Jun 13 12:32:34 PM PDT 24
Finished Jun 13 12:32:39 PM PDT 24
Peak memory 224992 kb
Host smart-18a60cc1-c90d-455a-8423-4b63cea6e8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609255881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.609255881
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.708047339
Short name T901
Test name
Test status
Simulation time 1192261818 ps
CPU time 13.62 seconds
Started Jun 13 12:32:39 PM PDT 24
Finished Jun 13 12:32:55 PM PDT 24
Peak memory 223716 kb
Host smart-d709d504-d544-4f76-a7b6-98cc0818fbf1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=708047339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.708047339
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2470728647
Short name T822
Test name
Test status
Simulation time 4530925726 ps
CPU time 14.38 seconds
Started Jun 13 12:32:39 PM PDT 24
Finished Jun 13 12:32:56 PM PDT 24
Peak memory 241552 kb
Host smart-f9e959d6-c002-4315-99b8-5473ed2adff0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470728647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2470728647
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1639733522
Short name T894
Test name
Test status
Simulation time 3390935702 ps
CPU time 7.89 seconds
Started Jun 13 12:32:35 PM PDT 24
Finished Jun 13 12:32:44 PM PDT 24
Peak memory 216876 kb
Host smart-82f971ec-e25d-4d41-940d-29274949f463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639733522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1639733522
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.266315785
Short name T725
Test name
Test status
Simulation time 99010100225 ps
CPU time 19.03 seconds
Started Jun 13 12:32:37 PM PDT 24
Finished Jun 13 12:32:57 PM PDT 24
Peak memory 218528 kb
Host smart-53119c7a-8b6f-400d-9a36-97d6c782e51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266315785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.266315785
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2626796931
Short name T638
Test name
Test status
Simulation time 216520479 ps
CPU time 2.37 seconds
Started Jun 13 12:32:24 PM PDT 24
Finished Jun 13 12:32:29 PM PDT 24
Peak memory 216936 kb
Host smart-380a333f-8148-40c0-96d5-35e5bbc21337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626796931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2626796931
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1738618196
Short name T711
Test name
Test status
Simulation time 678981577 ps
CPU time 0.87 seconds
Started Jun 13 12:32:51 PM PDT 24
Finished Jun 13 12:32:53 PM PDT 24
Peak memory 206452 kb
Host smart-70c8e5d9-0df0-4a11-b4e9-bba3d8ec5914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738618196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1738618196
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3452796832
Short name T132
Test name
Test status
Simulation time 347215803 ps
CPU time 2.57 seconds
Started Jun 13 12:32:51 PM PDT 24
Finished Jun 13 12:32:55 PM PDT 24
Peak memory 225092 kb
Host smart-0ebc237a-d1fd-4a51-b897-5a1cb6db5057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452796832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3452796832
Directory /workspace/9.spi_device_upload/latest
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