Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3260881	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3708765

1

T1

2

T2

14049

T3

1011

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3942591	1			T1	3		T2	21241		T3	237
values[0x0]	1513157	1			T2	7198		T3	450		T4	235
values[0x1]	1513898	1			T2	7033		T3	451		T4	163

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2316020	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4653626

1

T1

2

T2

20811

T3

1037

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26496	1			T2	140		T5	1		T11	14
valid_sources[0x01]	27195	1			T2	132		T5	1		T11	12
valid_sources[0x02]	32202	1			T2	166		T11	11		T13	148
valid_sources[0x03]	25653	1			T2	150		T5	11		T11	17
valid_sources[0x04]	25506	1			T2	123		T5	10		T11	28
valid_sources[0x05]	24807	1			T2	157		T5	14		T11	10
valid_sources[0x06]	25541	1			T2	147		T5	10		T11	9
valid_sources[0x07]	28032	1			T2	140		T5	5		T11	12
valid_sources[0x08]	25704	1			T2	130		T5	2		T11	11
valid_sources[0x09]	29258	1			T2	110		T5	9		T11	16
valid_sources[0x0a]	27832	1			T2	98		T5	2		T11	8
valid_sources[0x0b]	25546	1			T2	177		T5	2		T11	17
valid_sources[0x0c]	26151	1			T2	154		T4	399		T5	4
valid_sources[0x0d]	31411	1			T2	184		T5	14		T11	13
valid_sources[0x0e]	26978	1			T2	102		T5	7		T11	8
valid_sources[0x0f]	26163	1			T2	162		T5	5		T11	21
valid_sources[0x10]	29038	1			T2	125		T5	10		T11	12
valid_sources[0x11]	27016	1			T2	171		T5	4		T11	14
valid_sources[0x12]	27254	1			T2	182		T5	14		T11	8
valid_sources[0x13]	26450	1			T2	157		T5	4		T11	14
valid_sources[0x14]	25086	1			T2	157		T5	18		T11	11
valid_sources[0x15]	26008	1			T2	139		T5	2		T11	12
valid_sources[0x16]	25356	1			T2	136		T5	4		T11	21
valid_sources[0x17]	28759	1			T2	174		T5	4		T11	13
valid_sources[0x18]	25638	1			T2	156		T11	15		T13	161
valid_sources[0x19]	25255	1			T2	184		T5	22		T11	9
valid_sources[0x1a]	28373	1			T2	146		T5	10		T10	2
valid_sources[0x1b]	24701	1			T2	141		T5	11		T11	11
valid_sources[0x1c]	27790	1			T2	176		T11	9		T13	142
valid_sources[0x1d]	26744	1			T2	116		T5	17		T11	11
valid_sources[0x1e]	28072	1			T2	151		T5	5		T11	7
valid_sources[0x1f]	25110	1			T2	146		T5	3		T11	18
valid_sources[0x20]	27122	1			T2	127		T5	8		T11	5
valid_sources[0x21]	28808	1			T2	120		T5	1		T11	14
valid_sources[0x22]	26808	1			T2	162		T5	10		T11	6
valid_sources[0x23]	26862	1			T2	128		T5	6		T11	12
valid_sources[0x24]	31386	1			T2	136		T11	10		T13	171
valid_sources[0x25]	30747	1			T2	150		T5	2		T11	10
valid_sources[0x26]	26359	1			T2	119		T5	7		T11	15
valid_sources[0x27]	27450	1			T2	147		T5	5		T11	10
valid_sources[0x28]	27440	1			T2	164		T5	6		T11	15
valid_sources[0x29]	28332	1			T2	171		T5	3		T11	6
valid_sources[0x2a]	23865	1			T2	128		T11	6		T13	148
valid_sources[0x2b]	25676	1			T2	126		T5	9		T11	15
valid_sources[0x2c]	27251	1			T2	122		T5	1		T11	9
valid_sources[0x2d]	26067	1			T2	125		T3	681		T5	5
valid_sources[0x2e]	27063	1			T2	165		T5	7		T11	15
valid_sources[0x2f]	56714	1			T1	3		T2	156		T5	20
valid_sources[0x30]	25981	1			T2	119		T8	1		T11	18
valid_sources[0x31]	28501	1			T2	143		T5	17		T11	18
valid_sources[0x32]	29237	1			T2	152		T5	6		T11	13
valid_sources[0x33]	30428	1			T2	176		T5	4		T11	14
valid_sources[0x34]	25409	1			T2	128		T5	1		T11	4
valid_sources[0x35]	24012	1			T2	182		T5	12		T11	14
valid_sources[0x36]	25289	1			T2	112		T5	1		T8	2
valid_sources[0x37]	25864	1			T2	193		T5	7		T11	12
valid_sources[0x38]	23943	1			T2	139		T5	5		T11	12
valid_sources[0x39]	24791	1			T2	154		T5	11		T11	16
valid_sources[0x3a]	27004	1			T2	142		T5	1		T11	8
valid_sources[0x3b]	26968	1			T2	120		T11	17		T13	191
valid_sources[0x3c]	26346	1			T2	110		T11	9		T13	220
valid_sources[0x3d]	29383	1			T2	153		T5	2		T11	22
valid_sources[0x3e]	25592	1			T2	153		T5	8		T11	16
valid_sources[0x3f]	34152	1			T2	162		T5	5		T11	18
valid_sources[0x40]	24180	1			T2	186		T5	1		T11	20
valid_sources[0x41]	25831	1			T2	123		T5	6		T7	6
valid_sources[0x42]	26747	1			T2	89		T5	4		T11	15
valid_sources[0x43]	24738	1			T2	181		T5	4		T11	19
valid_sources[0x44]	27929	1			T2	122		T5	14		T11	12
valid_sources[0x45]	24047	1			T2	137		T5	12		T11	7
valid_sources[0x46]	26168	1			T2	170		T5	1		T8	2
valid_sources[0x47]	24576	1			T2	146		T5	1		T11	8
valid_sources[0x48]	25197	1			T2	85		T5	9		T11	14
valid_sources[0x49]	27403	1			T2	120		T11	11		T13	207
valid_sources[0x4a]	28943	1			T2	121		T5	3		T11	22
valid_sources[0x4b]	28004	1			T2	125		T5	11		T11	10
valid_sources[0x4c]	26336	1			T2	114		T5	14		T11	12
valid_sources[0x4d]	28859	1			T2	100		T11	13		T13	197
valid_sources[0x4e]	28234	1			T2	133		T5	9		T11	8
valid_sources[0x4f]	26487	1			T2	122		T5	16		T11	15
valid_sources[0x50]	26986	1			T2	108		T5	12		T11	18
valid_sources[0x51]	25562	1			T2	128		T5	7		T11	15
valid_sources[0x52]	24381	1			T2	112		T5	2		T11	13
valid_sources[0x53]	29513	1			T2	169		T5	14		T11	21
valid_sources[0x54]	26408	1			T2	149		T5	8		T11	16
valid_sources[0x55]	26522	1			T2	119		T5	5		T11	14
valid_sources[0x56]	26928	1			T2	149		T3	6		T5	20
valid_sources[0x57]	25277	1			T2	100		T5	2		T10	3
valid_sources[0x58]	26163	1			T2	119		T5	18		T11	19
valid_sources[0x59]	28283	1			T2	125		T11	8		T13	156
valid_sources[0x5a]	24677	1			T2	143		T11	10		T13	164
valid_sources[0x5b]	68996	1			T2	137		T5	2		T10	2
valid_sources[0x5c]	25903	1			T2	120		T11	9		T13	174
valid_sources[0x5d]	28000	1			T2	167		T5	5		T11	19
valid_sources[0x5e]	24878	1			T2	145		T11	16		T13	157
valid_sources[0x5f]	25726	1			T2	127		T8	1		T11	16
valid_sources[0x60]	26374	1			T2	145		T5	15		T11	10
valid_sources[0x61]	26548	1			T2	179		T3	451		T5	11
valid_sources[0x62]	28283	1			T2	116		T11	12		T13	189
valid_sources[0x63]	25754	1			T2	208		T5	12		T11	13
valid_sources[0x64]	27320	1			T2	141		T11	22		T13	231
valid_sources[0x65]	30680	1			T2	130		T5	5		T8	3
valid_sources[0x66]	29291	1			T2	158		T11	15		T13	140
valid_sources[0x67]	26539	1			T2	125		T5	10		T11	13
valid_sources[0x68]	24773	1			T2	124		T5	1		T11	11
valid_sources[0x69]	25716	1			T2	171		T5	2		T11	11
valid_sources[0x6a]	25346	1			T2	110		T5	1		T11	11
valid_sources[0x6b]	25387	1			T2	102		T5	2		T11	8
valid_sources[0x6c]	29384	1			T2	150		T5	7		T11	10
valid_sources[0x6d]	24218	1			T2	96		T5	2		T10	1
valid_sources[0x6e]	30812	1			T2	154		T5	3		T11	15
valid_sources[0x6f]	26580	1			T2	123		T5	3		T11	12
valid_sources[0x70]	24628	1			T2	111		T5	8		T11	14
valid_sources[0x71]	24568	1			T2	138		T5	15		T11	14
valid_sources[0x72]	23663	1			T2	123		T5	10		T10	1
valid_sources[0x73]	29342	1			T2	106		T5	5		T11	12
valid_sources[0x74]	27392	1			T2	119		T5	2		T11	11
valid_sources[0x75]	25335	1			T2	213		T5	9		T11	17
valid_sources[0x76]	28427	1			T2	126		T5	3		T11	16
valid_sources[0x77]	28931	1			T2	109		T5	10		T11	7
valid_sources[0x78]	23899	1			T2	125		T5	15		T11	6
valid_sources[0x79]	26438	1			T2	123		T5	1		T11	9
valid_sources[0x7a]	25541	1			T2	140		T5	10		T11	23
valid_sources[0x7b]	25786	1			T2	115		T5	1		T11	14
valid_sources[0x7c]	28258	1			T2	144		T5	15		T11	17
valid_sources[0x7d]	26255	1			T2	115		T11	9		T12	1
valid_sources[0x7e]	34898	1			T2	118		T5	8		T11	26
valid_sources[0x7f]	27403	1			T2	112		T11	26		T13	156
valid_sources[0x80]	24393	1			T2	116		T5	7		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

979987

1

T1

2

T2

1790

T3

116

values[0x0]

all_enables

biggest_size

1375425

1

T2

6256

T3

448

T4

203

values[0x1]

all_enables

biggest_size

1353353

1

T2

6003

T3

447

T4

135