Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3286789

1

T1

1

T2

21423

T3

127

full_word

3710291

1

T1

2

T2

14049

T3

1011

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6996700	1			T1	3		T2	35472		T3	1138
auto[TlIntgErrCmd]	122	1			T58	11		T85	4		T86	7
auto[TlIntgErrData]	130	1			T58	7		T85	2		T86	11
auto[TlIntgErrBoth]	128	1			T58	12		T85	4		T86	12

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3946962

1

T1

3

T2

21241

T3

237

auto[1]

3050118

1

T2

14231

T3

901

T4

398

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2966426	1			T1	1		T2	19451		T3	121
auto[TlIntgErrNone]	partial	auto[1]	320007	1			T2	1972		T3	6		T4	60
auto[TlIntgErrNone]	full_word	auto[0]	980359	1			T1	2		T2	1790		T3	116
auto[TlIntgErrNone]	full_word	auto[1]	2729908	1			T2	12259		T3	895		T4	338
auto[TlIntgErrCmd]	partial	auto[0]	58	1			T58	4		T85	1		T86	4
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T58	7		T85	3		T86	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T96	1		T250	1		T248	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T250	2		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	64	1			T58	5		T86	6		T96	3
auto[TlIntgErrData]	partial	auto[1]	54	1			T58	2		T85	2		T86	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T86	1		T247	1		T251	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T86	1		T135	1		T252	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T58	5		T85	1		T86	7
auto[TlIntgErrBoth]	partial	auto[1]	77	1			T58	7		T85	3		T86	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T253	1		T254	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T255	1		T135	1		T248	1