Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	520506669	2843932	0	0
gen_wmask[1].MaskCheckPortA_A	520506669	2843932	0	0
gen_wmask[2].MaskCheckPortA_A	520506669	2843932	0	0
gen_wmask[3].MaskCheckPortA_A	520506669	2843932	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520506669	2843932	0	0
T2	387886	9164	0	0
T3	37982	832	0	0
T4	150334	0	0	0
T5	34980	832	0	0
T6	27752	832	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1370	1	0	0
T11	71561	832	0	0
T12	216	0	0	0
T13	797243	14030	0	0
T14	488125	10376	0	0
T15	0	1995	0	0
T16	0	832	0	0
T17	0	4528	0	0
T18	0	7350	0	0
T29	0	590	0	0
T33	0	14541	0	0
T34	0	5299	0	0
T35	0	1822	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520506669	2843932	0	0
T2	387886	9164	0	0
T3	37982	832	0	0
T4	150334	0	0	0
T5	34980	832	0	0
T6	27752	832	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1370	1	0	0
T11	71561	832	0	0
T12	216	0	0	0
T13	797243	14030	0	0
T14	488125	10376	0	0
T15	0	1995	0	0
T16	0	832	0	0
T17	0	4528	0	0
T18	0	7350	0	0
T29	0	590	0	0
T33	0	14541	0	0
T34	0	5299	0	0
T35	0	1822	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520506669	2843932	0	0
T2	387886	9164	0	0
T3	37982	832	0	0
T4	150334	0	0	0
T5	34980	832	0	0
T6	27752	832	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1370	1	0	0
T11	71561	832	0	0
T12	216	0	0	0
T13	797243	14030	0	0
T14	488125	10376	0	0
T15	0	1995	0	0
T16	0	832	0	0
T17	0	4528	0	0
T18	0	7350	0	0
T29	0	590	0	0
T33	0	14541	0	0
T34	0	5299	0	0
T35	0	1822	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520506669	2843932	0	0
T2	387886	9164	0	0
T3	37982	832	0	0
T4	150334	0	0	0
T5	34980	832	0	0
T6	27752	832	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1370	1	0	0
T11	71561	832	0	0
T12	216	0	0	0
T13	797243	14030	0	0
T14	488125	10376	0	0
T15	0	1995	0	0
T16	0	832	0	0
T17	0	4528	0	0
T18	0	7350	0	0
T29	0	590	0	0
T33	0	14541	0	0
T34	0	5299	0	0
T35	0	1822	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	397353182	1743214	0	0
gen_wmask[1].MaskCheckPortA_A	397353182	1743214	0	0
gen_wmask[2].MaskCheckPortA_A	397353182	1743214	0	0
gen_wmask[3].MaskCheckPortA_A	397353182	1743214	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397353182	1743214	0	0
T2	160529	4884	0	0
T3	11894	832	0	0
T4	59077	0	0	0
T5	13951	832	0	0
T6	9522	832	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1282	1	0	0
T11	61209	832	0	0
T13	0	10499	0	0
T14	0	4858	0	0
T15	0	548	0	0
T16	0	832	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397353182	1743214	0	0
T2	160529	4884	0	0
T3	11894	832	0	0
T4	59077	0	0	0
T5	13951	832	0	0
T6	9522	832	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1282	1	0	0
T11	61209	832	0	0
T13	0	10499	0	0
T14	0	4858	0	0
T15	0	548	0	0
T16	0	832	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397353182	1743214	0	0
T2	160529	4884	0	0
T3	11894	832	0	0
T4	59077	0	0	0
T5	13951	832	0	0
T6	9522	832	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1282	1	0	0
T11	61209	832	0	0
T13	0	10499	0	0
T14	0	4858	0	0
T15	0	548	0	0
T16	0	832	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397353182	1743214	0	0
T2	160529	4884	0	0
T3	11894	832	0	0
T4	59077	0	0	0
T5	13951	832	0	0
T6	9522	832	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1282	1	0	0
T11	61209	832	0	0
T13	0	10499	0	0
T14	0	4858	0	0
T15	0	548	0	0
T16	0	832	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T13,T14
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T13,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	123153487	1100718	0	0
gen_wmask[1].MaskCheckPortA_A	123153487	1100718	0	0
gen_wmask[2].MaskCheckPortA_A	123153487	1100718	0	0
gen_wmask[3].MaskCheckPortA_A	123153487	1100718	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	1100718	0	0
T2	227357	4280	0	0
T3	26088	0	0	0
T4	91257	0	0	0
T5	21029	0	0	0
T6	18230	0	0	0
T10	88	0	0	0
T11	10352	0	0	0
T12	216	0	0	0
T13	797243	3531	0	0
T14	488125	5518	0	0
T15	0	1447	0	0
T17	0	4528	0	0
T18	0	7350	0	0
T29	0	590	0	0
T33	0	14541	0	0
T34	0	5299	0	0
T35	0	1822	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	1100718	0	0
T2	227357	4280	0	0
T3	26088	0	0	0
T4	91257	0	0	0
T5	21029	0	0	0
T6	18230	0	0	0
T10	88	0	0	0
T11	10352	0	0	0
T12	216	0	0	0
T13	797243	3531	0	0
T14	488125	5518	0	0
T15	0	1447	0	0
T17	0	4528	0	0
T18	0	7350	0	0
T29	0	590	0	0
T33	0	14541	0	0
T34	0	5299	0	0
T35	0	1822	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	1100718	0	0
T2	227357	4280	0	0
T3	26088	0	0	0
T4	91257	0	0	0
T5	21029	0	0	0
T6	18230	0	0	0
T10	88	0	0	0
T11	10352	0	0	0
T12	216	0	0	0
T13	797243	3531	0	0
T14	488125	5518	0	0
T15	0	1447	0	0
T17	0	4528	0	0
T18	0	7350	0	0
T29	0	590	0	0
T33	0	14541	0	0
T34	0	5299	0	0
T35	0	1822	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	1100718	0	0
T2	227357	4280	0	0
T3	26088	0	0	0
T4	91257	0	0	0
T5	21029	0	0	0
T6	18230	0	0	0
T10	88	0	0	0
T11	10352	0	0	0
T12	216	0	0	0
T13	797243	3531	0	0
T14	488125	5518	0	0
T15	0	1447	0	0
T17	0	4528	0	0
T18	0	7350	0	0
T29	0	590	0	0
T33	0	14541	0	0
T34	0	5299	0	0
T35	0	1822	0	0