Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	399727289	2367050	0	0
DepthKnown_A	399727289	399598431	0	0
RvalidKnown_A	399727289	399598431	0	0
WreadyKnown_A	399727289	399598431	0	0
gen_passthru_fifo.paramCheckPass	1080	1080	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	2367050	0	0
T2	160529	5822	0	0
T3	11894	1664	0	0
T4	59077	0	0	0
T5	13951	832	0	0
T6	9522	1663	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1282	0	0	0
T11	61209	832	0	0
T13	0	15809	0	0
T14	0	5822	0	0
T16	0	832	0	0
T17	0	15814	0	0
T18	0	13307	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	399598431	0	0
T1	4693	4593	0	0
T2	160529	160520	0	0
T3	11894	11815	0	0
T4	59077	58988	0	0
T5	13951	13893	0	0
T6	9522	9430	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1282	1199	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	399598431	0	0
T1	4693	4593	0	0
T2	160529	160520	0	0
T3	11894	11815	0	0
T4	59077	58988	0	0
T5	13951	13893	0	0
T6	9522	9430	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1282	1199	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	399598431	0	0
T1	4693	4593	0	0
T2	160529	160520	0	0
T3	11894	11815	0	0
T4	59077	58988	0	0
T5	13951	13893	0	0
T6	9522	9430	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1282	1199	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1080	1080	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	399727289	2698177	0	0
DepthKnown_A	399727289	399598431	0	0
RvalidKnown_A	399727289	399598431	0	0
WreadyKnown_A	399727289	399598431	0	0
gen_passthru_fifo.paramCheckPass	1080	1080	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	2698177	0	0
T2	160529	4160	0	0
T3	11894	833	0	0
T4	59077	0	0	0
T5	13951	832	0	0
T6	9522	832	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1282	0	0	0
T11	61209	2585	0	0
T13	0	16750	0	0
T14	0	13170	0	0
T16	0	832	0	0
T17	0	14337	0	0
T18	0	9152	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	399598431	0	0
T1	4693	4593	0	0
T2	160529	160520	0	0
T3	11894	11815	0	0
T4	59077	58988	0	0
T5	13951	13893	0	0
T6	9522	9430	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1282	1199	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	399598431	0	0
T1	4693	4593	0	0
T2	160529	160520	0	0
T3	11894	11815	0	0
T4	59077	58988	0	0
T5	13951	13893	0	0
T6	9522	9430	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1282	1199	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	399598431	0	0
T1	4693	4593	0	0
T2	160529	160520	0	0
T3	11894	11815	0	0
T4	59077	58988	0	0
T5	13951	13893	0	0
T6	9522	9430	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1282	1199	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1080	1080	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	399727289	172178	0	0
DepthKnown_A	399727289	399598431	0	0
RvalidKnown_A	399727289	399598431	0	0
WreadyKnown_A	399727289	399598431	0	0
gen_passthru_fifo.paramCheckPass	1080	1080	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	172178	0	0
T2	160529	647	0	0
T3	11894	0	0	0
T4	59077	0	0	0
T5	13951	0	0	0
T6	9522	0	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1282	0	0	0
T11	61209	0	0	0
T13	0	683	0	0
T14	0	1066	0	0
T15	0	373	0	0
T17	0	763	0	0
T18	0	1820	0	0
T29	0	150	0	0
T33	0	1149	0	0
T34	0	161	0	0
T35	0	386	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	399598431	0	0
T1	4693	4593	0	0
T2	160529	160520	0	0
T3	11894	11815	0	0
T4	59077	58988	0	0
T5	13951	13893	0	0
T6	9522	9430	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1282	1199	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	399598431	0	0
T1	4693	4593	0	0
T2	160529	160520	0	0
T3	11894	11815	0	0
T4	59077	58988	0	0
T5	13951	13893	0	0
T6	9522	9430	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1282	1199	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	399598431	0	0
T1	4693	4593	0	0
T2	160529	160520	0	0
T3	11894	11815	0	0
T4	59077	58988	0	0
T5	13951	13893	0	0
T6	9522	9430	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1282	1199	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1080	1080	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	399727289	388879	0	0
DepthKnown_A	399727289	399598431	0	0
RvalidKnown_A	399727289	399598431	0	0
WreadyKnown_A	399727289	399598431	0	0
gen_passthru_fifo.paramCheckPass	1080	1080	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	388879	0	0
T2	160529	647	0	0
T3	11894	0	0	0
T4	59077	0	0	0
T5	13951	0	0	0
T6	9522	0	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1282	0	0	0
T11	61209	0	0	0
T13	0	2028	0	0
T14	0	4493	0	0
T15	0	373	0	0
T17	0	2311	0	0
T18	0	1820	0	0
T29	0	150	0	0
T33	0	3561	0	0
T34	0	278	0	0
T35	0	1747	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	399598431	0	0
T1	4693	4593	0	0
T2	160529	160520	0	0
T3	11894	11815	0	0
T4	59077	58988	0	0
T5	13951	13893	0	0
T6	9522	9430	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1282	1199	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	399598431	0	0
T1	4693	4593	0	0
T2	160529	160520	0	0
T3	11894	11815	0	0
T4	59077	58988	0	0
T5	13951	13893	0	0
T6	9522	9430	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1282	1199	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	399598431	0	0
T1	4693	4593	0	0
T2	160529	160520	0	0
T3	11894	11815	0	0
T4	59077	58988	0	0
T5	13951	13893	0	0
T6	9522	9430	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1282	1199	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1080	1080	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	399727289	5629474	0	0
DepthKnown_A	399727289	399598431	0	0
RvalidKnown_A	399727289	399598431	0	0
WreadyKnown_A	399727289	399598431	0	0
gen_passthru_fifo.paramCheckPass	1080	1080	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	5629474	0	0
T1	4693	3	0	0
T2	160529	31042	0	0
T3	11894	306	0	0
T4	59077	399	0	0
T5	13951	799	0	0
T6	9522	411	0	0
T7	1408	9	0	0
T8	1137	12	0	0
T9	812	5	0	0
T10	1282	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	399598431	0	0
T1	4693	4593	0	0
T2	160529	160520	0	0
T3	11894	11815	0	0
T4	59077	58988	0	0
T5	13951	13893	0	0
T6	9522	9430	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1282	1199	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	399598431	0	0
T1	4693	4593	0	0
T2	160529	160520	0	0
T3	11894	11815	0	0
T4	59077	58988	0	0
T5	13951	13893	0	0
T6	9522	9430	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1282	1199	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	399598431	0	0
T1	4693	4593	0	0
T2	160529	160520	0	0
T3	11894	11815	0	0
T4	59077	58988	0	0
T5	13951	13893	0	0
T6	9522	9430	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1282	1199	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1080	1080	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	399727289	11515299	0	0
DepthKnown_A	399727289	399598431	0	0
RvalidKnown_A	399727289	399598431	0	0
WreadyKnown_A	399727289	399598431	0	0
gen_passthru_fifo.paramCheckPass	1080	1080	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	11515299	0	0
T1	4693	10	0	0
T2	160529	30665	0	0
T3	11894	1345	0	0
T4	59077	399	0	0
T5	13951	799	0	0
T6	9522	411	0	0
T7	1408	9	0	0
T8	1137	12	0	0
T9	812	18	0	0
T10	1282	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	399598431	0	0
T1	4693	4593	0	0
T2	160529	160520	0	0
T3	11894	11815	0	0
T4	59077	58988	0	0
T5	13951	13893	0	0
T6	9522	9430	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1282	1199	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	399598431	0	0
T1	4693	4593	0	0
T2	160529	160520	0	0
T3	11894	11815	0	0
T4	59077	58988	0	0
T5	13951	13893	0	0
T6	9522	9430	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1282	1199	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399727289	399598431	0	0
T1	4693	4593	0	0
T2	160529	160520	0	0
T3	11894	11815	0	0
T4	59077	58988	0	0
T5	13951	13893	0	0
T6	9522	9430	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1282	1199	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1080	1080	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0