Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T13,T14
1	0	Covered	T2,T10,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T10
1	0	Unreachable
1	1	Covered	T2,T10,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T13,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T13,T14
1	0	Covered	T2,T13,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Unreachable
1	1	Covered	T2,T13,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T13,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T10,T13
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	643660156	519230170	0	0
CheckNGreaterZero_A	2715	2715	0	0
GntImpliesReady_A	643660156	3194454	0	0
GntImpliesValid_A	643660156	3194454	0	0
GrantKnown_A	643660156	519230170	0	0
IdxKnown_A	643660156	519230170	0	0
IndexIsCorrect_A	643660156	3194454	0	0
LockArbDecision_A	643660156	0	0	0
NoReadyValidNoGrant_A	643660156	0	0	0
ReadyAndValidImplyGrant_A	643660156	3194454	0	0
ReqAndReadyImplyGrant_A	643660156	3194454	0	0
ReqImpliesValid_A	643660156	3194454	0	0
ReqStaysHighUntilGranted0_M	643660156	0	0	0
RoundRobin_A	643660156	4	0	905
ValidKnown_A	643660156	519230170	0	0
gen_data_port_assertion.DataFlow_A	643660156	3194454	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643660156	519230170	0	0
T1	4693	4593	0	0
T2	615243	385205	0	0
T3	64070	37779	0	0
T4	241591	145252	0	0
T5	56009	34437	0	0
T6	45982	27660	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1458	1287	0	0
T11	20704	10352	0	0
T12	432	216	0	0
T13	1594486	792828	0	0
T14	976250	481874	0	0
T15	0	49160	0	0
T16	0	54048	0	0
T17	0	1002547	0	0
T18	0	917190	0	0
T26	0	67728	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2715	2715	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643660156	3194454	0	0
T2	615243	10618	0	0
T3	64070	832	0	0
T4	241591	0	0	0
T5	56009	832	0	0
T6	45982	832	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1458	3	0	0
T11	81913	832	0	0
T12	432	0	0	0
T13	1594486	15297	0	0
T14	976250	12081	0	0
T15	0	2980	0	0
T16	0	832	0	0
T17	0	5549	0	0
T18	0	10515	0	0
T29	0	816	0	0
T33	0	15705	0	0
T34	0	5299	0	0
T35	0	1822	0	0
T36	0	6181	0	0
T42	0	5713	0	0
T43	0	5205	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643660156	3194454	0	0
T2	615243	10618	0	0
T3	64070	832	0	0
T4	241591	0	0	0
T5	56009	832	0	0
T6	45982	832	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1458	3	0	0
T11	81913	832	0	0
T12	432	0	0	0
T13	1594486	15297	0	0
T14	976250	12081	0	0
T15	0	2980	0	0
T16	0	832	0	0
T17	0	5549	0	0
T18	0	10515	0	0
T29	0	816	0	0
T33	0	15705	0	0
T34	0	5299	0	0
T35	0	1822	0	0
T36	0	6181	0	0
T42	0	5713	0	0
T43	0	5205	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643660156	519230170	0	0
T1	4693	4593	0	0
T2	615243	385205	0	0
T3	64070	37779	0	0
T4	241591	145252	0	0
T5	56009	34437	0	0
T6	45982	27660	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1458	1287	0	0
T11	20704	10352	0	0
T12	432	216	0	0
T13	1594486	792828	0	0
T14	976250	481874	0	0
T15	0	49160	0	0
T16	0	54048	0	0
T17	0	1002547	0	0
T18	0	917190	0	0
T26	0	67728	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643660156	519230170	0	0
T1	4693	4593	0	0
T2	615243	385205	0	0
T3	64070	37779	0	0
T4	241591	145252	0	0
T5	56009	34437	0	0
T6	45982	27660	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1458	1287	0	0
T11	20704	10352	0	0
T12	432	216	0	0
T13	1594486	792828	0	0
T14	976250	481874	0	0
T15	0	49160	0	0
T16	0	54048	0	0
T17	0	1002547	0	0
T18	0	917190	0	0
T26	0	67728	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643660156	3194454	0	0
T2	615243	10618	0	0
T3	64070	832	0	0
T4	241591	0	0	0
T5	56009	832	0	0
T6	45982	832	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1458	3	0	0
T11	81913	832	0	0
T12	432	0	0	0
T13	1594486	15297	0	0
T14	976250	12081	0	0
T15	0	2980	0	0
T16	0	832	0	0
T17	0	5549	0	0
T18	0	10515	0	0
T29	0	816	0	0
T33	0	15705	0	0
T34	0	5299	0	0
T35	0	1822	0	0
T36	0	6181	0	0
T42	0	5713	0	0
T43	0	5205	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643660156	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643660156	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643660156	3194454	0	0
T2	615243	10618	0	0
T3	64070	832	0	0
T4	241591	0	0	0
T5	56009	832	0	0
T6	45982	832	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1458	3	0	0
T11	81913	832	0	0
T12	432	0	0	0
T13	1594486	15297	0	0
T14	976250	12081	0	0
T15	0	2980	0	0
T16	0	832	0	0
T17	0	5549	0	0
T18	0	10515	0	0
T29	0	816	0	0
T33	0	15705	0	0
T34	0	5299	0	0
T35	0	1822	0	0
T36	0	6181	0	0
T42	0	5713	0	0
T43	0	5205	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643660156	3194454	0	0
T2	615243	10618	0	0
T3	64070	832	0	0
T4	241591	0	0	0
T5	56009	832	0	0
T6	45982	832	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1458	3	0	0
T11	81913	832	0	0
T12	432	0	0	0
T13	1594486	15297	0	0
T14	976250	12081	0	0
T15	0	2980	0	0
T16	0	832	0	0
T17	0	5549	0	0
T18	0	10515	0	0
T29	0	816	0	0
T33	0	15705	0	0
T34	0	5299	0	0
T35	0	1822	0	0
T36	0	6181	0	0
T42	0	5713	0	0
T43	0	5205	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643660156	3194454	0	0
T2	615243	10618	0	0
T3	64070	832	0	0
T4	241591	0	0	0
T5	56009	832	0	0
T6	45982	832	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1458	3	0	0
T11	81913	832	0	0
T12	432	0	0	0
T13	1594486	15297	0	0
T14	976250	12081	0	0
T15	0	2980	0	0
T16	0	832	0	0
T17	0	5549	0	0
T18	0	10515	0	0
T29	0	816	0	0
T33	0	15705	0	0
T34	0	5299	0	0
T35	0	1822	0	0
T36	0	6181	0	0
T42	0	5713	0	0
T43	0	5205	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	643660156	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643660156	4	0	905
T44	151212	1	0	1
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	3846	0	0	1
T49	10321	0	0	1
T50	111126	0	0	1
T51	10586	0	0	1
T52	6353	0	0	1
T53	36670	0	0	1
T54	141672	0	0	1
T55	1456	0	0	1
T56	284751	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643660156	519230170	0	0
T1	4693	4593	0	0
T2	615243	385205	0	0
T3	64070	37779	0	0
T4	241591	145252	0	0
T5	56009	34437	0	0
T6	45982	27660	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1458	1287	0	0
T11	20704	10352	0	0
T12	432	216	0	0
T13	1594486	792828	0	0
T14	976250	481874	0	0
T15	0	49160	0	0
T16	0	54048	0	0
T17	0	1002547	0	0
T18	0	917190	0	0
T26	0	67728	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643660156	3194454	0	0
T2	615243	10618	0	0
T3	64070	832	0	0
T4	241591	0	0	0
T5	56009	832	0	0
T6	45982	832	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1458	3	0	0
T11	81913	832	0	0
T12	432	0	0	0
T13	1594486	15297	0	0
T14	976250	12081	0	0
T15	0	2980	0	0
T16	0	832	0	0
T17	0	5549	0	0
T18	0	10515	0	0
T29	0	816	0	0
T33	0	15705	0	0
T34	0	5299	0	0
T35	0	1822	0	0
T36	0	6181	0	0
T42	0	5713	0	0
T43	0	5205	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T13,T14
1	0	Covered	T2,T10,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T10
1	0	Unreachable
1	1	Covered	T2,T10,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T10,T13
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T10

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	123153487	24476539	0	0
CheckNGreaterZero_A	905	905	0	0
GntImpliesReady_A	123153487	583044	0	0
GntImpliesValid_A	123153487	583044	0	0
GrantKnown_A	123153487	24476539	0	0
IdxKnown_A	123153487	24476539	0	0
IndexIsCorrect_A	123153487	583044	0	0
LockArbDecision_A	123153487	0	0	0
NoReadyValidNoGrant_A	123153487	0	0	0
ReadyAndValidImplyGrant_A	123153487	583044	0	0
ReqAndReadyImplyGrant_A	123153487	583044	0	0
ReqImpliesValid_A	123153487	583044	0	0
ReqStaysHighUntilGranted0_M	123153487	0	0	0
RoundRobin_A	123153487	0	0	0
ValidKnown_A	123153487	24476539	0	0
gen_data_port_assertion.DataFlow_A	123153487	583044	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	24476539	0	0
T2	227357	47584	0	0
T3	26088	0	0	0
T4	91257	86264	0	0
T5	21029	0	0	0
T6	18230	0	0	0
T10	88	88	0	0
T11	10352	0	0	0
T12	216	216	0	0
T13	797243	46776	0	0
T14	488125	270632	0	0
T15	0	49160	0	0
T17	0	257984	0	0
T18	0	468784	0	0
T26	0	67728	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	583044	0	0
T2	227357	2239	0	0
T3	26088	0	0	0
T4	91257	0	0	0
T5	21029	0	0	0
T6	18230	0	0	0
T10	88	2	0	0
T11	10352	0	0	0
T12	216	0	0	0
T13	797243	1850	0	0
T14	488125	2615	0	0
T15	0	2059	0	0
T17	0	3161	0	0
T18	0	9222	0	0
T29	0	816	0	0
T33	0	2768	0	0
T42	0	5713	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	583044	0	0
T2	227357	2239	0	0
T3	26088	0	0	0
T4	91257	0	0	0
T5	21029	0	0	0
T6	18230	0	0	0
T10	88	2	0	0
T11	10352	0	0	0
T12	216	0	0	0
T13	797243	1850	0	0
T14	488125	2615	0	0
T15	0	2059	0	0
T17	0	3161	0	0
T18	0	9222	0	0
T29	0	816	0	0
T33	0	2768	0	0
T42	0	5713	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	24476539	0	0
T2	227357	47584	0	0
T3	26088	0	0	0
T4	91257	86264	0	0
T5	21029	0	0	0
T6	18230	0	0	0
T10	88	88	0	0
T11	10352	0	0	0
T12	216	216	0	0
T13	797243	46776	0	0
T14	488125	270632	0	0
T15	0	49160	0	0
T17	0	257984	0	0
T18	0	468784	0	0
T26	0	67728	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	24476539	0	0
T2	227357	47584	0	0
T3	26088	0	0	0
T4	91257	86264	0	0
T5	21029	0	0	0
T6	18230	0	0	0
T10	88	88	0	0
T11	10352	0	0	0
T12	216	216	0	0
T13	797243	46776	0	0
T14	488125	270632	0	0
T15	0	49160	0	0
T17	0	257984	0	0
T18	0	468784	0	0
T26	0	67728	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	583044	0	0
T2	227357	2239	0	0
T3	26088	0	0	0
T4	91257	0	0	0
T5	21029	0	0	0
T6	18230	0	0	0
T10	88	2	0	0
T11	10352	0	0	0
T12	216	0	0	0
T13	797243	1850	0	0
T14	488125	2615	0	0
T15	0	2059	0	0
T17	0	3161	0	0
T18	0	9222	0	0
T29	0	816	0	0
T33	0	2768	0	0
T42	0	5713	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	583044	0	0
T2	227357	2239	0	0
T3	26088	0	0	0
T4	91257	0	0	0
T5	21029	0	0	0
T6	18230	0	0	0
T10	88	2	0	0
T11	10352	0	0	0
T12	216	0	0	0
T13	797243	1850	0	0
T14	488125	2615	0	0
T15	0	2059	0	0
T17	0	3161	0	0
T18	0	9222	0	0
T29	0	816	0	0
T33	0	2768	0	0
T42	0	5713	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	583044	0	0
T2	227357	2239	0	0
T3	26088	0	0	0
T4	91257	0	0	0
T5	21029	0	0	0
T6	18230	0	0	0
T10	88	2	0	0
T11	10352	0	0	0
T12	216	0	0	0
T13	797243	1850	0	0
T14	488125	2615	0	0
T15	0	2059	0	0
T17	0	3161	0	0
T18	0	9222	0	0
T29	0	816	0	0
T33	0	2768	0	0
T42	0	5713	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	583044	0	0
T2	227357	2239	0	0
T3	26088	0	0	0
T4	91257	0	0	0
T5	21029	0	0	0
T6	18230	0	0	0
T10	88	2	0	0
T11	10352	0	0	0
T12	216	0	0	0
T13	797243	1850	0	0
T14	488125	2615	0	0
T15	0	2059	0	0
T17	0	3161	0	0
T18	0	9222	0	0
T29	0	816	0	0
T33	0	2768	0	0
T42	0	5713	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	24476539	0	0
T2	227357	47584	0	0
T3	26088	0	0	0
T4	91257	86264	0	0
T5	21029	0	0	0
T6	18230	0	0	0
T10	88	88	0	0
T11	10352	0	0	0
T12	216	216	0	0
T13	797243	46776	0	0
T14	488125	270632	0	0
T15	0	49160	0	0
T17	0	257984	0	0
T18	0	468784	0	0
T26	0	67728	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	583044	0	0
T2	227357	2239	0	0
T3	26088	0	0	0
T4	91257	0	0	0
T5	21029	0	0	0
T6	18230	0	0	0
T10	88	2	0	0
T11	10352	0	0	0
T12	216	0	0	0
T13	797243	1850	0	0
T14	488125	2615	0	0
T15	0	2059	0	0
T17	0	3161	0	0
T18	0	9222	0	0
T29	0	816	0	0
T33	0	2768	0	0
T42	0	5713	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T13,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T13,T14
1	0	Covered	T2,T13,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Unreachable
1	1	Covered	T2,T13,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T13,T14
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T13,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	123153487	97485720	0	0
CheckNGreaterZero_A	905	905	0	0
GntImpliesReady_A	123153487	706929	0	0
GntImpliesValid_A	123153487	706929	0	0
GrantKnown_A	123153487	97485720	0	0
IdxKnown_A	123153487	97485720	0	0
IndexIsCorrect_A	123153487	706929	0	0
LockArbDecision_A	123153487	0	0	0
NoReadyValidNoGrant_A	123153487	0	0	0
ReadyAndValidImplyGrant_A	123153487	706929	0	0
ReqAndReadyImplyGrant_A	123153487	706929	0	0
ReqImpliesValid_A	123153487	706929	0	0
ReqStaysHighUntilGranted0_M	123153487	0	0	0
RoundRobin_A	123153487	0	0	0
ValidKnown_A	123153487	97485720	0	0
gen_data_port_assertion.DataFlow_A	123153487	706929	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	97485720	0	0
T2	227357	177101	0	0
T3	26088	25964	0	0
T4	91257	0	0	0
T5	21029	20544	0	0
T6	18230	18230	0	0
T10	88	0	0	0
T11	10352	10352	0	0
T12	216	0	0	0
T13	797243	746052	0	0
T14	488125	211242	0	0
T16	0	54048	0	0
T17	0	744563	0	0
T18	0	448406	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	706929	0	0
T2	227357	2835	0	0
T3	26088	0	0	0
T4	91257	0	0	0
T5	21029	0	0	0
T6	18230	0	0	0
T10	88	0	0	0
T11	10352	0	0	0
T12	216	0	0	0
T13	797243	2247	0	0
T14	488125	3666	0	0
T17	0	2388	0	0
T18	0	1293	0	0
T33	0	12937	0	0
T34	0	5299	0	0
T35	0	1822	0	0
T36	0	6181	0	0
T43	0	5205	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	706929	0	0
T2	227357	2835	0	0
T3	26088	0	0	0
T4	91257	0	0	0
T5	21029	0	0	0
T6	18230	0	0	0
T10	88	0	0	0
T11	10352	0	0	0
T12	216	0	0	0
T13	797243	2247	0	0
T14	488125	3666	0	0
T17	0	2388	0	0
T18	0	1293	0	0
T33	0	12937	0	0
T34	0	5299	0	0
T35	0	1822	0	0
T36	0	6181	0	0
T43	0	5205	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	97485720	0	0
T2	227357	177101	0	0
T3	26088	25964	0	0
T4	91257	0	0	0
T5	21029	20544	0	0
T6	18230	18230	0	0
T10	88	0	0	0
T11	10352	10352	0	0
T12	216	0	0	0
T13	797243	746052	0	0
T14	488125	211242	0	0
T16	0	54048	0	0
T17	0	744563	0	0
T18	0	448406	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	97485720	0	0
T2	227357	177101	0	0
T3	26088	25964	0	0
T4	91257	0	0	0
T5	21029	20544	0	0
T6	18230	18230	0	0
T10	88	0	0	0
T11	10352	10352	0	0
T12	216	0	0	0
T13	797243	746052	0	0
T14	488125	211242	0	0
T16	0	54048	0	0
T17	0	744563	0	0
T18	0	448406	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	706929	0	0
T2	227357	2835	0	0
T3	26088	0	0	0
T4	91257	0	0	0
T5	21029	0	0	0
T6	18230	0	0	0
T10	88	0	0	0
T11	10352	0	0	0
T12	216	0	0	0
T13	797243	2247	0	0
T14	488125	3666	0	0
T17	0	2388	0	0
T18	0	1293	0	0
T33	0	12937	0	0
T34	0	5299	0	0
T35	0	1822	0	0
T36	0	6181	0	0
T43	0	5205	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	706929	0	0
T2	227357	2835	0	0
T3	26088	0	0	0
T4	91257	0	0	0
T5	21029	0	0	0
T6	18230	0	0	0
T10	88	0	0	0
T11	10352	0	0	0
T12	216	0	0	0
T13	797243	2247	0	0
T14	488125	3666	0	0
T17	0	2388	0	0
T18	0	1293	0	0
T33	0	12937	0	0
T34	0	5299	0	0
T35	0	1822	0	0
T36	0	6181	0	0
T43	0	5205	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	706929	0	0
T2	227357	2835	0	0
T3	26088	0	0	0
T4	91257	0	0	0
T5	21029	0	0	0
T6	18230	0	0	0
T10	88	0	0	0
T11	10352	0	0	0
T12	216	0	0	0
T13	797243	2247	0	0
T14	488125	3666	0	0
T17	0	2388	0	0
T18	0	1293	0	0
T33	0	12937	0	0
T34	0	5299	0	0
T35	0	1822	0	0
T36	0	6181	0	0
T43	0	5205	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	706929	0	0
T2	227357	2835	0	0
T3	26088	0	0	0
T4	91257	0	0	0
T5	21029	0	0	0
T6	18230	0	0	0
T10	88	0	0	0
T11	10352	0	0	0
T12	216	0	0	0
T13	797243	2247	0	0
T14	488125	3666	0	0
T17	0	2388	0	0
T18	0	1293	0	0
T33	0	12937	0	0
T34	0	5299	0	0
T35	0	1822	0	0
T36	0	6181	0	0
T43	0	5205	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	97485720	0	0
T2	227357	177101	0	0
T3	26088	25964	0	0
T4	91257	0	0	0
T5	21029	20544	0	0
T6	18230	18230	0	0
T10	88	0	0	0
T11	10352	10352	0	0
T12	216	0	0	0
T13	797243	746052	0	0
T14	488125	211242	0	0
T16	0	54048	0	0
T17	0	744563	0	0
T18	0	448406	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123153487	706929	0	0
T2	227357	2835	0	0
T3	26088	0	0	0
T4	91257	0	0	0
T5	21029	0	0	0
T6	18230	0	0	0
T10	88	0	0	0
T11	10352	0	0	0
T12	216	0	0	0
T13	797243	2247	0	0
T14	488125	3666	0	0
T17	0	2388	0	0
T18	0	1293	0	0
T33	0	12937	0	0
T34	0	5299	0	0
T35	0	1822	0	0
T36	0	6181	0	0
T43	0	5205	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T13,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T10,T13
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	397353182	397267911	0	0
CheckNGreaterZero_A	905	905	0	0
GntImpliesReady_A	397353182	1904481	0	0
GntImpliesValid_A	397353182	1904481	0	0
GrantKnown_A	397353182	397267911	0	0
IdxKnown_A	397353182	397267911	0	0
IndexIsCorrect_A	397353182	1904481	0	0
LockArbDecision_A	397353182	0	0	0
NoReadyValidNoGrant_A	397353182	0	0	0
ReadyAndValidImplyGrant_A	397353182	1904481	0	0
ReqAndReadyImplyGrant_A	397353182	1904481	0	0
ReqImpliesValid_A	397353182	1904481	0	0
ReqStaysHighUntilGranted0_M	397353182	0	0	0
RoundRobin_A	397353182	4	0	905
ValidKnown_A	397353182	397267911	0	0
gen_data_port_assertion.DataFlow_A	397353182	1904481	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397353182	397267911	0	0
T1	4693	4593	0	0
T2	160529	160520	0	0
T3	11894	11815	0	0
T4	59077	58988	0	0
T5	13951	13893	0	0
T6	9522	9430	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1282	1199	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397353182	1904481	0	0
T2	160529	5544	0	0
T3	11894	832	0	0
T4	59077	0	0	0
T5	13951	832	0	0
T6	9522	832	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1282	1	0	0
T11	61209	832	0	0
T13	0	11200	0	0
T14	0	5800	0	0
T15	0	921	0	0
T16	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397353182	1904481	0	0
T2	160529	5544	0	0
T3	11894	832	0	0
T4	59077	0	0	0
T5	13951	832	0	0
T6	9522	832	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1282	1	0	0
T11	61209	832	0	0
T13	0	11200	0	0
T14	0	5800	0	0
T15	0	921	0	0
T16	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397353182	397267911	0	0
T1	4693	4593	0	0
T2	160529	160520	0	0
T3	11894	11815	0	0
T4	59077	58988	0	0
T5	13951	13893	0	0
T6	9522	9430	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1282	1199	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397353182	397267911	0	0
T1	4693	4593	0	0
T2	160529	160520	0	0
T3	11894	11815	0	0
T4	59077	58988	0	0
T5	13951	13893	0	0
T6	9522	9430	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1282	1199	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397353182	1904481	0	0
T2	160529	5544	0	0
T3	11894	832	0	0
T4	59077	0	0	0
T5	13951	832	0	0
T6	9522	832	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1282	1	0	0
T11	61209	832	0	0
T13	0	11200	0	0
T14	0	5800	0	0
T15	0	921	0	0
T16	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397353182	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397353182	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397353182	1904481	0	0
T2	160529	5544	0	0
T3	11894	832	0	0
T4	59077	0	0	0
T5	13951	832	0	0
T6	9522	832	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1282	1	0	0
T11	61209	832	0	0
T13	0	11200	0	0
T14	0	5800	0	0
T15	0	921	0	0
T16	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397353182	1904481	0	0
T2	160529	5544	0	0
T3	11894	832	0	0
T4	59077	0	0	0
T5	13951	832	0	0
T6	9522	832	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1282	1	0	0
T11	61209	832	0	0
T13	0	11200	0	0
T14	0	5800	0	0
T15	0	921	0	0
T16	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397353182	1904481	0	0
T2	160529	5544	0	0
T3	11894	832	0	0
T4	59077	0	0	0
T5	13951	832	0	0
T6	9522	832	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1282	1	0	0
T11	61209	832	0	0
T13	0	11200	0	0
T14	0	5800	0	0
T15	0	921	0	0
T16	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	397353182	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397353182	4	0	905
T44	151212	1	0	1
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	3846	0	0	1
T49	10321	0	0	1
T50	111126	0	0	1
T51	10586	0	0	1
T52	6353	0	0	1
T53	36670	0	0	1
T54	141672	0	0	1
T55	1456	0	0	1
T56	284751	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397353182	397267911	0	0
T1	4693	4593	0	0
T2	160529	160520	0	0
T3	11894	11815	0	0
T4	59077	58988	0	0
T5	13951	13893	0	0
T6	9522	9430	0	0
T7	1408	1316	0	0
T8	1137	1063	0	0
T9	812	744	0	0
T10	1282	1199	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397353182	1904481	0	0
T2	160529	5544	0	0
T3	11894	832	0	0
T4	59077	0	0	0
T5	13951	832	0	0
T6	9522	832	0	0
T7	1408	0	0	0
T8	1137	0	0	0
T9	812	0	0	0
T10	1282	1	0	0
T11	61209	832	0	0
T13	0	11200	0	0
T14	0	5800	0	0
T15	0	921	0	0
T16	0	832	0	0