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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 98.38 93.98 98.62 89.36 97.19 95.45 99.20


Total test records in report: 1080
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T1009 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3047185064 Jun 21 06:59:21 PM PDT 24 Jun 21 06:59:30 PM PDT 24 50125717 ps
T1010 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.318267048 Jun 21 06:59:30 PM PDT 24 Jun 21 06:59:36 PM PDT 24 46277375 ps
T1011 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2642510215 Jun 21 06:59:14 PM PDT 24 Jun 21 06:59:23 PM PDT 24 114135023 ps
T247 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.858301104 Jun 21 06:59:18 PM PDT 24 Jun 21 06:59:45 PM PDT 24 843380278 ps
T251 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3686022706 Jun 21 06:59:11 PM PDT 24 Jun 21 06:59:39 PM PDT 24 1341365025 ps
T1012 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3951202571 Jun 21 06:59:30 PM PDT 24 Jun 21 06:59:37 PM PDT 24 43810970 ps
T1013 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2247669591 Jun 21 06:59:20 PM PDT 24 Jun 21 06:59:27 PM PDT 24 327924615 ps
T1014 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.473804989 Jun 21 06:59:02 PM PDT 24 Jun 21 06:59:08 PM PDT 24 12221695 ps
T250 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3017356637 Jun 21 06:59:10 PM PDT 24 Jun 21 06:59:33 PM PDT 24 866037962 ps
T1015 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3934613618 Jun 21 06:59:30 PM PDT 24 Jun 21 06:59:36 PM PDT 24 15051579 ps
T1016 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1228889142 Jun 21 06:59:01 PM PDT 24 Jun 21 06:59:07 PM PDT 24 120627750 ps
T1017 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2593819746 Jun 21 06:59:31 PM PDT 24 Jun 21 06:59:38 PM PDT 24 23609180 ps
T1018 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.774520894 Jun 21 06:59:10 PM PDT 24 Jun 21 06:59:14 PM PDT 24 16663662 ps
T1019 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1309270226 Jun 21 06:59:20 PM PDT 24 Jun 21 06:59:26 PM PDT 24 20818044 ps
T1020 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2727464896 Jun 21 06:59:28 PM PDT 24 Jun 21 06:59:34 PM PDT 24 46981638 ps
T1021 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.440128999 Jun 21 06:59:32 PM PDT 24 Jun 21 06:59:39 PM PDT 24 793087818 ps
T1022 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3004958149 Jun 21 06:59:02 PM PDT 24 Jun 21 06:59:20 PM PDT 24 196174198 ps
T79 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2271057275 Jun 21 06:59:11 PM PDT 24 Jun 21 06:59:16 PM PDT 24 21597932 ps
T1023 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1222613329 Jun 21 06:59:09 PM PDT 24 Jun 21 06:59:14 PM PDT 24 27508596 ps
T1024 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3886803754 Jun 21 06:59:23 PM PDT 24 Jun 21 06:59:29 PM PDT 24 12513526 ps
T1025 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2101479014 Jun 21 06:59:13 PM PDT 24 Jun 21 06:59:19 PM PDT 24 144583671 ps
T1026 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2842968414 Jun 21 06:59:14 PM PDT 24 Jun 21 06:59:41 PM PDT 24 1112471717 ps
T1027 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1540976422 Jun 21 06:59:21 PM PDT 24 Jun 21 06:59:27 PM PDT 24 112351515 ps
T1028 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2072863550 Jun 21 06:59:13 PM PDT 24 Jun 21 06:59:18 PM PDT 24 20715281 ps
T1029 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3420077917 Jun 21 06:59:19 PM PDT 24 Jun 21 06:59:26 PM PDT 24 73381007 ps
T1030 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2712896112 Jun 21 06:59:31 PM PDT 24 Jun 21 06:59:38 PM PDT 24 17309982 ps
T1031 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3002287528 Jun 21 06:59:18 PM PDT 24 Jun 21 06:59:38 PM PDT 24 2222233397 ps
T1032 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3082402625 Jun 21 06:59:30 PM PDT 24 Jun 21 06:59:37 PM PDT 24 20555312 ps
T1033 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1398524467 Jun 21 06:59:15 PM PDT 24 Jun 21 06:59:24 PM PDT 24 64343715 ps
T1034 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1555751762 Jun 21 06:59:31 PM PDT 24 Jun 21 06:59:40 PM PDT 24 55601041 ps
T253 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1743541016 Jun 21 06:59:20 PM PDT 24 Jun 21 06:59:34 PM PDT 24 1295855190 ps
T1035 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.364851637 Jun 21 06:59:18 PM PDT 24 Jun 21 06:59:28 PM PDT 24 150477526 ps
T1036 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3442684484 Jun 21 06:59:27 PM PDT 24 Jun 21 06:59:33 PM PDT 24 11339047 ps
T1037 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4178015004 Jun 21 06:59:08 PM PDT 24 Jun 21 06:59:13 PM PDT 24 159527810 ps
T1038 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.843118550 Jun 21 06:59:32 PM PDT 24 Jun 21 06:59:42 PM PDT 24 155380575 ps
T1039 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3652503001 Jun 21 06:59:13 PM PDT 24 Jun 21 06:59:18 PM PDT 24 10982204 ps
T1040 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2844860500 Jun 21 06:59:23 PM PDT 24 Jun 21 06:59:30 PM PDT 24 18888583 ps
T1041 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3799676265 Jun 21 06:59:13 PM PDT 24 Jun 21 06:59:18 PM PDT 24 67758660 ps
T1042 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.974822538 Jun 21 06:59:11 PM PDT 24 Jun 21 06:59:16 PM PDT 24 28833756 ps
T1043 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.409383323 Jun 21 06:59:17 PM PDT 24 Jun 21 06:59:25 PM PDT 24 197923758 ps
T1044 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1199283398 Jun 21 06:59:30 PM PDT 24 Jun 21 06:59:37 PM PDT 24 24690724 ps
T1045 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1488637509 Jun 21 06:59:13 PM PDT 24 Jun 21 06:59:18 PM PDT 24 29276526 ps
T1046 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.877030809 Jun 21 06:59:22 PM PDT 24 Jun 21 06:59:31 PM PDT 24 414118470 ps
T248 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4115506716 Jun 21 06:59:10 PM PDT 24 Jun 21 06:59:32 PM PDT 24 297374346 ps
T1047 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.600345221 Jun 21 06:59:09 PM PDT 24 Jun 21 06:59:17 PM PDT 24 75122127 ps
T1048 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.151148998 Jun 21 06:59:02 PM PDT 24 Jun 21 06:59:08 PM PDT 24 141572245 ps
T1049 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.475765207 Jun 21 06:59:11 PM PDT 24 Jun 21 06:59:38 PM PDT 24 302161834 ps
T1050 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.311552208 Jun 21 06:59:32 PM PDT 24 Jun 21 06:59:51 PM PDT 24 2119018148 ps
T1051 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.266319626 Jun 21 06:59:30 PM PDT 24 Jun 21 06:59:36 PM PDT 24 14407519 ps
T1052 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3315822231 Jun 21 06:59:15 PM PDT 24 Jun 21 06:59:21 PM PDT 24 190796634 ps
T1053 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.112410909 Jun 21 06:59:20 PM PDT 24 Jun 21 06:59:28 PM PDT 24 147823495 ps
T1054 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1950768834 Jun 21 06:59:14 PM PDT 24 Jun 21 06:59:23 PM PDT 24 209867432 ps
T1055 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.793047101 Jun 21 06:59:19 PM PDT 24 Jun 21 06:59:27 PM PDT 24 435710128 ps
T1056 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3828448146 Jun 21 06:59:19 PM PDT 24 Jun 21 06:59:25 PM PDT 24 97656629 ps
T1057 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3625649226 Jun 21 06:59:19 PM PDT 24 Jun 21 06:59:25 PM PDT 24 50072418 ps
T1058 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3298958263 Jun 21 06:59:31 PM PDT 24 Jun 21 06:59:37 PM PDT 24 12620272 ps
T1059 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2161942556 Jun 21 06:59:31 PM PDT 24 Jun 21 06:59:38 PM PDT 24 50372527 ps
T1060 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.294704675 Jun 21 06:59:09 PM PDT 24 Jun 21 06:59:14 PM PDT 24 106156119 ps
T1061 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3852257782 Jun 21 06:59:20 PM PDT 24 Jun 21 06:59:28 PM PDT 24 157899181 ps
T1062 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4071792917 Jun 21 06:59:07 PM PDT 24 Jun 21 06:59:11 PM PDT 24 110824046 ps
T1063 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1261189750 Jun 21 06:59:17 PM PDT 24 Jun 21 06:59:23 PM PDT 24 27053822 ps
T1064 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4029403144 Jun 21 06:59:17 PM PDT 24 Jun 21 06:59:23 PM PDT 24 33578097 ps
T1065 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3767179712 Jun 21 06:59:23 PM PDT 24 Jun 21 06:59:29 PM PDT 24 22188361 ps
T1066 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2579233777 Jun 21 06:59:15 PM PDT 24 Jun 21 06:59:23 PM PDT 24 158107494 ps
T1067 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.568947203 Jun 21 06:59:19 PM PDT 24 Jun 21 06:59:28 PM PDT 24 566503619 ps
T1068 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3745252510 Jun 21 06:59:18 PM PDT 24 Jun 21 06:59:24 PM PDT 24 245526848 ps
T1069 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.233956836 Jun 21 06:59:28 PM PDT 24 Jun 21 06:59:34 PM PDT 24 46436398 ps
T1070 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.200775561 Jun 21 06:59:10 PM PDT 24 Jun 21 06:59:17 PM PDT 24 61206842 ps
T249 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1903512460 Jun 21 06:59:31 PM PDT 24 Jun 21 06:59:45 PM PDT 24 1033992120 ps
T1071 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1352488680 Jun 21 06:59:20 PM PDT 24 Jun 21 06:59:27 PM PDT 24 28212943 ps
T1072 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1353976601 Jun 21 06:59:12 PM PDT 24 Jun 21 06:59:17 PM PDT 24 15511336 ps
T1073 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3374815943 Jun 21 06:59:30 PM PDT 24 Jun 21 06:59:39 PM PDT 24 1167480950 ps
T254 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1747219723 Jun 21 06:59:19 PM PDT 24 Jun 21 06:59:30 PM PDT 24 100931386 ps
T1074 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2604842714 Jun 21 06:59:14 PM PDT 24 Jun 21 06:59:21 PM PDT 24 62247104 ps
T1075 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2766226320 Jun 21 06:59:20 PM PDT 24 Jun 21 06:59:30 PM PDT 24 378457844 ps
T1076 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3396629368 Jun 21 06:59:27 PM PDT 24 Jun 21 06:59:33 PM PDT 24 25500437 ps
T1077 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3868632095 Jun 21 06:59:23 PM PDT 24 Jun 21 06:59:33 PM PDT 24 815621012 ps
T1078 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3084828019 Jun 21 06:59:20 PM PDT 24 Jun 21 06:59:29 PM PDT 24 150731163 ps
T1079 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1260691098 Jun 21 06:59:20 PM PDT 24 Jun 21 06:59:29 PM PDT 24 333375101 ps
T1080 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2387023900 Jun 21 06:59:30 PM PDT 24 Jun 21 06:59:40 PM PDT 24 159349438 ps

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.19919458
Short name T2
Test name
Test status
Simulation time 16052953693 ps
CPU time 160.87 seconds
Started Jun 21 07:01:39 PM PDT 24
Finished Jun 21 07:04:28 PM PDT 24
Peak memory 250436 kb
Host smart-ba1150de-c2b2-4846-bb4a-e59347ea14d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19919458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.19919458
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2463275356
Short name T18
Test name
Test status
Simulation time 38910946679 ps
CPU time 129.21 seconds
Started Jun 21 07:02:08 PM PDT 24
Finished Jun 21 07:04:21 PM PDT 24
Peak memory 249468 kb
Host smart-5048916d-55d4-4bde-8184-be58f1ed97d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463275356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2463275356
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1017217628
Short name T19
Test name
Test status
Simulation time 1472738190944 ps
CPU time 782.47 seconds
Started Jun 21 06:59:43 PM PDT 24
Finished Jun 21 07:12:50 PM PDT 24
Peak memory 282136 kb
Host smart-ded17cce-3b78-467d-a7d0-0f8376108da3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017217628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1017217628
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2900369653
Short name T58
Test name
Test status
Simulation time 935134181 ps
CPU time 20.4 seconds
Started Jun 21 06:59:20 PM PDT 24
Finished Jun 21 06:59:46 PM PDT 24
Peak memory 216304 kb
Host smart-23a888ab-1c96-4de9-a122-617e1730ff4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900369653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2900369653
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1212807729
Short name T60
Test name
Test status
Simulation time 19109175 ps
CPU time 0.76 seconds
Started Jun 21 06:59:45 PM PDT 24
Finished Jun 21 06:59:50 PM PDT 24
Peak memory 216168 kb
Host smart-1827a8c9-6fb1-49a3-bf4c-6c5e4c340f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212807729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1212807729
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3799639060
Short name T20
Test name
Test status
Simulation time 657320041753 ps
CPU time 801.21 seconds
Started Jun 21 07:00:13 PM PDT 24
Finished Jun 21 07:13:41 PM PDT 24
Peak memory 266016 kb
Host smart-bbfa1f00-58c6-4769-ab54-a84324cd223f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799639060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3799639060
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.620036178
Short name T32
Test name
Test status
Simulation time 12378335993 ps
CPU time 196.03 seconds
Started Jun 21 07:02:12 PM PDT 24
Finished Jun 21 07:05:33 PM PDT 24
Peak memory 265796 kb
Host smart-c1715ab7-f999-40d9-83bf-249a1a57584c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620036178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.620036178
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.984882528
Short name T17
Test name
Test status
Simulation time 4324688039 ps
CPU time 96.02 seconds
Started Jun 21 07:00:27 PM PDT 24
Finished Jun 21 07:02:14 PM PDT 24
Peak memory 256852 kb
Host smart-4733b516-7a10-450a-b0f7-e2e5b7d9607d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984882528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.984882528
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3415633114
Short name T87
Test name
Test status
Simulation time 499379292 ps
CPU time 3.33 seconds
Started Jun 21 06:59:20 PM PDT 24
Finished Jun 21 06:59:29 PM PDT 24
Peak memory 216144 kb
Host smart-75bc6a46-8a72-4ba0-b5c3-2f892c660b18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415633114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3415633114
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.979283193
Short name T148
Test name
Test status
Simulation time 147563324706 ps
CPU time 596.64 seconds
Started Jun 21 07:02:26 PM PDT 24
Finished Jun 21 07:12:28 PM PDT 24
Peak memory 268584 kb
Host smart-61647f44-e29c-4be0-9771-2df671f13cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979283193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.979283193
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2754194843
Short name T155
Test name
Test status
Simulation time 902528878182 ps
CPU time 363.46 seconds
Started Jun 21 07:00:21 PM PDT 24
Finished Jun 21 07:06:33 PM PDT 24
Peak memory 272924 kb
Host smart-cf77e051-5abf-47d6-8c05-178502c870f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754194843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2754194843
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2301678164
Short name T25
Test name
Test status
Simulation time 64176504 ps
CPU time 1.14 seconds
Started Jun 21 06:59:44 PM PDT 24
Finished Jun 21 06:59:50 PM PDT 24
Peak memory 235116 kb
Host smart-13964dd5-27e3-4a7a-aa59-3a7573844fdf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301678164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2301678164
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1051437154
Short name T128
Test name
Test status
Simulation time 3375021845 ps
CPU time 22.67 seconds
Started Jun 21 07:01:22 PM PDT 24
Finished Jun 21 07:01:48 PM PDT 24
Peak memory 233000 kb
Host smart-77f63909-7170-4889-b54b-1c61ac18ad89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051437154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1051437154
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.716281831
Short name T189
Test name
Test status
Simulation time 61569013337 ps
CPU time 590.45 seconds
Started Jun 21 07:00:02 PM PDT 24
Finished Jun 21 07:09:57 PM PDT 24
Peak memory 269868 kb
Host smart-7496462f-1f20-4252-b1e4-02b57752d56d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716281831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.716281831
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.199509000
Short name T101
Test name
Test status
Simulation time 10617165433 ps
CPU time 27.57 seconds
Started Jun 21 06:59:13 PM PDT 24
Finished Jun 21 06:59:45 PM PDT 24
Peak memory 207792 kb
Host smart-932b4199-b24d-4b99-9d8f-a44cdffce60f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199509000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.199509000
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.4234161411
Short name T36
Test name
Test status
Simulation time 6671836097 ps
CPU time 118.02 seconds
Started Jun 21 07:00:40 PM PDT 24
Finished Jun 21 07:02:46 PM PDT 24
Peak memory 273508 kb
Host smart-61d9b8a2-d2e1-4603-8f9f-f06e655c0f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234161411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.4234161411
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3995952184
Short name T195
Test name
Test status
Simulation time 37749639738 ps
CPU time 314.29 seconds
Started Jun 21 07:00:11 PM PDT 24
Finished Jun 21 07:05:32 PM PDT 24
Peak memory 283040 kb
Host smart-0f5f71a9-1cec-45a8-9258-688b7041145b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995952184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3995952184
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3248404828
Short name T31
Test name
Test status
Simulation time 71018336206 ps
CPU time 284.9 seconds
Started Jun 21 07:01:10 PM PDT 24
Finished Jun 21 07:05:58 PM PDT 24
Peak memory 271952 kb
Host smart-f822cb29-7453-4407-96a8-0fb8fc2d73c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248404828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3248404828
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.404066871
Short name T180
Test name
Test status
Simulation time 32342470545 ps
CPU time 351.97 seconds
Started Jun 21 07:01:09 PM PDT 24
Finished Jun 21 07:07:03 PM PDT 24
Peak memory 257624 kb
Host smart-54b713c3-31c6-48e6-ba94-8084b4b7e95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404066871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.404066871
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1968421034
Short name T234
Test name
Test status
Simulation time 43732266290 ps
CPU time 324.17 seconds
Started Jun 21 07:01:10 PM PDT 24
Finished Jun 21 07:06:37 PM PDT 24
Peak memory 252140 kb
Host smart-02a5005f-b5bc-4e60-a991-5d63f4347b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968421034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1968421034
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.509182361
Short name T13
Test name
Test status
Simulation time 160430642358 ps
CPU time 305.34 seconds
Started Jun 21 07:00:01 PM PDT 24
Finished Jun 21 07:05:10 PM PDT 24
Peak memory 266672 kb
Host smart-2f4a0b57-1ac7-4397-ae5c-caa074949df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509182361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
509182361
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.493897400
Short name T47
Test name
Test status
Simulation time 141349805205 ps
CPU time 328.59 seconds
Started Jun 21 07:00:06 PM PDT 24
Finished Jun 21 07:05:40 PM PDT 24
Peak memory 263924 kb
Host smart-0243ec61-c804-4b7c-82cc-d0166b759034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493897400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.493897400
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1500433838
Short name T145
Test name
Test status
Simulation time 110904151880 ps
CPU time 258.87 seconds
Started Jun 21 07:01:21 PM PDT 24
Finished Jun 21 07:05:43 PM PDT 24
Peak memory 250472 kb
Host smart-18f9b475-ce08-469b-b495-af8117fa978a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500433838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1500433838
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2495253092
Short name T353
Test name
Test status
Simulation time 39360189 ps
CPU time 0.71 seconds
Started Jun 21 06:59:41 PM PDT 24
Finished Jun 21 06:59:46 PM PDT 24
Peak memory 205508 kb
Host smart-36976593-4c9b-4164-abfe-440b6d09796d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495253092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
495253092
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2429416361
Short name T213
Test name
Test status
Simulation time 13585117499 ps
CPU time 167.98 seconds
Started Jun 21 07:01:21 PM PDT 24
Finished Jun 21 07:04:12 PM PDT 24
Peak memory 251400 kb
Host smart-91ef6309-592e-449d-aaaf-bddef8faab9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429416361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2429416361
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4115506716
Short name T248
Test name
Test status
Simulation time 297374346 ps
CPU time 18.13 seconds
Started Jun 21 06:59:10 PM PDT 24
Finished Jun 21 06:59:32 PM PDT 24
Peak memory 215980 kb
Host smart-58cc36a9-b8ce-446f-85ba-d32df8a6fadb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115506716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.4115506716
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1761602394
Short name T14
Test name
Test status
Simulation time 2005554461 ps
CPU time 47.03 seconds
Started Jun 21 07:01:46 PM PDT 24
Finished Jun 21 07:02:42 PM PDT 24
Peak memory 253592 kb
Host smart-bf7d514d-6e67-4651-8406-6e94eb4d72fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761602394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1761602394
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1357392105
Short name T211
Test name
Test status
Simulation time 5142457503 ps
CPU time 108.97 seconds
Started Jun 21 07:02:14 PM PDT 24
Finished Jun 21 07:04:07 PM PDT 24
Peak memory 257004 kb
Host smart-aa0880ab-c832-48a5-b20f-16426d05c19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357392105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1357392105
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1227640986
Short name T5
Test name
Test status
Simulation time 139537431 ps
CPU time 4.26 seconds
Started Jun 21 07:02:10 PM PDT 24
Finished Jun 21 07:02:19 PM PDT 24
Peak memory 224696 kb
Host smart-2a1467fb-a68f-42ab-9277-b6de049d83a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227640986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1227640986
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1353170538
Short name T313
Test name
Test status
Simulation time 1649707909 ps
CPU time 19.62 seconds
Started Jun 21 07:00:59 PM PDT 24
Finished Jun 21 07:01:24 PM PDT 24
Peak memory 249220 kb
Host smart-ae6bda7f-dc8f-4955-8bee-926de72af267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353170538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1353170538
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.368730650
Short name T212
Test name
Test status
Simulation time 435986099017 ps
CPU time 456.2 seconds
Started Jun 21 07:02:19 PM PDT 24
Finished Jun 21 07:09:58 PM PDT 24
Peak memory 265692 kb
Host smart-c3b9570f-0c0b-474c-88bc-f454fed998c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368730650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.368730650
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2517474871
Short name T207
Test name
Test status
Simulation time 14542331329 ps
CPU time 106.56 seconds
Started Jun 21 07:02:22 PM PDT 24
Finished Jun 21 07:04:13 PM PDT 24
Peak memory 269764 kb
Host smart-cd4214f1-4618-4ac4-bbce-a4630f211a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517474871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2517474871
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2412667069
Short name T89
Test name
Test status
Simulation time 160699742 ps
CPU time 3.68 seconds
Started Jun 21 06:59:23 PM PDT 24
Finished Jun 21 06:59:32 PM PDT 24
Peak memory 216192 kb
Host smart-b8c0a91d-7bcb-4775-82cf-f5c310808869
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412667069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2412667069
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1631164486
Short name T158
Test name
Test status
Simulation time 17690825055 ps
CPU time 80.68 seconds
Started Jun 21 07:00:42 PM PDT 24
Finished Jun 21 07:02:10 PM PDT 24
Peak memory 257512 kb
Host smart-5d97e49b-d91d-4cb0-b219-8bf0208c5b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631164486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1631164486
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1535140186
Short name T216
Test name
Test status
Simulation time 51607019378 ps
CPU time 378.82 seconds
Started Jun 21 07:01:44 PM PDT 24
Finished Jun 21 07:08:11 PM PDT 24
Peak memory 264040 kb
Host smart-f5d4b07b-c28d-40a6-bc87-f30fd000ee50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535140186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1535140186
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.803465469
Short name T811
Test name
Test status
Simulation time 868190870 ps
CPU time 7.08 seconds
Started Jun 21 07:02:19 PM PDT 24
Finished Jun 21 07:02:30 PM PDT 24
Peak memory 232900 kb
Host smart-84f4bd7e-7cec-463e-ac47-aff0be4bcc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803465469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.803465469
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3004958149
Short name T1022
Test name
Test status
Simulation time 196174198 ps
CPU time 12.47 seconds
Started Jun 21 06:59:02 PM PDT 24
Finished Jun 21 06:59:20 PM PDT 24
Peak memory 215988 kb
Host smart-93768ffd-5d1f-4c43-a06f-359206788ee4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004958149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3004958149
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1743541016
Short name T253
Test name
Test status
Simulation time 1295855190 ps
CPU time 7.7 seconds
Started Jun 21 06:59:20 PM PDT 24
Finished Jun 21 06:59:34 PM PDT 24
Peak memory 215928 kb
Host smart-16f4fbf6-c312-4ef1-b08f-b64f9ed906b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743541016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1743541016
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3017356637
Short name T250
Test name
Test status
Simulation time 866037962 ps
CPU time 20.73 seconds
Started Jun 21 06:59:10 PM PDT 24
Finished Jun 21 06:59:33 PM PDT 24
Peak memory 215920 kb
Host smart-68ef14cb-42f8-4275-9760-89bc8f0dffbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017356637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3017356637
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.4232296417
Short name T142
Test name
Test status
Simulation time 3077088961 ps
CPU time 70.86 seconds
Started Jun 21 07:00:22 PM PDT 24
Finished Jun 21 07:01:42 PM PDT 24
Peak memory 253656 kb
Host smart-8443b1ab-77ac-4f13-9ad1-c8688b96006b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232296417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.4232296417
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2560069992
Short name T196
Test name
Test status
Simulation time 22669060685 ps
CPU time 99.09 seconds
Started Jun 21 07:00:22 PM PDT 24
Finished Jun 21 07:02:10 PM PDT 24
Peak memory 265768 kb
Host smart-a47a011e-ad93-48b9-8970-60a1d72e0656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560069992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2560069992
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.630888871
Short name T227
Test name
Test status
Simulation time 172866433305 ps
CPU time 814.12 seconds
Started Jun 21 07:00:23 PM PDT 24
Finished Jun 21 07:14:06 PM PDT 24
Peak memory 255084 kb
Host smart-18ec00ab-5393-4fc5-8ec8-829a3f8efd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630888871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.630888871
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_upload.543161280
Short name T945
Test name
Test status
Simulation time 17546368256 ps
CPU time 25.21 seconds
Started Jun 21 07:00:23 PM PDT 24
Finished Jun 21 07:00:58 PM PDT 24
Peak memory 224744 kb
Host smart-e9e5ddbf-4fa5-4a37-8984-ce7feecd6cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543161280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.543161280
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3006753484
Short name T334
Test name
Test status
Simulation time 3708350728 ps
CPU time 83.5 seconds
Started Jun 21 07:00:40 PM PDT 24
Finished Jun 21 07:02:12 PM PDT 24
Peak memory 256032 kb
Host smart-bf9c5c16-37bb-4214-a27a-20aa3bfc2e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006753484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3006753484
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.121879561
Short name T261
Test name
Test status
Simulation time 198732110 ps
CPU time 2.57 seconds
Started Jun 21 07:01:13 PM PDT 24
Finished Jun 21 07:01:18 PM PDT 24
Peak memory 232880 kb
Host smart-5873689c-28d1-4134-b149-33d132e484ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121879561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.121879561
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.309245004
Short name T30
Test name
Test status
Simulation time 1360438889 ps
CPU time 8.83 seconds
Started Jun 21 07:00:19 PM PDT 24
Finished Jun 21 07:00:36 PM PDT 24
Peak memory 249220 kb
Host smart-2ffa7504-04d3-4dc8-9489-e179b74c3641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309245004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.309245004
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2271057275
Short name T79
Test name
Test status
Simulation time 21597932 ps
CPU time 1 seconds
Started Jun 21 06:59:11 PM PDT 24
Finished Jun 21 06:59:16 PM PDT 24
Peak memory 207408 kb
Host smart-0749f659-9ef6-4daa-a323-feb9bace4bd6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271057275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2271057275
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.600345221
Short name T1047
Test name
Test status
Simulation time 75122127 ps
CPU time 4.91 seconds
Started Jun 21 06:59:09 PM PDT 24
Finished Jun 21 06:59:17 PM PDT 24
Peak memory 216096 kb
Host smart-f73b9b20-e7fa-49d8-9d53-cb05c84c36d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600345221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.600345221
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2842968414
Short name T1026
Test name
Test status
Simulation time 1112471717 ps
CPU time 23.05 seconds
Started Jun 21 06:59:14 PM PDT 24
Finished Jun 21 06:59:41 PM PDT 24
Peak memory 215928 kb
Host smart-8ccdb969-2f41-4948-9001-dfb182abd5c1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842968414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2842968414
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2259102277
Short name T1005
Test name
Test status
Simulation time 82456888 ps
CPU time 1.75 seconds
Started Jun 21 06:59:07 PM PDT 24
Finished Jun 21 06:59:12 PM PDT 24
Peak memory 217028 kb
Host smart-adfa1492-6883-49c9-ae5b-77d1f12ed608
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259102277 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2259102277
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2786174374
Short name T999
Test name
Test status
Simulation time 53070344 ps
CPU time 1.96 seconds
Started Jun 21 06:59:13 PM PDT 24
Finished Jun 21 06:59:20 PM PDT 24
Peak memory 215996 kb
Host smart-12921aef-601b-4e21-8363-f2f26647e701
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786174374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
786174374
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.473804989
Short name T1014
Test name
Test status
Simulation time 12221695 ps
CPU time 0.77 seconds
Started Jun 21 06:59:02 PM PDT 24
Finished Jun 21 06:59:08 PM PDT 24
Peak memory 204660 kb
Host smart-3dfce32e-262b-48d8-90ab-ff5957728b31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473804989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.473804989
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.424818090
Short name T106
Test name
Test status
Simulation time 397518822 ps
CPU time 1.34 seconds
Started Jun 21 06:59:10 PM PDT 24
Finished Jun 21 06:59:15 PM PDT 24
Peak memory 215896 kb
Host smart-51f260fe-d282-4b78-a52b-f466810edaac
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424818090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.424818090
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.151148998
Short name T1048
Test name
Test status
Simulation time 141572245 ps
CPU time 0.69 seconds
Started Jun 21 06:59:02 PM PDT 24
Finished Jun 21 06:59:08 PM PDT 24
Peak memory 204268 kb
Host smart-80aa7903-28be-4d46-9a04-c84da27ac3bf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151148998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.151148998
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3263342200
Short name T1001
Test name
Test status
Simulation time 126713788 ps
CPU time 3.92 seconds
Started Jun 21 06:59:09 PM PDT 24
Finished Jun 21 06:59:16 PM PDT 24
Peak memory 215940 kb
Host smart-65b98a36-0b6c-4fa9-97d1-f70229fb0313
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263342200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3263342200
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1228889142
Short name T1016
Test name
Test status
Simulation time 120627750 ps
CPU time 1.95 seconds
Started Jun 21 06:59:01 PM PDT 24
Finished Jun 21 06:59:07 PM PDT 24
Peak memory 216240 kb
Host smart-d8c96457-4b34-41d8-988a-56609fc2be69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228889142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
228889142
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.506779363
Short name T108
Test name
Test status
Simulation time 1603118276 ps
CPU time 8.88 seconds
Started Jun 21 06:59:11 PM PDT 24
Finished Jun 21 06:59:24 PM PDT 24
Peak memory 207716 kb
Host smart-3ccaca3c-36e8-419a-8375-0cf80810937c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506779363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.506779363
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.549947272
Short name T987
Test name
Test status
Simulation time 1461630820 ps
CPU time 22.63 seconds
Started Jun 21 06:59:11 PM PDT 24
Finished Jun 21 06:59:38 PM PDT 24
Peak memory 207680 kb
Host smart-f3de9afe-aef1-4253-ade0-4b6e0616170f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549947272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.549947272
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3315822231
Short name T1052
Test name
Test status
Simulation time 190796634 ps
CPU time 0.91 seconds
Started Jun 21 06:59:15 PM PDT 24
Finished Jun 21 06:59:21 PM PDT 24
Peak memory 207500 kb
Host smart-a7cbc9f7-3a54-4937-8ad8-533925845d44
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315822231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3315822231
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2579233777
Short name T1066
Test name
Test status
Simulation time 158107494 ps
CPU time 3.75 seconds
Started Jun 21 06:59:15 PM PDT 24
Finished Jun 21 06:59:23 PM PDT 24
Peak memory 217812 kb
Host smart-c43c2ed4-c425-41e4-9bab-2f497a253427
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579233777 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2579233777
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.564651757
Short name T1003
Test name
Test status
Simulation time 139276862 ps
CPU time 1.29 seconds
Started Jun 21 06:59:11 PM PDT 24
Finished Jun 21 06:59:16 PM PDT 24
Peak memory 207768 kb
Host smart-99e08bb5-5ed9-4d2d-bc21-fadb2ae58c7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564651757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.564651757
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2072863550
Short name T1028
Test name
Test status
Simulation time 20715281 ps
CPU time 0.72 seconds
Started Jun 21 06:59:13 PM PDT 24
Finished Jun 21 06:59:18 PM PDT 24
Peak memory 204360 kb
Host smart-697acfc5-5d1e-40a8-9169-de9a409007f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072863550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
072863550
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3799676265
Short name T1041
Test name
Test status
Simulation time 67758660 ps
CPU time 1.45 seconds
Started Jun 21 06:59:13 PM PDT 24
Finished Jun 21 06:59:18 PM PDT 24
Peak memory 215960 kb
Host smart-8c715812-7d1d-4540-a6c0-045a0c81876f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799676265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3799676265
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4071792917
Short name T1062
Test name
Test status
Simulation time 110824046 ps
CPU time 0.64 seconds
Started Jun 21 06:59:07 PM PDT 24
Finished Jun 21 06:59:11 PM PDT 24
Peak memory 204228 kb
Host smart-cee1ff23-8328-4ce5-8d9a-32971cba8a96
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071792917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.4071792917
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1222613329
Short name T1023
Test name
Test status
Simulation time 27508596 ps
CPU time 1.68 seconds
Started Jun 21 06:59:09 PM PDT 24
Finished Jun 21 06:59:14 PM PDT 24
Peak memory 215904 kb
Host smart-a8a85f01-c2bd-4380-bfab-c00da56356cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222613329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1222613329
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3323059778
Short name T85
Test name
Test status
Simulation time 2982532904 ps
CPU time 7.95 seconds
Started Jun 21 06:59:14 PM PDT 24
Finished Jun 21 06:59:27 PM PDT 24
Peak memory 215936 kb
Host smart-7a89e335-3e21-4935-9fa4-2973c7ea5f87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323059778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3323059778
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3958766949
Short name T84
Test name
Test status
Simulation time 202733357 ps
CPU time 1.78 seconds
Started Jun 21 06:59:20 PM PDT 24
Finished Jun 21 06:59:28 PM PDT 24
Peak memory 216068 kb
Host smart-e004e07b-dbcf-43d4-a52c-a97c278e931a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958766949 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3958766949
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1964658177
Short name T972
Test name
Test status
Simulation time 33913124 ps
CPU time 1.18 seconds
Started Jun 21 06:59:30 PM PDT 24
Finished Jun 21 06:59:37 PM PDT 24
Peak memory 207748 kb
Host smart-ee02fd23-ac00-44a6-8d7b-30b68f556e41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964658177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1964658177
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2161942556
Short name T1059
Test name
Test status
Simulation time 50372527 ps
CPU time 0.76 seconds
Started Jun 21 06:59:31 PM PDT 24
Finished Jun 21 06:59:38 PM PDT 24
Peak memory 203692 kb
Host smart-53a629ea-48e2-44c4-9f0a-459dc4cfaeb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161942556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2161942556
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3264781205
Short name T136
Test name
Test status
Simulation time 1144331353 ps
CPU time 4.26 seconds
Started Jun 21 06:59:30 PM PDT 24
Finished Jun 21 06:59:40 PM PDT 24
Peak memory 215892 kb
Host smart-6f2c5f38-df22-4231-b35a-718098d9da9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264781205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3264781205
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3960394028
Short name T59
Test name
Test status
Simulation time 163209529 ps
CPU time 4.11 seconds
Started Jun 21 06:59:21 PM PDT 24
Finished Jun 21 06:59:30 PM PDT 24
Peak memory 216080 kb
Host smart-9b91f7bc-2357-4857-8628-0ddadf5a6b4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960394028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3960394028
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.491338879
Short name T974
Test name
Test status
Simulation time 102582073 ps
CPU time 1.85 seconds
Started Jun 21 06:59:20 PM PDT 24
Finished Jun 21 06:59:28 PM PDT 24
Peak memory 216952 kb
Host smart-6ed8e9c1-985c-4c3e-accc-c903cd1414d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491338879 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.491338879
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2593819746
Short name T1017
Test name
Test status
Simulation time 23609180 ps
CPU time 1.4 seconds
Started Jun 21 06:59:31 PM PDT 24
Finished Jun 21 06:59:38 PM PDT 24
Peak memory 215780 kb
Host smart-168d0fe6-5b2e-47a4-8705-d925cabb8437
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593819746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2593819746
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1540976422
Short name T1027
Test name
Test status
Simulation time 112351515 ps
CPU time 0.76 seconds
Started Jun 21 06:59:21 PM PDT 24
Finished Jun 21 06:59:27 PM PDT 24
Peak memory 204360 kb
Host smart-c9beebc5-a73c-482c-ad3f-44cee323e8e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540976422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1540976422
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2387023900
Short name T1080
Test name
Test status
Simulation time 159349438 ps
CPU time 4.13 seconds
Started Jun 21 06:59:30 PM PDT 24
Finished Jun 21 06:59:40 PM PDT 24
Peak memory 215960 kb
Host smart-9bd34a52-b5e5-492b-bb04-cde6c335ce3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387023900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2387023900
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2541876890
Short name T973
Test name
Test status
Simulation time 133946095 ps
CPU time 2.13 seconds
Started Jun 21 06:59:21 PM PDT 24
Finished Jun 21 06:59:29 PM PDT 24
Peak memory 219572 kb
Host smart-35e4e9a0-24c3-42c6-9789-2378efa501c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541876890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2541876890
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.746638832
Short name T88
Test name
Test status
Simulation time 59220412 ps
CPU time 1.89 seconds
Started Jun 21 06:59:23 PM PDT 24
Finished Jun 21 06:59:31 PM PDT 24
Peak memory 216028 kb
Host smart-7cf05e12-2954-4607-a6bf-34d2b9c76e63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746638832 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.746638832
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3294671074
Short name T107
Test name
Test status
Simulation time 18782723 ps
CPU time 1.13 seconds
Started Jun 21 06:59:21 PM PDT 24
Finished Jun 21 06:59:28 PM PDT 24
Peak memory 207752 kb
Host smart-6b5c4bbb-1abd-4d65-86fc-fe3089f4a591
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294671074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3294671074
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1500405498
Short name T1004
Test name
Test status
Simulation time 125626690 ps
CPU time 0.76 seconds
Started Jun 21 06:59:19 PM PDT 24
Finished Jun 21 06:59:25 PM PDT 24
Peak memory 204352 kb
Host smart-beb8fbf7-f8df-4d0b-97c6-c083b6b792b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500405498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1500405498
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3374815943
Short name T1073
Test name
Test status
Simulation time 1167480950 ps
CPU time 3.25 seconds
Started Jun 21 06:59:30 PM PDT 24
Finished Jun 21 06:59:39 PM PDT 24
Peak memory 215908 kb
Host smart-618ce113-417f-4c14-9913-add6ef54d815
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374815943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3374815943
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3948217924
Short name T94
Test name
Test status
Simulation time 362280976 ps
CPU time 6.24 seconds
Started Jun 21 06:59:20 PM PDT 24
Finished Jun 21 06:59:32 PM PDT 24
Peak memory 217708 kb
Host smart-7dc700b0-549d-4132-b272-8b2b91c1dda5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948217924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3948217924
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.790608314
Short name T255
Test name
Test status
Simulation time 213067298 ps
CPU time 6.76 seconds
Started Jun 21 06:59:20 PM PDT 24
Finished Jun 21 06:59:32 PM PDT 24
Peak memory 215896 kb
Host smart-d065be4f-f390-4b40-8c71-8f6d35b556dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790608314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.790608314
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.568947203
Short name T1067
Test name
Test status
Simulation time 566503619 ps
CPU time 3.69 seconds
Started Jun 21 06:59:19 PM PDT 24
Finished Jun 21 06:59:28 PM PDT 24
Peak memory 217964 kb
Host smart-afb6927d-917e-4e40-ab1d-f055b1d1c4b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568947203 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.568947203
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2844860500
Short name T1040
Test name
Test status
Simulation time 18888583 ps
CPU time 1.28 seconds
Started Jun 21 06:59:23 PM PDT 24
Finished Jun 21 06:59:30 PM PDT 24
Peak memory 207740 kb
Host smart-869cada9-ecf2-4367-a7ce-48f1fae66414
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844860500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2844860500
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3117431250
Short name T957
Test name
Test status
Simulation time 49541003 ps
CPU time 0.73 seconds
Started Jun 21 06:59:19 PM PDT 24
Finished Jun 21 06:59:25 PM PDT 24
Peak memory 204664 kb
Host smart-24eaa928-78f7-44ba-930c-c6f3c8e11c12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117431250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3117431250
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3868632095
Short name T1077
Test name
Test status
Simulation time 815621012 ps
CPU time 4.32 seconds
Started Jun 21 06:59:23 PM PDT 24
Finished Jun 21 06:59:33 PM PDT 24
Peak memory 215932 kb
Host smart-3e2c3b08-d7ef-4917-93ad-2002958a7e42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868632095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3868632095
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.858301104
Short name T247
Test name
Test status
Simulation time 843380278 ps
CPU time 22.36 seconds
Started Jun 21 06:59:18 PM PDT 24
Finished Jun 21 06:59:45 PM PDT 24
Peak memory 216468 kb
Host smart-5a1fff98-51d0-4fdf-90a8-e5c958f7a4dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858301104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.858301104
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3620870939
Short name T992
Test name
Test status
Simulation time 173266076 ps
CPU time 2.46 seconds
Started Jun 21 06:59:18 PM PDT 24
Finished Jun 21 06:59:26 PM PDT 24
Peak memory 217328 kb
Host smart-32b2ca57-0006-4b1c-960d-6632ec7abdde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620870939 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3620870939
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1309270226
Short name T1019
Test name
Test status
Simulation time 20818044 ps
CPU time 1.19 seconds
Started Jun 21 06:59:20 PM PDT 24
Finished Jun 21 06:59:26 PM PDT 24
Peak memory 215952 kb
Host smart-3e2bf66f-ddfc-4378-8506-d442ae888f65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309270226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1309270226
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3828448146
Short name T1056
Test name
Test status
Simulation time 97656629 ps
CPU time 0.75 seconds
Started Jun 21 06:59:19 PM PDT 24
Finished Jun 21 06:59:25 PM PDT 24
Peak memory 204708 kb
Host smart-5fac5b95-2f58-4398-bf72-71e910f028df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828448146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3828448146
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2973168126
Short name T998
Test name
Test status
Simulation time 408856488 ps
CPU time 3.75 seconds
Started Jun 21 06:59:22 PM PDT 24
Finished Jun 21 06:59:32 PM PDT 24
Peak memory 215864 kb
Host smart-eca907c2-e05a-4649-bd98-6c252294a9b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973168126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2973168126
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.877030809
Short name T1046
Test name
Test status
Simulation time 414118470 ps
CPU time 4.11 seconds
Started Jun 21 06:59:22 PM PDT 24
Finished Jun 21 06:59:31 PM PDT 24
Peak memory 216204 kb
Host smart-0722647b-c2f6-48a4-88a5-da1ca9d82d8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877030809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.877030809
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1238356227
Short name T246
Test name
Test status
Simulation time 1233771167 ps
CPU time 11.18 seconds
Started Jun 21 06:59:17 PM PDT 24
Finished Jun 21 06:59:34 PM PDT 24
Peak memory 216060 kb
Host smart-a6e61577-d1a2-47a7-8cc6-dcebe8dcfb72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238356227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1238356227
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1352488680
Short name T1071
Test name
Test status
Simulation time 28212943 ps
CPU time 2.02 seconds
Started Jun 21 06:59:20 PM PDT 24
Finished Jun 21 06:59:27 PM PDT 24
Peak memory 217012 kb
Host smart-a6c5f5de-5889-44ac-85ec-3c2c6d7e44e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352488680 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1352488680
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3420077917
Short name T1029
Test name
Test status
Simulation time 73381007 ps
CPU time 1.27 seconds
Started Jun 21 06:59:19 PM PDT 24
Finished Jun 21 06:59:26 PM PDT 24
Peak memory 216052 kb
Host smart-d9001b34-1b94-4e23-a195-693947dc5e93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420077917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3420077917
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3625649226
Short name T1057
Test name
Test status
Simulation time 50072418 ps
CPU time 0.8 seconds
Started Jun 21 06:59:19 PM PDT 24
Finished Jun 21 06:59:25 PM PDT 24
Peak memory 204352 kb
Host smart-9c112e3e-7b04-4bb4-a387-fe6e2a584035
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625649226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3625649226
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3318217902
Short name T975
Test name
Test status
Simulation time 60325438 ps
CPU time 1.83 seconds
Started Jun 21 06:59:19 PM PDT 24
Finished Jun 21 06:59:26 PM PDT 24
Peak memory 207748 kb
Host smart-3b88ee99-c17f-41ef-8998-d521791b5fb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318217902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3318217902
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3047185064
Short name T1009
Test name
Test status
Simulation time 50125717 ps
CPU time 3.33 seconds
Started Jun 21 06:59:21 PM PDT 24
Finished Jun 21 06:59:30 PM PDT 24
Peak memory 216116 kb
Host smart-4f30697e-81aa-4a1b-b4bf-5bc03c518460
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047185064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3047185064
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.393212699
Short name T96
Test name
Test status
Simulation time 2221423337 ps
CPU time 13.93 seconds
Started Jun 21 06:59:19 PM PDT 24
Finished Jun 21 06:59:38 PM PDT 24
Peak memory 216344 kb
Host smart-95c151a3-4236-41e0-91fd-9e02f08024a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393212699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.393212699
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3084828019
Short name T1078
Test name
Test status
Simulation time 150731163 ps
CPU time 3.86 seconds
Started Jun 21 06:59:20 PM PDT 24
Finished Jun 21 06:59:29 PM PDT 24
Peak memory 217656 kb
Host smart-cbed8e2b-81de-47a9-b588-e9613db1a3c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084828019 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3084828019
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4199660673
Short name T104
Test name
Test status
Simulation time 91803950 ps
CPU time 2.54 seconds
Started Jun 21 06:59:19 PM PDT 24
Finished Jun 21 06:59:26 PM PDT 24
Peak memory 216008 kb
Host smart-d63b5f8f-a78e-4bc0-8db3-693a211eafda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199660673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
4199660673
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3879328720
Short name T988
Test name
Test status
Simulation time 18381310 ps
CPU time 0.79 seconds
Started Jun 21 06:59:22 PM PDT 24
Finished Jun 21 06:59:28 PM PDT 24
Peak memory 204344 kb
Host smart-d3a5d10f-150a-4a6b-bec1-2eef763a0491
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879328720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3879328720
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3832150191
Short name T137
Test name
Test status
Simulation time 691323608 ps
CPU time 4.12 seconds
Started Jun 21 06:59:31 PM PDT 24
Finished Jun 21 06:59:41 PM PDT 24
Peak memory 215272 kb
Host smart-78acdfae-1c2f-4245-b978-196924e6e002
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832150191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3832150191
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3801307777
Short name T92
Test name
Test status
Simulation time 178694088 ps
CPU time 4.11 seconds
Started Jun 21 06:59:20 PM PDT 24
Finished Jun 21 06:59:29 PM PDT 24
Peak memory 216068 kb
Host smart-4a19531e-509c-460f-b316-858e45d5a0c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801307777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3801307777
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.578979766
Short name T1000
Test name
Test status
Simulation time 202784566 ps
CPU time 12.63 seconds
Started Jun 21 06:59:31 PM PDT 24
Finished Jun 21 06:59:49 PM PDT 24
Peak memory 215964 kb
Host smart-762c2579-5068-4205-a224-b014c64946e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578979766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.578979766
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2928573511
Short name T57
Test name
Test status
Simulation time 179254870 ps
CPU time 1.94 seconds
Started Jun 21 06:59:30 PM PDT 24
Finished Jun 21 06:59:38 PM PDT 24
Peak memory 217076 kb
Host smart-37e7b816-faa9-4e39-bcaf-92664b85d5b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928573511 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2928573511
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3745252510
Short name T1068
Test name
Test status
Simulation time 245526848 ps
CPU time 1.24 seconds
Started Jun 21 06:59:18 PM PDT 24
Finished Jun 21 06:59:24 PM PDT 24
Peak memory 207764 kb
Host smart-18c27baa-d91c-4db2-bfad-d7db9c51c1ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745252510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3745252510
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3886803754
Short name T1024
Test name
Test status
Simulation time 12513526 ps
CPU time 0.79 seconds
Started Jun 21 06:59:23 PM PDT 24
Finished Jun 21 06:59:29 PM PDT 24
Peak memory 204664 kb
Host smart-af9b8f38-a8fe-4ba7-bc52-bc7c8415133b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886803754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3886803754
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2851419345
Short name T997
Test name
Test status
Simulation time 59706808 ps
CPU time 1.86 seconds
Started Jun 21 06:59:19 PM PDT 24
Finished Jun 21 06:59:25 PM PDT 24
Peak memory 215928 kb
Host smart-6ed420a3-1fd4-470a-8ae0-bc92814bb888
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851419345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2851419345
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2499612370
Short name T982
Test name
Test status
Simulation time 404360960 ps
CPU time 6.29 seconds
Started Jun 21 06:59:20 PM PDT 24
Finished Jun 21 06:59:32 PM PDT 24
Peak memory 216096 kb
Host smart-995e0066-cddb-4517-b8d4-ec0f0f8af5a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499612370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2499612370
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1555751762
Short name T1034
Test name
Test status
Simulation time 55601041 ps
CPU time 3.38 seconds
Started Jun 21 06:59:31 PM PDT 24
Finished Jun 21 06:59:40 PM PDT 24
Peak memory 217700 kb
Host smart-3e717751-6090-4819-b04e-3d286fba016b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555751762 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1555751762
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3137359016
Short name T98
Test name
Test status
Simulation time 42022137 ps
CPU time 1.33 seconds
Started Jun 21 06:59:30 PM PDT 24
Finished Jun 21 06:59:38 PM PDT 24
Peak memory 207780 kb
Host smart-6ff91cda-fd6d-4c22-9f86-bd867099beef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137359016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3137359016
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.399660192
Short name T986
Test name
Test status
Simulation time 63646173 ps
CPU time 0.76 seconds
Started Jun 21 06:59:28 PM PDT 24
Finished Jun 21 06:59:34 PM PDT 24
Peak memory 204036 kb
Host smart-c0026f63-8c90-4c15-9b65-eaa624f2998e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399660192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.399660192
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1371747444
Short name T994
Test name
Test status
Simulation time 578891384 ps
CPU time 3.75 seconds
Started Jun 21 06:59:29 PM PDT 24
Finished Jun 21 06:59:39 PM PDT 24
Peak memory 215908 kb
Host smart-b23d81fb-7129-4a61-9bc2-c6ed2f28d5c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371747444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1371747444
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2544524347
Short name T991
Test name
Test status
Simulation time 3116680912 ps
CPU time 4.54 seconds
Started Jun 21 06:59:31 PM PDT 24
Finished Jun 21 06:59:41 PM PDT 24
Peak memory 216168 kb
Host smart-1df61d49-f8db-45b2-862d-52b977db12c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544524347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2544524347
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.311552208
Short name T1050
Test name
Test status
Simulation time 2119018148 ps
CPU time 13.19 seconds
Started Jun 21 06:59:32 PM PDT 24
Finished Jun 21 06:59:51 PM PDT 24
Peak memory 216560 kb
Host smart-6ae7dc8f-8f6f-492d-9e8a-bd56f092fda3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311552208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.311552208
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3231805334
Short name T95
Test name
Test status
Simulation time 59367767 ps
CPU time 1.75 seconds
Started Jun 21 06:59:30 PM PDT 24
Finished Jun 21 06:59:37 PM PDT 24
Peak memory 217008 kb
Host smart-5baa722c-cab7-4bac-8f96-1160b31e6b97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231805334 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3231805334
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.440128999
Short name T1021
Test name
Test status
Simulation time 793087818 ps
CPU time 1.88 seconds
Started Jun 21 06:59:32 PM PDT 24
Finished Jun 21 06:59:39 PM PDT 24
Peak memory 207804 kb
Host smart-d902051c-dc87-4c0f-99d3-bd056fc55caf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440128999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.440128999
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1194535084
Short name T968
Test name
Test status
Simulation time 35055950 ps
CPU time 0.71 seconds
Started Jun 21 06:59:29 PM PDT 24
Finished Jun 21 06:59:36 PM PDT 24
Peak memory 204344 kb
Host smart-19c86587-3e4f-4f29-a827-9d4d2e257a27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194535084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1194535084
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2406549389
Short name T989
Test name
Test status
Simulation time 151018225 ps
CPU time 3.93 seconds
Started Jun 21 06:59:29 PM PDT 24
Finished Jun 21 06:59:39 PM PDT 24
Peak memory 215956 kb
Host smart-c883fc2e-a109-4e52-bb62-9d861b610fb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406549389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2406549389
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.843118550
Short name T1038
Test name
Test status
Simulation time 155380575 ps
CPU time 4.34 seconds
Started Jun 21 06:59:32 PM PDT 24
Finished Jun 21 06:59:42 PM PDT 24
Peak memory 217124 kb
Host smart-0d7d3b7c-4d7c-4877-817a-b39d6babbdf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843118550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.843118550
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1903512460
Short name T249
Test name
Test status
Simulation time 1033992120 ps
CPU time 8.13 seconds
Started Jun 21 06:59:31 PM PDT 24
Finished Jun 21 06:59:45 PM PDT 24
Peak memory 217160 kb
Host smart-c8d73432-1669-462f-afe1-dacc8e337d55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903512460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1903512460
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2853342221
Short name T962
Test name
Test status
Simulation time 318488391 ps
CPU time 20.69 seconds
Started Jun 21 06:59:11 PM PDT 24
Finished Jun 21 06:59:35 PM PDT 24
Peak memory 215964 kb
Host smart-d11e9b97-40f6-4629-a60c-dd4abb83990e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853342221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2853342221
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3037206733
Short name T956
Test name
Test status
Simulation time 20138480608 ps
CPU time 22.99 seconds
Started Jun 21 06:59:16 PM PDT 24
Finished Jun 21 06:59:44 PM PDT 24
Peak memory 207852 kb
Host smart-2a9ee79a-ee0e-4440-8c6b-f7df27663d82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037206733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3037206733
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.612557739
Short name T76
Test name
Test status
Simulation time 20637152 ps
CPU time 1.13 seconds
Started Jun 21 06:59:11 PM PDT 24
Finished Jun 21 06:59:17 PM PDT 24
Peak memory 207696 kb
Host smart-05f52144-3238-41a5-822a-8de1b4472d68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612557739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.612557739
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2642510215
Short name T1011
Test name
Test status
Simulation time 114135023 ps
CPU time 3.76 seconds
Started Jun 21 06:59:14 PM PDT 24
Finished Jun 21 06:59:23 PM PDT 24
Peak memory 217852 kb
Host smart-10fe9c3f-4dc1-48b9-9dc0-b5c6cc01f474
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642510215 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2642510215
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.294704675
Short name T1060
Test name
Test status
Simulation time 106156119 ps
CPU time 1.86 seconds
Started Jun 21 06:59:09 PM PDT 24
Finished Jun 21 06:59:14 PM PDT 24
Peak memory 215932 kb
Host smart-d176c8de-54c2-4875-8be3-d7eb3f96b5a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294704675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.294704675
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.161639648
Short name T976
Test name
Test status
Simulation time 22059066 ps
CPU time 0.74 seconds
Started Jun 21 06:59:14 PM PDT 24
Finished Jun 21 06:59:20 PM PDT 24
Peak memory 204664 kb
Host smart-4fb95bcd-f62d-49fd-9b4f-5c7e63f105ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161639648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.161639648
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2012417840
Short name T102
Test name
Test status
Simulation time 220198898 ps
CPU time 1.97 seconds
Started Jun 21 06:59:10 PM PDT 24
Finished Jun 21 06:59:15 PM PDT 24
Peak memory 215932 kb
Host smart-7de54e26-7ed9-4251-bbeb-b4f6818cb24d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012417840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2012417840
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3652503001
Short name T1039
Test name
Test status
Simulation time 10982204 ps
CPU time 0.64 seconds
Started Jun 21 06:59:13 PM PDT 24
Finished Jun 21 06:59:18 PM PDT 24
Peak memory 204616 kb
Host smart-6a848f5e-c583-4413-b7c1-02cb7001f909
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652503001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3652503001
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3252912377
Short name T993
Test name
Test status
Simulation time 42614671 ps
CPU time 2.6 seconds
Started Jun 21 06:59:08 PM PDT 24
Finished Jun 21 06:59:14 PM PDT 24
Peak memory 215928 kb
Host smart-e1b65f65-aa43-44c1-a873-9288d4e5a19d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252912377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3252912377
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.147474081
Short name T245
Test name
Test status
Simulation time 481316467 ps
CPU time 4.05 seconds
Started Jun 21 06:59:10 PM PDT 24
Finished Jun 21 06:59:18 PM PDT 24
Peak memory 220748 kb
Host smart-225b4cd1-58fe-4527-882e-0fe99e1ea056
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147474081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.147474081
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2227847297
Short name T967
Test name
Test status
Simulation time 43885689 ps
CPU time 0.77 seconds
Started Jun 21 06:59:30 PM PDT 24
Finished Jun 21 06:59:36 PM PDT 24
Peak memory 204668 kb
Host smart-ad649655-bab0-49da-9596-43d221d064b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227847297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2227847297
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3132021558
Short name T964
Test name
Test status
Simulation time 54087663 ps
CPU time 0.72 seconds
Started Jun 21 06:59:28 PM PDT 24
Finished Jun 21 06:59:34 PM PDT 24
Peak memory 204676 kb
Host smart-67de92fd-4b50-4bb3-8830-59d9f76919e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132021558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3132021558
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.640330142
Short name T963
Test name
Test status
Simulation time 28812276 ps
CPU time 0.72 seconds
Started Jun 21 06:59:29 PM PDT 24
Finished Jun 21 06:59:36 PM PDT 24
Peak memory 204360 kb
Host smart-9fd6a681-045d-456f-a699-6e2ff6de85b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640330142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.640330142
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3319807649
Short name T981
Test name
Test status
Simulation time 43633096 ps
CPU time 0.74 seconds
Started Jun 21 06:59:29 PM PDT 24
Finished Jun 21 06:59:35 PM PDT 24
Peak memory 204356 kb
Host smart-c1746cde-5e3f-4d1a-8317-fb33118a464b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319807649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3319807649
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3396629368
Short name T1076
Test name
Test status
Simulation time 25500437 ps
CPU time 0.72 seconds
Started Jun 21 06:59:27 PM PDT 24
Finished Jun 21 06:59:33 PM PDT 24
Peak memory 204668 kb
Host smart-3651b95f-255c-48d1-b3b7-3677a982c4e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396629368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3396629368
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2712896112
Short name T1030
Test name
Test status
Simulation time 17309982 ps
CPU time 0.77 seconds
Started Jun 21 06:59:31 PM PDT 24
Finished Jun 21 06:59:38 PM PDT 24
Peak memory 204664 kb
Host smart-847eaadb-5b2b-441d-9592-2f71effc9a2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712896112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2712896112
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4253450916
Short name T977
Test name
Test status
Simulation time 22189683 ps
CPU time 0.7 seconds
Started Jun 21 06:59:31 PM PDT 24
Finished Jun 21 06:59:38 PM PDT 24
Peak memory 204384 kb
Host smart-dd792c39-bf74-4d57-a23f-25e4fad33401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253450916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
4253450916
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.116848310
Short name T966
Test name
Test status
Simulation time 121882085 ps
CPU time 0.74 seconds
Started Jun 21 06:59:29 PM PDT 24
Finished Jun 21 06:59:34 PM PDT 24
Peak memory 204344 kb
Host smart-123a8982-b645-457a-95a7-f4f94db83bd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116848310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.116848310
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.233956836
Short name T1069
Test name
Test status
Simulation time 46436398 ps
CPU time 0.77 seconds
Started Jun 21 06:59:28 PM PDT 24
Finished Jun 21 06:59:34 PM PDT 24
Peak memory 203996 kb
Host smart-c975c324-387b-4b7d-b44f-54a3e436d7f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233956836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.233956836
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1864496947
Short name T970
Test name
Test status
Simulation time 41372967 ps
CPU time 0.7 seconds
Started Jun 21 06:59:28 PM PDT 24
Finished Jun 21 06:59:34 PM PDT 24
Peak memory 204392 kb
Host smart-c5ce30ee-5ec2-4594-ad3e-c44a473cbeec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864496947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1864496947
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.475765207
Short name T1049
Test name
Test status
Simulation time 302161834 ps
CPU time 21.85 seconds
Started Jun 21 06:59:11 PM PDT 24
Finished Jun 21 06:59:38 PM PDT 24
Peak memory 215936 kb
Host smart-7d260af9-f3ca-4d62-9478-49ff9eaff739
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475765207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.475765207
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2574867554
Short name T1008
Test name
Test status
Simulation time 1465551028 ps
CPU time 22.48 seconds
Started Jun 21 06:59:11 PM PDT 24
Finished Jun 21 06:59:37 PM PDT 24
Peak memory 215876 kb
Host smart-78f85de3-2ffd-4fb7-9163-3b2b437ad3fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574867554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2574867554
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.173487528
Short name T77
Test name
Test status
Simulation time 119888451 ps
CPU time 0.95 seconds
Started Jun 21 06:59:10 PM PDT 24
Finished Jun 21 06:59:14 PM PDT 24
Peak memory 207464 kb
Host smart-a1629530-ec60-4b25-bffa-1025f90d353e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173487528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.173487528
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2604842714
Short name T1074
Test name
Test status
Simulation time 62247104 ps
CPU time 1.8 seconds
Started Jun 21 06:59:14 PM PDT 24
Finished Jun 21 06:59:21 PM PDT 24
Peak memory 217016 kb
Host smart-23c1a45c-62f9-4fde-ba44-1168f6132691
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604842714 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2604842714
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4178015004
Short name T1037
Test name
Test status
Simulation time 159527810 ps
CPU time 1.36 seconds
Started Jun 21 06:59:08 PM PDT 24
Finished Jun 21 06:59:13 PM PDT 24
Peak memory 215956 kb
Host smart-01a714ff-bb7f-4fab-a447-6becd0380777
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178015004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4
178015004
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.774520894
Short name T1018
Test name
Test status
Simulation time 16663662 ps
CPU time 0.81 seconds
Started Jun 21 06:59:10 PM PDT 24
Finished Jun 21 06:59:14 PM PDT 24
Peak memory 204348 kb
Host smart-bd20812e-1419-40ea-bdd2-fa37e8a980d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774520894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.774520894
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2069021530
Short name T110
Test name
Test status
Simulation time 258482844 ps
CPU time 2.06 seconds
Started Jun 21 06:59:11 PM PDT 24
Finished Jun 21 06:59:17 PM PDT 24
Peak memory 215976 kb
Host smart-69e70019-8243-49d3-81d2-ff35f49e2180
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069021530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2069021530
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3584545850
Short name T978
Test name
Test status
Simulation time 19574908 ps
CPU time 0.66 seconds
Started Jun 21 06:59:14 PM PDT 24
Finished Jun 21 06:59:19 PM PDT 24
Peak memory 204284 kb
Host smart-998a56ff-6c94-4c05-91e2-3af0c5d382df
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584545850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3584545850
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1817094508
Short name T960
Test name
Test status
Simulation time 102584344 ps
CPU time 1.8 seconds
Started Jun 21 06:59:13 PM PDT 24
Finished Jun 21 06:59:19 PM PDT 24
Peak memory 215956 kb
Host smart-726239cb-5472-4221-909f-7060cd897e39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817094508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1817094508
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2253258141
Short name T90
Test name
Test status
Simulation time 218043138 ps
CPU time 3.8 seconds
Started Jun 21 06:59:14 PM PDT 24
Finished Jun 21 06:59:22 PM PDT 24
Peak memory 216220 kb
Host smart-16780b73-0810-4b8e-b304-b738e3d6d8a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253258141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
253258141
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3686022706
Short name T251
Test name
Test status
Simulation time 1341365025 ps
CPU time 23.83 seconds
Started Jun 21 06:59:11 PM PDT 24
Finished Jun 21 06:59:39 PM PDT 24
Peak memory 216148 kb
Host smart-e5faa998-e97b-4576-a8ce-c48db65e1373
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686022706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3686022706
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3442684484
Short name T1036
Test name
Test status
Simulation time 11339047 ps
CPU time 0.76 seconds
Started Jun 21 06:59:27 PM PDT 24
Finished Jun 21 06:59:33 PM PDT 24
Peak memory 204620 kb
Host smart-5f87c01c-a9f1-46f5-8cf8-13a9b3bb7ab0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442684484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3442684484
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3951202571
Short name T1012
Test name
Test status
Simulation time 43810970 ps
CPU time 0.7 seconds
Started Jun 21 06:59:30 PM PDT 24
Finished Jun 21 06:59:37 PM PDT 24
Peak memory 204344 kb
Host smart-c8997f40-4401-4bb5-a5e9-e841f03adb5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951202571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3951202571
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2165786706
Short name T990
Test name
Test status
Simulation time 33403940 ps
CPU time 0.76 seconds
Started Jun 21 06:59:29 PM PDT 24
Finished Jun 21 06:59:35 PM PDT 24
Peak memory 204264 kb
Host smart-7302bfe5-25cf-4639-acf3-a7b5d4cac070
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165786706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2165786706
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3934613618
Short name T1015
Test name
Test status
Simulation time 15051579 ps
CPU time 0.71 seconds
Started Jun 21 06:59:30 PM PDT 24
Finished Jun 21 06:59:36 PM PDT 24
Peak memory 204364 kb
Host smart-2caade81-2e7c-4db8-9892-04a290bf7df5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934613618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3934613618
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1199283398
Short name T1044
Test name
Test status
Simulation time 24690724 ps
CPU time 0.72 seconds
Started Jun 21 06:59:30 PM PDT 24
Finished Jun 21 06:59:37 PM PDT 24
Peak memory 204344 kb
Host smart-808b742e-0d7d-4b3b-b33d-09d427280f43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199283398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1199283398
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1498029865
Short name T958
Test name
Test status
Simulation time 37087558 ps
CPU time 0.75 seconds
Started Jun 21 06:59:29 PM PDT 24
Finished Jun 21 06:59:35 PM PDT 24
Peak memory 204652 kb
Host smart-eae9afd3-909f-4aac-a63b-2d355be3174f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498029865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1498029865
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2727464896
Short name T1020
Test name
Test status
Simulation time 46981638 ps
CPU time 0.7 seconds
Started Jun 21 06:59:28 PM PDT 24
Finished Jun 21 06:59:34 PM PDT 24
Peak memory 204664 kb
Host smart-89620061-d42d-40c8-9b4e-61ab3a1d97a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727464896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2727464896
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.195993124
Short name T971
Test name
Test status
Simulation time 12983115 ps
CPU time 0.71 seconds
Started Jun 21 06:59:31 PM PDT 24
Finished Jun 21 06:59:37 PM PDT 24
Peak memory 204348 kb
Host smart-368bc52a-412d-495e-99b3-82f0f2579030
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195993124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.195993124
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3082402625
Short name T1032
Test name
Test status
Simulation time 20555312 ps
CPU time 0.68 seconds
Started Jun 21 06:59:30 PM PDT 24
Finished Jun 21 06:59:37 PM PDT 24
Peak memory 204352 kb
Host smart-ab89d7fe-11bc-405d-acc5-d65b538127a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082402625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3082402625
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2602185577
Short name T965
Test name
Test status
Simulation time 57076910 ps
CPU time 0.7 seconds
Started Jun 21 06:59:31 PM PDT 24
Finished Jun 21 06:59:37 PM PDT 24
Peak memory 204348 kb
Host smart-36f38501-a3b8-4f54-a5fd-e31f799394b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602185577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2602185577
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2878019438
Short name T984
Test name
Test status
Simulation time 985588229 ps
CPU time 8.38 seconds
Started Jun 21 06:59:14 PM PDT 24
Finished Jun 21 06:59:26 PM PDT 24
Peak memory 207756 kb
Host smart-4caef48d-7cf7-428c-8474-822c311b5bc3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878019438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2878019438
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2210500275
Short name T103
Test name
Test status
Simulation time 19277797757 ps
CPU time 40.68 seconds
Started Jun 21 06:59:14 PM PDT 24
Finished Jun 21 07:00:00 PM PDT 24
Peak memory 207736 kb
Host smart-a43a4321-74f6-4572-beac-b6a4bcfc2a26
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210500275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2210500275
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.21245898
Short name T78
Test name
Test status
Simulation time 223722691 ps
CPU time 1.13 seconds
Started Jun 21 06:59:11 PM PDT 24
Finished Jun 21 06:59:15 PM PDT 24
Peak memory 207736 kb
Host smart-861d8701-68df-4a02-a92a-365e70fe886e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21245898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_
hw_reset.21245898
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2795019351
Short name T1006
Test name
Test status
Simulation time 25333561 ps
CPU time 1.73 seconds
Started Jun 21 06:59:09 PM PDT 24
Finished Jun 21 06:59:13 PM PDT 24
Peak memory 216980 kb
Host smart-ea0d6004-bb0d-401e-973c-743ff1567548
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795019351 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2795019351
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4135070476
Short name T105
Test name
Test status
Simulation time 376367236 ps
CPU time 2.67 seconds
Started Jun 21 06:59:11 PM PDT 24
Finished Jun 21 06:59:17 PM PDT 24
Peak memory 215972 kb
Host smart-20dbbaf8-11b5-4c42-b671-ed47caa86fda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135070476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4
135070476
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3562473114
Short name T980
Test name
Test status
Simulation time 39241838 ps
CPU time 0.78 seconds
Started Jun 21 06:59:15 PM PDT 24
Finished Jun 21 06:59:20 PM PDT 24
Peak memory 204664 kb
Host smart-16148b7c-4599-4e6b-8968-d7b54a8ec372
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562473114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
562473114
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4079822956
Short name T111
Test name
Test status
Simulation time 245596528 ps
CPU time 1.18 seconds
Started Jun 21 06:59:14 PM PDT 24
Finished Jun 21 06:59:20 PM PDT 24
Peak memory 215772 kb
Host smart-ef397f30-3571-4faa-9aef-05def6337b12
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079822956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.4079822956
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1488637509
Short name T1045
Test name
Test status
Simulation time 29276526 ps
CPU time 0.63 seconds
Started Jun 21 06:59:13 PM PDT 24
Finished Jun 21 06:59:18 PM PDT 24
Peak memory 204268 kb
Host smart-77a764ea-2c19-44d6-8944-6e31b60575d2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488637509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1488637509
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2832948881
Short name T126
Test name
Test status
Simulation time 173136882 ps
CPU time 3.51 seconds
Started Jun 21 06:59:13 PM PDT 24
Finished Jun 21 06:59:21 PM PDT 24
Peak memory 215932 kb
Host smart-a2111acd-7501-40a0-a9c9-1ab9cafcc677
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832948881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2832948881
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2425815719
Short name T244
Test name
Test status
Simulation time 60288322 ps
CPU time 2.93 seconds
Started Jun 21 06:59:14 PM PDT 24
Finished Jun 21 06:59:21 PM PDT 24
Peak memory 216184 kb
Host smart-1972743a-3ec3-445d-8bbb-d91f17867052
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425815719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
425815719
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1664912812
Short name T86
Test name
Test status
Simulation time 301363625 ps
CPU time 18.99 seconds
Started Jun 21 06:59:08 PM PDT 24
Finished Jun 21 06:59:30 PM PDT 24
Peak memory 215788 kb
Host smart-ae41d95b-ca49-4d83-b2c8-32e80378c4cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664912812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1664912812
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.594055039
Short name T959
Test name
Test status
Simulation time 44870379 ps
CPU time 0.74 seconds
Started Jun 21 06:59:31 PM PDT 24
Finished Jun 21 06:59:38 PM PDT 24
Peak memory 204680 kb
Host smart-905bc23b-0021-401d-9e5d-fbe2345e8de5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594055039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.594055039
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1557979613
Short name T969
Test name
Test status
Simulation time 12134528 ps
CPU time 0.76 seconds
Started Jun 21 06:59:30 PM PDT 24
Finished Jun 21 06:59:37 PM PDT 24
Peak memory 204664 kb
Host smart-fdd9fbca-ca44-4f6a-a8bd-8423ddc94a64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557979613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1557979613
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.318267048
Short name T1010
Test name
Test status
Simulation time 46277375 ps
CPU time 0.77 seconds
Started Jun 21 06:59:30 PM PDT 24
Finished Jun 21 06:59:36 PM PDT 24
Peak memory 204332 kb
Host smart-cdac60fc-9f78-4954-a322-5e82bfc780db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318267048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.318267048
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.266319626
Short name T1051
Test name
Test status
Simulation time 14407519 ps
CPU time 0.79 seconds
Started Jun 21 06:59:30 PM PDT 24
Finished Jun 21 06:59:36 PM PDT 24
Peak memory 204680 kb
Host smart-fc204413-9458-4528-a8b7-5ac8047498fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266319626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.266319626
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3298958263
Short name T1058
Test name
Test status
Simulation time 12620272 ps
CPU time 0.71 seconds
Started Jun 21 06:59:31 PM PDT 24
Finished Jun 21 06:59:37 PM PDT 24
Peak memory 204368 kb
Host smart-c56480d1-212d-48bb-8630-b6ec662bae90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298958263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3298958263
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.695308338
Short name T1002
Test name
Test status
Simulation time 14591370 ps
CPU time 0.69 seconds
Started Jun 21 06:59:31 PM PDT 24
Finished Jun 21 06:59:37 PM PDT 24
Peak memory 204352 kb
Host smart-52c9afbb-6c21-43c3-ba02-da51f5c414c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695308338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.695308338
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2563057464
Short name T979
Test name
Test status
Simulation time 12865958 ps
CPU time 0.71 seconds
Started Jun 21 06:59:31 PM PDT 24
Finished Jun 21 06:59:37 PM PDT 24
Peak memory 204352 kb
Host smart-7c6b87c7-2dec-41a0-9c09-05e164be835d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563057464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2563057464
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1353134853
Short name T961
Test name
Test status
Simulation time 47360926 ps
CPU time 0.75 seconds
Started Jun 21 06:59:40 PM PDT 24
Finished Jun 21 06:59:43 PM PDT 24
Peak memory 204716 kb
Host smart-942a9f9e-8f5b-471e-ab25-469531b5505d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353134853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1353134853
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2441100114
Short name T983
Test name
Test status
Simulation time 11401382 ps
CPU time 0.69 seconds
Started Jun 21 06:59:40 PM PDT 24
Finished Jun 21 06:59:44 PM PDT 24
Peak memory 204656 kb
Host smart-f02e391e-9971-4e48-b6e4-aec4a0b7dfa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441100114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2441100114
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1762077048
Short name T996
Test name
Test status
Simulation time 11785648 ps
CPU time 0.72 seconds
Started Jun 21 06:59:39 PM PDT 24
Finished Jun 21 06:59:42 PM PDT 24
Peak memory 204344 kb
Host smart-4c70dddd-f910-4156-9bec-8fb308401c58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762077048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1762077048
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2872507548
Short name T93
Test name
Test status
Simulation time 167570422 ps
CPU time 2.77 seconds
Started Jun 21 06:59:11 PM PDT 24
Finished Jun 21 06:59:17 PM PDT 24
Peak memory 217312 kb
Host smart-ef9e7cfe-9270-4031-acff-eecca8ab4072
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872507548 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2872507548
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2993711183
Short name T99
Test name
Test status
Simulation time 82211570 ps
CPU time 2.02 seconds
Started Jun 21 06:59:17 PM PDT 24
Finished Jun 21 06:59:24 PM PDT 24
Peak memory 207768 kb
Host smart-08de3860-ac29-4cee-9a98-16a73cd059e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993711183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
993711183
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1261189750
Short name T1063
Test name
Test status
Simulation time 27053822 ps
CPU time 0.75 seconds
Started Jun 21 06:59:17 PM PDT 24
Finished Jun 21 06:59:23 PM PDT 24
Peak memory 204384 kb
Host smart-56e0a20a-718c-4679-8e02-70d9a02d7082
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261189750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
261189750
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1398524467
Short name T1033
Test name
Test status
Simulation time 64343715 ps
CPU time 3.94 seconds
Started Jun 21 06:59:15 PM PDT 24
Finished Jun 21 06:59:24 PM PDT 24
Peak memory 215908 kb
Host smart-3ec0989b-f4e8-463c-8ddd-d4222a5a9211
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398524467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1398524467
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.138315322
Short name T91
Test name
Test status
Simulation time 106876223 ps
CPU time 3.57 seconds
Started Jun 21 06:59:14 PM PDT 24
Finished Jun 21 06:59:22 PM PDT 24
Peak memory 216396 kb
Host smart-9ca5880a-8a35-489d-9cba-dd29dae664da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138315322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.138315322
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2640481429
Short name T252
Test name
Test status
Simulation time 101403273 ps
CPU time 6.5 seconds
Started Jun 21 06:59:16 PM PDT 24
Finished Jun 21 06:59:28 PM PDT 24
Peak memory 215984 kb
Host smart-b1a8a5e3-bf15-4eda-a530-a27754f303c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640481429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2640481429
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2101479014
Short name T1025
Test name
Test status
Simulation time 144583671 ps
CPU time 2.28 seconds
Started Jun 21 06:59:13 PM PDT 24
Finished Jun 21 06:59:19 PM PDT 24
Peak memory 218156 kb
Host smart-4b4fb443-643b-4e2d-b90b-2a4ef0fdff95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101479014 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2101479014
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.974822538
Short name T1042
Test name
Test status
Simulation time 28833756 ps
CPU time 1.79 seconds
Started Jun 21 06:59:11 PM PDT 24
Finished Jun 21 06:59:16 PM PDT 24
Peak memory 215992 kb
Host smart-7fd0b40b-f2cf-4cb4-961d-4eedfceda9ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974822538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.974822538
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4029403144
Short name T1064
Test name
Test status
Simulation time 33578097 ps
CPU time 0.69 seconds
Started Jun 21 06:59:17 PM PDT 24
Finished Jun 21 06:59:23 PM PDT 24
Peak memory 204400 kb
Host smart-72f2bb59-586b-4522-b953-df506373ec18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029403144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.4
029403144
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.124052245
Short name T1007
Test name
Test status
Simulation time 162810774 ps
CPU time 4.34 seconds
Started Jun 21 06:59:17 PM PDT 24
Finished Jun 21 06:59:27 PM PDT 24
Peak memory 215896 kb
Host smart-59647503-745c-49d4-9b0c-4cb6a04d421b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124052245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.124052245
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1950768834
Short name T1054
Test name
Test status
Simulation time 209867432 ps
CPU time 3.91 seconds
Started Jun 21 06:59:14 PM PDT 24
Finished Jun 21 06:59:23 PM PDT 24
Peak memory 216184 kb
Host smart-d59523a9-b8a5-443e-9e2d-94bc7c4ed029
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950768834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
950768834
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3332470630
Short name T135
Test name
Test status
Simulation time 1461079317 ps
CPU time 7.15 seconds
Started Jun 21 06:59:15 PM PDT 24
Finished Jun 21 06:59:27 PM PDT 24
Peak memory 215904 kb
Host smart-ceca66c9-ac17-4c40-8799-7d2aa05a438d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332470630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3332470630
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.349973493
Short name T995
Test name
Test status
Simulation time 462553437 ps
CPU time 1.68 seconds
Started Jun 21 06:59:10 PM PDT 24
Finished Jun 21 06:59:14 PM PDT 24
Peak memory 217072 kb
Host smart-83bba714-48ef-475b-8213-23c2afeeb838
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349973493 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.349973493
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1438519591
Short name T109
Test name
Test status
Simulation time 39185050 ps
CPU time 2.39 seconds
Started Jun 21 06:59:16 PM PDT 24
Finished Jun 21 06:59:23 PM PDT 24
Peak memory 215924 kb
Host smart-2a89cdc8-5a98-43db-8a32-9175234b9d03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438519591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
438519591
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1353976601
Short name T1072
Test name
Test status
Simulation time 15511336 ps
CPU time 0.74 seconds
Started Jun 21 06:59:12 PM PDT 24
Finished Jun 21 06:59:17 PM PDT 24
Peak memory 204716 kb
Host smart-085c8ffd-b40b-4af9-bc9f-ed235ea82366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353976601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
353976601
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.409383323
Short name T1043
Test name
Test status
Simulation time 197923758 ps
CPU time 2.94 seconds
Started Jun 21 06:59:17 PM PDT 24
Finished Jun 21 06:59:25 PM PDT 24
Peak memory 215912 kb
Host smart-b4f069bd-ffcd-49a8-9b89-f5c3bbee7cb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409383323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.409383323
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.364851637
Short name T1035
Test name
Test status
Simulation time 150477526 ps
CPU time 4.5 seconds
Started Jun 21 06:59:18 PM PDT 24
Finished Jun 21 06:59:28 PM PDT 24
Peak memory 216172 kb
Host smart-6bbb7936-f403-41d7-a16c-5a2ae8a5b4d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364851637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.364851637
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3002287528
Short name T1031
Test name
Test status
Simulation time 2222233397 ps
CPU time 14.41 seconds
Started Jun 21 06:59:18 PM PDT 24
Finished Jun 21 06:59:38 PM PDT 24
Peak memory 216588 kb
Host smart-76b8e5ab-0bb4-4024-bd96-c502b4d681c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002287528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3002287528
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2247669591
Short name T1013
Test name
Test status
Simulation time 327924615 ps
CPU time 1.52 seconds
Started Jun 21 06:59:20 PM PDT 24
Finished Jun 21 06:59:27 PM PDT 24
Peak memory 216028 kb
Host smart-c6e5fd37-8f93-4a03-a7d6-571de8b57672
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247669591 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2247669591
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2327327749
Short name T100
Test name
Test status
Simulation time 452068528 ps
CPU time 2.15 seconds
Started Jun 21 06:59:23 PM PDT 24
Finished Jun 21 06:59:31 PM PDT 24
Peak memory 207760 kb
Host smart-6d10e685-bf2e-4e59-a368-636ed8d889ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327327749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
327327749
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.312034652
Short name T985
Test name
Test status
Simulation time 110997102 ps
CPU time 0.79 seconds
Started Jun 21 06:59:10 PM PDT 24
Finished Jun 21 06:59:14 PM PDT 24
Peak memory 204336 kb
Host smart-0357a6ca-dce0-4b2f-bd57-445d7c6676c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312034652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.312034652
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.793047101
Short name T1055
Test name
Test status
Simulation time 435710128 ps
CPU time 2.92 seconds
Started Jun 21 06:59:19 PM PDT 24
Finished Jun 21 06:59:27 PM PDT 24
Peak memory 215936 kb
Host smart-b763ccac-08ce-4822-888e-3fef2af08b55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793047101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.793047101
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.200775561
Short name T1070
Test name
Test status
Simulation time 61206842 ps
CPU time 3.51 seconds
Started Jun 21 06:59:10 PM PDT 24
Finished Jun 21 06:59:17 PM PDT 24
Peak memory 216180 kb
Host smart-95672c92-7256-4e43-a746-459d62a3cc93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200775561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.200775561
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.112410909
Short name T1053
Test name
Test status
Simulation time 147823495 ps
CPU time 3.64 seconds
Started Jun 21 06:59:20 PM PDT 24
Finished Jun 21 06:59:28 PM PDT 24
Peak memory 218212 kb
Host smart-97b5393d-5828-40a0-89f0-48df36225f05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112410909 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.112410909
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1260691098
Short name T1079
Test name
Test status
Simulation time 333375101 ps
CPU time 2.5 seconds
Started Jun 21 06:59:20 PM PDT 24
Finished Jun 21 06:59:29 PM PDT 24
Peak memory 215948 kb
Host smart-6fa394ff-1265-46fd-b01d-039d5a37186f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260691098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
260691098
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3767179712
Short name T1065
Test name
Test status
Simulation time 22188361 ps
CPU time 0.74 seconds
Started Jun 21 06:59:23 PM PDT 24
Finished Jun 21 06:59:29 PM PDT 24
Peak memory 204664 kb
Host smart-52c935c3-b5a6-4d13-9651-22d099d71965
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767179712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
767179712
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3852257782
Short name T1061
Test name
Test status
Simulation time 157899181 ps
CPU time 2.04 seconds
Started Jun 21 06:59:20 PM PDT 24
Finished Jun 21 06:59:28 PM PDT 24
Peak memory 215944 kb
Host smart-bd714f61-b469-4c98-8896-0c9a8669297a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852257782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3852257782
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2766226320
Short name T1075
Test name
Test status
Simulation time 378457844 ps
CPU time 4.12 seconds
Started Jun 21 06:59:20 PM PDT 24
Finished Jun 21 06:59:30 PM PDT 24
Peak memory 216100 kb
Host smart-5bfefb54-c802-432f-b237-8daa67925b59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766226320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
766226320
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1747219723
Short name T254
Test name
Test status
Simulation time 100931386 ps
CPU time 5.99 seconds
Started Jun 21 06:59:19 PM PDT 24
Finished Jun 21 06:59:30 PM PDT 24
Peak memory 215944 kb
Host smart-87fdf5d0-90ba-4212-92d4-4bad92adc6bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747219723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1747219723
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1566478326
Short name T69
Test name
Test status
Simulation time 8637683248 ps
CPU time 25.61 seconds
Started Jun 21 06:59:42 PM PDT 24
Finished Jun 21 07:00:11 PM PDT 24
Peak memory 224820 kb
Host smart-9a9a32a5-cd45-438c-b209-e3646d32ee65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566478326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1566478326
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3169137229
Short name T431
Test name
Test status
Simulation time 66895311 ps
CPU time 0.82 seconds
Started Jun 21 06:59:40 PM PDT 24
Finished Jun 21 06:59:44 PM PDT 24
Peak memory 206724 kb
Host smart-492ae493-09b9-4ed9-8c62-10d3af0fe65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169137229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3169137229
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3306202961
Short name T644
Test name
Test status
Simulation time 1189376877 ps
CPU time 6.76 seconds
Started Jun 21 06:59:41 PM PDT 24
Finished Jun 21 06:59:51 PM PDT 24
Peak memory 224592 kb
Host smart-5e7a02d1-9b0c-4e1e-859c-85dd2037c6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306202961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3306202961
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2194860074
Short name T281
Test name
Test status
Simulation time 7042509244 ps
CPU time 56.85 seconds
Started Jun 21 06:59:43 PM PDT 24
Finished Jun 21 07:00:44 PM PDT 24
Peak memory 249440 kb
Host smart-9bd4912d-ae30-4b47-b199-704a929d6808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194860074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2194860074
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3760601879
Short name T816
Test name
Test status
Simulation time 55433260404 ps
CPU time 164.23 seconds
Started Jun 21 06:59:44 PM PDT 24
Finished Jun 21 07:02:32 PM PDT 24
Peak memory 249508 kb
Host smart-bebc94bd-cee4-4aed-8c64-0a3e9f5e6b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760601879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3760601879
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.562056130
Short name T395
Test name
Test status
Simulation time 232614286 ps
CPU time 3.82 seconds
Started Jun 21 06:59:45 PM PDT 24
Finished Jun 21 06:59:53 PM PDT 24
Peak memory 232972 kb
Host smart-1f909347-fdb0-474b-bd52-0b7c5c5cf423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562056130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.562056130
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.918761197
Short name T274
Test name
Test status
Simulation time 2945849986 ps
CPU time 3.86 seconds
Started Jun 21 06:59:45 PM PDT 24
Finished Jun 21 06:59:53 PM PDT 24
Peak memory 224748 kb
Host smart-07895820-b1f0-4a52-8cea-3f3d3a06bcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918761197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.918761197
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.523110197
Short name T928
Test name
Test status
Simulation time 2137228383 ps
CPU time 12.93 seconds
Started Jun 21 06:59:45 PM PDT 24
Finished Jun 21 07:00:02 PM PDT 24
Peak memory 224720 kb
Host smart-4aeb81e2-feb8-49f5-a689-92d0ad0f18c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523110197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.523110197
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1774660594
Short name T284
Test name
Test status
Simulation time 43237634 ps
CPU time 2.44 seconds
Started Jun 21 06:59:39 PM PDT 24
Finished Jun 21 06:59:44 PM PDT 24
Peak memory 232832 kb
Host smart-38e2497d-3f29-4714-ad97-a7de50456837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774660594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1774660594
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1064678600
Short name T574
Test name
Test status
Simulation time 801359758 ps
CPU time 4.98 seconds
Started Jun 21 06:59:43 PM PDT 24
Finished Jun 21 06:59:53 PM PDT 24
Peak memory 224572 kb
Host smart-8b4199b8-be53-4826-a300-f97be73d8fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064678600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1064678600
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2653834064
Short name T132
Test name
Test status
Simulation time 1454712941 ps
CPU time 7.67 seconds
Started Jun 21 06:59:42 PM PDT 24
Finished Jun 21 06:59:54 PM PDT 24
Peak memory 222572 kb
Host smart-99b1ef78-3b08-4772-a2fd-2a043c381610
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2653834064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2653834064
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.216464374
Short name T62
Test name
Test status
Simulation time 100700160 ps
CPU time 1.2 seconds
Started Jun 21 06:59:42 PM PDT 24
Finished Jun 21 06:59:47 PM PDT 24
Peak memory 236948 kb
Host smart-9bb2b091-0831-4a4e-8cd8-1dc8d58adbd5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216464374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.216464374
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.214361895
Short name T22
Test name
Test status
Simulation time 19533828129 ps
CPU time 59.91 seconds
Started Jun 21 06:59:45 PM PDT 24
Finished Jun 21 07:00:50 PM PDT 24
Peak memory 255180 kb
Host smart-c4ea6258-0101-4e1f-b413-efddeac4d2dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214361895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.214361895
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2474517048
Short name T396
Test name
Test status
Simulation time 3841529485 ps
CPU time 3.43 seconds
Started Jun 21 06:59:41 PM PDT 24
Finished Jun 21 06:59:48 PM PDT 24
Peak memory 216520 kb
Host smart-5552d8a0-6533-4be4-b182-3e2dc7a2b17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474517048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2474517048
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.449799796
Short name T462
Test name
Test status
Simulation time 4310347013 ps
CPU time 14.57 seconds
Started Jun 21 06:59:42 PM PDT 24
Finished Jun 21 07:00:00 PM PDT 24
Peak memory 216540 kb
Host smart-bb3fde83-e011-46cd-93f6-0ffc8127b9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449799796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.449799796
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3534562578
Short name T780
Test name
Test status
Simulation time 30917322 ps
CPU time 1.25 seconds
Started Jun 21 06:59:40 PM PDT 24
Finished Jun 21 06:59:44 PM PDT 24
Peak memory 216340 kb
Host smart-d6073976-8d6e-4cab-b31b-3dfe13e7c27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534562578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3534562578
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1648288456
Short name T660
Test name
Test status
Simulation time 209711843 ps
CPU time 0.89 seconds
Started Jun 21 06:59:39 PM PDT 24
Finished Jun 21 06:59:43 PM PDT 24
Peak memory 207164 kb
Host smart-00d566a0-931b-4300-9333-27d3432efa9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648288456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1648288456
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2748546129
Short name T460
Test name
Test status
Simulation time 2869225278 ps
CPU time 6.73 seconds
Started Jun 21 06:59:38 PM PDT 24
Finished Jun 21 06:59:47 PM PDT 24
Peak memory 224776 kb
Host smart-096971a1-6d8f-42b9-98c3-a20380576bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748546129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2748546129
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2230431545
Short name T337
Test name
Test status
Simulation time 10915560 ps
CPU time 0.77 seconds
Started Jun 21 06:59:43 PM PDT 24
Finished Jun 21 06:59:49 PM PDT 24
Peak memory 204948 kb
Host smart-611cc548-944c-4fca-8457-5f7cf383d1f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230431545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
230431545
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1539810954
Short name T690
Test name
Test status
Simulation time 472800019 ps
CPU time 2.54 seconds
Started Jun 21 06:59:43 PM PDT 24
Finished Jun 21 06:59:50 PM PDT 24
Peak memory 224628 kb
Host smart-3b1ca2c8-ddbe-44b6-8337-e6e21efc558e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539810954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1539810954
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3076854660
Short name T729
Test name
Test status
Simulation time 81723449 ps
CPU time 0.81 seconds
Started Jun 21 06:59:45 PM PDT 24
Finished Jun 21 06:59:50 PM PDT 24
Peak memory 206708 kb
Host smart-46e1867e-cb07-493f-8dba-0b31ada6dc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076854660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3076854660
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2349552685
Short name T742
Test name
Test status
Simulation time 79315764996 ps
CPU time 142.87 seconds
Started Jun 21 06:59:42 PM PDT 24
Finished Jun 21 07:02:09 PM PDT 24
Peak memory 239580 kb
Host smart-74516ec5-dd34-4737-9379-655b5c9fac95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349552685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2349552685
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.39749863
Short name T232
Test name
Test status
Simulation time 18700462544 ps
CPU time 235.64 seconds
Started Jun 21 06:59:42 PM PDT 24
Finished Jun 21 07:03:42 PM PDT 24
Peak memory 256508 kb
Host smart-b90bd1be-f3b0-485d-8875-da9a38b85139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39749863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.39749863
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3105598610
Short name T154
Test name
Test status
Simulation time 9458449046 ps
CPU time 54.82 seconds
Started Jun 21 06:59:41 PM PDT 24
Finished Jun 21 07:00:40 PM PDT 24
Peak memory 252440 kb
Host smart-9e4972b5-fb85-493f-92f1-df7a738dc44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105598610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3105598610
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1293693581
Short name T618
Test name
Test status
Simulation time 122979556 ps
CPU time 6.9 seconds
Started Jun 21 06:59:44 PM PDT 24
Finished Jun 21 06:59:56 PM PDT 24
Peak memory 224596 kb
Host smart-e458c3f3-d3eb-436e-adc2-2cd31838dfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293693581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1293693581
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.4124381758
Short name T118
Test name
Test status
Simulation time 390141081 ps
CPU time 6.11 seconds
Started Jun 21 06:59:43 PM PDT 24
Finished Jun 21 06:59:54 PM PDT 24
Peak memory 224612 kb
Host smart-1d9c867b-af48-42f1-b89d-dbd0e35d65bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124381758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.4124381758
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1303811111
Short name T183
Test name
Test status
Simulation time 13745310815 ps
CPU time 109.49 seconds
Started Jun 21 06:59:40 PM PDT 24
Finished Jun 21 07:01:33 PM PDT 24
Peak memory 244376 kb
Host smart-a7eaaa15-57df-46c7-aa83-15bb3b912d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303811111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1303811111
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3537444582
Short name T812
Test name
Test status
Simulation time 6418002680 ps
CPU time 16.83 seconds
Started Jun 21 06:59:39 PM PDT 24
Finished Jun 21 06:59:58 PM PDT 24
Peak memory 224776 kb
Host smart-335e350e-39e3-46bc-9502-adc83c4f616f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537444582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3537444582
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.70856069
Short name T486
Test name
Test status
Simulation time 44530089333 ps
CPU time 25.95 seconds
Started Jun 21 06:59:40 PM PDT 24
Finished Jun 21 07:00:09 PM PDT 24
Peak memory 249348 kb
Host smart-ac4b5f5a-cb7a-4e4c-8fda-e8bff8dc3f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70856069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.70856069
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.355426834
Short name T131
Test name
Test status
Simulation time 1859043654 ps
CPU time 6.72 seconds
Started Jun 21 06:59:43 PM PDT 24
Finished Jun 21 06:59:54 PM PDT 24
Peak memory 222652 kb
Host smart-9a2ecc4b-d30a-46d0-9747-a4ede0ef586f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=355426834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.355426834
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1807959550
Short name T61
Test name
Test status
Simulation time 82053110 ps
CPU time 1.15 seconds
Started Jun 21 06:59:40 PM PDT 24
Finished Jun 21 06:59:44 PM PDT 24
Peak memory 235896 kb
Host smart-a6186e10-4df3-45bc-aebd-db52eb271e1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807959550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1807959550
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3394117481
Short name T235
Test name
Test status
Simulation time 15699958475 ps
CPU time 127.19 seconds
Started Jun 21 06:59:41 PM PDT 24
Finished Jun 21 07:01:51 PM PDT 24
Peak memory 249568 kb
Host smart-41cac3e3-c7ff-46fd-8714-658c1fc39022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394117481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3394117481
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3939735322
Short name T323
Test name
Test status
Simulation time 16276741275 ps
CPU time 16.94 seconds
Started Jun 21 06:59:43 PM PDT 24
Finished Jun 21 07:00:04 PM PDT 24
Peak memory 216516 kb
Host smart-91f997c0-5cca-4067-99ab-0e7586bff91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939735322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3939735322
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.4292660963
Short name T350
Test name
Test status
Simulation time 644854624 ps
CPU time 2.52 seconds
Started Jun 21 06:59:40 PM PDT 24
Finished Jun 21 06:59:45 PM PDT 24
Peak memory 216404 kb
Host smart-7aa74ff4-7ddf-4119-a1cd-f0a63ac15f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292660963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.4292660963
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.278349226
Short name T890
Test name
Test status
Simulation time 225240294 ps
CPU time 1.35 seconds
Started Jun 21 06:59:43 PM PDT 24
Finished Jun 21 06:59:49 PM PDT 24
Peak memory 216388 kb
Host smart-2b5e327a-2fc3-4118-941a-b71d625b37b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278349226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.278349226
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3226723446
Short name T785
Test name
Test status
Simulation time 269969848 ps
CPU time 0.9 seconds
Started Jun 21 06:59:39 PM PDT 24
Finished Jun 21 06:59:42 PM PDT 24
Peak memory 206096 kb
Host smart-20fbc247-8ea0-4f1a-a7ac-3974dff15190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226723446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3226723446
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.543034808
Short name T303
Test name
Test status
Simulation time 1496097784 ps
CPU time 2.97 seconds
Started Jun 21 06:59:44 PM PDT 24
Finished Jun 21 06:59:51 PM PDT 24
Peak memory 224708 kb
Host smart-0846a654-731d-40fe-8b45-672506d8446b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543034808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.543034808
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.4236671147
Short name T592
Test name
Test status
Simulation time 59430562 ps
CPU time 0.69 seconds
Started Jun 21 07:00:12 PM PDT 24
Finished Jun 21 07:00:20 PM PDT 24
Peak memory 204944 kb
Host smart-50747344-d0ad-400b-a358-694b3c51deb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236671147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
4236671147
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2932279783
Short name T306
Test name
Test status
Simulation time 1919634373 ps
CPU time 4.87 seconds
Started Jun 21 07:00:11 PM PDT 24
Finished Jun 21 07:00:23 PM PDT 24
Peak memory 224640 kb
Host smart-491df479-e291-4092-bfa2-60741c9b64e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932279783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2932279783
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2219785743
Short name T475
Test name
Test status
Simulation time 34657822 ps
CPU time 0.78 seconds
Started Jun 21 07:00:12 PM PDT 24
Finished Jun 21 07:00:20 PM PDT 24
Peak memory 206744 kb
Host smart-7865153b-dc07-4754-9b0f-63ec7778d97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219785743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2219785743
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.896573124
Short name T423
Test name
Test status
Simulation time 2870955998 ps
CPU time 47.32 seconds
Started Jun 21 07:00:13 PM PDT 24
Finished Jun 21 07:01:07 PM PDT 24
Peak memory 249768 kb
Host smart-6fc5e402-e856-4592-b1c2-5fd288202754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896573124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.896573124
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1086179314
Short name T699
Test name
Test status
Simulation time 17495107914 ps
CPU time 61.35 seconds
Started Jun 21 07:00:10 PM PDT 24
Finished Jun 21 07:01:18 PM PDT 24
Peak memory 257272 kb
Host smart-ebfe38da-2d8f-44f2-bb2f-ad5232b3ad85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086179314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1086179314
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1818156021
Short name T121
Test name
Test status
Simulation time 2016726251 ps
CPU time 51.17 seconds
Started Jun 21 07:00:19 PM PDT 24
Finished Jun 21 07:01:19 PM PDT 24
Peak memory 249448 kb
Host smart-cb2ba08e-c2ec-46a2-9641-21bd1770bcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818156021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1818156021
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1755021106
Short name T38
Test name
Test status
Simulation time 798641997 ps
CPU time 8.19 seconds
Started Jun 21 07:00:11 PM PDT 24
Finished Jun 21 07:00:26 PM PDT 24
Peak memory 232836 kb
Host smart-75f30597-c08a-453d-973a-b774e687853b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755021106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1755021106
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2548404279
Short name T156
Test name
Test status
Simulation time 3373379964 ps
CPU time 14.71 seconds
Started Jun 21 07:00:19 PM PDT 24
Finished Jun 21 07:00:42 PM PDT 24
Peak memory 224780 kb
Host smart-d0810c65-fee1-4fbb-a648-b108556ee583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548404279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2548404279
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.85766172
Short name T871
Test name
Test status
Simulation time 168411184268 ps
CPU time 99.89 seconds
Started Jun 21 07:00:16 PM PDT 24
Finished Jun 21 07:02:04 PM PDT 24
Peak memory 232948 kb
Host smart-8b25d591-9014-4051-94f7-fd9d84ab3fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85766172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.85766172
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.4099748194
Short name T902
Test name
Test status
Simulation time 41057651548 ps
CPU time 32.98 seconds
Started Jun 21 07:00:13 PM PDT 24
Finished Jun 21 07:00:53 PM PDT 24
Peak memory 249328 kb
Host smart-e5815e6c-7beb-49e8-b248-3df8e513cc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099748194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.4099748194
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.762893295
Short name T689
Test name
Test status
Simulation time 8782630050 ps
CPU time 18.73 seconds
Started Jun 21 07:00:11 PM PDT 24
Finished Jun 21 07:00:37 PM PDT 24
Peak memory 232988 kb
Host smart-330377b9-6107-4205-9685-2da85dd08620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762893295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.762893295
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3361441526
Short name T657
Test name
Test status
Simulation time 403441072 ps
CPU time 3.69 seconds
Started Jun 21 07:00:10 PM PDT 24
Finished Jun 21 07:00:21 PM PDT 24
Peak memory 220172 kb
Host smart-dceed7ad-59e2-4d78-836c-db6e9cbaf10c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3361441526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3361441526
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1699407289
Short name T48
Test name
Test status
Simulation time 38492668 ps
CPU time 0.89 seconds
Started Jun 21 07:00:09 PM PDT 24
Finished Jun 21 07:00:16 PM PDT 24
Peak memory 207076 kb
Host smart-6b3ad193-e15f-4fec-b97c-46d98be58185
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699407289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1699407289
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.383349958
Short name T325
Test name
Test status
Simulation time 4142216531 ps
CPU time 27.23 seconds
Started Jun 21 07:00:10 PM PDT 24
Finished Jun 21 07:00:44 PM PDT 24
Peak memory 216528 kb
Host smart-fc59288b-db91-4d68-ba0f-640c7668efb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383349958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.383349958
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.181166213
Short name T476
Test name
Test status
Simulation time 4659707249 ps
CPU time 7.88 seconds
Started Jun 21 07:00:11 PM PDT 24
Finished Jun 21 07:00:26 PM PDT 24
Peak memory 216528 kb
Host smart-5cbe6fbf-ccf2-4ba7-85d4-c80443628b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181166213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.181166213
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.193406136
Short name T820
Test name
Test status
Simulation time 55233779 ps
CPU time 1.83 seconds
Started Jun 21 07:00:10 PM PDT 24
Finished Jun 21 07:00:19 PM PDT 24
Peak memory 216400 kb
Host smart-68a52066-9970-42a2-a570-68dabc6019ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193406136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.193406136
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.440779066
Short name T442
Test name
Test status
Simulation time 69566037 ps
CPU time 0.95 seconds
Started Jun 21 07:00:10 PM PDT 24
Finished Jun 21 07:00:18 PM PDT 24
Peak memory 206096 kb
Host smart-535cffec-0ebd-4180-ade7-dbc61ac7bc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440779066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.440779066
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1586533074
Short name T295
Test name
Test status
Simulation time 402496821 ps
CPU time 7.17 seconds
Started Jun 21 07:00:12 PM PDT 24
Finished Jun 21 07:00:26 PM PDT 24
Peak memory 232884 kb
Host smart-4d0e0231-5765-4ccd-b025-740dd256dc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586533074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1586533074
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1198261006
Short name T393
Test name
Test status
Simulation time 32116059 ps
CPU time 0.68 seconds
Started Jun 21 07:00:16 PM PDT 24
Finished Jun 21 07:00:25 PM PDT 24
Peak memory 205520 kb
Host smart-9eda651d-4921-4fd2-bf56-d9e5f2af67f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198261006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1198261006
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.244117123
Short name T906
Test name
Test status
Simulation time 206485188 ps
CPU time 3.87 seconds
Started Jun 21 07:00:08 PM PDT 24
Finished Jun 21 07:00:19 PM PDT 24
Peak memory 232868 kb
Host smart-0ecb0b32-e61f-43c2-85c1-ed58661cdb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244117123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.244117123
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1510128270
Short name T790
Test name
Test status
Simulation time 15800432 ps
CPU time 0.76 seconds
Started Jun 21 07:00:11 PM PDT 24
Finished Jun 21 07:00:18 PM PDT 24
Peak memory 205712 kb
Host smart-95eabc6e-72e4-4026-9252-64df3cb87efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510128270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1510128270
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3209924571
Short name T884
Test name
Test status
Simulation time 26242034495 ps
CPU time 190.28 seconds
Started Jun 21 07:00:11 PM PDT 24
Finished Jun 21 07:03:28 PM PDT 24
Peak memory 249432 kb
Host smart-b0af6848-209a-45bf-a4dc-085d9b6ec431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209924571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3209924571
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2654484364
Short name T734
Test name
Test status
Simulation time 14278416689 ps
CPU time 129.42 seconds
Started Jun 21 07:00:10 PM PDT 24
Finished Jun 21 07:02:26 PM PDT 24
Peak memory 249432 kb
Host smart-f8685759-c565-4b62-8a79-46f207a0042f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654484364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2654484364
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3052135676
Short name T808
Test name
Test status
Simulation time 2482885747 ps
CPU time 36.66 seconds
Started Jun 21 07:00:13 PM PDT 24
Finished Jun 21 07:00:56 PM PDT 24
Peak memory 233052 kb
Host smart-837aa393-f575-40bd-a852-75bab375f765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052135676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3052135676
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1403600825
Short name T575
Test name
Test status
Simulation time 216761752 ps
CPU time 2.51 seconds
Started Jun 21 07:00:10 PM PDT 24
Finished Jun 21 07:00:19 PM PDT 24
Peak memory 224660 kb
Host smart-58c590fa-a5b0-413b-98c7-b8c5c35ea5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403600825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1403600825
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2374776159
Short name T624
Test name
Test status
Simulation time 597952159 ps
CPU time 3.63 seconds
Started Jun 21 07:00:11 PM PDT 24
Finished Jun 21 07:00:21 PM PDT 24
Peak memory 232896 kb
Host smart-6c473e8d-ec4b-417f-a5b5-db716609ac01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374776159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2374776159
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.122445134
Short name T187
Test name
Test status
Simulation time 1916441867 ps
CPU time 24.58 seconds
Started Jun 21 07:00:16 PM PDT 24
Finished Jun 21 07:00:49 PM PDT 24
Peak memory 249016 kb
Host smart-dd096efe-0eec-49e4-8bb3-740f36f0131a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122445134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.122445134
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2508119842
Short name T159
Test name
Test status
Simulation time 4016507443 ps
CPU time 6.29 seconds
Started Jun 21 07:00:12 PM PDT 24
Finished Jun 21 07:00:25 PM PDT 24
Peak memory 232848 kb
Host smart-2270bca6-4822-42ea-99ad-f5fd5d342c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508119842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2508119842
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2585855905
Short name T856
Test name
Test status
Simulation time 799465608 ps
CPU time 11.2 seconds
Started Jun 21 07:00:11 PM PDT 24
Finished Jun 21 07:00:29 PM PDT 24
Peak memory 222080 kb
Host smart-829b136a-8f2e-41b1-88ea-1c8e49e79889
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2585855905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2585855905
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1303812283
Short name T517
Test name
Test status
Simulation time 18357805144 ps
CPU time 45.9 seconds
Started Jun 21 07:00:15 PM PDT 24
Finished Jun 21 07:01:07 PM PDT 24
Peak memory 216572 kb
Host smart-e0269a76-b107-4e18-bd5b-71aa7c622ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303812283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1303812283
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2704250519
Short name T413
Test name
Test status
Simulation time 2379470848 ps
CPU time 4.25 seconds
Started Jun 21 07:00:11 PM PDT 24
Finished Jun 21 07:00:22 PM PDT 24
Peak memory 216552 kb
Host smart-754fb74b-94e5-4825-9acc-988207668227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704250519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2704250519
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2423209542
Short name T553
Test name
Test status
Simulation time 230943872 ps
CPU time 1.93 seconds
Started Jun 21 07:00:14 PM PDT 24
Finished Jun 21 07:00:23 PM PDT 24
Peak memory 216448 kb
Host smart-58d1f2c9-fb9d-4226-844e-8b962da33240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423209542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2423209542
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.736617401
Short name T420
Test name
Test status
Simulation time 210123194 ps
CPU time 0.8 seconds
Started Jun 21 07:00:12 PM PDT 24
Finished Jun 21 07:00:19 PM PDT 24
Peak memory 206112 kb
Host smart-1991fb02-72f9-4e64-8222-a69ae447a3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736617401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.736617401
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.563289362
Short name T293
Test name
Test status
Simulation time 275766759 ps
CPU time 4.12 seconds
Started Jun 21 07:00:13 PM PDT 24
Finished Jun 21 07:00:24 PM PDT 24
Peak memory 232852 kb
Host smart-94b092b4-c997-47f1-ae6d-487bfe8ec024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563289362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.563289362
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2353294037
Short name T428
Test name
Test status
Simulation time 36063621 ps
CPU time 0.69 seconds
Started Jun 21 07:00:19 PM PDT 24
Finished Jun 21 07:00:28 PM PDT 24
Peak memory 205528 kb
Host smart-15d3963d-4d70-466e-bffe-92f1f5a1dc7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353294037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2353294037
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.629970163
Short name T720
Test name
Test status
Simulation time 1189509521 ps
CPU time 4.78 seconds
Started Jun 21 07:00:24 PM PDT 24
Finished Jun 21 07:00:38 PM PDT 24
Peak memory 232816 kb
Host smart-0bd0ad40-464c-423e-903a-1aca87e9a01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629970163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.629970163
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.572558748
Short name T703
Test name
Test status
Simulation time 19071699 ps
CPU time 0.82 seconds
Started Jun 21 07:00:13 PM PDT 24
Finished Jun 21 07:00:21 PM PDT 24
Peak memory 206724 kb
Host smart-f6c98bbc-cf57-4ad1-afa8-e1ff4bc883e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572558748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.572558748
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1515369382
Short name T931
Test name
Test status
Simulation time 2278550364 ps
CPU time 21.92 seconds
Started Jun 21 07:00:21 PM PDT 24
Finished Jun 21 07:00:51 PM PDT 24
Peak memory 241164 kb
Host smart-71a33747-9fc5-4d4f-a0e7-94eecfd98a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515369382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1515369382
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3658208195
Short name T635
Test name
Test status
Simulation time 24754670475 ps
CPU time 234.67 seconds
Started Jun 21 07:00:22 PM PDT 24
Finished Jun 21 07:04:26 PM PDT 24
Peak memory 249400 kb
Host smart-8e160b81-c1f1-426a-b273-baee7a8c3494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658208195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3658208195
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3974687293
Short name T316
Test name
Test status
Simulation time 459779127 ps
CPU time 11.93 seconds
Started Jun 21 07:00:22 PM PDT 24
Finished Jun 21 07:00:42 PM PDT 24
Peak memory 224672 kb
Host smart-8c83cb10-3483-4e74-9368-9b54a0e68c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974687293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3974687293
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2717713798
Short name T642
Test name
Test status
Simulation time 1282603380 ps
CPU time 3.15 seconds
Started Jun 21 07:00:21 PM PDT 24
Finished Jun 21 07:00:33 PM PDT 24
Peak memory 224560 kb
Host smart-ba3dbb28-b090-483f-8698-e8525a4ddca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717713798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2717713798
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1496347854
Short name T519
Test name
Test status
Simulation time 4075233189 ps
CPU time 40.76 seconds
Started Jun 21 07:00:20 PM PDT 24
Finished Jun 21 07:01:09 PM PDT 24
Peak memory 241164 kb
Host smart-ea756a6e-03fb-406c-845e-56d92e41dbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496347854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1496347854
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2045047831
Short name T666
Test name
Test status
Simulation time 3763292644 ps
CPU time 5.16 seconds
Started Jun 21 07:00:21 PM PDT 24
Finished Jun 21 07:00:35 PM PDT 24
Peak memory 232560 kb
Host smart-cd9acee4-1c33-4c9f-be79-fe04000a6fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045047831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2045047831
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1127547770
Short name T782
Test name
Test status
Simulation time 4274711699 ps
CPU time 6.15 seconds
Started Jun 21 07:00:21 PM PDT 24
Finished Jun 21 07:00:35 PM PDT 24
Peak memory 232992 kb
Host smart-a88599fa-7453-42ea-81a5-81517289207d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127547770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1127547770
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3231827617
Short name T446
Test name
Test status
Simulation time 95715864 ps
CPU time 4.2 seconds
Started Jun 21 07:00:25 PM PDT 24
Finished Jun 21 07:00:39 PM PDT 24
Peak memory 223172 kb
Host smart-db64bd37-12e5-48aa-b115-bfc46ce6af99
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3231827617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3231827617
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2730408317
Short name T45
Test name
Test status
Simulation time 112626740908 ps
CPU time 273.98 seconds
Started Jun 21 07:00:23 PM PDT 24
Finished Jun 21 07:05:06 PM PDT 24
Peak memory 254196 kb
Host smart-7a2b6724-2b18-4b39-81c9-1d085bd1e697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730408317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2730408317
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3344140023
Short name T952
Test name
Test status
Simulation time 8846546656 ps
CPU time 24.91 seconds
Started Jun 21 07:00:12 PM PDT 24
Finished Jun 21 07:00:43 PM PDT 24
Peak memory 216808 kb
Host smart-6e00efff-9943-442f-9e3c-82986a2f66b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344140023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3344140023
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3077636176
Short name T907
Test name
Test status
Simulation time 6251243780 ps
CPU time 6.71 seconds
Started Jun 21 07:00:10 PM PDT 24
Finished Jun 21 07:00:23 PM PDT 24
Peak memory 216508 kb
Host smart-301d667a-fa3c-4404-954a-54464ecd1ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077636176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3077636176
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1340005502
Short name T791
Test name
Test status
Simulation time 99224909 ps
CPU time 1.45 seconds
Started Jun 21 07:00:22 PM PDT 24
Finished Jun 21 07:00:32 PM PDT 24
Peak memory 216392 kb
Host smart-10e08545-819d-4e5f-8c45-b4f248b37e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340005502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1340005502
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.366024908
Short name T333
Test name
Test status
Simulation time 187214327 ps
CPU time 0.83 seconds
Started Jun 21 07:00:22 PM PDT 24
Finished Jun 21 07:00:31 PM PDT 24
Peak memory 206100 kb
Host smart-a76f5dcb-f807-47b9-a8d6-862c287d55f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366024908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.366024908
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3209030232
Short name T632
Test name
Test status
Simulation time 185517355 ps
CPU time 3.56 seconds
Started Jun 21 07:00:20 PM PDT 24
Finished Jun 21 07:00:32 PM PDT 24
Peak memory 224716 kb
Host smart-ee395709-bbc3-4ab2-8d27-ef1afa75109a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209030232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3209030232
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2470131035
Short name T117
Test name
Test status
Simulation time 43522711 ps
CPU time 0.76 seconds
Started Jun 21 07:00:21 PM PDT 24
Finished Jun 21 07:00:30 PM PDT 24
Peak memory 205464 kb
Host smart-71cc41ba-e0d9-427c-b7d9-3901f61ccf82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470131035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2470131035
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3548684346
Short name T49
Test name
Test status
Simulation time 108659154 ps
CPU time 3.39 seconds
Started Jun 21 07:00:20 PM PDT 24
Finished Jun 21 07:00:32 PM PDT 24
Peak memory 232872 kb
Host smart-2064cf61-5ecc-4a9f-a818-3250bbeb36bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548684346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3548684346
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.989867634
Short name T448
Test name
Test status
Simulation time 19569660 ps
CPU time 0.8 seconds
Started Jun 21 07:00:23 PM PDT 24
Finished Jun 21 07:00:32 PM PDT 24
Peak memory 206744 kb
Host smart-e04c2884-0b6b-432c-bd9a-fe084fc95a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989867634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.989867634
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2248090801
Short name T144
Test name
Test status
Simulation time 16726408192 ps
CPU time 50.16 seconds
Started Jun 21 07:00:22 PM PDT 24
Finished Jun 21 07:01:22 PM PDT 24
Peak memory 252384 kb
Host smart-de3f1ceb-779f-4c89-9e96-163603a5b350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248090801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2248090801
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2000740312
Short name T243
Test name
Test status
Simulation time 4213920158 ps
CPU time 86.08 seconds
Started Jun 21 07:00:22 PM PDT 24
Finished Jun 21 07:01:58 PM PDT 24
Peak memory 257616 kb
Host smart-a30eac47-ceef-4d2a-82a3-b642be060abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000740312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2000740312
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.237361458
Short name T772
Test name
Test status
Simulation time 92096505 ps
CPU time 5.12 seconds
Started Jun 21 07:00:20 PM PDT 24
Finished Jun 21 07:00:34 PM PDT 24
Peak memory 232760 kb
Host smart-ddd323d4-9afb-4874-a1ee-79b2e7feaaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237361458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.237361458
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.4275761377
Short name T882
Test name
Test status
Simulation time 119717648 ps
CPU time 2.99 seconds
Started Jun 21 07:00:19 PM PDT 24
Finished Jun 21 07:00:30 PM PDT 24
Peak memory 232884 kb
Host smart-1194fcc3-d78f-4102-b5bd-37f0c82ae290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275761377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.4275761377
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.4221864699
Short name T197
Test name
Test status
Simulation time 1673251563 ps
CPU time 8.19 seconds
Started Jun 21 07:00:21 PM PDT 24
Finished Jun 21 07:00:38 PM PDT 24
Peak memory 224556 kb
Host smart-ea49031e-38a4-4093-b458-7a245ee5d2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221864699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.4221864699
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1548563316
Short name T269
Test name
Test status
Simulation time 54129894332 ps
CPU time 39.67 seconds
Started Jun 21 07:00:22 PM PDT 24
Finished Jun 21 07:01:10 PM PDT 24
Peak memory 234892 kb
Host smart-921cfca8-d73a-4aad-a987-7dab473e311d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548563316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1548563316
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2210227297
Short name T565
Test name
Test status
Simulation time 724297049 ps
CPU time 6.08 seconds
Started Jun 21 07:00:23 PM PDT 24
Finished Jun 21 07:00:38 PM PDT 24
Peak memory 240460 kb
Host smart-fea2d998-a93b-4199-840e-d52425f2e549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210227297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2210227297
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1917361854
Short name T757
Test name
Test status
Simulation time 681963692 ps
CPU time 6.71 seconds
Started Jun 21 07:00:24 PM PDT 24
Finished Jun 21 07:00:40 PM PDT 24
Peak memory 219440 kb
Host smart-a8ce00c2-9965-42c1-bd69-705cc669e5d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1917361854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1917361854
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1864592583
Short name T307
Test name
Test status
Simulation time 77063999825 ps
CPU time 51.05 seconds
Started Jun 21 07:00:21 PM PDT 24
Finished Jun 21 07:01:21 PM PDT 24
Peak memory 241244 kb
Host smart-1ff47c78-91eb-4a7d-b51c-d6e402a90c63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864592583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1864592583
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1075764723
Short name T509
Test name
Test status
Simulation time 14377742 ps
CPU time 0.74 seconds
Started Jun 21 07:00:24 PM PDT 24
Finished Jun 21 07:00:35 PM PDT 24
Peak memory 205792 kb
Host smart-4a9dd4da-13d1-4ff1-a61c-a046033ed53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075764723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1075764723
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3943858154
Short name T819
Test name
Test status
Simulation time 3825156763 ps
CPU time 10.47 seconds
Started Jun 21 07:00:21 PM PDT 24
Finished Jun 21 07:00:40 PM PDT 24
Peak memory 216272 kb
Host smart-5287373b-f83d-44c7-956b-a5685add2e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943858154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3943858154
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3813184950
Short name T367
Test name
Test status
Simulation time 47211849 ps
CPU time 1.36 seconds
Started Jun 21 07:00:22 PM PDT 24
Finished Jun 21 07:00:33 PM PDT 24
Peak memory 216416 kb
Host smart-ae093b9b-3a49-473d-b4ad-d3d7a7a4c2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813184950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3813184950
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3278252843
Short name T358
Test name
Test status
Simulation time 56464776 ps
CPU time 0.78 seconds
Started Jun 21 07:00:23 PM PDT 24
Finished Jun 21 07:00:32 PM PDT 24
Peak memory 206104 kb
Host smart-bae8a1b7-a65c-40bb-a10c-0a4531da30d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278252843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3278252843
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3457239868
Short name T865
Test name
Test status
Simulation time 7019135423 ps
CPU time 13.08 seconds
Started Jun 21 07:00:22 PM PDT 24
Finished Jun 21 07:00:45 PM PDT 24
Peak memory 233000 kb
Host smart-c2ec1d25-7755-4e24-b966-3a63e2331ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457239868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3457239868
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3105502621
Short name T474
Test name
Test status
Simulation time 16050387 ps
CPU time 0.71 seconds
Started Jun 21 07:00:21 PM PDT 24
Finished Jun 21 07:00:30 PM PDT 24
Peak memory 205524 kb
Host smart-db9fae83-30c0-4a37-a1dd-63e65207aea4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105502621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3105502621
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.977920605
Short name T561
Test name
Test status
Simulation time 263625384 ps
CPU time 3.61 seconds
Started Jun 21 07:00:22 PM PDT 24
Finished Jun 21 07:00:35 PM PDT 24
Peak memory 224600 kb
Host smart-dc6d4278-c791-4716-b70e-08dcb54b5efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977920605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.977920605
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2690565088
Short name T536
Test name
Test status
Simulation time 20156013 ps
CPU time 0.76 seconds
Started Jun 21 07:00:20 PM PDT 24
Finished Jun 21 07:00:29 PM PDT 24
Peak memory 206748 kb
Host smart-0022c3ad-3f94-4c24-a13c-58c0ce5711eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690565088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2690565088
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3301457992
Short name T171
Test name
Test status
Simulation time 251680160671 ps
CPU time 488.06 seconds
Started Jun 21 07:00:23 PM PDT 24
Finished Jun 21 07:08:40 PM PDT 24
Peak memory 281544 kb
Host smart-93a60953-a2b4-494e-ae26-97b01f1a7a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301457992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3301457992
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1966242437
Short name T600
Test name
Test status
Simulation time 1606958918 ps
CPU time 14.27 seconds
Started Jun 21 07:00:21 PM PDT 24
Finished Jun 21 07:00:44 PM PDT 24
Peak memory 238180 kb
Host smart-2de47136-457c-4c96-8bbe-2ffbc77b3fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966242437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1966242437
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2767525674
Short name T813
Test name
Test status
Simulation time 38006315 ps
CPU time 2.05 seconds
Started Jun 21 07:00:21 PM PDT 24
Finished Jun 21 07:00:32 PM PDT 24
Peak memory 222828 kb
Host smart-4d6e6ebf-740a-4eaa-9f4b-3e4ef5f2e662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767525674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2767525674
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.18834431
Short name T640
Test name
Test status
Simulation time 805820329 ps
CPU time 2.77 seconds
Started Jun 21 07:00:25 PM PDT 24
Finished Jun 21 07:00:38 PM PDT 24
Peak memory 224480 kb
Host smart-916dc496-40cb-484c-b71e-372b4aa1bd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18834431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.18834431
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.132205718
Short name T612
Test name
Test status
Simulation time 7709879122 ps
CPU time 8.35 seconds
Started Jun 21 07:00:21 PM PDT 24
Finished Jun 21 07:00:38 PM PDT 24
Peak memory 224648 kb
Host smart-c0d03495-fcad-4f96-90a9-cefd493b218f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132205718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.132205718
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3503468824
Short name T713
Test name
Test status
Simulation time 4692814728 ps
CPU time 9.83 seconds
Started Jun 21 07:00:26 PM PDT 24
Finished Jun 21 07:00:45 PM PDT 24
Peak memory 233004 kb
Host smart-80faca6f-6a2e-4974-8b0e-b8b2eee0fe26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503468824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3503468824
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2087872606
Short name T863
Test name
Test status
Simulation time 466195542 ps
CPU time 4.36 seconds
Started Jun 21 07:00:23 PM PDT 24
Finished Jun 21 07:00:37 PM PDT 24
Peak memory 220108 kb
Host smart-cf4128c0-8028-487d-8730-f57eb5370600
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2087872606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2087872606
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1899441506
Short name T138
Test name
Test status
Simulation time 60987235 ps
CPU time 1.06 seconds
Started Jun 21 07:00:20 PM PDT 24
Finished Jun 21 07:00:30 PM PDT 24
Peak memory 207240 kb
Host smart-f4c12675-11f8-4fb8-896d-0a8a41010652
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899441506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1899441506
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2691927779
Short name T29
Test name
Test status
Simulation time 1476152915 ps
CPU time 3.74 seconds
Started Jun 21 07:00:22 PM PDT 24
Finished Jun 21 07:00:35 PM PDT 24
Peak memory 216724 kb
Host smart-e318ccd7-b6a8-4432-a2bb-e7d27a422d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691927779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2691927779
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1225711284
Short name T355
Test name
Test status
Simulation time 1550988031 ps
CPU time 2.28 seconds
Started Jun 21 07:00:22 PM PDT 24
Finished Jun 21 07:00:34 PM PDT 24
Peak memory 216380 kb
Host smart-4352b4a4-9214-48d4-9077-e3f6ab3e0998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225711284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1225711284
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3982048090
Short name T567
Test name
Test status
Simulation time 90256593 ps
CPU time 1.3 seconds
Started Jun 21 07:00:23 PM PDT 24
Finished Jun 21 07:00:33 PM PDT 24
Peak memory 216304 kb
Host smart-e2a4f1d6-6afa-467a-830c-1a8948f5cc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982048090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3982048090
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3977002965
Short name T547
Test name
Test status
Simulation time 34860112 ps
CPU time 0.78 seconds
Started Jun 21 07:00:25 PM PDT 24
Finished Jun 21 07:00:36 PM PDT 24
Peak memory 206112 kb
Host smart-e60bd67a-4be2-4c7c-9d55-6a296869898c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977002965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3977002965
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3798375790
Short name T292
Test name
Test status
Simulation time 3257558310 ps
CPU time 10.02 seconds
Started Jun 21 07:00:23 PM PDT 24
Finished Jun 21 07:00:42 PM PDT 24
Peak memory 224796 kb
Host smart-34d33361-4f5e-4127-b8be-a172c88bf91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798375790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3798375790
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1950490589
Short name T617
Test name
Test status
Simulation time 76335000 ps
CPU time 0.72 seconds
Started Jun 21 07:00:22 PM PDT 24
Finished Jun 21 07:00:32 PM PDT 24
Peak memory 204932 kb
Host smart-d2d78dfc-9bf8-4ffc-82a1-bb43faee8646
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950490589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1950490589
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3875508365
Short name T924
Test name
Test status
Simulation time 3310061901 ps
CPU time 10.56 seconds
Started Jun 21 07:00:25 PM PDT 24
Finished Jun 21 07:00:46 PM PDT 24
Peak memory 224632 kb
Host smart-0d107c52-a2b3-4237-939e-622f1f51795e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875508365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3875508365
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1287539566
Short name T489
Test name
Test status
Simulation time 16755104 ps
CPU time 0.79 seconds
Started Jun 21 07:00:25 PM PDT 24
Finished Jun 21 07:00:36 PM PDT 24
Peak memory 206728 kb
Host smart-d2784c80-4c61-4668-8279-4d4bc296fe6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287539566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1287539566
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3952755428
Short name T56
Test name
Test status
Simulation time 105463636003 ps
CPU time 211.7 seconds
Started Jun 21 07:00:23 PM PDT 24
Finished Jun 21 07:04:04 PM PDT 24
Peak memory 250888 kb
Host smart-e8434e86-b5c2-4d19-8023-690486c87225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952755428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3952755428
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3184037559
Short name T210
Test name
Test status
Simulation time 6167795676 ps
CPU time 121.37 seconds
Started Jun 21 07:00:22 PM PDT 24
Finished Jun 21 07:02:33 PM PDT 24
Peak memory 250440 kb
Host smart-829c37aa-ed12-4020-8e7c-6114ca2dfe34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184037559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3184037559
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.4042466150
Short name T220
Test name
Test status
Simulation time 24087115163 ps
CPU time 46.93 seconds
Started Jun 21 07:00:22 PM PDT 24
Finished Jun 21 07:01:18 PM PDT 24
Peak memory 231668 kb
Host smart-d723cea9-7c2a-4426-b99a-c630a6e7db18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042466150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.4042466150
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1452114221
Short name T764
Test name
Test status
Simulation time 19021591575 ps
CPU time 30.64 seconds
Started Jun 21 07:00:27 PM PDT 24
Finished Jun 21 07:01:08 PM PDT 24
Peak memory 232924 kb
Host smart-d17bbf9c-a592-404e-85df-405050c6a071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452114221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1452114221
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1180992330
Short name T893
Test name
Test status
Simulation time 312720547 ps
CPU time 2.11 seconds
Started Jun 21 07:00:22 PM PDT 24
Finished Jun 21 07:00:34 PM PDT 24
Peak memory 223056 kb
Host smart-517993fc-7392-4515-a660-d033b2f1a056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180992330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1180992330
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.271458716
Short name T773
Test name
Test status
Simulation time 4427152274 ps
CPU time 4.79 seconds
Started Jun 21 07:00:25 PM PDT 24
Finished Jun 21 07:00:40 PM PDT 24
Peak memory 224760 kb
Host smart-8df8c828-3635-4bf5-8124-2dded89c472f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271458716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.271458716
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3300861963
Short name T804
Test name
Test status
Simulation time 29458577775 ps
CPU time 7.56 seconds
Started Jun 21 07:00:25 PM PDT 24
Finished Jun 21 07:00:43 PM PDT 24
Peak memory 232980 kb
Host smart-37502776-3c8e-4f32-be44-1a935aeb0d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300861963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3300861963
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1203842401
Short name T39
Test name
Test status
Simulation time 4806933950 ps
CPU time 16 seconds
Started Jun 21 07:00:25 PM PDT 24
Finished Jun 21 07:00:51 PM PDT 24
Peak memory 240336 kb
Host smart-2f4487e1-d263-4ccb-9ff6-411d6e2ab7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203842401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1203842401
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2299513007
Short name T751
Test name
Test status
Simulation time 5013921472 ps
CPU time 13.1 seconds
Started Jun 21 07:00:28 PM PDT 24
Finished Jun 21 07:00:51 PM PDT 24
Peak memory 222364 kb
Host smart-6173dd80-3c1a-45a0-a259-1b355640d527
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2299513007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2299513007
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.887966818
Short name T682
Test name
Test status
Simulation time 2849997242 ps
CPU time 29.26 seconds
Started Jun 21 07:00:20 PM PDT 24
Finished Jun 21 07:00:58 PM PDT 24
Peak memory 216516 kb
Host smart-de80217e-06b5-4aa7-8b56-c414531389c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887966818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.887966818
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1498844003
Short name T684
Test name
Test status
Simulation time 12898815004 ps
CPU time 6.24 seconds
Started Jun 21 07:00:23 PM PDT 24
Finished Jun 21 07:00:39 PM PDT 24
Peak memory 216548 kb
Host smart-26a1db58-4e7a-4211-b283-4d4100c1e992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498844003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1498844003
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3877642028
Short name T940
Test name
Test status
Simulation time 301136811 ps
CPU time 1.93 seconds
Started Jun 21 07:00:22 PM PDT 24
Finished Jun 21 07:00:33 PM PDT 24
Peak memory 216464 kb
Host smart-81d9f23d-f095-4b83-8cc0-683130622bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877642028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3877642028
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2795276747
Short name T362
Test name
Test status
Simulation time 32712665 ps
CPU time 0.84 seconds
Started Jun 21 07:00:28 PM PDT 24
Finished Jun 21 07:00:39 PM PDT 24
Peak memory 207100 kb
Host smart-b9049c6b-7cb9-454d-be9d-6f76ece295da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795276747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2795276747
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.777494505
Short name T55
Test name
Test status
Simulation time 14590892 ps
CPU time 0.71 seconds
Started Jun 21 07:00:27 PM PDT 24
Finished Jun 21 07:00:39 PM PDT 24
Peak memory 205856 kb
Host smart-1dba17fb-8704-475f-b632-56c3e97270d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777494505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.777494505
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.588512940
Short name T815
Test name
Test status
Simulation time 200779501 ps
CPU time 4.58 seconds
Started Jun 21 07:00:32 PM PDT 24
Finished Jun 21 07:00:46 PM PDT 24
Peak memory 224684 kb
Host smart-28eccb07-9bf8-4b25-96a2-27c840095f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588512940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.588512940
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2578275511
Short name T363
Test name
Test status
Simulation time 12988828 ps
CPU time 0.78 seconds
Started Jun 21 07:00:31 PM PDT 24
Finished Jun 21 07:00:41 PM PDT 24
Peak memory 205700 kb
Host smart-c77e3718-bc6d-4e74-af6a-01d3ecdaa6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578275511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2578275511
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1543081353
Short name T796
Test name
Test status
Simulation time 13078214 ps
CPU time 0.79 seconds
Started Jun 21 07:00:33 PM PDT 24
Finished Jun 21 07:00:43 PM PDT 24
Peak memory 215964 kb
Host smart-8e53305e-172b-46b9-99f2-aa2de47e5fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543081353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1543081353
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3427248016
Short name T262
Test name
Test status
Simulation time 226330610981 ps
CPU time 593.96 seconds
Started Jun 21 07:00:31 PM PDT 24
Finished Jun 21 07:10:35 PM PDT 24
Peak memory 257016 kb
Host smart-d5a7dab9-e3de-4005-beeb-c5882d8e0f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427248016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3427248016
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1848901889
Short name T236
Test name
Test status
Simulation time 124813567971 ps
CPU time 559.55 seconds
Started Jun 21 07:00:32 PM PDT 24
Finished Jun 21 07:10:01 PM PDT 24
Peak memory 269432 kb
Host smart-cf3043bb-c335-451c-a05a-d9526500c6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848901889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1848901889
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.225123257
Short name T82
Test name
Test status
Simulation time 1569082429 ps
CPU time 7.64 seconds
Started Jun 21 07:00:30 PM PDT 24
Finished Jun 21 07:00:47 PM PDT 24
Peak memory 235748 kb
Host smart-6ddcd889-8e27-4cb2-b3ef-ef2a23c94543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225123257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.225123257
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3064710442
Short name T557
Test name
Test status
Simulation time 487942333 ps
CPU time 2.49 seconds
Started Jun 21 07:00:29 PM PDT 24
Finished Jun 21 07:00:41 PM PDT 24
Peak memory 224576 kb
Host smart-ff0c14ac-f8eb-4961-882f-a51be253a397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064710442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3064710442
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2117828537
Short name T769
Test name
Test status
Simulation time 74706365 ps
CPU time 3.32 seconds
Started Jun 21 07:00:32 PM PDT 24
Finished Jun 21 07:00:45 PM PDT 24
Peak memory 232868 kb
Host smart-84892607-3911-4cd8-94f5-6da1edef9eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117828537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2117828537
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2848883980
Short name T97
Test name
Test status
Simulation time 10998032931 ps
CPU time 31.89 seconds
Started Jun 21 07:00:28 PM PDT 24
Finished Jun 21 07:01:10 PM PDT 24
Peak memory 240808 kb
Host smart-e3918ffe-bf30-416f-918e-74f6eaed71c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848883980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2848883980
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1239405940
Short name T185
Test name
Test status
Simulation time 231787365 ps
CPU time 2.68 seconds
Started Jun 21 07:00:34 PM PDT 24
Finished Jun 21 07:00:45 PM PDT 24
Peak memory 232876 kb
Host smart-031463f7-3ed1-4ad2-974f-238eb026db69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239405940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1239405940
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2546971095
Short name T421
Test name
Test status
Simulation time 621983129 ps
CPU time 6.16 seconds
Started Jun 21 07:00:39 PM PDT 24
Finished Jun 21 07:00:54 PM PDT 24
Peak memory 219604 kb
Host smart-0762b347-dfaf-4cdc-8acc-54557b175036
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2546971095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2546971095
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1465473562
Short name T203
Test name
Test status
Simulation time 132380629716 ps
CPU time 381.15 seconds
Started Jun 21 07:00:28 PM PDT 24
Finished Jun 21 07:06:59 PM PDT 24
Peak memory 273964 kb
Host smart-0b59c89d-2d00-45f2-98e4-be7014a8bf7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465473562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1465473562
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2470131941
Short name T467
Test name
Test status
Simulation time 4953967736 ps
CPU time 28.14 seconds
Started Jun 21 07:00:34 PM PDT 24
Finished Jun 21 07:01:11 PM PDT 24
Peak memory 216544 kb
Host smart-de13344a-3e42-4dc4-bdf4-5e055c5aae7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470131941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2470131941
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.4085273670
Short name T346
Test name
Test status
Simulation time 1296528619 ps
CPU time 4.06 seconds
Started Jun 21 07:00:48 PM PDT 24
Finished Jun 21 07:00:58 PM PDT 24
Peak memory 216360 kb
Host smart-67607339-e789-4d10-b4c2-07dbf7cf5b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085273670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.4085273670
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.318155989
Short name T482
Test name
Test status
Simulation time 222948188 ps
CPU time 1.89 seconds
Started Jun 21 07:00:28 PM PDT 24
Finished Jun 21 07:00:41 PM PDT 24
Peak memory 216356 kb
Host smart-813a3f41-f79c-466c-a788-30f3b5318250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318155989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.318155989
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2287993970
Short name T543
Test name
Test status
Simulation time 62565828 ps
CPU time 0.93 seconds
Started Jun 21 07:00:30 PM PDT 24
Finished Jun 21 07:00:40 PM PDT 24
Peak memory 207120 kb
Host smart-c3cb0c5b-df77-43df-99ac-5e8998631260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287993970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2287993970
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2714912993
Short name T503
Test name
Test status
Simulation time 20672611883 ps
CPU time 14.45 seconds
Started Jun 21 07:00:31 PM PDT 24
Finished Jun 21 07:00:55 PM PDT 24
Peak memory 224740 kb
Host smart-3a04c9ca-aca0-4e9c-9d34-cbc085c7e075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714912993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2714912993
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1673452091
Short name T848
Test name
Test status
Simulation time 44082362 ps
CPU time 0.71 seconds
Started Jun 21 07:00:31 PM PDT 24
Finished Jun 21 07:00:41 PM PDT 24
Peak memory 205024 kb
Host smart-21cc8ff1-c03f-4577-9fd1-064576c41a44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673452091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1673452091
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3405518832
Short name T591
Test name
Test status
Simulation time 1425870443 ps
CPU time 7.77 seconds
Started Jun 21 07:00:29 PM PDT 24
Finished Jun 21 07:00:47 PM PDT 24
Peak memory 232832 kb
Host smart-badfe523-7ef8-4f88-b1f5-d31c7ffbc8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405518832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3405518832
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2418122044
Short name T480
Test name
Test status
Simulation time 15728430 ps
CPU time 0.8 seconds
Started Jun 21 07:00:33 PM PDT 24
Finished Jun 21 07:00:43 PM PDT 24
Peak memory 206724 kb
Host smart-7565bc92-18ee-4770-ac70-e7a4472c72a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418122044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2418122044
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.924291074
Short name T204
Test name
Test status
Simulation time 291538181721 ps
CPU time 528.91 seconds
Started Jun 21 07:00:32 PM PDT 24
Finished Jun 21 07:09:30 PM PDT 24
Peak memory 273664 kb
Host smart-7f87a6ac-db41-46a8-ac62-dc3b89dd9f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924291074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.924291074
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.498844664
Short name T760
Test name
Test status
Simulation time 31625317924 ps
CPU time 187.92 seconds
Started Jun 21 07:00:31 PM PDT 24
Finished Jun 21 07:03:48 PM PDT 24
Peak memory 249448 kb
Host smart-93af9806-8bab-49d1-a06f-c5fb66700ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498844664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.498844664
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.454399482
Short name T125
Test name
Test status
Simulation time 21778999188 ps
CPU time 54.75 seconds
Started Jun 21 07:00:31 PM PDT 24
Finished Jun 21 07:01:35 PM PDT 24
Peak memory 254108 kb
Host smart-27710eb5-3173-46d4-b2a0-bebf2d542950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454399482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.454399482
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.699817946
Short name T427
Test name
Test status
Simulation time 1192782891 ps
CPU time 5.23 seconds
Started Jun 21 07:00:30 PM PDT 24
Finished Jun 21 07:00:45 PM PDT 24
Peak memory 224684 kb
Host smart-dae516db-b3c3-4ca2-aa4e-a3c1fb958e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699817946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.699817946
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3830235285
Short name T301
Test name
Test status
Simulation time 1171006538 ps
CPU time 4.19 seconds
Started Jun 21 07:00:31 PM PDT 24
Finished Jun 21 07:00:45 PM PDT 24
Peak memory 224592 kb
Host smart-37f9e76e-e40d-4e68-8c7b-62026b0a0ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830235285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3830235285
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.4079253876
Short name T170
Test name
Test status
Simulation time 159757950 ps
CPU time 3.98 seconds
Started Jun 21 07:00:32 PM PDT 24
Finished Jun 21 07:00:45 PM PDT 24
Peak memory 232864 kb
Host smart-c82b6db7-9269-403c-971f-6ec94f944510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079253876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.4079253876
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.112075221
Short name T209
Test name
Test status
Simulation time 10875542538 ps
CPU time 8.04 seconds
Started Jun 21 07:00:31 PM PDT 24
Finished Jun 21 07:00:49 PM PDT 24
Peak memory 232876 kb
Host smart-04fa237e-7207-4154-b89a-29ed5b569917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112075221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.112075221
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1122617553
Short name T194
Test name
Test status
Simulation time 11889867230 ps
CPU time 19.39 seconds
Started Jun 21 07:00:30 PM PDT 24
Finished Jun 21 07:01:00 PM PDT 24
Peak memory 233016 kb
Host smart-3d984a2f-fcb3-4850-8eed-e9b449b00bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122617553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1122617553
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.433126742
Short name T616
Test name
Test status
Simulation time 4679628332 ps
CPU time 11.57 seconds
Started Jun 21 07:00:43 PM PDT 24
Finished Jun 21 07:01:02 PM PDT 24
Peak memory 223300 kb
Host smart-358a2e0b-32a3-47e8-80f8-4a729fd307a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=433126742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.433126742
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.623989064
Short name T205
Test name
Test status
Simulation time 46836526552 ps
CPU time 228.35 seconds
Started Jun 21 07:00:43 PM PDT 24
Finished Jun 21 07:04:39 PM PDT 24
Peak memory 267140 kb
Host smart-37d09e7d-32bb-4c4d-b193-baa7478fd9a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623989064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.623989064
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1917247351
Short name T457
Test name
Test status
Simulation time 6847525406 ps
CPU time 20.4 seconds
Started Jun 21 07:00:29 PM PDT 24
Finished Jun 21 07:01:00 PM PDT 24
Peak memory 216524 kb
Host smart-c04db804-c55d-4938-bf3e-9195944b9391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917247351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1917247351
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.428373949
Short name T378
Test name
Test status
Simulation time 1778830819 ps
CPU time 5.01 seconds
Started Jun 21 07:00:28 PM PDT 24
Finished Jun 21 07:00:43 PM PDT 24
Peak memory 216456 kb
Host smart-21490da2-2677-4329-86fb-d2ed69611c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428373949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.428373949
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1186548200
Short name T376
Test name
Test status
Simulation time 28027027 ps
CPU time 0.93 seconds
Started Jun 21 07:00:30 PM PDT 24
Finished Jun 21 07:00:41 PM PDT 24
Peak memory 207380 kb
Host smart-4a4aa8e8-336c-45de-9db2-807c781aa048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186548200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1186548200
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.213336990
Short name T438
Test name
Test status
Simulation time 96293068 ps
CPU time 0.77 seconds
Started Jun 21 07:00:35 PM PDT 24
Finished Jun 21 07:00:44 PM PDT 24
Peak memory 206080 kb
Host smart-70a37553-1fa8-45a0-afd8-79aba378f5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213336990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.213336990
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3278017948
Short name T299
Test name
Test status
Simulation time 11340374276 ps
CPU time 13.9 seconds
Started Jun 21 07:00:31 PM PDT 24
Finished Jun 21 07:00:54 PM PDT 24
Peak memory 249116 kb
Host smart-ba3e9dac-89ac-462a-8be9-5d0d40db67e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278017948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3278017948
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2023000881
Short name T674
Test name
Test status
Simulation time 24240181 ps
CPU time 0.71 seconds
Started Jun 21 07:00:41 PM PDT 24
Finished Jun 21 07:00:50 PM PDT 24
Peak memory 205540 kb
Host smart-a6434195-def2-473a-95cb-be457195c881
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023000881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2023000881
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.679559310
Short name T257
Test name
Test status
Simulation time 35113666 ps
CPU time 2.57 seconds
Started Jun 21 07:00:31 PM PDT 24
Finished Jun 21 07:00:44 PM PDT 24
Peak memory 232776 kb
Host smart-e25ef54b-5951-4780-9007-bbdfe6da9ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679559310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.679559310
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.636511298
Short name T491
Test name
Test status
Simulation time 34866057 ps
CPU time 0.74 seconds
Started Jun 21 07:00:35 PM PDT 24
Finished Jun 21 07:00:44 PM PDT 24
Peak memory 205704 kb
Host smart-257fc0d3-9f7f-45e2-ae89-c6df664009a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636511298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.636511298
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3179414048
Short name T761
Test name
Test status
Simulation time 72231930081 ps
CPU time 70.79 seconds
Started Jun 21 07:00:36 PM PDT 24
Finished Jun 21 07:01:56 PM PDT 24
Peak memory 256708 kb
Host smart-1e996834-5035-49e8-bf97-824f3091f89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179414048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3179414048
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2851084373
Short name T951
Test name
Test status
Simulation time 1416923650 ps
CPU time 21.94 seconds
Started Jun 21 07:00:32 PM PDT 24
Finished Jun 21 07:01:03 PM PDT 24
Peak memory 237996 kb
Host smart-f55af8a2-a421-4532-bfb6-fdddad34f51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851084373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2851084373
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2012969628
Short name T119
Test name
Test status
Simulation time 426379162 ps
CPU time 2.45 seconds
Started Jun 21 07:00:30 PM PDT 24
Finished Jun 21 07:00:42 PM PDT 24
Peak memory 232556 kb
Host smart-271926a1-6b6a-4ba6-aeef-dfe5e521c33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012969628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2012969628
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.250372986
Short name T678
Test name
Test status
Simulation time 33455786229 ps
CPU time 63.24 seconds
Started Jun 21 07:00:33 PM PDT 24
Finished Jun 21 07:01:45 PM PDT 24
Peak memory 235960 kb
Host smart-86530659-9d07-4ade-9238-737a2404ced5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250372986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.250372986
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3235743568
Short name T936
Test name
Test status
Simulation time 4972602668 ps
CPU time 4.71 seconds
Started Jun 21 07:00:34 PM PDT 24
Finished Jun 21 07:00:47 PM PDT 24
Peak memory 224684 kb
Host smart-0dfd2944-e5c3-4fbd-82b2-3a963a4acb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235743568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3235743568
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2323731234
Short name T569
Test name
Test status
Simulation time 166778923 ps
CPU time 2.84 seconds
Started Jun 21 07:00:36 PM PDT 24
Finished Jun 21 07:00:47 PM PDT 24
Peak memory 224636 kb
Host smart-70cf56ed-da33-49a3-8034-4e5e3d5d6363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323731234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2323731234
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.309890397
Short name T774
Test name
Test status
Simulation time 4857990254 ps
CPU time 11.91 seconds
Started Jun 21 07:00:31 PM PDT 24
Finished Jun 21 07:00:52 PM PDT 24
Peak memory 223316 kb
Host smart-308902bc-0c6f-4063-8cef-04a54ee7ae86
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=309890397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.309890397
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.4206376510
Short name T140
Test name
Test status
Simulation time 125825111086 ps
CPU time 263.13 seconds
Started Jun 21 07:00:43 PM PDT 24
Finished Jun 21 07:05:13 PM PDT 24
Peak memory 257632 kb
Host smart-403358ee-85e2-4ef5-b6cc-c96aa319069b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206376510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.4206376510
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3260962659
Short name T835
Test name
Test status
Simulation time 54050549 ps
CPU time 0.68 seconds
Started Jun 21 07:00:32 PM PDT 24
Finished Jun 21 07:00:42 PM PDT 24
Peak memory 205812 kb
Host smart-e054ac77-8637-4437-85cc-a3f6b7457226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260962659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3260962659
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3956550236
Short name T384
Test name
Test status
Simulation time 53997710906 ps
CPU time 18.23 seconds
Started Jun 21 07:00:32 PM PDT 24
Finished Jun 21 07:00:59 PM PDT 24
Peak memory 216548 kb
Host smart-6a126ad5-0fd7-4e1f-8fd5-f3bdf219e052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956550236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3956550236
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2303566124
Short name T923
Test name
Test status
Simulation time 12918359 ps
CPU time 0.78 seconds
Started Jun 21 07:00:33 PM PDT 24
Finished Jun 21 07:00:43 PM PDT 24
Peak memory 206112 kb
Host smart-251fe12b-9c8d-4a75-9244-85a74340316f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303566124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2303566124
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3005688573
Short name T368
Test name
Test status
Simulation time 115027956 ps
CPU time 0.86 seconds
Started Jun 21 07:00:32 PM PDT 24
Finished Jun 21 07:00:42 PM PDT 24
Peak memory 206112 kb
Host smart-1c6f819d-e350-4d26-a617-9010c1fd544f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005688573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3005688573
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3306895105
Short name T177
Test name
Test status
Simulation time 680161114 ps
CPU time 3.8 seconds
Started Jun 21 07:00:30 PM PDT 24
Finished Jun 21 07:00:43 PM PDT 24
Peak memory 232876 kb
Host smart-52981f20-d7a8-41a1-beb6-3bf439ca3fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306895105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3306895105
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.4210492699
Short name T435
Test name
Test status
Simulation time 162529437 ps
CPU time 0.71 seconds
Started Jun 21 07:00:39 PM PDT 24
Finished Jun 21 07:00:47 PM PDT 24
Peak memory 205524 kb
Host smart-84d8ba16-2976-47f9-97c4-8061c2806337
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210492699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
4210492699
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2181218440
Short name T888
Test name
Test status
Simulation time 493127209 ps
CPU time 2.92 seconds
Started Jun 21 07:00:43 PM PDT 24
Finished Jun 21 07:00:54 PM PDT 24
Peak memory 224676 kb
Host smart-3ee8c865-9acf-420d-a2bf-76beb40f5cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181218440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2181218440
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.885750591
Short name T419
Test name
Test status
Simulation time 83797047 ps
CPU time 0.76 seconds
Started Jun 21 07:00:46 PM PDT 24
Finished Jun 21 07:00:53 PM PDT 24
Peak memory 206740 kb
Host smart-7ff01c8c-07ce-4e6c-afcc-4891a2dc645a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885750591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.885750591
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2793253430
Short name T73
Test name
Test status
Simulation time 29924911607 ps
CPU time 144.28 seconds
Started Jun 21 07:00:42 PM PDT 24
Finished Jun 21 07:03:14 PM PDT 24
Peak memory 257576 kb
Host smart-fbcbf4f4-cea6-4165-85a9-1ae7b32008ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793253430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2793253430
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3148694258
Short name T717
Test name
Test status
Simulation time 47146077316 ps
CPU time 128.29 seconds
Started Jun 21 07:00:39 PM PDT 24
Finished Jun 21 07:02:55 PM PDT 24
Peak memory 249200 kb
Host smart-837cb531-343d-492b-b3c7-d2cd738acfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148694258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3148694258
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.4147510238
Short name T696
Test name
Test status
Simulation time 138905504 ps
CPU time 2.55 seconds
Started Jun 21 07:00:40 PM PDT 24
Finished Jun 21 07:00:50 PM PDT 24
Peak memory 224612 kb
Host smart-9d01669b-82c8-4fe5-9880-929c8426bc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147510238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.4147510238
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3082350615
Short name T818
Test name
Test status
Simulation time 84928354 ps
CPU time 2.89 seconds
Started Jun 21 07:00:43 PM PDT 24
Finished Jun 21 07:00:54 PM PDT 24
Peak memory 232892 kb
Host smart-c0cb2d2f-b530-474d-b99a-c4641941478c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082350615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3082350615
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.673254335
Short name T452
Test name
Test status
Simulation time 64148583735 ps
CPU time 28.99 seconds
Started Jun 21 07:00:49 PM PDT 24
Finished Jun 21 07:01:24 PM PDT 24
Peak memory 232944 kb
Host smart-c21b795d-b73e-4ce2-b6f5-840c0cf3d3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673254335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.673254335
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2054337174
Short name T621
Test name
Test status
Simulation time 12861653242 ps
CPU time 12.51 seconds
Started Jun 21 07:00:41 PM PDT 24
Finished Jun 21 07:01:01 PM PDT 24
Peak memory 232940 kb
Host smart-956c821c-ccef-4707-af83-d232c7343f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054337174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2054337174
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2839381288
Short name T286
Test name
Test status
Simulation time 25280464121 ps
CPU time 13.11 seconds
Started Jun 21 07:00:44 PM PDT 24
Finished Jun 21 07:01:04 PM PDT 24
Peak memory 224768 kb
Host smart-679c946c-0515-4777-bdf6-cead49728bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839381288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2839381288
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3248780017
Short name T447
Test name
Test status
Simulation time 273602157 ps
CPU time 3.12 seconds
Started Jun 21 07:00:40 PM PDT 24
Finished Jun 21 07:00:51 PM PDT 24
Peak memory 220232 kb
Host smart-754b74ba-a229-42a1-8153-fedfefa6c344
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3248780017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3248780017
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2989948971
Short name T854
Test name
Test status
Simulation time 42950580 ps
CPU time 0.99 seconds
Started Jun 21 07:00:44 PM PDT 24
Finished Jun 21 07:00:53 PM PDT 24
Peak memory 207072 kb
Host smart-ed73bf68-64b2-4128-a8c0-ad4408c8434e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989948971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2989948971
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.4205022619
Short name T387
Test name
Test status
Simulation time 44126211 ps
CPU time 0.72 seconds
Started Jun 21 07:00:42 PM PDT 24
Finished Jun 21 07:00:50 PM PDT 24
Peak memory 205780 kb
Host smart-e58255ab-dc89-4a53-9e1e-a2ee4603aaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205022619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.4205022619
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2072894740
Short name T930
Test name
Test status
Simulation time 36027922 ps
CPU time 0.7 seconds
Started Jun 21 07:00:49 PM PDT 24
Finished Jun 21 07:00:56 PM PDT 24
Peak memory 205772 kb
Host smart-ce1b8b33-3b55-4645-91dc-7cfa331a8499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072894740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2072894740
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.469145961
Short name T405
Test name
Test status
Simulation time 125294680 ps
CPU time 2.38 seconds
Started Jun 21 07:00:45 PM PDT 24
Finished Jun 21 07:00:54 PM PDT 24
Peak memory 216404 kb
Host smart-65fc6c10-a3c5-400b-b942-beeb6b4a1424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469145961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.469145961
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2672485642
Short name T755
Test name
Test status
Simulation time 25971920 ps
CPU time 0.78 seconds
Started Jun 21 07:00:40 PM PDT 24
Finished Jun 21 07:00:49 PM PDT 24
Peak memory 206120 kb
Host smart-f32514de-97f8-44cc-bd96-f7a42be0ca8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672485642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2672485642
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2183994406
Short name T432
Test name
Test status
Simulation time 7051376571 ps
CPU time 20.36 seconds
Started Jun 21 07:00:42 PM PDT 24
Finished Jun 21 07:01:11 PM PDT 24
Peak memory 232624 kb
Host smart-9ca56cb4-ca97-427d-850a-b6ba753311a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183994406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2183994406
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.4117815739
Short name T7
Test name
Test status
Simulation time 14539512 ps
CPU time 0.73 seconds
Started Jun 21 06:59:41 PM PDT 24
Finished Jun 21 06:59:46 PM PDT 24
Peak memory 205564 kb
Host smart-b2a3ec72-1ad3-4f00-abf1-636b782900ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117815739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.4
117815739
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1899960784
Short name T298
Test name
Test status
Simulation time 202049154 ps
CPU time 3.5 seconds
Started Jun 21 06:59:44 PM PDT 24
Finished Jun 21 06:59:52 PM PDT 24
Peak memory 232788 kb
Host smart-11988bef-5c73-4ce2-a9f6-42fc17eb412c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899960784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1899960784
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.321166951
Short name T876
Test name
Test status
Simulation time 134537663 ps
CPU time 0.78 seconds
Started Jun 21 06:59:41 PM PDT 24
Finished Jun 21 06:59:45 PM PDT 24
Peak memory 206736 kb
Host smart-e9128d64-f841-42a3-9a61-469348d900ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321166951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.321166951
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1610488430
Short name T230
Test name
Test status
Simulation time 55058260826 ps
CPU time 145.28 seconds
Started Jun 21 06:59:40 PM PDT 24
Finished Jun 21 07:02:09 PM PDT 24
Peak memory 256016 kb
Host smart-edfcd3e8-6412-4360-baf8-4b2dec9a30ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610488430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1610488430
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2323794689
Short name T821
Test name
Test status
Simulation time 8124851605 ps
CPU time 26.55 seconds
Started Jun 21 06:59:44 PM PDT 24
Finished Jun 21 07:00:15 PM PDT 24
Peak memory 217616 kb
Host smart-cc0ec50d-8ec7-481a-ac1d-ce09f0407068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323794689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2323794689
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1459323889
Short name T463
Test name
Test status
Simulation time 90881355 ps
CPU time 0.81 seconds
Started Jun 21 06:59:43 PM PDT 24
Finished Jun 21 06:59:49 PM PDT 24
Peak memory 217264 kb
Host smart-15306adb-ae0b-492c-8a07-22b5db6a217e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459323889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1459323889
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.783918729
Short name T311
Test name
Test status
Simulation time 652281645 ps
CPU time 11.64 seconds
Started Jun 21 06:59:43 PM PDT 24
Finished Jun 21 06:59:59 PM PDT 24
Peak memory 232948 kb
Host smart-d3bd4585-3e93-4d0e-bed8-3b4488e585b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783918729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.783918729
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2999457270
Short name T763
Test name
Test status
Simulation time 31981373 ps
CPU time 2.02 seconds
Started Jun 21 06:59:43 PM PDT 24
Finished Jun 21 06:59:50 PM PDT 24
Peak memory 224532 kb
Host smart-0d781b69-3d61-4b18-8988-ad3101c564d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999457270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2999457270
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.4114742523
Short name T622
Test name
Test status
Simulation time 1119859588 ps
CPU time 18.31 seconds
Started Jun 21 06:59:44 PM PDT 24
Finished Jun 21 07:00:07 PM PDT 24
Peak memory 232848 kb
Host smart-e285fd22-e675-46d5-aa37-8bce2d755b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114742523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.4114742523
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1137991344
Short name T950
Test name
Test status
Simulation time 122973657 ps
CPU time 3.02 seconds
Started Jun 21 06:59:39 PM PDT 24
Finished Jun 21 06:59:44 PM PDT 24
Peak memory 232828 kb
Host smart-28189675-f2a7-4492-8be6-234f73db1bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137991344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1137991344
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3919516614
Short name T515
Test name
Test status
Simulation time 862263308 ps
CPU time 4.21 seconds
Started Jun 21 06:59:44 PM PDT 24
Finished Jun 21 06:59:53 PM PDT 24
Peak memory 224620 kb
Host smart-c0db385a-7535-4723-9b69-855092ddae99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919516614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3919516614
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2198246602
Short name T855
Test name
Test status
Simulation time 337320492 ps
CPU time 3.6 seconds
Started Jun 21 06:59:45 PM PDT 24
Finished Jun 21 06:59:54 PM PDT 24
Peak memory 222732 kb
Host smart-09450ac1-0b86-46f3-8cea-17083d04fffa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2198246602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2198246602
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.4089572154
Short name T762
Test name
Test status
Simulation time 1486814157 ps
CPU time 8.25 seconds
Started Jun 21 06:59:44 PM PDT 24
Finished Jun 21 06:59:56 PM PDT 24
Peak memory 216404 kb
Host smart-d6c7eacb-bfff-4ae1-98ca-cffb4bc40ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089572154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.4089572154
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3094256249
Short name T406
Test name
Test status
Simulation time 13394196 ps
CPU time 0.73 seconds
Started Jun 21 06:59:43 PM PDT 24
Finished Jun 21 06:59:49 PM PDT 24
Peak memory 205780 kb
Host smart-e9f24417-fa27-4677-9aa9-6d0e0dd025e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094256249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3094256249
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2191313146
Short name T716
Test name
Test status
Simulation time 29775803 ps
CPU time 1.01 seconds
Started Jun 21 06:59:45 PM PDT 24
Finished Jun 21 06:59:51 PM PDT 24
Peak memory 208100 kb
Host smart-794b77d1-4d0d-437e-a441-cd17338ddb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191313146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2191313146
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1075203718
Short name T544
Test name
Test status
Simulation time 32312506 ps
CPU time 0.79 seconds
Started Jun 21 06:59:43 PM PDT 24
Finished Jun 21 06:59:48 PM PDT 24
Peak memory 206084 kb
Host smart-512b367a-3d53-4a4f-bdf5-c90306850980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075203718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1075203718
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1771063545
Short name T570
Test name
Test status
Simulation time 5402004044 ps
CPU time 7.93 seconds
Started Jun 21 06:59:40 PM PDT 24
Finished Jun 21 06:59:50 PM PDT 24
Peak memory 224760 kb
Host smart-14a3091d-5777-4313-bcf7-ac1c1b2868c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771063545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1771063545
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1300360922
Short name T562
Test name
Test status
Simulation time 30920999 ps
CPU time 0.7 seconds
Started Jun 21 07:00:39 PM PDT 24
Finished Jun 21 07:00:48 PM PDT 24
Peak memory 205532 kb
Host smart-567cc53c-ea53-4118-be79-a9dda7c2dfec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300360922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1300360922
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1479692763
Short name T549
Test name
Test status
Simulation time 965800688 ps
CPU time 4.5 seconds
Started Jun 21 07:00:47 PM PDT 24
Finished Jun 21 07:00:58 PM PDT 24
Peak memory 232828 kb
Host smart-6045fc1e-7086-4c16-8e3e-f0583aa2132d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479692763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1479692763
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1721083044
Short name T380
Test name
Test status
Simulation time 23664030 ps
CPU time 0.78 seconds
Started Jun 21 07:00:40 PM PDT 24
Finished Jun 21 07:00:49 PM PDT 24
Peak memory 206724 kb
Host smart-0be29717-2434-4ec2-b3ba-c0769f1a6923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721083044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1721083044
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1764122993
Short name T610
Test name
Test status
Simulation time 24659730 ps
CPU time 0.76 seconds
Started Jun 21 07:00:41 PM PDT 24
Finished Jun 21 07:00:50 PM PDT 24
Peak memory 215912 kb
Host smart-64796137-0daa-494e-9bb8-7d86e462c720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764122993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1764122993
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.4015944638
Short name T214
Test name
Test status
Simulation time 41547760982 ps
CPU time 423.35 seconds
Started Jun 21 07:00:44 PM PDT 24
Finished Jun 21 07:07:55 PM PDT 24
Peak memory 256492 kb
Host smart-d4477aab-4ea1-4a25-bb46-ac4c65acf7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015944638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.4015944638
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3142811791
Short name T814
Test name
Test status
Simulation time 5406193396 ps
CPU time 31.94 seconds
Started Jun 21 07:00:42 PM PDT 24
Finished Jun 21 07:01:21 PM PDT 24
Peak memory 217864 kb
Host smart-25c1eb01-5c95-4976-9f49-cb2d2e45b502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142811791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3142811791
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3572812809
Short name T129
Test name
Test status
Simulation time 436061604 ps
CPU time 5 seconds
Started Jun 21 07:00:46 PM PDT 24
Finished Jun 21 07:00:58 PM PDT 24
Peak memory 220856 kb
Host smart-b0a049db-98d9-4c77-a3e4-d240d45d1d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572812809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3572812809
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.270722098
Short name T478
Test name
Test status
Simulation time 1259323794 ps
CPU time 7.48 seconds
Started Jun 21 07:00:39 PM PDT 24
Finished Jun 21 07:00:55 PM PDT 24
Peak memory 232860 kb
Host smart-ecc7a425-7493-46e2-b518-d7325dd182bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270722098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.270722098
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2888042856
Short name T582
Test name
Test status
Simulation time 1686969543 ps
CPU time 7.71 seconds
Started Jun 21 07:00:51 PM PDT 24
Finished Jun 21 07:01:04 PM PDT 24
Peak memory 238360 kb
Host smart-f7c555da-5c62-4d9b-907d-950671431459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888042856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2888042856
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.119952284
Short name T165
Test name
Test status
Simulation time 613817684 ps
CPU time 4.19 seconds
Started Jun 21 07:00:39 PM PDT 24
Finished Jun 21 07:00:51 PM PDT 24
Peak memory 224612 kb
Host smart-af0d0aa3-4512-4b6b-b1cd-5baa78bd0580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119952284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.119952284
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2165012249
Short name T481
Test name
Test status
Simulation time 6914048130 ps
CPU time 6.69 seconds
Started Jun 21 07:00:46 PM PDT 24
Finished Jun 21 07:01:00 PM PDT 24
Peak memory 232944 kb
Host smart-4367c451-f2a3-4f8c-a34e-4ef07f27f78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165012249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2165012249
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1526323159
Short name T709
Test name
Test status
Simulation time 13760857018 ps
CPU time 11.06 seconds
Started Jun 21 07:00:41 PM PDT 24
Finished Jun 21 07:01:00 PM PDT 24
Peak memory 219256 kb
Host smart-458bc73d-9339-4ecb-83c8-69dc5e0557df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1526323159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1526323159
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2957270908
Short name T577
Test name
Test status
Simulation time 90452704 ps
CPU time 1.11 seconds
Started Jun 21 07:00:43 PM PDT 24
Finished Jun 21 07:00:51 PM PDT 24
Peak memory 207920 kb
Host smart-84e08127-1fa3-4615-a9b2-65cffa351e33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957270908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2957270908
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.559745658
Short name T321
Test name
Test status
Simulation time 17998014889 ps
CPU time 17.4 seconds
Started Jun 21 07:00:42 PM PDT 24
Finished Jun 21 07:01:07 PM PDT 24
Peak memory 216748 kb
Host smart-0ecdf4af-4013-40a7-a85d-dce0847af8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559745658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.559745658
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3587790476
Short name T599
Test name
Test status
Simulation time 2784598596 ps
CPU time 4.73 seconds
Started Jun 21 07:00:41 PM PDT 24
Finished Jun 21 07:00:54 PM PDT 24
Peak memory 216572 kb
Host smart-27de4cc4-f8a0-4300-9b4e-08ab5f1323a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587790476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3587790476
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1091004676
Short name T850
Test name
Test status
Simulation time 58105229 ps
CPU time 0.92 seconds
Started Jun 21 07:00:40 PM PDT 24
Finished Jun 21 07:00:49 PM PDT 24
Peak memory 206860 kb
Host smart-aa7bb884-c5a7-441f-a883-021f655159c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091004676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1091004676
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1728816752
Short name T414
Test name
Test status
Simulation time 69591040 ps
CPU time 0.91 seconds
Started Jun 21 07:00:45 PM PDT 24
Finished Jun 21 07:00:53 PM PDT 24
Peak memory 207116 kb
Host smart-09e85482-8491-4f8f-a563-e445a48c436f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728816752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1728816752
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1825867640
Short name T939
Test name
Test status
Simulation time 627246898 ps
CPU time 6.12 seconds
Started Jun 21 07:00:48 PM PDT 24
Finished Jun 21 07:01:00 PM PDT 24
Peak memory 239464 kb
Host smart-27e5add3-d44d-42e9-9a75-27f28e4a6857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825867640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1825867640
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1224689134
Short name T646
Test name
Test status
Simulation time 21071808 ps
CPU time 0.75 seconds
Started Jun 21 07:00:50 PM PDT 24
Finished Jun 21 07:00:56 PM PDT 24
Peak memory 205552 kb
Host smart-2abd3cea-f18f-4004-9740-8f7119b5bbf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224689134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1224689134
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1775410620
Short name T555
Test name
Test status
Simulation time 40863370 ps
CPU time 2.38 seconds
Started Jun 21 07:00:48 PM PDT 24
Finished Jun 21 07:00:57 PM PDT 24
Peak memory 224552 kb
Host smart-08098b32-70d7-4920-afd6-f26f15a8ad1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775410620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1775410620
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1368341186
Short name T344
Test name
Test status
Simulation time 13465721 ps
CPU time 0.78 seconds
Started Jun 21 07:00:46 PM PDT 24
Finished Jun 21 07:00:54 PM PDT 24
Peak memory 206716 kb
Host smart-b02d5906-58c0-4e7a-b368-c749df9983e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368341186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1368341186
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.51337172
Short name T290
Test name
Test status
Simulation time 1182050232 ps
CPU time 19.95 seconds
Started Jun 21 07:00:53 PM PDT 24
Finished Jun 21 07:01:19 PM PDT 24
Peak memory 249472 kb
Host smart-30d45327-593a-47c5-a016-008b527fc6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51337172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.51337172
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1746625485
Short name T779
Test name
Test status
Simulation time 24355630410 ps
CPU time 166.68 seconds
Started Jun 21 07:00:48 PM PDT 24
Finished Jun 21 07:03:41 PM PDT 24
Peak memory 250596 kb
Host smart-802e10dc-1e12-4145-9d83-04eaff84269d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746625485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1746625485
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1073023799
Short name T506
Test name
Test status
Simulation time 18994923699 ps
CPU time 155.26 seconds
Started Jun 21 07:00:58 PM PDT 24
Finished Jun 21 07:03:40 PM PDT 24
Peak memory 257284 kb
Host smart-b869ec17-0b24-4ba0-8289-35203ac1590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073023799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1073023799
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2678303228
Short name T338
Test name
Test status
Simulation time 1231125243 ps
CPU time 5.77 seconds
Started Jun 21 07:00:51 PM PDT 24
Finished Jun 21 07:01:02 PM PDT 24
Peak memory 219928 kb
Host smart-f80c780d-7e67-4492-9406-daec1e9dbe80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678303228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2678303228
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1433700226
Short name T731
Test name
Test status
Simulation time 1557384237 ps
CPU time 14.46 seconds
Started Jun 21 07:00:43 PM PDT 24
Finished Jun 21 07:01:05 PM PDT 24
Peak memory 232864 kb
Host smart-9aac98a6-f405-4896-92b1-69f6ad7ce6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433700226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1433700226
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2224616382
Short name T900
Test name
Test status
Simulation time 4479608586 ps
CPU time 10.65 seconds
Started Jun 21 07:00:54 PM PDT 24
Finished Jun 21 07:01:10 PM PDT 24
Peak memory 232920 kb
Host smart-baa76d3a-351c-47a5-8380-b0d2705b5eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224616382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2224616382
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.873256154
Short name T919
Test name
Test status
Simulation time 4265663159 ps
CPU time 3.66 seconds
Started Jun 21 07:00:40 PM PDT 24
Finished Jun 21 07:00:52 PM PDT 24
Peak memory 224732 kb
Host smart-5bfa8b5b-d999-417b-a33b-58b6d706daac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873256154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.873256154
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1832483462
Short name T603
Test name
Test status
Simulation time 1383819392 ps
CPU time 5.03 seconds
Started Jun 21 07:00:49 PM PDT 24
Finished Jun 21 07:01:00 PM PDT 24
Peak memory 224668 kb
Host smart-a67df15c-05dd-4d57-8ab0-1ee63792b695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832483462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1832483462
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3857406193
Short name T792
Test name
Test status
Simulation time 935999076 ps
CPU time 6.79 seconds
Started Jun 21 07:00:51 PM PDT 24
Finished Jun 21 07:01:03 PM PDT 24
Peak memory 223340 kb
Host smart-cc16e596-f14a-40ef-9aca-56d3c98e0d50
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3857406193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3857406193
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3582450584
Short name T783
Test name
Test status
Simulation time 108936865 ps
CPU time 1.12 seconds
Started Jun 21 07:00:49 PM PDT 24
Finished Jun 21 07:00:56 PM PDT 24
Peak memory 207064 kb
Host smart-a76031bc-b75b-42a4-b803-0b77560b7850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582450584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3582450584
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3787257034
Short name T700
Test name
Test status
Simulation time 4575591594 ps
CPU time 16.34 seconds
Started Jun 21 07:00:42 PM PDT 24
Finished Jun 21 07:01:06 PM PDT 24
Peak memory 216960 kb
Host smart-bb7e50d9-e21c-466e-baf6-a3d1b76067f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787257034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3787257034
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2042461064
Short name T904
Test name
Test status
Simulation time 32679049332 ps
CPU time 22.4 seconds
Started Jun 21 07:00:40 PM PDT 24
Finished Jun 21 07:01:11 PM PDT 24
Peak memory 216640 kb
Host smart-1c35916c-8649-4243-bcd9-2829dda6a14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042461064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2042461064
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3850775774
Short name T331
Test name
Test status
Simulation time 28945324 ps
CPU time 1 seconds
Started Jun 21 07:00:40 PM PDT 24
Finished Jun 21 07:00:49 PM PDT 24
Peak memory 207648 kb
Host smart-3e13420c-42ba-4a05-a550-d24deba10de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850775774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3850775774
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3712196701
Short name T581
Test name
Test status
Simulation time 64003158 ps
CPU time 0.77 seconds
Started Jun 21 07:00:40 PM PDT 24
Finished Jun 21 07:00:48 PM PDT 24
Peak memory 206072 kb
Host smart-134e9f94-fa05-42b4-a714-3c5d6aaf7fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712196701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3712196701
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.654719852
Short name T466
Test name
Test status
Simulation time 17710812537 ps
CPU time 15.82 seconds
Started Jun 21 07:00:51 PM PDT 24
Finished Jun 21 07:01:12 PM PDT 24
Peak memory 239568 kb
Host smart-b9f312c0-cfbe-4b0a-87d3-c54f248a7387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654719852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.654719852
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.703975455
Short name T479
Test name
Test status
Simulation time 12596062 ps
CPU time 0.78 seconds
Started Jun 21 07:00:55 PM PDT 24
Finished Jun 21 07:01:01 PM PDT 24
Peak memory 205856 kb
Host smart-284fe7ec-1fc2-4c83-a9bf-3420fae08408
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703975455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.703975455
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.91761690
Short name T840
Test name
Test status
Simulation time 1098489490 ps
CPU time 3.23 seconds
Started Jun 21 07:00:48 PM PDT 24
Finished Jun 21 07:00:58 PM PDT 24
Peak memory 232856 kb
Host smart-21aaa136-f261-4c1b-9d67-23b68e5bbaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91761690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.91761690
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2214930604
Short name T866
Test name
Test status
Simulation time 76930187 ps
CPU time 0.77 seconds
Started Jun 21 07:00:53 PM PDT 24
Finished Jun 21 07:00:59 PM PDT 24
Peak memory 206704 kb
Host smart-3f3bcab8-f865-44ab-95eb-8b93d856b75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214930604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2214930604
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3454734698
Short name T556
Test name
Test status
Simulation time 33472301241 ps
CPU time 61.67 seconds
Started Jun 21 07:00:48 PM PDT 24
Finished Jun 21 07:01:56 PM PDT 24
Peak memory 249396 kb
Host smart-1e19eb4d-c916-4d6f-b014-a41df33d1f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454734698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3454734698
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.558169050
Short name T422
Test name
Test status
Simulation time 31674102082 ps
CPU time 272.55 seconds
Started Jun 21 07:00:51 PM PDT 24
Finished Jun 21 07:05:29 PM PDT 24
Peak memory 250552 kb
Host smart-d06c9329-71a8-4086-859d-da8f94918e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558169050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.558169050
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3870959317
Short name T918
Test name
Test status
Simulation time 3203137080 ps
CPU time 63.59 seconds
Started Jun 21 07:00:59 PM PDT 24
Finished Jun 21 07:02:08 PM PDT 24
Peak memory 257184 kb
Host smart-8c385f59-c471-47b7-84e4-d82cf0655487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870959317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3870959317
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.4106519198
Short name T315
Test name
Test status
Simulation time 2516881190 ps
CPU time 13.29 seconds
Started Jun 21 07:00:56 PM PDT 24
Finished Jun 21 07:01:15 PM PDT 24
Peak memory 232968 kb
Host smart-ba23941b-3319-4b6c-b056-ccc45433433d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106519198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.4106519198
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.954593744
Short name T3
Test name
Test status
Simulation time 122631458 ps
CPU time 4.2 seconds
Started Jun 21 07:00:48 PM PDT 24
Finished Jun 21 07:00:59 PM PDT 24
Peak memory 232880 kb
Host smart-9e699361-0e70-4d5c-b66f-163044f813a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954593744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.954593744
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3754395553
Short name T938
Test name
Test status
Simulation time 28369040188 ps
CPU time 69.44 seconds
Started Jun 21 07:00:53 PM PDT 24
Finished Jun 21 07:02:07 PM PDT 24
Peak memory 224780 kb
Host smart-3a6f6c92-8959-40e2-82e7-28fba070ad40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754395553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3754395553
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.352835580
Short name T238
Test name
Test status
Simulation time 474266463 ps
CPU time 7.62 seconds
Started Jun 21 07:00:51 PM PDT 24
Finished Jun 21 07:01:04 PM PDT 24
Peak memory 224652 kb
Host smart-21d7a535-4fa3-451e-a9fc-24f02e19e053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352835580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.352835580
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1535421399
Short name T534
Test name
Test status
Simulation time 1685909413 ps
CPU time 3.62 seconds
Started Jun 21 07:00:48 PM PDT 24
Finished Jun 21 07:00:58 PM PDT 24
Peak memory 232888 kb
Host smart-dadc8f46-3264-4b52-8865-8e9daf9d9b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535421399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1535421399
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1612624112
Short name T693
Test name
Test status
Simulation time 280811513 ps
CPU time 3.68 seconds
Started Jun 21 07:00:54 PM PDT 24
Finished Jun 21 07:01:03 PM PDT 24
Peak memory 222724 kb
Host smart-dae529b7-934d-41a3-b9d6-be8bc22fe39f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1612624112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1612624112
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3426024476
Short name T139
Test name
Test status
Simulation time 55864223161 ps
CPU time 235.55 seconds
Started Jun 21 07:00:48 PM PDT 24
Finished Jun 21 07:04:50 PM PDT 24
Peak memory 266200 kb
Host smart-ad490c48-7863-4fc3-9df5-e3c166ea8d8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426024476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3426024476
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2058890694
Short name T911
Test name
Test status
Simulation time 24464440908 ps
CPU time 29.43 seconds
Started Jun 21 07:00:48 PM PDT 24
Finished Jun 21 07:01:24 PM PDT 24
Peak memory 216556 kb
Host smart-1318e2dd-61d9-43ad-8733-e8f5b146611b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058890694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2058890694
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.796104375
Short name T434
Test name
Test status
Simulation time 718411365 ps
CPU time 5.34 seconds
Started Jun 21 07:00:48 PM PDT 24
Finished Jun 21 07:01:00 PM PDT 24
Peak memory 216452 kb
Host smart-c16cad47-a868-449f-8b33-1d97d7e2c277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796104375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.796104375
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1940433368
Short name T623
Test name
Test status
Simulation time 803437483 ps
CPU time 2.74 seconds
Started Jun 21 07:00:55 PM PDT 24
Finished Jun 21 07:01:04 PM PDT 24
Peak memory 216464 kb
Host smart-9b19a545-2dee-4ae4-b861-f4bead6471b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940433368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1940433368
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2720656094
Short name T408
Test name
Test status
Simulation time 59084427 ps
CPU time 0.86 seconds
Started Jun 21 07:00:50 PM PDT 24
Finished Jun 21 07:00:56 PM PDT 24
Peak memory 206108 kb
Host smart-3352eb44-d716-416f-9a93-18412ce2ddb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720656094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2720656094
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3571476200
Short name T266
Test name
Test status
Simulation time 1888025266 ps
CPU time 7.96 seconds
Started Jun 21 07:00:50 PM PDT 24
Finished Jun 21 07:01:03 PM PDT 24
Peak memory 232872 kb
Host smart-dbba5ba3-afac-4cbe-9d51-613537d34ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571476200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3571476200
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.463685735
Short name T354
Test name
Test status
Simulation time 32305259 ps
CPU time 0.74 seconds
Started Jun 21 07:00:47 PM PDT 24
Finished Jun 21 07:00:55 PM PDT 24
Peak memory 205500 kb
Host smart-e83cd8c8-80a1-427d-a0e7-5121bb60e555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463685735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.463685735
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1722048439
Short name T81
Test name
Test status
Simulation time 217863044 ps
CPU time 5.03 seconds
Started Jun 21 07:00:53 PM PDT 24
Finished Jun 21 07:01:03 PM PDT 24
Peak memory 232872 kb
Host smart-3f5f7711-d353-49a2-ae0c-620b6c99afe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722048439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1722048439
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.207078594
Short name T645
Test name
Test status
Simulation time 19891872 ps
CPU time 0.75 seconds
Started Jun 21 07:00:48 PM PDT 24
Finished Jun 21 07:00:56 PM PDT 24
Peak memory 205716 kb
Host smart-a5a15ab9-2e41-4509-98d6-9fb57ddd7a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207078594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.207078594
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.488948443
Short name T256
Test name
Test status
Simulation time 11202955499 ps
CPU time 100.24 seconds
Started Jun 21 07:00:52 PM PDT 24
Finished Jun 21 07:02:37 PM PDT 24
Peak memory 250692 kb
Host smart-4d9f8ecb-6d13-46c8-84fc-6ea7544faee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488948443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.488948443
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3456480396
Short name T631
Test name
Test status
Simulation time 10546822817 ps
CPU time 51.63 seconds
Started Jun 21 07:00:52 PM PDT 24
Finished Jun 21 07:01:49 PM PDT 24
Peak memory 239332 kb
Host smart-5f70c3af-a3c2-4f15-beed-a8a76f35dfcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456480396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3456480396
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3590685897
Short name T662
Test name
Test status
Simulation time 3079160032 ps
CPU time 53.63 seconds
Started Jun 21 07:00:52 PM PDT 24
Finished Jun 21 07:01:51 PM PDT 24
Peak memory 256540 kb
Host smart-943efe82-3d85-4db6-ac00-1d2b37682515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590685897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3590685897
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.4281952773
Short name T130
Test name
Test status
Simulation time 163404041 ps
CPU time 5.53 seconds
Started Jun 21 07:00:56 PM PDT 24
Finished Jun 21 07:01:08 PM PDT 24
Peak memory 224696 kb
Host smart-4180c3eb-999b-4f13-b3f6-967d3bb4688e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281952773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.4281952773
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3545395789
Short name T777
Test name
Test status
Simulation time 1283201171 ps
CPU time 13.89 seconds
Started Jun 21 07:00:48 PM PDT 24
Finished Jun 21 07:01:08 PM PDT 24
Peak memory 232884 kb
Host smart-4271f6b0-863b-44b4-a617-3c055763a981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545395789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3545395789
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1963320179
Short name T160
Test name
Test status
Simulation time 21128753550 ps
CPU time 51.57 seconds
Started Jun 21 07:00:53 PM PDT 24
Finished Jun 21 07:01:51 PM PDT 24
Peak memory 241072 kb
Host smart-a37daf7d-a47c-482d-86b4-c6b11fa75cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963320179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1963320179
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2483346522
Short name T686
Test name
Test status
Simulation time 289509751 ps
CPU time 2.4 seconds
Started Jun 21 07:00:53 PM PDT 24
Finished Jun 21 07:01:01 PM PDT 24
Peak memory 223836 kb
Host smart-58bae97a-fbe5-4731-b4b5-a9714d4dfd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483346522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2483346522
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.57602442
Short name T667
Test name
Test status
Simulation time 12659088624 ps
CPU time 8.94 seconds
Started Jun 21 07:00:53 PM PDT 24
Finished Jun 21 07:01:07 PM PDT 24
Peak memory 232964 kb
Host smart-7da7cc44-ba14-41df-bfad-d931c2999434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57602442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.57602442
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1098986073
Short name T675
Test name
Test status
Simulation time 4124929255 ps
CPU time 6.12 seconds
Started Jun 21 07:00:51 PM PDT 24
Finished Jun 21 07:01:02 PM PDT 24
Peak memory 220568 kb
Host smart-b9a462d0-55ac-4906-ab89-579025c82908
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1098986073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1098986073
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3340430880
Short name T915
Test name
Test status
Simulation time 5490690503 ps
CPU time 126.96 seconds
Started Jun 21 07:00:50 PM PDT 24
Finished Jun 21 07:03:02 PM PDT 24
Peak memory 272656 kb
Host smart-8baeaa56-77d7-49a7-8142-4eac978fd01d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340430880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3340430880
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.191502912
Short name T330
Test name
Test status
Simulation time 859444547 ps
CPU time 5.59 seconds
Started Jun 21 07:00:56 PM PDT 24
Finished Jun 21 07:01:08 PM PDT 24
Peak memory 216452 kb
Host smart-582e9e4c-a19b-4ab2-90e2-5d281c5340ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191502912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.191502912
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2192845788
Short name T670
Test name
Test status
Simulation time 7065397343 ps
CPU time 6.23 seconds
Started Jun 21 07:00:56 PM PDT 24
Finished Jun 21 07:01:07 PM PDT 24
Peak memory 216548 kb
Host smart-372d1c02-0ad1-4a18-b068-48b7a749b321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192845788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2192845788
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2696534006
Short name T748
Test name
Test status
Simulation time 44083344 ps
CPU time 1.31 seconds
Started Jun 21 07:00:55 PM PDT 24
Finished Jun 21 07:01:02 PM PDT 24
Peak memory 208200 kb
Host smart-e9ced774-96cf-48d4-abba-ab18255c6758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696534006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2696534006
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.798097250
Short name T687
Test name
Test status
Simulation time 26665447 ps
CPU time 0.69 seconds
Started Jun 21 07:00:48 PM PDT 24
Finished Jun 21 07:00:55 PM PDT 24
Peak memory 205780 kb
Host smart-505cfcd9-084d-4045-b193-c58ce1dc67f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798097250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.798097250
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1727761820
Short name T636
Test name
Test status
Simulation time 15980097357 ps
CPU time 28.6 seconds
Started Jun 21 07:01:00 PM PDT 24
Finished Jun 21 07:01:34 PM PDT 24
Peak memory 232952 kb
Host smart-850e4e3d-e80f-4aef-a770-67eed970851e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727761820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1727761820
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3226027391
Short name T115
Test name
Test status
Simulation time 20255655 ps
CPU time 0.74 seconds
Started Jun 21 07:00:58 PM PDT 24
Finished Jun 21 07:01:05 PM PDT 24
Peak memory 205792 kb
Host smart-1ceb465d-3e89-4272-943c-7bf92883118c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226027391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3226027391
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2813126598
Short name T164
Test name
Test status
Simulation time 55477074 ps
CPU time 2.82 seconds
Started Jun 21 07:01:00 PM PDT 24
Finished Jun 21 07:01:09 PM PDT 24
Peak memory 232852 kb
Host smart-5ce67f2e-915f-4ee7-b04d-40217f2c605e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813126598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2813126598
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1070199626
Short name T726
Test name
Test status
Simulation time 35998572 ps
CPU time 0.85 seconds
Started Jun 21 07:00:53 PM PDT 24
Finished Jun 21 07:00:59 PM PDT 24
Peak memory 206740 kb
Host smart-185dee78-8576-4b36-a7ab-a676c741ee39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070199626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1070199626
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2012040127
Short name T151
Test name
Test status
Simulation time 20061107264 ps
CPU time 158.12 seconds
Started Jun 21 07:01:00 PM PDT 24
Finished Jun 21 07:03:43 PM PDT 24
Peak memory 249396 kb
Host smart-7e019aae-e9b2-4cf1-91a0-3189b0fc1959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012040127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2012040127
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3986198599
Short name T917
Test name
Test status
Simulation time 9601139891 ps
CPU time 20.56 seconds
Started Jun 21 07:00:59 PM PDT 24
Finished Jun 21 07:01:25 PM PDT 24
Peak memory 217816 kb
Host smart-9405f7ac-72c1-4a73-96dd-cdaa9d60593a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986198599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3986198599
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2661530496
Short name T935
Test name
Test status
Simulation time 5708968341 ps
CPU time 32.01 seconds
Started Jun 21 07:00:56 PM PDT 24
Finished Jun 21 07:01:34 PM PDT 24
Peak memory 217724 kb
Host smart-3ff4b21c-9a51-41eb-b83d-6a17bac3f24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661530496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2661530496
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.621820682
Short name T586
Test name
Test status
Simulation time 54142311 ps
CPU time 3.54 seconds
Started Jun 21 07:00:59 PM PDT 24
Finished Jun 21 07:01:08 PM PDT 24
Peak memory 224620 kb
Host smart-30aff35d-5202-459b-a518-e03a8c69805a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621820682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.621820682
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2039090444
Short name T752
Test name
Test status
Simulation time 3761808661 ps
CPU time 27.75 seconds
Started Jun 21 07:00:57 PM PDT 24
Finished Jun 21 07:01:31 PM PDT 24
Peak memory 224764 kb
Host smart-8e8bfd54-9d6e-4564-9357-2e04473bc93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039090444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2039090444
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1450810672
Short name T192
Test name
Test status
Simulation time 371423937 ps
CPU time 9.55 seconds
Started Jun 21 07:00:57 PM PDT 24
Finished Jun 21 07:01:12 PM PDT 24
Peak memory 240912 kb
Host smart-8cb508de-3c3c-4091-a02c-97f33f78d391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450810672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1450810672
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3429272872
Short name T282
Test name
Test status
Simulation time 3814138194 ps
CPU time 9.1 seconds
Started Jun 21 07:00:58 PM PDT 24
Finished Jun 21 07:01:13 PM PDT 24
Peak memory 241008 kb
Host smart-23628109-49fa-4ad2-9883-fa3929f74e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429272872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3429272872
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2734163606
Short name T891
Test name
Test status
Simulation time 103184940 ps
CPU time 2.79 seconds
Started Jun 21 07:00:58 PM PDT 24
Finished Jun 21 07:01:07 PM PDT 24
Peak memory 232876 kb
Host smart-7b0286da-d962-4814-bdc4-9117c9624957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734163606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2734163606
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2710866920
Short name T415
Test name
Test status
Simulation time 131450352 ps
CPU time 4.46 seconds
Started Jun 21 07:00:58 PM PDT 24
Finished Jun 21 07:01:08 PM PDT 24
Peak memory 222732 kb
Host smart-a04c4302-e787-4f66-8ee0-4a08f6efadb8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2710866920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2710866920
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2932889939
Short name T23
Test name
Test status
Simulation time 110631719 ps
CPU time 1 seconds
Started Jun 21 07:00:59 PM PDT 24
Finished Jun 21 07:01:05 PM PDT 24
Peak memory 215288 kb
Host smart-b7fd01a5-ae57-4160-b79d-a279a4b6ceda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932889939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2932889939
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1058095205
Short name T604
Test name
Test status
Simulation time 10856576773 ps
CPU time 9.97 seconds
Started Jun 21 07:00:58 PM PDT 24
Finished Jun 21 07:01:14 PM PDT 24
Peak memory 216556 kb
Host smart-c46d4586-defd-4829-afca-27fbb68d737d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058095205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1058095205
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.4040382177
Short name T741
Test name
Test status
Simulation time 2729582444 ps
CPU time 2.92 seconds
Started Jun 21 07:00:58 PM PDT 24
Finished Jun 21 07:01:07 PM PDT 24
Peak memory 208232 kb
Host smart-0ced32f5-a73b-4616-bc82-a88357ab13c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040382177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.4040382177
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.895139198
Short name T892
Test name
Test status
Simulation time 264019740 ps
CPU time 0.9 seconds
Started Jun 21 07:00:57 PM PDT 24
Finished Jun 21 07:01:04 PM PDT 24
Peak memory 206768 kb
Host smart-657f0951-16b8-4873-9c46-3e7907eefaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895139198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.895139198
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.521438005
Short name T550
Test name
Test status
Simulation time 62922076 ps
CPU time 0.8 seconds
Started Jun 21 07:01:00 PM PDT 24
Finished Jun 21 07:01:06 PM PDT 24
Peak memory 206100 kb
Host smart-86864c00-2110-4f49-aaae-6679508ed26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521438005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.521438005
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2516556309
Short name T300
Test name
Test status
Simulation time 1917530596 ps
CPU time 10.38 seconds
Started Jun 21 07:00:59 PM PDT 24
Finished Jun 21 07:01:15 PM PDT 24
Peak memory 232896 kb
Host smart-fcc5c4ae-b7c4-497f-813d-ac9f0d0b2318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516556309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2516556309
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2512565536
Short name T516
Test name
Test status
Simulation time 74914994 ps
CPU time 0.7 seconds
Started Jun 21 07:00:58 PM PDT 24
Finished Jun 21 07:01:05 PM PDT 24
Peak memory 205496 kb
Host smart-2b4732f7-20d6-46fa-81cd-847d98c50fd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512565536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2512565536
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3028723410
Short name T527
Test name
Test status
Simulation time 1164626116 ps
CPU time 5.39 seconds
Started Jun 21 07:01:00 PM PDT 24
Finished Jun 21 07:01:11 PM PDT 24
Peak memory 224680 kb
Host smart-f61a8194-4940-43fc-867f-74e4242368f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028723410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3028723410
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1880134951
Short name T373
Test name
Test status
Simulation time 120446814 ps
CPU time 0.76 seconds
Started Jun 21 07:00:59 PM PDT 24
Finished Jun 21 07:01:06 PM PDT 24
Peak memory 206060 kb
Host smart-b742e80b-3052-4e97-8543-a78e45890f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880134951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1880134951
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.4150184815
Short name T218
Test name
Test status
Simulation time 25707705715 ps
CPU time 182.88 seconds
Started Jun 21 07:00:59 PM PDT 24
Finished Jun 21 07:04:08 PM PDT 24
Peak memory 249264 kb
Host smart-c3c7159b-7e94-473c-9e38-13c31cafde34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150184815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.4150184815
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2411071474
Short name T926
Test name
Test status
Simulation time 7509957055 ps
CPU time 28.97 seconds
Started Jun 21 07:00:59 PM PDT 24
Finished Jun 21 07:01:33 PM PDT 24
Peak memory 224868 kb
Host smart-60dd0022-7c4b-4caf-8e52-9dfb61de878c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411071474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2411071474
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1556279678
Short name T219
Test name
Test status
Simulation time 6990044824 ps
CPU time 80.74 seconds
Started Jun 21 07:00:57 PM PDT 24
Finished Jun 21 07:02:23 PM PDT 24
Peak memory 252884 kb
Host smart-7436ea8a-5a29-4735-9ab8-72c3a03c0a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556279678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1556279678
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_intercept.721950049
Short name T83
Test name
Test status
Simulation time 4518447997 ps
CPU time 31.38 seconds
Started Jun 21 07:00:57 PM PDT 24
Finished Jun 21 07:01:34 PM PDT 24
Peak memory 224740 kb
Host smart-d7118947-a80f-4458-998a-4dae4d147812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721950049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.721950049
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.111129346
Short name T302
Test name
Test status
Simulation time 28618388706 ps
CPU time 64.18 seconds
Started Jun 21 07:01:00 PM PDT 24
Finished Jun 21 07:02:09 PM PDT 24
Peak memory 249300 kb
Host smart-dcc7a217-75a8-4071-9b3c-e8bc3b6547f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111129346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.111129346
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2117306297
Short name T241
Test name
Test status
Simulation time 2322655180 ps
CPU time 10.06 seconds
Started Jun 21 07:01:01 PM PDT 24
Finished Jun 21 07:01:16 PM PDT 24
Peak memory 240780 kb
Host smart-4105dd70-e6d5-4562-ac91-5b1026d84b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117306297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2117306297
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1827097866
Short name T499
Test name
Test status
Simulation time 9714463081 ps
CPU time 9.25 seconds
Started Jun 21 07:00:59 PM PDT 24
Finished Jun 21 07:01:14 PM PDT 24
Peak memory 232968 kb
Host smart-1d0ffd6e-1505-439e-b94f-de126256f861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827097866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1827097866
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.4263438760
Short name T37
Test name
Test status
Simulation time 10762900033 ps
CPU time 13.18 seconds
Started Jun 21 07:00:57 PM PDT 24
Finished Jun 21 07:01:16 PM PDT 24
Peak memory 222836 kb
Host smart-c4d15b77-55cd-44d6-9b93-19a02f8ce52f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4263438760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.4263438760
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1809391061
Short name T141
Test name
Test status
Simulation time 124405169578 ps
CPU time 289.08 seconds
Started Jun 21 07:00:56 PM PDT 24
Finished Jun 21 07:05:51 PM PDT 24
Peak memory 273988 kb
Host smart-b129980b-fe5b-46d2-ab67-63da403d783d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809391061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1809391061
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.56435611
Short name T580
Test name
Test status
Simulation time 642981557 ps
CPU time 8.11 seconds
Started Jun 21 07:00:57 PM PDT 24
Finished Jun 21 07:01:10 PM PDT 24
Peak memory 216432 kb
Host smart-f076dfea-fa9b-45a2-9b5d-d857c8c1cd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56435611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.56435611
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2711496723
Short name T356
Test name
Test status
Simulation time 14481916 ps
CPU time 0.7 seconds
Started Jun 21 07:00:59 PM PDT 24
Finished Jun 21 07:01:06 PM PDT 24
Peak memory 205800 kb
Host smart-a40eefd1-2c74-4c32-9a0f-c6b726dba11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711496723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2711496723
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2446862535
Short name T677
Test name
Test status
Simulation time 67741857 ps
CPU time 1.81 seconds
Started Jun 21 07:00:58 PM PDT 24
Finished Jun 21 07:01:06 PM PDT 24
Peak memory 216444 kb
Host smart-a5f330ee-32d5-4edb-9883-fb7124cca232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446862535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2446862535
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.323390081
Short name T833
Test name
Test status
Simulation time 28310505 ps
CPU time 0.77 seconds
Started Jun 21 07:00:58 PM PDT 24
Finished Jun 21 07:01:05 PM PDT 24
Peak memory 206200 kb
Host smart-96f29c89-d0d8-4d9b-ba9a-00fcd6e72e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323390081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.323390081
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.4076900952
Short name T150
Test name
Test status
Simulation time 795694572 ps
CPU time 2.99 seconds
Started Jun 21 07:00:59 PM PDT 24
Finished Jun 21 07:01:08 PM PDT 24
Peak memory 224612 kb
Host smart-c3a61728-5a68-4af1-99a8-91eaf00a9f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076900952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.4076900952
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.4274352136
Short name T540
Test name
Test status
Simulation time 16139260 ps
CPU time 0.75 seconds
Started Jun 21 07:01:12 PM PDT 24
Finished Jun 21 07:01:15 PM PDT 24
Peak memory 205576 kb
Host smart-4ddd6691-9f84-43df-9047-70e79f9195cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274352136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
4274352136
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.607655429
Short name T875
Test name
Test status
Simulation time 2565915800 ps
CPU time 30.38 seconds
Started Jun 21 07:01:11 PM PDT 24
Finished Jun 21 07:01:44 PM PDT 24
Peak memory 224760 kb
Host smart-0847edc3-f988-4864-8bf5-d251792960db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607655429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.607655429
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2881665888
Short name T894
Test name
Test status
Simulation time 52358573 ps
CPU time 0.77 seconds
Started Jun 21 07:01:00 PM PDT 24
Finished Jun 21 07:01:06 PM PDT 24
Peak memory 206036 kb
Host smart-2ab13d28-efc5-49ed-b6ff-77c2c85bc223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881665888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2881665888
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2026009039
Short name T75
Test name
Test status
Simulation time 133374159414 ps
CPU time 235.77 seconds
Started Jun 21 07:01:11 PM PDT 24
Finished Jun 21 07:05:09 PM PDT 24
Peak memory 257612 kb
Host smart-3f63a34a-7502-489c-b254-ab274ae5991e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026009039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2026009039
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.687407535
Short name T120
Test name
Test status
Simulation time 17304125659 ps
CPU time 146.76 seconds
Started Jun 21 07:01:11 PM PDT 24
Finished Jun 21 07:03:41 PM PDT 24
Peak memory 257436 kb
Host smart-77eb1426-b721-4ab6-b943-8c96797db93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687407535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.687407535
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2432452335
Short name T683
Test name
Test status
Simulation time 111198963 ps
CPU time 3.12 seconds
Started Jun 21 07:01:12 PM PDT 24
Finished Jun 21 07:01:18 PM PDT 24
Peak memory 224604 kb
Host smart-64567b7c-d40c-4b37-80c3-7ef60839b969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432452335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2432452335
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.281720781
Short name T754
Test name
Test status
Simulation time 20427736442 ps
CPU time 22.64 seconds
Started Jun 21 07:01:13 PM PDT 24
Finished Jun 21 07:01:38 PM PDT 24
Peak memory 224732 kb
Host smart-9a510ec2-b438-47cf-8cec-648e8050e5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281720781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.281720781
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1482969377
Short name T275
Test name
Test status
Simulation time 5449693064 ps
CPU time 15.73 seconds
Started Jun 21 07:01:10 PM PDT 24
Finished Jun 21 07:01:28 PM PDT 24
Peak memory 232964 kb
Host smart-8bae9ef2-4afc-4a4d-b2db-a2a09cbf92bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482969377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1482969377
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.846099297
Short name T473
Test name
Test status
Simulation time 73054664 ps
CPU time 2.23 seconds
Started Jun 21 07:01:10 PM PDT 24
Finished Jun 21 07:01:15 PM PDT 24
Peak memory 223180 kb
Host smart-69a69b7e-cfa3-465d-ae6a-c8285fe1085e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846099297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.846099297
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3412454372
Short name T112
Test name
Test status
Simulation time 74083978988 ps
CPU time 20.34 seconds
Started Jun 21 07:01:12 PM PDT 24
Finished Jun 21 07:01:35 PM PDT 24
Peak memory 233028 kb
Host smart-6d642c1b-63ca-47fd-a971-f9c1f235aae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412454372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3412454372
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3948273313
Short name T706
Test name
Test status
Simulation time 570495174 ps
CPU time 6.41 seconds
Started Jun 21 07:01:12 PM PDT 24
Finished Jun 21 07:01:21 PM PDT 24
Peak memory 219244 kb
Host smart-d79d5b6d-6a3a-4bad-8838-44572638a7a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3948273313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3948273313
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2270114356
Short name T798
Test name
Test status
Simulation time 147420857 ps
CPU time 1.24 seconds
Started Jun 21 07:01:10 PM PDT 24
Finished Jun 21 07:01:13 PM PDT 24
Peak memory 207072 kb
Host smart-d15f937b-4a65-45ba-8c27-433316b0060e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270114356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2270114356
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3780303900
Short name T823
Test name
Test status
Simulation time 8130016476 ps
CPU time 43.23 seconds
Started Jun 21 07:00:59 PM PDT 24
Finished Jun 21 07:01:48 PM PDT 24
Peak memory 216676 kb
Host smart-05d514f0-45e0-42cd-85dd-927035bf448e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780303900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3780303900
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2423920935
Short name T66
Test name
Test status
Simulation time 43725042 ps
CPU time 0.74 seconds
Started Jun 21 07:00:58 PM PDT 24
Finished Jun 21 07:01:05 PM PDT 24
Peak memory 205804 kb
Host smart-82b07634-5131-447d-b44f-83f1f168ce2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423920935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2423920935
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2693785557
Short name T440
Test name
Test status
Simulation time 26757155 ps
CPU time 1.06 seconds
Started Jun 21 07:00:57 PM PDT 24
Finished Jun 21 07:01:03 PM PDT 24
Peak memory 207712 kb
Host smart-4e7c50dc-8370-48f6-9962-c1830653d6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693785557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2693785557
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.20230096
Short name T439
Test name
Test status
Simulation time 862367968 ps
CPU time 0.85 seconds
Started Jun 21 07:00:57 PM PDT 24
Finished Jun 21 07:01:03 PM PDT 24
Peak memory 206120 kb
Host smart-21a94d92-6cc8-471c-85f5-ae77cc845bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20230096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.20230096
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2574749796
Short name T545
Test name
Test status
Simulation time 298203618 ps
CPU time 2.99 seconds
Started Jun 21 07:01:11 PM PDT 24
Finished Jun 21 07:01:17 PM PDT 24
Peak memory 232892 kb
Host smart-a479fe84-c235-4e94-bea6-ad50b1f010f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574749796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2574749796
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3625350801
Short name T829
Test name
Test status
Simulation time 26477482 ps
CPU time 0.73 seconds
Started Jun 21 07:01:10 PM PDT 24
Finished Jun 21 07:01:13 PM PDT 24
Peak memory 205496 kb
Host smart-634ce762-9c2a-44d7-88e7-7865be46b4b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625350801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3625350801
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1584352854
Short name T594
Test name
Test status
Simulation time 13240067 ps
CPU time 0.78 seconds
Started Jun 21 07:01:11 PM PDT 24
Finished Jun 21 07:01:14 PM PDT 24
Peak memory 205736 kb
Host smart-9224b4e6-3e3c-4bbc-944a-f7dc8331f63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584352854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1584352854
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3584197395
Short name T914
Test name
Test status
Simulation time 20723625467 ps
CPU time 223.58 seconds
Started Jun 21 07:01:12 PM PDT 24
Finished Jun 21 07:04:59 PM PDT 24
Peak memory 255716 kb
Host smart-de74cff5-8735-4557-8b09-495fe3e9b1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584197395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3584197395
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1445032549
Short name T237
Test name
Test status
Simulation time 29041184318 ps
CPU time 189.52 seconds
Started Jun 21 07:01:10 PM PDT 24
Finished Jun 21 07:04:22 PM PDT 24
Peak memory 249400 kb
Host smart-4fa3bc66-5646-4123-9839-4bca339df8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445032549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1445032549
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1347130808
Short name T437
Test name
Test status
Simulation time 2104869253 ps
CPU time 10.25 seconds
Started Jun 21 07:01:10 PM PDT 24
Finished Jun 21 07:01:22 PM PDT 24
Peak memory 224672 kb
Host smart-c80abddf-21cb-4292-b016-9f8c28142bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347130808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1347130808
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2465102061
Short name T749
Test name
Test status
Simulation time 3264785969 ps
CPU time 6.44 seconds
Started Jun 21 07:01:11 PM PDT 24
Finished Jun 21 07:01:20 PM PDT 24
Peak memory 230044 kb
Host smart-55b327c2-deb5-4c5f-9c21-7ad687b94061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465102061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2465102061
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3349103988
Short name T347
Test name
Test status
Simulation time 2123235920 ps
CPU time 12 seconds
Started Jun 21 07:01:10 PM PDT 24
Finished Jun 21 07:01:25 PM PDT 24
Peak memory 249240 kb
Host smart-c696c7a9-754f-4aa3-9e2c-87d723e3901a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349103988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3349103988
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1266071787
Short name T16
Test name
Test status
Simulation time 755968981 ps
CPU time 5.73 seconds
Started Jun 21 07:01:11 PM PDT 24
Finished Jun 21 07:01:19 PM PDT 24
Peak memory 224564 kb
Host smart-42dab0ba-af6b-42f5-a2ac-848070081037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266071787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1266071787
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2068991502
Short name T297
Test name
Test status
Simulation time 2023694769 ps
CPU time 5.46 seconds
Started Jun 21 07:01:11 PM PDT 24
Finished Jun 21 07:01:19 PM PDT 24
Peak memory 224636 kb
Host smart-b8f6f6af-10f4-43e8-8dcf-c62d07b2445a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068991502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2068991502
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1230006228
Short name T6
Test name
Test status
Simulation time 198417425 ps
CPU time 4.29 seconds
Started Jun 21 07:01:10 PM PDT 24
Finished Jun 21 07:01:17 PM PDT 24
Peak memory 222112 kb
Host smart-409d90bb-bea5-4dab-a4d7-152138b6609c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1230006228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1230006228
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.4010959461
Short name T521
Test name
Test status
Simulation time 1278004210 ps
CPU time 16.65 seconds
Started Jun 21 07:01:11 PM PDT 24
Finished Jun 21 07:01:31 PM PDT 24
Peak memory 220256 kb
Host smart-45f961cf-385a-475d-9de1-63e20b83cf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010959461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.4010959461
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2472965082
Short name T669
Test name
Test status
Simulation time 8275269739 ps
CPU time 22.41 seconds
Started Jun 21 07:01:12 PM PDT 24
Finished Jun 21 07:01:37 PM PDT 24
Peak memory 216508 kb
Host smart-f8d8652f-a0bd-4584-844d-6816d81d4df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472965082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2472965082
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2689373449
Short name T608
Test name
Test status
Simulation time 13321567 ps
CPU time 0.73 seconds
Started Jun 21 07:01:14 PM PDT 24
Finished Jun 21 07:01:17 PM PDT 24
Peak memory 206096 kb
Host smart-96517839-8c6e-483c-840e-f819eaa782b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689373449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2689373449
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2429178529
Short name T775
Test name
Test status
Simulation time 113226484 ps
CPU time 0.87 seconds
Started Jun 21 07:01:12 PM PDT 24
Finished Jun 21 07:01:15 PM PDT 24
Peak memory 206096 kb
Host smart-4df83da6-56ec-44ed-81fb-34a4800ca14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429178529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2429178529
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.904690821
Short name T514
Test name
Test status
Simulation time 8787555076 ps
CPU time 28.83 seconds
Started Jun 21 07:01:14 PM PDT 24
Finished Jun 21 07:01:45 PM PDT 24
Peak memory 232916 kb
Host smart-38c31b0b-5f1d-4cf9-8a41-a952bce4ab01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904690821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.904690821
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2263550095
Short name T691
Test name
Test status
Simulation time 24427734 ps
CPU time 0.72 seconds
Started Jun 21 07:01:20 PM PDT 24
Finished Jun 21 07:01:22 PM PDT 24
Peak memory 205524 kb
Host smart-02d18716-3062-4792-bff8-146d6472a3ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263550095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2263550095
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.529559938
Short name T584
Test name
Test status
Simulation time 171945983 ps
CPU time 3.51 seconds
Started Jun 21 07:01:23 PM PDT 24
Finished Jun 21 07:01:30 PM PDT 24
Peak memory 224248 kb
Host smart-aa86dacd-62bb-4942-8fd8-c76f098be519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529559938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.529559938
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.4285371049
Short name T837
Test name
Test status
Simulation time 47267191 ps
CPU time 0.77 seconds
Started Jun 21 07:01:12 PM PDT 24
Finished Jun 21 07:01:16 PM PDT 24
Peak memory 206744 kb
Host smart-4dac6489-6119-483a-9069-449a8e116363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285371049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.4285371049
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2327366535
Short name T149
Test name
Test status
Simulation time 328528722724 ps
CPU time 111.19 seconds
Started Jun 21 07:01:21 PM PDT 24
Finished Jun 21 07:03:14 PM PDT 24
Peak memory 249388 kb
Host smart-ea8dc1aa-23c3-4908-be54-0f311e3a5347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327366535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2327366535
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1279952347
Short name T122
Test name
Test status
Simulation time 5414885855 ps
CPU time 50.32 seconds
Started Jun 21 07:01:22 PM PDT 24
Finished Jun 21 07:02:15 PM PDT 24
Peak memory 249784 kb
Host smart-e3a9df61-0408-4c9d-a743-1e4e180c0602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279952347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1279952347
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1096317914
Short name T627
Test name
Test status
Simulation time 209972796353 ps
CPU time 243.48 seconds
Started Jun 21 07:01:22 PM PDT 24
Finished Jun 21 07:05:29 PM PDT 24
Peak memory 251408 kb
Host smart-3203521b-294e-4530-bac4-49049bee7647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096317914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1096317914
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1393133210
Short name T379
Test name
Test status
Simulation time 150825733 ps
CPU time 3.71 seconds
Started Jun 21 07:01:12 PM PDT 24
Finished Jun 21 07:01:18 PM PDT 24
Peak memory 224672 kb
Host smart-bd29730e-0ddb-4210-b243-a59895f8f3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393133210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1393133210
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.4234817300
Short name T637
Test name
Test status
Simulation time 12766929512 ps
CPU time 120.26 seconds
Started Jun 21 07:01:10 PM PDT 24
Finished Jun 21 07:03:12 PM PDT 24
Peak memory 249904 kb
Host smart-9845af92-780b-430e-b353-72cf15264286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234817300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.4234817300
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.36623130
Short name T206
Test name
Test status
Simulation time 8553896056 ps
CPU time 25.11 seconds
Started Jun 21 07:01:12 PM PDT 24
Finished Jun 21 07:01:40 PM PDT 24
Peak memory 232940 kb
Host smart-0570b68d-4d22-460a-953d-3b1d1997fb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36623130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.36623130
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2053206275
Short name T296
Test name
Test status
Simulation time 1896655116 ps
CPU time 7.2 seconds
Started Jun 21 07:01:12 PM PDT 24
Finished Jun 21 07:01:22 PM PDT 24
Peak memory 232864 kb
Host smart-9767f03f-783f-4baf-801c-d9a9f19b103c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053206275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2053206275
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3984107406
Short name T371
Test name
Test status
Simulation time 711347745 ps
CPU time 9.33 seconds
Started Jun 21 07:01:22 PM PDT 24
Finished Jun 21 07:01:34 PM PDT 24
Peak memory 220380 kb
Host smart-3b352eb2-fd80-4b41-8681-41f16f78fa4c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3984107406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3984107406
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.4112281851
Short name T477
Test name
Test status
Simulation time 54594670733 ps
CPU time 145.02 seconds
Started Jun 21 07:01:21 PM PDT 24
Finished Jun 21 07:03:49 PM PDT 24
Peak memory 252336 kb
Host smart-f8b96574-09ba-4757-a7ec-34f0c83b24d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112281851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.4112281851
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3398230727
Short name T320
Test name
Test status
Simulation time 6972315766 ps
CPU time 10.42 seconds
Started Jun 21 07:01:10 PM PDT 24
Finished Jun 21 07:01:22 PM PDT 24
Peak memory 216656 kb
Host smart-9f4bf972-9d87-4ae0-a75a-d4d37bb54b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398230727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3398230727
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3441796809
Short name T793
Test name
Test status
Simulation time 159091207 ps
CPU time 1.59 seconds
Started Jun 21 07:01:10 PM PDT 24
Finished Jun 21 07:01:13 PM PDT 24
Peak memory 208108 kb
Host smart-ee552e18-cd61-4d39-83c5-b37e5e61d093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441796809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3441796809
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.753161423
Short name T771
Test name
Test status
Simulation time 110506631 ps
CPU time 0.89 seconds
Started Jun 21 07:01:11 PM PDT 24
Finished Jun 21 07:01:14 PM PDT 24
Peak memory 208092 kb
Host smart-6c3ae8be-9126-47fb-8b66-789d3f9160e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753161423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.753161423
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.317788867
Short name T784
Test name
Test status
Simulation time 56389837 ps
CPU time 0.86 seconds
Started Jun 21 07:01:13 PM PDT 24
Finished Jun 21 07:01:16 PM PDT 24
Peak memory 206108 kb
Host smart-5b682477-2e0f-464f-ac06-f262c4b59755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317788867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.317788867
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3624191725
Short name T913
Test name
Test status
Simulation time 806621103 ps
CPU time 9.02 seconds
Started Jun 21 07:01:21 PM PDT 24
Finished Jun 21 07:01:32 PM PDT 24
Peak memory 233840 kb
Host smart-a4850785-a632-4a8e-9460-747c24d1a4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624191725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3624191725
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2457899703
Short name T727
Test name
Test status
Simulation time 16309805 ps
CPU time 0.75 seconds
Started Jun 21 07:01:20 PM PDT 24
Finished Jun 21 07:01:23 PM PDT 24
Peak memory 205872 kb
Host smart-afac6fa4-9b1b-4dda-9622-71ad149b9ab8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457899703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2457899703
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.276591940
Short name T732
Test name
Test status
Simulation time 34055438 ps
CPU time 2.53 seconds
Started Jun 21 07:01:22 PM PDT 24
Finished Jun 21 07:01:28 PM PDT 24
Peak memory 232872 kb
Host smart-94b4738c-3f8f-450a-9cad-61c51c7ea071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276591940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.276591940
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1945167800
Short name T766
Test name
Test status
Simulation time 17299001 ps
CPU time 0.78 seconds
Started Jun 21 07:01:23 PM PDT 24
Finished Jun 21 07:01:28 PM PDT 24
Peak memory 207060 kb
Host smart-f89267fc-5394-4f4b-b410-90f605ac1398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945167800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1945167800
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1771471696
Short name T43
Test name
Test status
Simulation time 47741454613 ps
CPU time 478.43 seconds
Started Jun 21 07:01:22 PM PDT 24
Finished Jun 21 07:09:23 PM PDT 24
Peak memory 262080 kb
Host smart-52cdf726-df8c-49dd-a642-9d8901ea58b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771471696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1771471696
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.372787355
Short name T671
Test name
Test status
Simulation time 1295959277 ps
CPU time 18.86 seconds
Started Jun 21 07:01:23 PM PDT 24
Finished Jun 21 07:01:46 PM PDT 24
Peak memory 239096 kb
Host smart-74d8f920-8b73-4ffd-9469-88c20f18b9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372787355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.372787355
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1082849366
Short name T800
Test name
Test status
Simulation time 1015012870 ps
CPU time 5.59 seconds
Started Jun 21 07:01:20 PM PDT 24
Finished Jun 21 07:01:27 PM PDT 24
Peak memory 232452 kb
Host smart-b80fa320-7ac3-4479-a08f-8c5eb4b96c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082849366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1082849366
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.4080749254
Short name T797
Test name
Test status
Simulation time 7009575810 ps
CPU time 31.78 seconds
Started Jun 21 07:01:22 PM PDT 24
Finished Jun 21 07:01:58 PM PDT 24
Peak memory 232956 kb
Host smart-bdd9c3f8-49ca-4b1d-adad-6bf48f32121e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080749254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.4080749254
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2334906104
Short name T872
Test name
Test status
Simulation time 82192577 ps
CPU time 2.57 seconds
Started Jun 21 07:01:23 PM PDT 24
Finished Jun 21 07:01:29 PM PDT 24
Peak memory 232840 kb
Host smart-bac4e479-df60-4c1f-84a6-e1b0421694a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334906104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2334906104
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2433700881
Short name T179
Test name
Test status
Simulation time 412446102 ps
CPU time 4.08 seconds
Started Jun 21 07:01:25 PM PDT 24
Finished Jun 21 07:01:33 PM PDT 24
Peak memory 224616 kb
Host smart-a92255d7-cf80-4c5b-9447-1890f8bb8ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433700881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2433700881
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.4245901201
Short name T613
Test name
Test status
Simulation time 8560210301 ps
CPU time 17.35 seconds
Started Jun 21 07:01:21 PM PDT 24
Finished Jun 21 07:01:41 PM PDT 24
Peak memory 220392 kb
Host smart-e5b742a9-404f-49e6-bbc7-ded75b327c9f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4245901201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.4245901201
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2185485968
Short name T223
Test name
Test status
Simulation time 543302122039 ps
CPU time 565.07 seconds
Started Jun 21 07:01:21 PM PDT 24
Finished Jun 21 07:10:50 PM PDT 24
Peak memory 288576 kb
Host smart-a0bf746b-5171-4a11-82c9-f27112d8196a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185485968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2185485968
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1139775834
Short name T397
Test name
Test status
Simulation time 4396974562 ps
CPU time 8.5 seconds
Started Jun 21 07:01:21 PM PDT 24
Finished Jun 21 07:01:32 PM PDT 24
Peak memory 216536 kb
Host smart-7e52693d-8928-4526-bdb2-b80cecbfad92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139775834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1139775834
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2300474762
Short name T885
Test name
Test status
Simulation time 1229804893 ps
CPU time 3.19 seconds
Started Jun 21 07:01:26 PM PDT 24
Finished Jun 21 07:01:33 PM PDT 24
Peak memory 216368 kb
Host smart-043f9496-94d3-460d-9e53-559f3a7ad713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300474762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2300474762
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3907893269
Short name T905
Test name
Test status
Simulation time 27146627 ps
CPU time 1.58 seconds
Started Jun 21 07:01:30 PM PDT 24
Finished Jun 21 07:01:38 PM PDT 24
Peak memory 208132 kb
Host smart-f8d49ad1-638d-4b81-9e01-b256459cd5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907893269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3907893269
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1339799780
Short name T360
Test name
Test status
Simulation time 175800802 ps
CPU time 0.89 seconds
Started Jun 21 07:01:20 PM PDT 24
Finished Jun 21 07:01:23 PM PDT 24
Peak memory 207132 kb
Host smart-ba3a271c-261d-43c6-90e0-7b8eb31e528d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339799780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1339799780
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.4148942819
Short name T181
Test name
Test status
Simulation time 1879355925 ps
CPU time 8.58 seconds
Started Jun 21 07:01:25 PM PDT 24
Finished Jun 21 07:01:37 PM PDT 24
Peak memory 249344 kb
Host smart-017ee280-1389-44c4-995d-9cd5c275535f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148942819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.4148942819
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2426289606
Short name T860
Test name
Test status
Simulation time 15381956 ps
CPU time 0.78 seconds
Started Jun 21 06:59:52 PM PDT 24
Finished Jun 21 06:59:56 PM PDT 24
Peak memory 204852 kb
Host smart-409e21c1-650e-4352-ab8c-3953344cf3b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426289606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
426289606
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.986146351
Short name T589
Test name
Test status
Simulation time 366273450 ps
CPU time 3.59 seconds
Started Jun 21 06:59:57 PM PDT 24
Finished Jun 21 07:00:04 PM PDT 24
Peak memory 224688 kb
Host smart-7d5ee56a-77f6-4dfb-aab5-1197eda7246f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986146351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.986146351
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1315143491
Short name T605
Test name
Test status
Simulation time 16404660 ps
CPU time 0.76 seconds
Started Jun 21 06:59:37 PM PDT 24
Finished Jun 21 06:59:41 PM PDT 24
Peak memory 206736 kb
Host smart-f3b4ee54-f772-4b90-b404-0ace84eeac2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315143491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1315143491
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2541885386
Short name T271
Test name
Test status
Simulation time 56812501836 ps
CPU time 92.35 seconds
Started Jun 21 06:59:53 PM PDT 24
Finished Jun 21 07:01:29 PM PDT 24
Peak memory 254896 kb
Host smart-4ee5f8fb-de59-4000-b28c-35fe633bd83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541885386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2541885386
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1704244590
Short name T620
Test name
Test status
Simulation time 31985375328 ps
CPU time 247.95 seconds
Started Jun 21 06:59:58 PM PDT 24
Finished Jun 21 07:04:09 PM PDT 24
Peak memory 249436 kb
Host smart-c794f23f-8ef6-4753-bd87-5edb6b05bae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704244590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1704244590
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3067583408
Short name T740
Test name
Test status
Simulation time 75136403129 ps
CPU time 174.61 seconds
Started Jun 21 06:59:50 PM PDT 24
Finished Jun 21 07:02:48 PM PDT 24
Peak memory 254808 kb
Host smart-33eb00d0-ccce-44ba-a2c8-cd2bf6f3497e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067583408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3067583408
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1037879349
Short name T801
Test name
Test status
Simulation time 45950113034 ps
CPU time 52.45 seconds
Started Jun 21 06:59:53 PM PDT 24
Finished Jun 21 07:00:49 PM PDT 24
Peak memory 232964 kb
Host smart-4202cdc6-41a2-4104-a657-067103756426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037879349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1037879349
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.4099316434
Short name T113
Test name
Test status
Simulation time 75352026 ps
CPU time 2.29 seconds
Started Jun 21 06:59:53 PM PDT 24
Finished Jun 21 06:59:58 PM PDT 24
Peak memory 222804 kb
Host smart-5bae2b5f-7422-4251-901c-707bc3077cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099316434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.4099316434
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2748411365
Short name T309
Test name
Test status
Simulation time 905421312 ps
CPU time 13.99 seconds
Started Jun 21 06:59:55 PM PDT 24
Finished Jun 21 07:00:12 PM PDT 24
Peak memory 249244 kb
Host smart-ebb01e2d-d3c5-417c-83ae-d99db133f91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748411365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2748411365
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3365249365
Short name T756
Test name
Test status
Simulation time 147650347 ps
CPU time 3.89 seconds
Started Jun 21 06:59:54 PM PDT 24
Finished Jun 21 07:00:01 PM PDT 24
Peak memory 232368 kb
Host smart-57640bc7-74a3-4030-bb9f-0e3e23c39cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365249365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3365249365
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.325451329
Short name T649
Test name
Test status
Simulation time 2513483927 ps
CPU time 10.57 seconds
Started Jun 21 06:59:49 PM PDT 24
Finished Jun 21 07:00:03 PM PDT 24
Peak memory 232924 kb
Host smart-1e75ce55-5e4a-42b3-9d3e-e508ee5ad00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325451329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.325451329
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.732762010
Short name T578
Test name
Test status
Simulation time 1498970702 ps
CPU time 9.82 seconds
Started Jun 21 06:59:53 PM PDT 24
Finished Jun 21 07:00:06 PM PDT 24
Peak memory 222668 kb
Host smart-4f9bcc4a-897e-4b75-b99c-fb24cb206107
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=732762010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.732762010
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2768363676
Short name T52
Test name
Test status
Simulation time 74779577 ps
CPU time 1.14 seconds
Started Jun 21 06:59:54 PM PDT 24
Finished Jun 21 06:59:58 PM PDT 24
Peak memory 235152 kb
Host smart-d4fbfc3a-160c-4768-bf1b-6b1d6ab2345d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768363676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2768363676
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3411412178
Short name T827
Test name
Test status
Simulation time 75275933533 ps
CPU time 609.51 seconds
Started Jun 21 06:59:51 PM PDT 24
Finished Jun 21 07:10:04 PM PDT 24
Peak memory 274020 kb
Host smart-ceb65475-bc86-44b2-b05a-36a95f3ec781
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411412178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3411412178
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2174285718
Short name T652
Test name
Test status
Simulation time 1071208010 ps
CPU time 5.28 seconds
Started Jun 21 06:59:49 PM PDT 24
Finished Jun 21 06:59:58 PM PDT 24
Peak memory 216332 kb
Host smart-f29d54dd-7b90-4604-a926-151761f5cc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174285718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2174285718
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3862147271
Short name T407
Test name
Test status
Simulation time 14597489534 ps
CPU time 8.99 seconds
Started Jun 21 06:59:44 PM PDT 24
Finished Jun 21 06:59:58 PM PDT 24
Peak memory 216404 kb
Host smart-317ee27c-b4c5-4afd-983c-6d9e524abc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862147271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3862147271
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2020093937
Short name T522
Test name
Test status
Simulation time 11036764 ps
CPU time 0.8 seconds
Started Jun 21 06:59:43 PM PDT 24
Finished Jun 21 06:59:47 PM PDT 24
Peak memory 205688 kb
Host smart-2f010533-a844-4365-9a59-f79ee25ac9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020093937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2020093937
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3072870980
Short name T409
Test name
Test status
Simulation time 26926659 ps
CPU time 0.76 seconds
Started Jun 21 06:59:45 PM PDT 24
Finished Jun 21 06:59:50 PM PDT 24
Peak memory 206128 kb
Host smart-e3b20c54-02c8-4131-91af-a38fa5d47081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072870980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3072870980
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3611236876
Short name T449
Test name
Test status
Simulation time 1560757806 ps
CPU time 9.25 seconds
Started Jun 21 06:59:51 PM PDT 24
Finished Jun 21 07:00:03 PM PDT 24
Peak memory 248280 kb
Host smart-077daca0-45c2-40dd-9ec1-9079c57aae3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611236876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3611236876
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.368144564
Short name T361
Test name
Test status
Simulation time 11614936 ps
CPU time 0.7 seconds
Started Jun 21 07:01:20 PM PDT 24
Finished Jun 21 07:01:22 PM PDT 24
Peak memory 205500 kb
Host smart-71eb89fe-93e9-426e-a8d7-3a0db6c8c2bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368144564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.368144564
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2652567954
Short name T260
Test name
Test status
Simulation time 292147838 ps
CPU time 3.6 seconds
Started Jun 21 07:01:21 PM PDT 24
Finished Jun 21 07:01:27 PM PDT 24
Peak memory 232680 kb
Host smart-01f55f09-d3a1-4a56-a69a-cd15779d94dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652567954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2652567954
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1182278152
Short name T787
Test name
Test status
Simulation time 44973028 ps
CPU time 0.82 seconds
Started Jun 21 07:01:19 PM PDT 24
Finished Jun 21 07:01:21 PM PDT 24
Peak memory 207020 kb
Host smart-9bc91a00-eb6e-4758-9482-4840b6767f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182278152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1182278152
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.729723559
Short name T231
Test name
Test status
Simulation time 18552679003 ps
CPU time 74.99 seconds
Started Jun 21 07:01:21 PM PDT 24
Finished Jun 21 07:02:38 PM PDT 24
Peak memory 254304 kb
Host smart-057e226c-69fb-47cd-a8c3-698456a9be3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729723559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.729723559
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.144185449
Short name T143
Test name
Test status
Simulation time 28300261006 ps
CPU time 248.76 seconds
Started Jun 21 07:01:20 PM PDT 24
Finished Jun 21 07:05:31 PM PDT 24
Peak memory 249448 kb
Host smart-c7c89818-7cfd-4ef9-bfb3-222340aca2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144185449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.144185449
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.254672795
Short name T222
Test name
Test status
Simulation time 6929142113 ps
CPU time 101.14 seconds
Started Jun 21 07:01:19 PM PDT 24
Finished Jun 21 07:03:02 PM PDT 24
Peak memory 255912 kb
Host smart-4f392b90-9d25-4e6d-8c46-f27942b8bdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254672795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.254672795
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.4210868515
Short name T28
Test name
Test status
Simulation time 1686689075 ps
CPU time 16.4 seconds
Started Jun 21 07:01:20 PM PDT 24
Finished Jun 21 07:01:39 PM PDT 24
Peak memory 237172 kb
Host smart-f11a1947-4f59-46d4-a383-87a960761c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210868515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.4210868515
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.17650185
Short name T392
Test name
Test status
Simulation time 53649083 ps
CPU time 2.54 seconds
Started Jun 21 07:01:23 PM PDT 24
Finished Jun 21 07:01:29 PM PDT 24
Peak memory 232876 kb
Host smart-73034a6b-14d0-4f20-8bba-5152d10fab4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17650185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.17650185
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1438939768
Short name T166
Test name
Test status
Simulation time 1038035740 ps
CPU time 5.73 seconds
Started Jun 21 07:01:20 PM PDT 24
Finished Jun 21 07:01:27 PM PDT 24
Peak memory 224172 kb
Host smart-77537629-2430-4517-b1a8-6c976fcbe2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438939768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1438939768
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.241600071
Short name T825
Test name
Test status
Simulation time 4388857523 ps
CPU time 4.49 seconds
Started Jun 21 07:01:20 PM PDT 24
Finished Jun 21 07:01:27 PM PDT 24
Peak memory 224740 kb
Host smart-07d974b5-e433-4dc0-98d1-a3fd88ecacc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241600071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.241600071
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1831719300
Short name T672
Test name
Test status
Simulation time 1315147585 ps
CPU time 7.46 seconds
Started Jun 21 07:01:26 PM PDT 24
Finished Jun 21 07:01:37 PM PDT 24
Peak memory 232840 kb
Host smart-a6624540-1ab3-4e00-8d15-7ccec950a6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831719300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1831719300
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1907087668
Short name T134
Test name
Test status
Simulation time 2269137643 ps
CPU time 9.47 seconds
Started Jun 21 07:01:18 PM PDT 24
Finished Jun 21 07:01:29 PM PDT 24
Peak memory 222380 kb
Host smart-1e504b0a-3262-43c1-81aa-bb408afe61f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1907087668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1907087668
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2940650577
Short name T870
Test name
Test status
Simulation time 67399269462 ps
CPU time 230.85 seconds
Started Jun 21 07:01:22 PM PDT 24
Finished Jun 21 07:05:17 PM PDT 24
Peak memory 272956 kb
Host smart-65d60f99-7efd-41f9-8ec6-e69223645efd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940650577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2940650577
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1167707963
Short name T42
Test name
Test status
Simulation time 6997864325 ps
CPU time 24.78 seconds
Started Jun 21 07:01:20 PM PDT 24
Finished Jun 21 07:01:47 PM PDT 24
Peak memory 216608 kb
Host smart-1471a6f8-3c66-42d5-9a0f-a51adcfc9e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167707963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1167707963
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2833696557
Short name T425
Test name
Test status
Simulation time 10098841799 ps
CPU time 25.66 seconds
Started Jun 21 07:01:22 PM PDT 24
Finished Jun 21 07:01:50 PM PDT 24
Peak memory 216516 kb
Host smart-2a400d30-fdaa-4c50-af0c-a09f5eb9416c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833696557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2833696557
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2402608476
Short name T451
Test name
Test status
Simulation time 216002492 ps
CPU time 1.08 seconds
Started Jun 21 07:01:21 PM PDT 24
Finished Jun 21 07:01:24 PM PDT 24
Peak memory 207212 kb
Host smart-c995e7c6-54f8-4050-874a-be031d90b13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402608476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2402608476
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2961642831
Short name T778
Test name
Test status
Simulation time 23304382 ps
CPU time 0.78 seconds
Started Jun 21 07:01:19 PM PDT 24
Finished Jun 21 07:01:21 PM PDT 24
Peak memory 206096 kb
Host smart-09640282-be93-4ba4-a424-99a5fa2d38ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961642831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2961642831
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2724486291
Short name T182
Test name
Test status
Simulation time 2139406481 ps
CPU time 8.1 seconds
Started Jun 21 07:01:20 PM PDT 24
Finished Jun 21 07:01:30 PM PDT 24
Peak memory 237840 kb
Host smart-dadfe760-1480-48ef-a9fb-14f2f4498965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724486291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2724486291
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1509188563
Short name T365
Test name
Test status
Simulation time 46806769 ps
CPU time 0.75 seconds
Started Jun 21 07:01:21 PM PDT 24
Finished Jun 21 07:01:24 PM PDT 24
Peak memory 204952 kb
Host smart-105d69ff-362f-473c-bd3e-cc03a51c54df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509188563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1509188563
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1086518995
Short name T173
Test name
Test status
Simulation time 18085191769 ps
CPU time 11.6 seconds
Started Jun 21 07:01:22 PM PDT 24
Finished Jun 21 07:01:37 PM PDT 24
Peak memory 224800 kb
Host smart-b5a68d81-f1a5-4d3e-924e-ab12b943de75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086518995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1086518995
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3046774823
Short name T339
Test name
Test status
Simulation time 58959516 ps
CPU time 0.81 seconds
Started Jun 21 07:01:18 PM PDT 24
Finished Jun 21 07:01:20 PM PDT 24
Peak memory 205652 kb
Host smart-cb7d2654-9467-4b75-b8ea-bf8143773e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046774823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3046774823
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.341826506
Short name T487
Test name
Test status
Simulation time 12707165480 ps
CPU time 41.34 seconds
Started Jun 21 07:01:22 PM PDT 24
Finished Jun 21 07:02:07 PM PDT 24
Peak memory 257476 kb
Host smart-238586eb-6640-4f9e-ae44-e3cf06951684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341826506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.341826506
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1279952800
Short name T285
Test name
Test status
Simulation time 9433669118 ps
CPU time 69.97 seconds
Started Jun 21 07:01:22 PM PDT 24
Finished Jun 21 07:02:36 PM PDT 24
Peak memory 249120 kb
Host smart-fd9c4e71-f8d1-49d2-93a3-bf93095acba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279952800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1279952800
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1780447929
Short name T394
Test name
Test status
Simulation time 443242341 ps
CPU time 8.09 seconds
Started Jun 21 07:01:26 PM PDT 24
Finished Jun 21 07:01:38 PM PDT 24
Peak memory 232832 kb
Host smart-8031aab6-7893-442a-a438-1d05666ba8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780447929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1780447929
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.947045472
Short name T614
Test name
Test status
Simulation time 90899472 ps
CPU time 3.34 seconds
Started Jun 21 07:01:21 PM PDT 24
Finished Jun 21 07:01:27 PM PDT 24
Peak memory 232820 kb
Host smart-ee5a5026-3bce-4680-b0aa-0d6bb8b312a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947045472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.947045472
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2618754119
Short name T736
Test name
Test status
Simulation time 11001484706 ps
CPU time 8.28 seconds
Started Jun 21 07:01:26 PM PDT 24
Finished Jun 21 07:01:38 PM PDT 24
Peak memory 232960 kb
Host smart-979cd18c-5982-44d9-84bd-1d1bab92fb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618754119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2618754119
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3065254537
Short name T625
Test name
Test status
Simulation time 151317544 ps
CPU time 2.18 seconds
Started Jun 21 07:01:20 PM PDT 24
Finished Jun 21 07:01:23 PM PDT 24
Peak memory 222904 kb
Host smart-80defc1b-eee6-4234-abff-ccb818f00b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065254537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3065254537
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3823399142
Short name T280
Test name
Test status
Simulation time 738651389 ps
CPU time 3.4 seconds
Started Jun 21 07:01:21 PM PDT 24
Finished Jun 21 07:01:26 PM PDT 24
Peak memory 232860 kb
Host smart-2456f587-34fd-42cd-a6bf-2ed4b7edbfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823399142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3823399142
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3990640047
Short name T830
Test name
Test status
Simulation time 1307356090 ps
CPU time 8.14 seconds
Started Jun 21 07:01:25 PM PDT 24
Finished Jun 21 07:01:38 PM PDT 24
Peak memory 223204 kb
Host smart-5726c931-f669-4d78-b8bf-3b677b26145f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3990640047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3990640047
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2192327961
Short name T70
Test name
Test status
Simulation time 33529996 ps
CPU time 0.9 seconds
Started Jun 21 07:01:23 PM PDT 24
Finished Jun 21 07:01:27 PM PDT 24
Peak memory 205732 kb
Host smart-4738a21e-fd16-4cd5-90f5-bd0847979dbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192327961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2192327961
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3204155435
Short name T909
Test name
Test status
Simulation time 3890596784 ps
CPU time 9.7 seconds
Started Jun 21 07:01:25 PM PDT 24
Finished Jun 21 07:01:39 PM PDT 24
Peak memory 216528 kb
Host smart-cb937f3d-8ad3-494c-9cfe-db0c9b47bb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204155435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3204155435
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.4147604397
Short name T537
Test name
Test status
Simulation time 6484609344 ps
CPU time 6.81 seconds
Started Jun 21 07:01:23 PM PDT 24
Finished Jun 21 07:01:34 PM PDT 24
Peak memory 216528 kb
Host smart-d03f6b7a-0bbc-4eaf-aaa0-ee36f92072e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147604397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.4147604397
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2210300590
Short name T341
Test name
Test status
Simulation time 650714622 ps
CPU time 7.34 seconds
Started Jun 21 07:01:20 PM PDT 24
Finished Jun 21 07:01:30 PM PDT 24
Peak memory 216472 kb
Host smart-bfb3ebc6-cf80-4937-ae23-55f2d7d66be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210300590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2210300590
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3089400146
Short name T390
Test name
Test status
Simulation time 123441044 ps
CPU time 0.95 seconds
Started Jun 21 07:01:21 PM PDT 24
Finished Jun 21 07:01:25 PM PDT 24
Peak memory 206332 kb
Host smart-a2beac3a-c5af-4def-8469-7064089b2628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089400146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3089400146
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.342343593
Short name T806
Test name
Test status
Simulation time 1949967465 ps
CPU time 8.39 seconds
Started Jun 21 07:01:24 PM PDT 24
Finished Jun 21 07:01:36 PM PDT 24
Peak memory 224648 kb
Host smart-ae4cd41f-d6c0-43e1-9021-e3dcf923b30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342343593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.342343593
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2388449039
Short name T889
Test name
Test status
Simulation time 27911327 ps
CPU time 0.78 seconds
Started Jun 21 07:01:33 PM PDT 24
Finished Jun 21 07:01:44 PM PDT 24
Peak memory 205592 kb
Host smart-990a822e-70c4-4b52-927c-6e26d65c1dd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388449039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2388449039
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1492915904
Short name T805
Test name
Test status
Simulation time 2795996429 ps
CPU time 7.62 seconds
Started Jun 21 07:01:30 PM PDT 24
Finished Jun 21 07:01:44 PM PDT 24
Peak memory 232904 kb
Host smart-e4240c18-7faa-41f9-93ee-99b600e66fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492915904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1492915904
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3561243779
Short name T942
Test name
Test status
Simulation time 16699357 ps
CPU time 0.75 seconds
Started Jun 21 07:01:23 PM PDT 24
Finished Jun 21 07:01:28 PM PDT 24
Peak memory 206740 kb
Host smart-47847565-b654-41f0-9342-ab915064de41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561243779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3561243779
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.528458312
Short name T277
Test name
Test status
Simulation time 11476475175 ps
CPU time 63.04 seconds
Started Jun 21 07:01:30 PM PDT 24
Finished Jun 21 07:02:40 PM PDT 24
Peak memory 252836 kb
Host smart-5c21cd48-5ad3-4e6b-966a-01e9bb61e7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528458312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.528458312
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1577847260
Short name T541
Test name
Test status
Simulation time 21223886 ps
CPU time 0.8 seconds
Started Jun 21 07:01:28 PM PDT 24
Finished Jun 21 07:01:34 PM PDT 24
Peak memory 217068 kb
Host smart-c5e52ac1-108b-4bc4-8e9e-cf7b142daccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577847260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1577847260
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2828918770
Short name T868
Test name
Test status
Simulation time 313958161757 ps
CPU time 555.44 seconds
Started Jun 21 07:01:30 PM PDT 24
Finished Jun 21 07:10:52 PM PDT 24
Peak memory 266272 kb
Host smart-9a5293e7-e1e6-4db2-aa5e-84fd7dc54d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828918770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2828918770
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.386455867
Short name T470
Test name
Test status
Simulation time 630613961 ps
CPU time 14.55 seconds
Started Jun 21 07:01:33 PM PDT 24
Finished Jun 21 07:01:57 PM PDT 24
Peak memory 241080 kb
Host smart-dedd45b5-6f8c-43ad-99e9-0b8ac405607d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386455867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.386455867
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2605096647
Short name T53
Test name
Test status
Simulation time 748383275 ps
CPU time 6.99 seconds
Started Jun 21 07:01:27 PM PDT 24
Finished Jun 21 07:01:38 PM PDT 24
Peak memory 224648 kb
Host smart-768c0fde-cd17-4bf1-bd9a-a964832b4ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605096647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2605096647
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3331656699
Short name T202
Test name
Test status
Simulation time 3382100027 ps
CPU time 23.1 seconds
Started Jun 21 07:01:29 PM PDT 24
Finished Jun 21 07:01:57 PM PDT 24
Peak memory 224752 kb
Host smart-f50bc5f5-a786-4d6b-b1dd-15f34069d5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331656699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3331656699
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1380096742
Short name T162
Test name
Test status
Simulation time 2608339337 ps
CPU time 5.99 seconds
Started Jun 21 07:01:31 PM PDT 24
Finished Jun 21 07:01:45 PM PDT 24
Peak memory 232920 kb
Host smart-7356deae-35f6-4159-b656-e2abfb7cd368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380096742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1380096742
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2644085230
Short name T153
Test name
Test status
Simulation time 104317764 ps
CPU time 2.08 seconds
Started Jun 21 07:01:28 PM PDT 24
Finished Jun 21 07:01:35 PM PDT 24
Peak memory 224684 kb
Host smart-0b8c2fec-fc62-4956-85ee-97f2b31ae7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644085230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2644085230
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.905443809
Short name T648
Test name
Test status
Simulation time 360144125 ps
CPU time 3.88 seconds
Started Jun 21 07:01:30 PM PDT 24
Finished Jun 21 07:01:41 PM PDT 24
Peak memory 222684 kb
Host smart-744e98a1-2c9a-42fb-b6fa-477ec585b3c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=905443809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.905443809
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.571227268
Short name T927
Test name
Test status
Simulation time 12807959275 ps
CPU time 97.15 seconds
Started Jun 21 07:01:29 PM PDT 24
Finished Jun 21 07:03:11 PM PDT 24
Peak memory 264224 kb
Host smart-6b9c8af9-7b62-4913-a906-a0dc6b16749f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571227268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.571227268
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3004815445
Short name T382
Test name
Test status
Simulation time 1338383855 ps
CPU time 7.87 seconds
Started Jun 21 07:01:22 PM PDT 24
Finished Jun 21 07:01:32 PM PDT 24
Peak memory 216416 kb
Host smart-64d3c100-bbc3-4011-94c9-a517e776096f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004815445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3004815445
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3637331309
Short name T879
Test name
Test status
Simulation time 23074330981 ps
CPU time 15.02 seconds
Started Jun 21 07:01:22 PM PDT 24
Finished Jun 21 07:01:40 PM PDT 24
Peak memory 216568 kb
Host smart-9fa7b6d4-1dd8-4c2d-a845-0e3081a09c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637331309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3637331309
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3193403362
Short name T861
Test name
Test status
Simulation time 652127789 ps
CPU time 4.21 seconds
Started Jun 21 07:01:26 PM PDT 24
Finished Jun 21 07:01:34 PM PDT 24
Peak memory 216412 kb
Host smart-7e484f9d-22c8-41b7-95c6-3361a07e1bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193403362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3193403362
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.60619266
Short name T72
Test name
Test status
Simulation time 125596712 ps
CPU time 0.82 seconds
Started Jun 21 07:01:25 PM PDT 24
Finished Jun 21 07:01:30 PM PDT 24
Peak memory 206076 kb
Host smart-53869211-0e1d-41f2-9ac9-629507277bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60619266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.60619266
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2191838699
Short name T495
Test name
Test status
Simulation time 1028612105 ps
CPU time 8.98 seconds
Started Jun 21 07:01:33 PM PDT 24
Finished Jun 21 07:01:51 PM PDT 24
Peak memory 249132 kb
Host smart-bd31f41d-e582-4454-991b-47da9739ef08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191838699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2191838699
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2497595429
Short name T336
Test name
Test status
Simulation time 21846069 ps
CPU time 0.7 seconds
Started Jun 21 07:01:31 PM PDT 24
Finished Jun 21 07:01:39 PM PDT 24
Peak memory 204940 kb
Host smart-1d0cfdc1-3de6-4c6a-9e9a-f31cee9240dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497595429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2497595429
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.37817145
Short name T258
Test name
Test status
Simulation time 547469951 ps
CPU time 6.86 seconds
Started Jun 21 07:01:35 PM PDT 24
Finished Jun 21 07:01:51 PM PDT 24
Peak memory 232804 kb
Host smart-c3c17087-618d-4d5a-933e-aa4469e55cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37817145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.37817145
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.4047921417
Short name T388
Test name
Test status
Simulation time 26898212 ps
CPU time 0.76 seconds
Started Jun 21 07:01:31 PM PDT 24
Finished Jun 21 07:01:40 PM PDT 24
Peak memory 205712 kb
Host smart-3e329f71-fdfe-4b2e-b973-55845a2a6c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047921417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.4047921417
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3067988406
Short name T932
Test name
Test status
Simulation time 1669449123 ps
CPU time 18.88 seconds
Started Jun 21 07:01:27 PM PDT 24
Finished Jun 21 07:01:50 PM PDT 24
Peak memory 248512 kb
Host smart-2dd48652-92a7-413a-9e69-2afd402bf850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067988406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3067988406
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2709920716
Short name T377
Test name
Test status
Simulation time 12015099968 ps
CPU time 113.29 seconds
Started Jun 21 07:01:27 PM PDT 24
Finished Jun 21 07:03:24 PM PDT 24
Peak memory 241180 kb
Host smart-ce9a4fd1-007a-4a80-8670-8112a2984da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709920716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2709920716
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.469068154
Short name T533
Test name
Test status
Simulation time 7501112488 ps
CPU time 41.86 seconds
Started Jun 21 07:01:31 PM PDT 24
Finished Jun 21 07:02:21 PM PDT 24
Peak memory 217868 kb
Host smart-2f3e7049-c641-4c8c-9257-51e85380a716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469068154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.469068154
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1491121954
Short name T899
Test name
Test status
Simulation time 1347828605 ps
CPU time 23.85 seconds
Started Jun 21 07:01:31 PM PDT 24
Finished Jun 21 07:02:03 PM PDT 24
Peak memory 232940 kb
Host smart-c1a72c0e-5b12-474e-8554-7c41fa2f8977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491121954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1491121954
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.689842589
Short name T842
Test name
Test status
Simulation time 59366337 ps
CPU time 2.4 seconds
Started Jun 21 07:01:29 PM PDT 24
Finished Jun 21 07:01:36 PM PDT 24
Peak memory 226704 kb
Host smart-fb6ec16e-8df6-4d28-a6c3-bca2e29d3650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689842589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.689842589
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3439238398
Short name T167
Test name
Test status
Simulation time 1753119903 ps
CPU time 9.09 seconds
Started Jun 21 07:01:32 PM PDT 24
Finished Jun 21 07:01:50 PM PDT 24
Peak memory 224328 kb
Host smart-f8278105-aed3-4c73-8a4e-0b69b9da2189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439238398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3439238398
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1325959087
Short name T176
Test name
Test status
Simulation time 2471260709 ps
CPU time 8.87 seconds
Started Jun 21 07:01:31 PM PDT 24
Finished Jun 21 07:01:48 PM PDT 24
Peak memory 240656 kb
Host smart-d7b0d740-8a89-4a29-95cb-e872c662d8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325959087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1325959087
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1535095981
Short name T728
Test name
Test status
Simulation time 129333843 ps
CPU time 3.37 seconds
Started Jun 21 07:01:27 PM PDT 24
Finished Jun 21 07:01:34 PM PDT 24
Peak memory 232948 kb
Host smart-770a8928-18e3-402e-9182-5c11630ac2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535095981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1535095981
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3930952361
Short name T873
Test name
Test status
Simulation time 478259124 ps
CPU time 6.09 seconds
Started Jun 21 07:01:31 PM PDT 24
Finished Jun 21 07:01:46 PM PDT 24
Peak memory 222444 kb
Host smart-85f95157-b23b-4dde-9bbd-2d8fda5a3b86
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3930952361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3930952361
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3056597492
Short name T697
Test name
Test status
Simulation time 10084082326 ps
CPU time 82.73 seconds
Started Jun 21 07:01:29 PM PDT 24
Finished Jun 21 07:02:57 PM PDT 24
Peak memory 257664 kb
Host smart-3821dd88-d585-4bc0-917a-7111ff0fa98d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056597492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3056597492
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2138553815
Short name T746
Test name
Test status
Simulation time 2113515351 ps
CPU time 16.51 seconds
Started Jun 21 07:01:29 PM PDT 24
Finished Jun 21 07:01:51 PM PDT 24
Peak memory 216480 kb
Host smart-91fabe9b-9e27-4a0b-8768-d5df60f61f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138553815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2138553815
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3563092583
Short name T558
Test name
Test status
Simulation time 10960125357 ps
CPU time 9.39 seconds
Started Jun 21 07:01:29 PM PDT 24
Finished Jun 21 07:01:45 PM PDT 24
Peak memory 216560 kb
Host smart-cb29effc-9b0b-429b-aecc-3b1dfef4cf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563092583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3563092583
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1219638836
Short name T944
Test name
Test status
Simulation time 214584585 ps
CPU time 1.78 seconds
Started Jun 21 07:01:30 PM PDT 24
Finished Jun 21 07:01:38 PM PDT 24
Peak memory 216448 kb
Host smart-ea78ec78-d4f3-4a2a-ac99-e04a9006daa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219638836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1219638836
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2782967196
Short name T416
Test name
Test status
Simulation time 110132213 ps
CPU time 0.79 seconds
Started Jun 21 07:01:32 PM PDT 24
Finished Jun 21 07:01:42 PM PDT 24
Peak memory 206104 kb
Host smart-73c05740-94e8-4d6b-a394-d4b7e220a1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782967196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2782967196
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.4250927438
Short name T643
Test name
Test status
Simulation time 406680963 ps
CPU time 3.16 seconds
Started Jun 21 07:01:30 PM PDT 24
Finished Jun 21 07:01:40 PM PDT 24
Peak memory 224672 kb
Host smart-7c29e26f-7af0-49d0-bcf1-4f2d1afd8f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250927438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.4250927438
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.620052542
Short name T844
Test name
Test status
Simulation time 12634019 ps
CPU time 0.69 seconds
Started Jun 21 07:01:32 PM PDT 24
Finished Jun 21 07:01:42 PM PDT 24
Peak memory 205272 kb
Host smart-ba632923-625a-4a2a-b8fe-32c942a9fcab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620052542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.620052542
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2736486518
Short name T554
Test name
Test status
Simulation time 237270660 ps
CPU time 3.43 seconds
Started Jun 21 07:01:32 PM PDT 24
Finished Jun 21 07:01:44 PM PDT 24
Peak memory 232836 kb
Host smart-ec5bb522-96e6-4fce-bcda-6c0859109274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736486518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2736486518
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.388150346
Short name T832
Test name
Test status
Simulation time 44632701 ps
CPU time 0.73 seconds
Started Jun 21 07:01:31 PM PDT 24
Finished Jun 21 07:01:40 PM PDT 24
Peak memory 205728 kb
Host smart-c1d67c97-582a-4f94-8753-784dfbbb3d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388150346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.388150346
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2167319954
Short name T767
Test name
Test status
Simulation time 7052968475 ps
CPU time 17.18 seconds
Started Jun 21 07:01:32 PM PDT 24
Finished Jun 21 07:01:58 PM PDT 24
Peak memory 232988 kb
Host smart-ed3111d0-85fb-4d53-84fc-e19e8f7bd109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167319954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2167319954
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3525841186
Short name T498
Test name
Test status
Simulation time 20102398573 ps
CPU time 81.67 seconds
Started Jun 21 07:01:35 PM PDT 24
Finished Jun 21 07:03:06 PM PDT 24
Peak memory 240696 kb
Host smart-73d247eb-8347-4f20-9415-1b39199457fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525841186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3525841186
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.457298752
Short name T228
Test name
Test status
Simulation time 25647832580 ps
CPU time 125.36 seconds
Started Jun 21 07:01:29 PM PDT 24
Finished Jun 21 07:03:41 PM PDT 24
Peak memory 265788 kb
Host smart-f1debc83-7aeb-468b-9d35-0cfd283f4617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457298752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.457298752
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3651511156
Short name T955
Test name
Test status
Simulation time 21752348423 ps
CPU time 66.6 seconds
Started Jun 21 07:01:35 PM PDT 24
Finished Jun 21 07:02:50 PM PDT 24
Peak memory 224796 kb
Host smart-0be504d3-4e1f-4f98-8395-d87afc37d15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651511156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3651511156
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3199896655
Short name T349
Test name
Test status
Simulation time 1392679305 ps
CPU time 2.19 seconds
Started Jun 21 07:01:31 PM PDT 24
Finished Jun 21 07:01:41 PM PDT 24
Peak memory 223228 kb
Host smart-64b78906-967c-4893-adca-3db9a7b1cce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199896655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3199896655
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2338408177
Short name T759
Test name
Test status
Simulation time 123242604 ps
CPU time 2.51 seconds
Started Jun 21 07:01:31 PM PDT 24
Finished Jun 21 07:01:41 PM PDT 24
Peak memory 232556 kb
Host smart-39d6b089-b152-4fa3-a3d6-0dc7fb6f7e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338408177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2338408177
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1516857798
Short name T433
Test name
Test status
Simulation time 1761201110 ps
CPU time 2.85 seconds
Started Jun 21 07:01:29 PM PDT 24
Finished Jun 21 07:01:39 PM PDT 24
Peak memory 224640 kb
Host smart-e43278e6-50cb-414b-9eac-ddd75b47f8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516857798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1516857798
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2850715274
Short name T172
Test name
Test status
Simulation time 377124170 ps
CPU time 5.75 seconds
Started Jun 21 07:01:30 PM PDT 24
Finished Jun 21 07:01:41 PM PDT 24
Peak memory 240988 kb
Host smart-77cb1b97-b999-467f-8def-13ebff018395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850715274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2850715274
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3189233820
Short name T51
Test name
Test status
Simulation time 106952358 ps
CPU time 3.73 seconds
Started Jun 21 07:01:30 PM PDT 24
Finished Jun 21 07:01:39 PM PDT 24
Peak memory 219128 kb
Host smart-757c6c79-b8a6-4691-b25c-e9754219ec53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3189233820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3189233820
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1680611759
Short name T897
Test name
Test status
Simulation time 72139533 ps
CPU time 1.08 seconds
Started Jun 21 07:01:30 PM PDT 24
Finished Jun 21 07:01:38 PM PDT 24
Peak memory 207080 kb
Host smart-f63cddb3-225c-4361-91e9-7e7da322e796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680611759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1680611759
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1199936105
Short name T712
Test name
Test status
Simulation time 1598614439 ps
CPU time 26.33 seconds
Started Jun 21 07:01:27 PM PDT 24
Finished Jun 21 07:01:58 PM PDT 24
Peak memory 219356 kb
Host smart-0ce56c35-9ddc-43f4-aa9c-801c15f1ee38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199936105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1199936105
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2642914542
Short name T507
Test name
Test status
Simulation time 8627616369 ps
CPU time 10.38 seconds
Started Jun 21 07:01:31 PM PDT 24
Finished Jun 21 07:01:49 PM PDT 24
Peak memory 216564 kb
Host smart-2e25d3c2-d18d-44ec-9842-41f03830dfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642914542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2642914542
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1885112008
Short name T883
Test name
Test status
Simulation time 14615332 ps
CPU time 0.79 seconds
Started Jun 21 07:01:33 PM PDT 24
Finished Jun 21 07:01:43 PM PDT 24
Peak memory 206132 kb
Host smart-9b90308c-3dc0-401a-9a9f-56ef4c6c3816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885112008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1885112008
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1266424074
Short name T737
Test name
Test status
Simulation time 90801854 ps
CPU time 0.92 seconds
Started Jun 21 07:01:35 PM PDT 24
Finished Jun 21 07:01:45 PM PDT 24
Peak memory 206108 kb
Host smart-faa3e184-5476-4899-964b-19c1e1e86c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266424074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1266424074
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.580276561
Short name T485
Test name
Test status
Simulation time 6488823306 ps
CPU time 22.59 seconds
Started Jun 21 07:01:29 PM PDT 24
Finished Jun 21 07:01:56 PM PDT 24
Peak memory 232940 kb
Host smart-b5183ab5-0e11-43aa-9937-bcecb97493b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580276561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.580276561
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2411442501
Short name T680
Test name
Test status
Simulation time 13749045 ps
CPU time 0.72 seconds
Started Jun 21 07:01:38 PM PDT 24
Finished Jun 21 07:01:47 PM PDT 24
Peak memory 204940 kb
Host smart-bf6fe0e9-b877-4745-ac00-bd15f6005b46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411442501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2411442501
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3457759227
Short name T606
Test name
Test status
Simulation time 2495102080 ps
CPU time 6.72 seconds
Started Jun 21 07:01:37 PM PDT 24
Finished Jun 21 07:01:52 PM PDT 24
Peak memory 232976 kb
Host smart-fc26e84f-0a33-4a8b-9172-68a7e2fd47b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457759227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3457759227
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3879703630
Short name T877
Test name
Test status
Simulation time 66929507 ps
CPU time 0.84 seconds
Started Jun 21 07:01:29 PM PDT 24
Finished Jun 21 07:01:35 PM PDT 24
Peak memory 206760 kb
Host smart-59e16874-9ed4-44a5-855e-7c682f54f427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879703630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3879703630
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.36073390
Short name T587
Test name
Test status
Simulation time 23849004 ps
CPU time 0.76 seconds
Started Jun 21 07:01:38 PM PDT 24
Finished Jun 21 07:01:47 PM PDT 24
Peak memory 215984 kb
Host smart-8b56bbab-216f-4b0a-af68-e92e33434e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36073390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.36073390
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3877249834
Short name T695
Test name
Test status
Simulation time 2069804965 ps
CPU time 29.95 seconds
Started Jun 21 07:01:39 PM PDT 24
Finished Jun 21 07:02:17 PM PDT 24
Peak memory 249260 kb
Host smart-92307cad-9eb8-48f9-9e4b-07528f7d62c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877249834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3877249834
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2200031442
Short name T229
Test name
Test status
Simulation time 8630337420 ps
CPU time 108.61 seconds
Started Jun 21 07:01:37 PM PDT 24
Finished Jun 21 07:03:34 PM PDT 24
Peak memory 253864 kb
Host smart-25e1586e-bf7d-49aa-a2af-8abc56be8208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200031442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2200031442
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3487178343
Short name T318
Test name
Test status
Simulation time 9477428806 ps
CPU time 52.66 seconds
Started Jun 21 07:01:39 PM PDT 24
Finished Jun 21 07:02:39 PM PDT 24
Peak memory 233628 kb
Host smart-bc55e5bc-7b4d-48c3-a014-71c2dc868e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487178343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3487178343
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1274991213
Short name T807
Test name
Test status
Simulation time 118405093 ps
CPU time 2.1 seconds
Started Jun 21 07:01:32 PM PDT 24
Finished Jun 21 07:01:42 PM PDT 24
Peak memory 232576 kb
Host smart-77874fa7-0414-4898-9711-8356d0359181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274991213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1274991213
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3716944683
Short name T198
Test name
Test status
Simulation time 8618576274 ps
CPU time 67.77 seconds
Started Jun 21 07:01:32 PM PDT 24
Finished Jun 21 07:02:49 PM PDT 24
Peak memory 238500 kb
Host smart-691b551e-20d9-4d4e-a7ee-77afcebc8c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716944683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3716944683
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3189494886
Short name T50
Test name
Test status
Simulation time 1133946402 ps
CPU time 7.31 seconds
Started Jun 21 07:01:30 PM PDT 24
Finished Jun 21 07:01:45 PM PDT 24
Peak memory 232836 kb
Host smart-73b75cde-f7ef-4140-a229-f378cc0ba621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189494886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3189494886
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2512374092
Short name T851
Test name
Test status
Simulation time 1143543640 ps
CPU time 12.07 seconds
Started Jun 21 07:01:28 PM PDT 24
Finished Jun 21 07:01:45 PM PDT 24
Peak memory 241072 kb
Host smart-11b09b59-32bf-452b-9581-cf5531fae9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512374092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2512374092
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3899282544
Short name T596
Test name
Test status
Simulation time 4526716480 ps
CPU time 10.02 seconds
Started Jun 21 07:01:39 PM PDT 24
Finished Jun 21 07:01:57 PM PDT 24
Peak memory 222260 kb
Host smart-7b3fca11-8685-42c1-91b2-09e07a595699
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3899282544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3899282544
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2626870630
Short name T803
Test name
Test status
Simulation time 42940196 ps
CPU time 0.93 seconds
Started Jun 21 07:01:53 PM PDT 24
Finished Jun 21 07:02:02 PM PDT 24
Peak memory 205912 kb
Host smart-dd2ba51f-cd57-4d0b-9af1-57576e5e6f66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626870630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2626870630
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2076196726
Short name T328
Test name
Test status
Simulation time 3708435212 ps
CPU time 20.26 seconds
Started Jun 21 07:01:29 PM PDT 24
Finished Jun 21 07:01:55 PM PDT 24
Peak memory 216552 kb
Host smart-8b39c892-8559-4a74-89a2-d988ef6b6b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076196726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2076196726
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.4231151949
Short name T518
Test name
Test status
Simulation time 14119570 ps
CPU time 0.73 seconds
Started Jun 21 07:01:33 PM PDT 24
Finished Jun 21 07:01:43 PM PDT 24
Peak memory 205828 kb
Host smart-342ac9f1-1033-44e0-bac3-427f4c2c1b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231151949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.4231151949
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3255161546
Short name T455
Test name
Test status
Simulation time 150265254 ps
CPU time 2.49 seconds
Started Jun 21 07:01:30 PM PDT 24
Finished Jun 21 07:01:38 PM PDT 24
Peak memory 216384 kb
Host smart-632392fa-16d0-422e-b3dc-1c4525ae83e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255161546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3255161546
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3190297235
Short name T351
Test name
Test status
Simulation time 232367033 ps
CPU time 0.88 seconds
Started Jun 21 07:01:29 PM PDT 24
Finished Jun 21 07:01:36 PM PDT 24
Peak memory 206124 kb
Host smart-b642b40e-e6bc-4d04-85d0-3970ae68c2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190297235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3190297235
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1152330711
Short name T826
Test name
Test status
Simulation time 2134143449 ps
CPU time 10.45 seconds
Started Jun 21 07:01:33 PM PDT 24
Finished Jun 21 07:01:53 PM PDT 24
Peak memory 240920 kb
Host smart-1d951712-c18b-44c7-bc8a-7756b3841042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152330711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1152330711
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3505417236
Short name T531
Test name
Test status
Simulation time 27958972 ps
CPU time 0.73 seconds
Started Jun 21 07:01:40 PM PDT 24
Finished Jun 21 07:01:49 PM PDT 24
Peak memory 204992 kb
Host smart-0685cf15-2141-4f7c-9905-5956eef4ca0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505417236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3505417236
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3692449508
Short name T595
Test name
Test status
Simulation time 3198256612 ps
CPU time 14.37 seconds
Started Jun 21 07:01:37 PM PDT 24
Finished Jun 21 07:01:59 PM PDT 24
Peak memory 232984 kb
Host smart-83eff68c-b5b8-4310-a352-86876e5c4d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692449508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3692449508
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.803212310
Short name T530
Test name
Test status
Simulation time 76339545 ps
CPU time 0.8 seconds
Started Jun 21 07:01:40 PM PDT 24
Finished Jun 21 07:01:49 PM PDT 24
Peak memory 206720 kb
Host smart-8089bef5-0f11-41fc-8caa-9d6fd2caa00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803212310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.803212310
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2695175014
Short name T412
Test name
Test status
Simulation time 6254149496 ps
CPU time 39.8 seconds
Started Jun 21 07:01:36 PM PDT 24
Finished Jun 21 07:02:24 PM PDT 24
Peak memory 249412 kb
Host smart-610be4c8-5114-4534-8cb4-1f857c01c132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695175014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2695175014
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1388717611
Short name T44
Test name
Test status
Simulation time 15429723566 ps
CPU time 139.67 seconds
Started Jun 21 07:01:41 PM PDT 24
Finished Jun 21 07:04:08 PM PDT 24
Peak memory 252064 kb
Host smart-0011b794-0ab0-4ea9-8b9d-418e00f81000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388717611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1388717611
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.846987918
Short name T133
Test name
Test status
Simulation time 115416716 ps
CPU time 3.82 seconds
Started Jun 21 07:01:38 PM PDT 24
Finished Jun 21 07:01:50 PM PDT 24
Peak memory 232868 kb
Host smart-68ab2e69-f116-4418-8f09-0fd344b63547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846987918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.846987918
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3526539284
Short name T265
Test name
Test status
Simulation time 298192237 ps
CPU time 2.82 seconds
Started Jun 21 07:01:35 PM PDT 24
Finished Jun 21 07:01:47 PM PDT 24
Peak memory 224596 kb
Host smart-5cb29f7a-f21c-4b59-9cd8-aa84cb02571e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526539284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3526539284
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.834379935
Short name T169
Test name
Test status
Simulation time 9492381051 ps
CPU time 95.27 seconds
Started Jun 21 07:01:41 PM PDT 24
Finished Jun 21 07:03:24 PM PDT 24
Peak memory 241208 kb
Host smart-026145db-894e-4a1a-819f-6e4cf5c6c759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834379935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.834379935
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2750358056
Short name T656
Test name
Test status
Simulation time 3249791285 ps
CPU time 6.34 seconds
Started Jun 21 07:01:40 PM PDT 24
Finished Jun 21 07:01:54 PM PDT 24
Peak memory 232908 kb
Host smart-8b8d60a1-9727-495d-9cfc-2ebb67ce1b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750358056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2750358056
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3300595894
Short name T653
Test name
Test status
Simulation time 3167273998 ps
CPU time 3.77 seconds
Started Jun 21 07:01:37 PM PDT 24
Finished Jun 21 07:01:49 PM PDT 24
Peak memory 224664 kb
Host smart-b6235934-bcec-4222-812e-9661f333af97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300595894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3300595894
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2760084887
Short name T743
Test name
Test status
Simulation time 3805944622 ps
CPU time 11.74 seconds
Started Jun 21 07:01:40 PM PDT 24
Finished Jun 21 07:02:00 PM PDT 24
Peak memory 221284 kb
Host smart-be1ace25-def5-4e64-8d18-551067044acd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2760084887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2760084887
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3098039327
Short name T724
Test name
Test status
Simulation time 13397330576 ps
CPU time 39.75 seconds
Started Jun 21 07:01:39 PM PDT 24
Finished Jun 21 07:02:26 PM PDT 24
Peak memory 217992 kb
Host smart-26380eaf-16c5-41e4-91bd-346dbe6c65bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098039327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3098039327
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2174059515
Short name T326
Test name
Test status
Simulation time 2359233688 ps
CPU time 5.63 seconds
Started Jun 21 07:01:39 PM PDT 24
Finished Jun 21 07:01:52 PM PDT 24
Peak memory 216544 kb
Host smart-fe262d56-84ad-481b-8dc0-c3456843aab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174059515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2174059515
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1783045984
Short name T908
Test name
Test status
Simulation time 84032376 ps
CPU time 1.17 seconds
Started Jun 21 07:01:38 PM PDT 24
Finished Jun 21 07:01:47 PM PDT 24
Peak memory 208096 kb
Host smart-2d98ea8c-90ee-47c4-ae1b-d2c203baf516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783045984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1783045984
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3530739980
Short name T925
Test name
Test status
Simulation time 60921404 ps
CPU time 1.42 seconds
Started Jun 21 07:01:40 PM PDT 24
Finished Jun 21 07:01:50 PM PDT 24
Peak memory 208196 kb
Host smart-90842262-b170-492d-bb0c-68a113e5adff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530739980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3530739980
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1251279296
Short name T12
Test name
Test status
Simulation time 20873667 ps
CPU time 0.73 seconds
Started Jun 21 07:01:37 PM PDT 24
Finished Jun 21 07:01:46 PM PDT 24
Peak memory 206100 kb
Host smart-254f3be2-1227-42b3-a26a-23e3a99ee95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251279296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1251279296
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.4098374084
Short name T831
Test name
Test status
Simulation time 14729596252 ps
CPU time 45.4 seconds
Started Jun 21 07:01:36 PM PDT 24
Finished Jun 21 07:02:30 PM PDT 24
Peak memory 240368 kb
Host smart-17b1b531-eb93-4290-82e6-0c0cb1beed6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098374084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.4098374084
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.809707514
Short name T471
Test name
Test status
Simulation time 48625918 ps
CPU time 0.72 seconds
Started Jun 21 07:01:39 PM PDT 24
Finished Jun 21 07:01:48 PM PDT 24
Peak memory 204940 kb
Host smart-a03e51ec-4c50-4491-b881-bff4dcd944aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809707514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.809707514
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2714251454
Short name T573
Test name
Test status
Simulation time 4482302050 ps
CPU time 13.08 seconds
Started Jun 21 07:01:40 PM PDT 24
Finished Jun 21 07:02:01 PM PDT 24
Peak memory 224756 kb
Host smart-1d3cb420-ff79-47d8-a37e-da57d6ac45f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714251454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2714251454
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.514811588
Short name T504
Test name
Test status
Simulation time 122402655 ps
CPU time 0.73 seconds
Started Jun 21 07:01:51 PM PDT 24
Finished Jun 21 07:02:00 PM PDT 24
Peak memory 205716 kb
Host smart-e5d91e9d-6eb7-4ac4-bb0f-47e2dceb184c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514811588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.514811588
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2221581488
Short name T836
Test name
Test status
Simulation time 91847608434 ps
CPU time 195.03 seconds
Started Jun 21 07:01:40 PM PDT 24
Finished Jun 21 07:05:03 PM PDT 24
Peak memory 251880 kb
Host smart-e1c2ff05-1bf0-4d10-a367-fe7ff3ff0382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221581488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2221581488
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.727293311
Short name T733
Test name
Test status
Simulation time 7916585684 ps
CPU time 26.1 seconds
Started Jun 21 07:01:41 PM PDT 24
Finished Jun 21 07:02:15 PM PDT 24
Peak memory 223596 kb
Host smart-2d974721-a966-49f6-a979-55bb327af46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727293311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.727293311
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.768392231
Short name T719
Test name
Test status
Simulation time 106758676374 ps
CPU time 160.66 seconds
Started Jun 21 07:01:38 PM PDT 24
Finished Jun 21 07:04:27 PM PDT 24
Peak memory 265840 kb
Host smart-22bedd3a-9ac6-4721-a858-2830ca2bb751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768392231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.768392231
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1448739121
Short name T673
Test name
Test status
Simulation time 1236497107 ps
CPU time 21.29 seconds
Started Jun 21 07:01:40 PM PDT 24
Finished Jun 21 07:02:09 PM PDT 24
Peak memory 224664 kb
Host smart-4a56fe4b-6f8a-4b17-b056-e95c32c36b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448739121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1448739121
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2315486092
Short name T268
Test name
Test status
Simulation time 1736650728 ps
CPU time 5.1 seconds
Started Jun 21 07:01:38 PM PDT 24
Finished Jun 21 07:01:51 PM PDT 24
Peak memory 232880 kb
Host smart-1275a349-9cbf-499f-8b52-4f8607c351e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315486092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2315486092
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3503203782
Short name T722
Test name
Test status
Simulation time 76582054 ps
CPU time 2.74 seconds
Started Jun 21 07:01:51 PM PDT 24
Finished Jun 21 07:02:02 PM PDT 24
Peak memory 232876 kb
Host smart-1f77db74-e541-4938-b23f-339f77bb7fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503203782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3503203782
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2690216124
Short name T40
Test name
Test status
Simulation time 826193477 ps
CPU time 12.29 seconds
Started Jun 21 07:01:45 PM PDT 24
Finished Jun 21 07:02:05 PM PDT 24
Peak memory 256544 kb
Host smart-00ec3eaf-54b1-4abf-9ab1-e3fed312a1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690216124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2690216124
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.4062510097
Short name T725
Test name
Test status
Simulation time 5240879361 ps
CPU time 9.29 seconds
Started Jun 21 07:01:44 PM PDT 24
Finished Jun 21 07:02:01 PM PDT 24
Peak memory 224720 kb
Host smart-fa34317f-b78d-48ce-88a4-abeddd0e9e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062510097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.4062510097
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2242772806
Short name T853
Test name
Test status
Simulation time 129181364 ps
CPU time 3.13 seconds
Started Jun 21 07:01:37 PM PDT 24
Finished Jun 21 07:01:48 PM PDT 24
Peak memory 219472 kb
Host smart-e9366a5f-1710-4ba5-8f13-1da1d0239507
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2242772806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2242772806
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1824202308
Short name T21
Test name
Test status
Simulation time 38034755 ps
CPU time 0.88 seconds
Started Jun 21 07:01:38 PM PDT 24
Finished Jun 21 07:01:48 PM PDT 24
Peak memory 207088 kb
Host smart-87640f0d-1c86-4c3b-9e0e-734dfb9d6a63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824202308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1824202308
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3323848949
Short name T572
Test name
Test status
Simulation time 247968949 ps
CPU time 2.9 seconds
Started Jun 21 07:01:36 PM PDT 24
Finished Jun 21 07:01:48 PM PDT 24
Peak memory 216608 kb
Host smart-3aef8e7c-0896-4f4e-870a-bf434f446a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323848949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3323848949
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.828890891
Short name T54
Test name
Test status
Simulation time 5903123116 ps
CPU time 5.32 seconds
Started Jun 21 07:01:38 PM PDT 24
Finished Jun 21 07:01:51 PM PDT 24
Peak memory 216532 kb
Host smart-9ad24889-ba49-4a7d-994b-8a22aa9566d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828890891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.828890891
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1486216422
Short name T862
Test name
Test status
Simulation time 29474540 ps
CPU time 1.08 seconds
Started Jun 21 07:01:38 PM PDT 24
Finished Jun 21 07:01:47 PM PDT 24
Peak memory 207212 kb
Host smart-01c99328-6d78-405a-89b9-a1af6034e9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486216422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1486216422
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.4085761820
Short name T639
Test name
Test status
Simulation time 92287756 ps
CPU time 0.76 seconds
Started Jun 21 07:01:38 PM PDT 24
Finished Jun 21 07:01:47 PM PDT 24
Peak memory 206100 kb
Host smart-41e1f343-dde3-4c46-91a9-8bf5324f9850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085761820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.4085761820
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2411499613
Short name T175
Test name
Test status
Simulation time 1587884193 ps
CPU time 7.34 seconds
Started Jun 21 07:01:39 PM PDT 24
Finished Jun 21 07:01:54 PM PDT 24
Peak memory 232864 kb
Host smart-8b1bc715-b94d-41fd-9db9-c9073a2adcfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411499613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2411499613
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2118306499
Short name T704
Test name
Test status
Simulation time 17138628 ps
CPU time 0.71 seconds
Started Jun 21 07:01:46 PM PDT 24
Finished Jun 21 07:01:55 PM PDT 24
Peak memory 205512 kb
Host smart-c54cd0f0-eb25-4a13-8dcf-f2f7c618e93f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118306499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2118306499
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2779684803
Short name T345
Test name
Test status
Simulation time 32784986 ps
CPU time 2.43 seconds
Started Jun 21 07:01:44 PM PDT 24
Finished Jun 21 07:01:55 PM PDT 24
Peak memory 232528 kb
Host smart-762d707c-b8e7-451d-b1dc-216bc37badf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779684803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2779684803
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1194074288
Short name T655
Test name
Test status
Simulation time 48287440 ps
CPU time 0.9 seconds
Started Jun 21 07:01:37 PM PDT 24
Finished Jun 21 07:01:47 PM PDT 24
Peak memory 206752 kb
Host smart-3e4537ca-17f0-4e17-8d03-807cecd6f963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194074288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1194074288
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3171150074
Short name T287
Test name
Test status
Simulation time 2635200930 ps
CPU time 19.47 seconds
Started Jun 21 07:01:46 PM PDT 24
Finished Jun 21 07:02:14 PM PDT 24
Peak memory 234972 kb
Host smart-9e08c267-f7e2-49c0-9e90-5c9b0f753286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171150074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3171150074
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3304401028
Short name T329
Test name
Test status
Simulation time 7760515037 ps
CPU time 41.42 seconds
Started Jun 21 07:01:46 PM PDT 24
Finished Jun 21 07:02:36 PM PDT 24
Peak memory 217876 kb
Host smart-1a7778f7-ddfb-4c9b-8e1f-a63785779c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304401028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3304401028
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1260501494
Short name T123
Test name
Test status
Simulation time 20223124218 ps
CPU time 114.36 seconds
Started Jun 21 07:01:46 PM PDT 24
Finished Jun 21 07:03:49 PM PDT 24
Peak memory 257508 kb
Host smart-1e47fc02-3c91-4907-a124-4294f609b849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260501494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1260501494
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2800796248
Short name T588
Test name
Test status
Simulation time 1685747463 ps
CPU time 11.26 seconds
Started Jun 21 07:01:38 PM PDT 24
Finished Jun 21 07:01:58 PM PDT 24
Peak memory 250048 kb
Host smart-779bf274-6a21-4b14-bff0-0303898af1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800796248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2800796248
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.4257160307
Short name T679
Test name
Test status
Simulation time 2814884326 ps
CPU time 25.49 seconds
Started Jun 21 07:01:45 PM PDT 24
Finished Jun 21 07:02:18 PM PDT 24
Peak memory 232988 kb
Host smart-5eb3e53e-9092-472b-a143-f3c1affa66fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257160307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.4257160307
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.774657777
Short name T568
Test name
Test status
Simulation time 824137872 ps
CPU time 9.37 seconds
Started Jun 21 07:01:39 PM PDT 24
Finished Jun 21 07:01:57 PM PDT 24
Peak memory 241032 kb
Host smart-48830115-c425-44f0-9f14-78bfa3468a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774657777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.774657777
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3316664340
Short name T308
Test name
Test status
Simulation time 40882360644 ps
CPU time 19.53 seconds
Started Jun 21 07:01:38 PM PDT 24
Finished Jun 21 07:02:05 PM PDT 24
Peak memory 240920 kb
Host smart-fa81d9ad-3b34-4938-a78b-5df986947851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316664340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3316664340
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2449099129
Short name T343
Test name
Test status
Simulation time 822311999 ps
CPU time 4.28 seconds
Started Jun 21 07:01:36 PM PDT 24
Finished Jun 21 07:01:49 PM PDT 24
Peak memory 232860 kb
Host smart-ef46e7ab-c47a-4d49-bb59-553940d76302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449099129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2449099129
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1016199201
Short name T901
Test name
Test status
Simulation time 272490705 ps
CPU time 5 seconds
Started Jun 21 07:01:47 PM PDT 24
Finished Jun 21 07:02:01 PM PDT 24
Peak memory 221900 kb
Host smart-5b7b38f7-cc7c-4be1-807a-22703026eb62
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1016199201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1016199201
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1042847478
Short name T152
Test name
Test status
Simulation time 43390591907 ps
CPU time 131.41 seconds
Started Jun 21 07:01:44 PM PDT 24
Finished Jun 21 07:04:04 PM PDT 24
Peak memory 257632 kb
Host smart-98f6d745-abe7-4109-a9a1-850b18684dc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042847478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1042847478
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3148716301
Short name T548
Test name
Test status
Simulation time 8317551225 ps
CPU time 10.94 seconds
Started Jun 21 07:01:37 PM PDT 24
Finished Jun 21 07:01:57 PM PDT 24
Peak memory 216480 kb
Host smart-c12afa3f-b9be-4b55-886e-37742ae759c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148716301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3148716301
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3988653687
Short name T867
Test name
Test status
Simulation time 14421427531 ps
CPU time 2.96 seconds
Started Jun 21 07:01:38 PM PDT 24
Finished Jun 21 07:01:50 PM PDT 24
Peak memory 208224 kb
Host smart-f34d5837-9770-4245-99aa-6a9371ac310d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988653687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3988653687
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.4051944851
Short name T641
Test name
Test status
Simulation time 63030824 ps
CPU time 1.53 seconds
Started Jun 21 07:01:36 PM PDT 24
Finished Jun 21 07:01:46 PM PDT 24
Peak memory 216388 kb
Host smart-eacb0271-c283-4fe2-ac3a-c965bc821f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051944851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.4051944851
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1892210232
Short name T116
Test name
Test status
Simulation time 241416234 ps
CPU time 0.81 seconds
Started Jun 21 07:01:45 PM PDT 24
Finished Jun 21 07:01:53 PM PDT 24
Peak memory 206100 kb
Host smart-07d3e2f7-605e-4357-a20b-2707acccceef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892210232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1892210232
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.135916655
Short name T291
Test name
Test status
Simulation time 1801679391 ps
CPU time 7.82 seconds
Started Jun 21 07:01:39 PM PDT 24
Finished Jun 21 07:01:55 PM PDT 24
Peak memory 239576 kb
Host smart-4716331b-78e2-4158-8516-2ccd51153c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135916655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.135916655
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.961365415
Short name T702
Test name
Test status
Simulation time 36338604 ps
CPU time 0.75 seconds
Started Jun 21 07:01:44 PM PDT 24
Finished Jun 21 07:01:53 PM PDT 24
Peak memory 205604 kb
Host smart-04bb3b78-1902-4686-9c45-ea3be3e0ebc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961365415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.961365415
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3616889142
Short name T664
Test name
Test status
Simulation time 169259404 ps
CPU time 3.98 seconds
Started Jun 21 07:01:46 PM PDT 24
Finished Jun 21 07:01:57 PM PDT 24
Peak memory 224636 kb
Host smart-50551011-6cb6-4c4e-94bf-0e8826669195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616889142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3616889142
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3332281321
Short name T436
Test name
Test status
Simulation time 17636418 ps
CPU time 0.79 seconds
Started Jun 21 07:01:46 PM PDT 24
Finished Jun 21 07:01:54 PM PDT 24
Peak memory 207040 kb
Host smart-41e1b8cb-5ce0-4a4a-a9fc-db4ebe3e64df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332281321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3332281321
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3639659964
Short name T34
Test name
Test status
Simulation time 20541946297 ps
CPU time 42.43 seconds
Started Jun 21 07:01:49 PM PDT 24
Finished Jun 21 07:02:40 PM PDT 24
Peak memory 249220 kb
Host smart-3a4ee869-2c09-4353-a0b4-1af4c0e177bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639659964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3639659964
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1217537717
Short name T896
Test name
Test status
Simulation time 99811727633 ps
CPU time 198.54 seconds
Started Jun 21 07:01:52 PM PDT 24
Finished Jun 21 07:05:19 PM PDT 24
Peak memory 257604 kb
Host smart-51b7ea68-c703-4898-816d-e373884ee979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217537717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1217537717
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2474287081
Short name T163
Test name
Test status
Simulation time 29705949360 ps
CPU time 199.62 seconds
Started Jun 21 07:01:51 PM PDT 24
Finished Jun 21 07:05:20 PM PDT 24
Peak memory 249388 kb
Host smart-1fd1b884-e30d-42b6-aa3f-bb62d1bbb2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474287081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2474287081
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1297624342
Short name T288
Test name
Test status
Simulation time 178786434 ps
CPU time 4.05 seconds
Started Jun 21 07:01:45 PM PDT 24
Finished Jun 21 07:01:57 PM PDT 24
Peak memory 224648 kb
Host smart-26e1e039-b11e-44a2-8c17-3f6b20f90ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297624342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1297624342
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2101461745
Short name T264
Test name
Test status
Simulation time 637889909 ps
CPU time 8.13 seconds
Started Jun 21 07:01:46 PM PDT 24
Finished Jun 21 07:02:02 PM PDT 24
Peak memory 224568 kb
Host smart-51b0816f-c82d-4c10-9e8f-2bf10208968b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101461745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2101461745
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2285214343
Short name T929
Test name
Test status
Simulation time 13534909054 ps
CPU time 58.6 seconds
Started Jun 21 07:01:46 PM PDT 24
Finished Jun 21 07:02:53 PM PDT 24
Peak memory 232932 kb
Host smart-e14b2aea-84a0-4883-977e-05f7cb38c8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285214343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2285214343
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1071069486
Short name T739
Test name
Test status
Simulation time 133546122 ps
CPU time 2.42 seconds
Started Jun 21 07:01:46 PM PDT 24
Finished Jun 21 07:01:57 PM PDT 24
Peak memory 224608 kb
Host smart-14ca77b9-3806-4b33-9a1c-1784d6b87a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071069486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1071069486
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2825682262
Short name T190
Test name
Test status
Simulation time 984984732 ps
CPU time 3.27 seconds
Started Jun 21 07:01:46 PM PDT 24
Finished Jun 21 07:01:58 PM PDT 24
Peak memory 232864 kb
Host smart-adbe1dd1-a01b-4d22-88a2-e4dd4ab73f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825682262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2825682262
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3314647585
Short name T838
Test name
Test status
Simulation time 3126796329 ps
CPU time 9.47 seconds
Started Jun 21 07:01:45 PM PDT 24
Finished Jun 21 07:02:02 PM PDT 24
Peak memory 223116 kb
Host smart-bd7263fc-8ba6-467d-b2a8-eb1b6cd1759e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3314647585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3314647585
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.538263986
Short name T24
Test name
Test status
Simulation time 17739334207 ps
CPU time 68.52 seconds
Started Jun 21 07:01:45 PM PDT 24
Finished Jun 21 07:03:01 PM PDT 24
Peak memory 240172 kb
Host smart-e914ac32-aef0-439a-be03-e9778b312637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538263986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.538263986
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2925731658
Short name T525
Test name
Test status
Simulation time 9707964877 ps
CPU time 17.51 seconds
Started Jun 21 07:01:46 PM PDT 24
Finished Jun 21 07:02:11 PM PDT 24
Peak memory 216476 kb
Host smart-f79d45a0-3c32-4fd1-b413-066d76d0a5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925731658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2925731658
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.86189935
Short name T841
Test name
Test status
Simulation time 579328764 ps
CPU time 2.33 seconds
Started Jun 21 07:01:44 PM PDT 24
Finished Jun 21 07:01:53 PM PDT 24
Peak memory 216248 kb
Host smart-48821a6b-37de-4b0c-bd43-a7cc7b5d16fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86189935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.86189935
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.842018566
Short name T492
Test name
Test status
Simulation time 806121657 ps
CPU time 8.34 seconds
Started Jun 21 07:01:47 PM PDT 24
Finished Jun 21 07:02:04 PM PDT 24
Peak memory 216384 kb
Host smart-105ffaee-25e2-46eb-9f15-eb26734d4570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842018566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.842018566
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.323797901
Short name T768
Test name
Test status
Simulation time 63829944 ps
CPU time 0.73 seconds
Started Jun 21 07:01:46 PM PDT 24
Finished Jun 21 07:01:55 PM PDT 24
Peak memory 206072 kb
Host smart-837af7f1-7fb8-4e3f-bf6c-94bb7e938fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323797901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.323797901
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1101743433
Short name T511
Test name
Test status
Simulation time 350940522 ps
CPU time 5.24 seconds
Started Jun 21 07:01:46 PM PDT 24
Finished Jun 21 07:01:59 PM PDT 24
Peak memory 224700 kb
Host smart-5d46de16-187f-4678-921a-091454f4af82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101743433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1101743433
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.4042893922
Short name T758
Test name
Test status
Simulation time 19578605 ps
CPU time 0.69 seconds
Started Jun 21 06:59:52 PM PDT 24
Finished Jun 21 06:59:56 PM PDT 24
Peak memory 204952 kb
Host smart-97bd06fd-0905-4a62-896f-8d57a7d09a9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042893922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.4
042893922
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.585148808
Short name T372
Test name
Test status
Simulation time 3965719702 ps
CPU time 11.05 seconds
Started Jun 21 07:00:02 PM PDT 24
Finished Jun 21 07:00:17 PM PDT 24
Peak memory 232912 kb
Host smart-6dd68ef8-b201-40e9-9733-4842caba7b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585148808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.585148808
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.272506239
Short name T602
Test name
Test status
Simulation time 43572070 ps
CPU time 0.77 seconds
Started Jun 21 06:59:55 PM PDT 24
Finished Jun 21 06:59:59 PM PDT 24
Peak memory 206760 kb
Host smart-3a1f9824-30e2-4d88-8375-76a978bcd724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272506239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.272506239
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3292096087
Short name T454
Test name
Test status
Simulation time 2874110330 ps
CPU time 37.38 seconds
Started Jun 21 07:00:02 PM PDT 24
Finished Jun 21 07:00:43 PM PDT 24
Peak memory 249384 kb
Host smart-1f015531-0fc7-4d19-8e3c-e51ba2aca000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292096087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3292096087
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1966177772
Short name T443
Test name
Test status
Simulation time 14477924791 ps
CPU time 28.37 seconds
Started Jun 21 06:59:54 PM PDT 24
Finished Jun 21 07:00:25 PM PDT 24
Peak memory 217856 kb
Host smart-aad3e01c-7e39-44a5-923a-2ed901e2b36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966177772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1966177772
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3768385814
Short name T15
Test name
Test status
Simulation time 12672650384 ps
CPU time 18.01 seconds
Started Jun 21 06:59:55 PM PDT 24
Finished Jun 21 07:00:16 PM PDT 24
Peak memory 217780 kb
Host smart-65db12d7-4dca-41f6-a06d-308ad78488f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768385814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3768385814
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3947007232
Short name T629
Test name
Test status
Simulation time 1399416703 ps
CPU time 3.13 seconds
Started Jun 21 06:59:54 PM PDT 24
Finished Jun 21 07:00:00 PM PDT 24
Peak memory 232856 kb
Host smart-5587c296-9f6c-4c54-8322-5e43b05addc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947007232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3947007232
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1854821282
Short name T598
Test name
Test status
Simulation time 943476204 ps
CPU time 6.72 seconds
Started Jun 21 06:59:52 PM PDT 24
Finished Jun 21 07:00:01 PM PDT 24
Peak memory 232896 kb
Host smart-7f4e129b-ed0b-4790-84e9-bea5d1cfc0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854821282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1854821282
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1804206334
Short name T385
Test name
Test status
Simulation time 1791492705 ps
CPU time 4.66 seconds
Started Jun 21 06:59:52 PM PDT 24
Finished Jun 21 07:00:00 PM PDT 24
Peak memory 224640 kb
Host smart-88c03122-71e2-4249-a9e0-95cf8cadf37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804206334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1804206334
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2446277439
Short name T240
Test name
Test status
Simulation time 232711073 ps
CPU time 2.8 seconds
Started Jun 21 06:59:59 PM PDT 24
Finished Jun 21 07:00:05 PM PDT 24
Peak memory 224604 kb
Host smart-f82f1ea9-36f3-4846-8169-529b5950f0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446277439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2446277439
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3396008302
Short name T450
Test name
Test status
Simulation time 481448008 ps
CPU time 3.21 seconds
Started Jun 21 06:59:52 PM PDT 24
Finished Jun 21 06:59:58 PM PDT 24
Peak memory 232888 kb
Host smart-e133ff0c-14db-41f7-bbd0-a649a518a818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396008302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3396008302
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.4229036347
Short name T611
Test name
Test status
Simulation time 1600176770 ps
CPU time 11.62 seconds
Started Jun 21 06:59:55 PM PDT 24
Finished Jun 21 07:00:10 PM PDT 24
Peak memory 223304 kb
Host smart-8fc38bb3-5bfc-4850-9bee-181bb99cca55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4229036347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.4229036347
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1987316457
Short name T63
Test name
Test status
Simulation time 121098826 ps
CPU time 1.09 seconds
Started Jun 21 07:00:02 PM PDT 24
Finished Jun 21 07:00:08 PM PDT 24
Peak memory 235764 kb
Host smart-481e8c99-9f6f-4134-a0d1-c938d02b430d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987316457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1987316457
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.408823655
Short name T579
Test name
Test status
Simulation time 12075830595 ps
CPU time 85.9 seconds
Started Jun 21 06:59:51 PM PDT 24
Finished Jun 21 07:01:20 PM PDT 24
Peak memory 257640 kb
Host smart-eab7ecd7-be59-474a-a60c-5dec23a25f15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408823655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.408823655
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3671672278
Short name T903
Test name
Test status
Simulation time 65670353109 ps
CPU time 26.3 seconds
Started Jun 21 06:59:51 PM PDT 24
Finished Jun 21 07:00:20 PM PDT 24
Peak memory 216472 kb
Host smart-c2527875-f59e-4826-9156-7b049be41b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671672278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3671672278
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2617812850
Short name T665
Test name
Test status
Simulation time 233531530 ps
CPU time 2.04 seconds
Started Jun 21 06:59:54 PM PDT 24
Finished Jun 21 06:59:59 PM PDT 24
Peak memory 216296 kb
Host smart-a349a1a0-6688-418b-8f8a-9d0533898b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617812850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2617812850
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.30385266
Short name T881
Test name
Test status
Simulation time 43774256 ps
CPU time 0.72 seconds
Started Jun 21 06:59:50 PM PDT 24
Finished Jun 21 06:59:55 PM PDT 24
Peak memory 206184 kb
Host smart-7c775a18-2d37-4745-8bde-ee2171e591f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30385266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.30385266
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3165812100
Short name T494
Test name
Test status
Simulation time 393312478 ps
CPU time 1.04 seconds
Started Jun 21 06:59:54 PM PDT 24
Finished Jun 21 06:59:58 PM PDT 24
Peak memory 207116 kb
Host smart-caf05bec-3f18-404f-b41c-8f5744a055c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165812100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3165812100
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3261802794
Short name T184
Test name
Test status
Simulation time 302492577 ps
CPU time 2.63 seconds
Started Jun 21 06:59:52 PM PDT 24
Finished Jun 21 06:59:57 PM PDT 24
Peak memory 224660 kb
Host smart-9e2bbe5f-94a6-43ae-8f57-f0d79d0292c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261802794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3261802794
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.684281894
Short name T8
Test name
Test status
Simulation time 24727124 ps
CPU time 0.71 seconds
Started Jun 21 07:01:48 PM PDT 24
Finished Jun 21 07:01:57 PM PDT 24
Peak memory 205508 kb
Host smart-039e29a7-4d06-400e-afa1-93763f445d5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684281894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.684281894
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3995852145
Short name T701
Test name
Test status
Simulation time 125425927 ps
CPU time 2.53 seconds
Started Jun 21 07:01:46 PM PDT 24
Finished Jun 21 07:01:57 PM PDT 24
Peak memory 232484 kb
Host smart-b3d96aa5-6c54-4364-8135-b95497d6436c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995852145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3995852145
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.941674235
Short name T681
Test name
Test status
Simulation time 132187922 ps
CPU time 0.77 seconds
Started Jun 21 07:01:46 PM PDT 24
Finished Jun 21 07:01:55 PM PDT 24
Peak memory 205728 kb
Host smart-e19fbef6-0262-4513-ab8c-f8338613f543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941674235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.941674235
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.709915664
Short name T221
Test name
Test status
Simulation time 84831153573 ps
CPU time 178.86 seconds
Started Jun 21 07:01:51 PM PDT 24
Finished Jun 21 07:04:59 PM PDT 24
Peak memory 264356 kb
Host smart-fde54208-d874-4dbd-afa6-aa2d8772d687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709915664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.709915664
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1778341510
Short name T524
Test name
Test status
Simulation time 4042530148 ps
CPU time 64.64 seconds
Started Jun 21 07:01:53 PM PDT 24
Finished Jun 21 07:03:07 PM PDT 24
Peak memory 249440 kb
Host smart-ffd3ebfb-5fd2-4f25-9a9c-71aacbe8a09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778341510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1778341510
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3130397413
Short name T319
Test name
Test status
Simulation time 2114231460 ps
CPU time 4.96 seconds
Started Jun 21 07:01:47 PM PDT 24
Finished Jun 21 07:02:01 PM PDT 24
Peak memory 224636 kb
Host smart-ae894448-666d-445b-8c52-858f2b4179e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130397413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3130397413
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2598928169
Short name T168
Test name
Test status
Simulation time 3129035926 ps
CPU time 10.4 seconds
Started Jun 21 07:01:47 PM PDT 24
Finished Jun 21 07:02:06 PM PDT 24
Peak memory 224612 kb
Host smart-ceee1c28-e7e3-4c1c-93b1-de994348ed5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598928169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2598928169
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.4120292593
Short name T922
Test name
Test status
Simulation time 34009847 ps
CPU time 2.11 seconds
Started Jun 21 07:01:46 PM PDT 24
Finished Jun 21 07:01:57 PM PDT 24
Peak memory 224572 kb
Host smart-5388987d-afe2-47ed-94d7-cc40c8018447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120292593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.4120292593
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.4207148098
Short name T776
Test name
Test status
Simulation time 1468069910 ps
CPU time 3.28 seconds
Started Jun 21 07:01:46 PM PDT 24
Finished Jun 21 07:01:58 PM PDT 24
Peak memory 224624 kb
Host smart-36b2b0af-0a34-4917-87d6-9d52ca9ff415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207148098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.4207148098
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.4150699793
Short name T375
Test name
Test status
Simulation time 267360070 ps
CPU time 5.8 seconds
Started Jun 21 07:01:53 PM PDT 24
Finished Jun 21 07:02:07 PM PDT 24
Peak memory 224688 kb
Host smart-d12821e5-5980-4288-89a3-846c9dfa63d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150699793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4150699793
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2499828669
Short name T564
Test name
Test status
Simulation time 3145609300 ps
CPU time 10.17 seconds
Started Jun 21 07:01:49 PM PDT 24
Finished Jun 21 07:02:07 PM PDT 24
Peak memory 223300 kb
Host smart-d376a8bf-118f-49b3-b96e-0e59552b9d2b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2499828669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2499828669
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3121095650
Short name T941
Test name
Test status
Simulation time 54922592 ps
CPU time 1.1 seconds
Started Jun 21 07:01:46 PM PDT 24
Finished Jun 21 07:01:55 PM PDT 24
Peak memory 207020 kb
Host smart-5930b121-5412-4773-b02f-b59b15c45f47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121095650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3121095650
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1459361529
Short name T322
Test name
Test status
Simulation time 17709342834 ps
CPU time 47.08 seconds
Started Jun 21 07:01:48 PM PDT 24
Finished Jun 21 07:02:43 PM PDT 24
Peak memory 216500 kb
Host smart-5e7c32bf-546e-4632-903d-acdd166292e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459361529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1459361529
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.4010889041
Short name T27
Test name
Test status
Simulation time 1381746214 ps
CPU time 4.85 seconds
Started Jun 21 07:01:52 PM PDT 24
Finished Jun 21 07:02:05 PM PDT 24
Peak memory 216428 kb
Host smart-11a75a4d-c245-4e76-8ad7-878a819d3ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010889041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.4010889041
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.4003954035
Short name T947
Test name
Test status
Simulation time 98561677 ps
CPU time 0.86 seconds
Started Jun 21 07:01:50 PM PDT 24
Finished Jun 21 07:01:59 PM PDT 24
Peak memory 207144 kb
Host smart-0bf8f57e-a2a8-4443-a288-1d2489a22f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003954035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.4003954035
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.4109280760
Short name T80
Test name
Test status
Simulation time 162505193 ps
CPU time 0.8 seconds
Started Jun 21 07:01:45 PM PDT 24
Finished Jun 21 07:01:53 PM PDT 24
Peak memory 206100 kb
Host smart-b83bbfa6-81e9-4ca4-a784-3fbc09957439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109280760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.4109280760
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3689810009
Short name T276
Test name
Test status
Simulation time 6094190783 ps
CPU time 7.79 seconds
Started Jun 21 07:01:53 PM PDT 24
Finished Jun 21 07:02:10 PM PDT 24
Peak memory 233024 kb
Host smart-951ebb3a-7746-4445-bf1b-96f35497c4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689810009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3689810009
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2073298786
Short name T501
Test name
Test status
Simulation time 18219444 ps
CPU time 0.67 seconds
Started Jun 21 07:01:52 PM PDT 24
Finished Jun 21 07:02:01 PM PDT 24
Peak memory 205520 kb
Host smart-6e535951-3346-44ae-88e1-32519baee70b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073298786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2073298786
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2601713136
Short name T552
Test name
Test status
Simulation time 327677746 ps
CPU time 2.71 seconds
Started Jun 21 07:01:53 PM PDT 24
Finished Jun 21 07:02:05 PM PDT 24
Peak memory 232868 kb
Host smart-e234c53f-e35d-4cf8-9f90-760471907210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601713136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2601713136
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2653344547
Short name T571
Test name
Test status
Simulation time 35125611 ps
CPU time 0.78 seconds
Started Jun 21 07:01:45 PM PDT 24
Finished Jun 21 07:01:54 PM PDT 24
Peak memory 206748 kb
Host smart-bd979941-9a9b-4480-962f-6889af9c8728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653344547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2653344547
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1160529123
Short name T224
Test name
Test status
Simulation time 8454644605 ps
CPU time 89.42 seconds
Started Jun 21 07:01:45 PM PDT 24
Finished Jun 21 07:03:23 PM PDT 24
Peak memory 273116 kb
Host smart-af134f06-df2c-4814-9e03-fbe963e30ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160529123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1160529123
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2937908224
Short name T233
Test name
Test status
Simulation time 5846865679 ps
CPU time 69.35 seconds
Started Jun 21 07:01:47 PM PDT 24
Finished Jun 21 07:03:05 PM PDT 24
Peak memory 250512 kb
Host smart-f2f8f225-970f-478e-b32b-a810605f4333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937908224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2937908224
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2996654824
Short name T283
Test name
Test status
Simulation time 12192529938 ps
CPU time 128.19 seconds
Started Jun 21 07:01:52 PM PDT 24
Finished Jun 21 07:04:08 PM PDT 24
Peak memory 257600 kb
Host smart-b17b8103-9df4-459e-a003-34baea3bae1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996654824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2996654824
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1859731652
Short name T824
Test name
Test status
Simulation time 164000717 ps
CPU time 7.95 seconds
Started Jun 21 07:01:48 PM PDT 24
Finished Jun 21 07:02:04 PM PDT 24
Peak memory 232876 kb
Host smart-5bff2eec-97fe-4a1d-80e3-04d07932d7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859731652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1859731652
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2424838965
Short name T65
Test name
Test status
Simulation time 617990728 ps
CPU time 7.35 seconds
Started Jun 21 07:01:46 PM PDT 24
Finished Jun 21 07:02:02 PM PDT 24
Peak memory 224536 kb
Host smart-2eb9c916-0bcd-41cc-a9ff-fa50f43ed8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424838965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2424838965
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1954336864
Short name T465
Test name
Test status
Simulation time 44854320517 ps
CPU time 84.79 seconds
Started Jun 21 07:01:45 PM PDT 24
Finished Jun 21 07:03:18 PM PDT 24
Peak memory 232964 kb
Host smart-5d1c3570-dfd2-431e-b757-6393c4e90f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954336864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1954336864
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1066300008
Short name T920
Test name
Test status
Simulation time 877952771 ps
CPU time 2.93 seconds
Started Jun 21 07:01:47 PM PDT 24
Finished Jun 21 07:01:59 PM PDT 24
Peak memory 232680 kb
Host smart-e22c3370-ae27-447e-8679-a5dd1f3663f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066300008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1066300008
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2498993599
Short name T200
Test name
Test status
Simulation time 8415570862 ps
CPU time 18.34 seconds
Started Jun 21 07:01:45 PM PDT 24
Finished Jun 21 07:02:12 PM PDT 24
Peak memory 232992 kb
Host smart-5dddd0d5-948e-4dc1-843a-88df0a853bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498993599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2498993599
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1748608368
Short name T857
Test name
Test status
Simulation time 1386056918 ps
CPU time 8.59 seconds
Started Jun 21 07:01:46 PM PDT 24
Finished Jun 21 07:02:03 PM PDT 24
Peak memory 222764 kb
Host smart-43173207-a43e-41b2-b972-d4e71dd1aca0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1748608368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1748608368
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.4035153223
Short name T497
Test name
Test status
Simulation time 202181860 ps
CPU time 2.96 seconds
Started Jun 21 07:01:47 PM PDT 24
Finished Jun 21 07:01:59 PM PDT 24
Peak memory 216480 kb
Host smart-ac0322f3-5913-4995-b60d-c9c46f320620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035153223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.4035153223
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.304466179
Short name T68
Test name
Test status
Simulation time 714048936 ps
CPU time 3.87 seconds
Started Jun 21 07:01:47 PM PDT 24
Finished Jun 21 07:02:00 PM PDT 24
Peak memory 216444 kb
Host smart-c31107cc-e5e0-4c7a-b964-f3d88ad9aaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304466179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.304466179
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3851108332
Short name T615
Test name
Test status
Simulation time 93155991 ps
CPU time 1.01 seconds
Started Jun 21 07:01:47 PM PDT 24
Finished Jun 21 07:01:56 PM PDT 24
Peak memory 207144 kb
Host smart-5689610a-6b08-4d55-90a5-b41bf301530f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851108332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3851108332
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1389428131
Short name T685
Test name
Test status
Simulation time 337633512 ps
CPU time 0.82 seconds
Started Jun 21 07:01:53 PM PDT 24
Finished Jun 21 07:02:02 PM PDT 24
Peak memory 206096 kb
Host smart-9e70c911-81dc-4da3-bd76-d0a45346e09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389428131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1389428131
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.196269649
Short name T272
Test name
Test status
Simulation time 1869103766 ps
CPU time 5.59 seconds
Started Jun 21 07:01:47 PM PDT 24
Finished Jun 21 07:02:01 PM PDT 24
Peak memory 224632 kb
Host smart-92b66c01-0715-449f-a93b-60a61c3394f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196269649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.196269649
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1879130661
Short name T9
Test name
Test status
Simulation time 32552155 ps
CPU time 0.69 seconds
Started Jun 21 07:01:55 PM PDT 24
Finished Jun 21 07:02:04 PM PDT 24
Peak memory 205492 kb
Host smart-cef18969-1870-4cf2-b862-e423777a0757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879130661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1879130661
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.618456534
Short name T513
Test name
Test status
Simulation time 735840301 ps
CPU time 7.85 seconds
Started Jun 21 07:01:53 PM PDT 24
Finished Jun 21 07:02:10 PM PDT 24
Peak memory 224616 kb
Host smart-546e0983-b6c3-4184-b13b-7cf50f2dc491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618456534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.618456534
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3326170218
Short name T369
Test name
Test status
Simulation time 27022469 ps
CPU time 0.75 seconds
Started Jun 21 07:01:55 PM PDT 24
Finished Jun 21 07:02:04 PM PDT 24
Peak memory 205736 kb
Host smart-0f039d88-9f3f-43b5-b1ef-63ef24b9399d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326170218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3326170218
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1164307968
Short name T1
Test name
Test status
Simulation time 46964850 ps
CPU time 1 seconds
Started Jun 21 07:01:53 PM PDT 24
Finished Jun 21 07:02:02 PM PDT 24
Peak memory 216136 kb
Host smart-db4209d4-d41e-4d25-9aad-6f44a79d4471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164307968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1164307968
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2658228959
Short name T33
Test name
Test status
Simulation time 356257112359 ps
CPU time 829.83 seconds
Started Jun 21 07:01:55 PM PDT 24
Finished Jun 21 07:15:53 PM PDT 24
Peak memory 273704 kb
Host smart-9623a6fa-c62c-48e4-8043-0031a4dcb42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658228959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2658228959
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2848158616
Short name T267
Test name
Test status
Simulation time 9846016216 ps
CPU time 24.07 seconds
Started Jun 21 07:01:53 PM PDT 24
Finished Jun 21 07:02:26 PM PDT 24
Peak memory 241228 kb
Host smart-07768c8d-1909-44ae-b12c-006c941b7e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848158616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2848158616
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1362905996
Short name T312
Test name
Test status
Simulation time 13486105791 ps
CPU time 33.99 seconds
Started Jun 21 07:01:53 PM PDT 24
Finished Jun 21 07:02:36 PM PDT 24
Peak memory 234420 kb
Host smart-70203e70-d55d-4e1c-af5a-19922df07976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362905996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1362905996
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.4282163159
Short name T898
Test name
Test status
Simulation time 480018161 ps
CPU time 7.62 seconds
Started Jun 21 07:01:54 PM PDT 24
Finished Jun 21 07:02:10 PM PDT 24
Peak memory 232876 kb
Host smart-7430c454-d8b2-4e31-8a40-70da681462cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282163159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.4282163159
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2745846365
Short name T294
Test name
Test status
Simulation time 759154547 ps
CPU time 4.16 seconds
Started Jun 21 07:01:54 PM PDT 24
Finished Jun 21 07:02:07 PM PDT 24
Peak memory 232872 kb
Host smart-33ec9a75-ef24-49a0-b01e-8e46109f3495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745846365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2745846365
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1506216627
Short name T809
Test name
Test status
Simulation time 9591770498 ps
CPU time 8.44 seconds
Started Jun 21 07:01:53 PM PDT 24
Finished Jun 21 07:02:10 PM PDT 24
Peak memory 224740 kb
Host smart-042c4d8b-23ab-4c4b-8284-a93f54fa321d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506216627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1506216627
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1840291210
Short name T304
Test name
Test status
Simulation time 1989975634 ps
CPU time 8.38 seconds
Started Jun 21 07:01:55 PM PDT 24
Finished Jun 21 07:02:11 PM PDT 24
Peak memory 232856 kb
Host smart-ceab521a-26d4-4783-a6a8-2891ba7a8904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840291210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1840291210
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3605750675
Short name T404
Test name
Test status
Simulation time 923676162 ps
CPU time 5.56 seconds
Started Jun 21 07:01:54 PM PDT 24
Finished Jun 21 07:02:08 PM PDT 24
Peak memory 222532 kb
Host smart-21bcfd43-3619-4d76-b558-70e3cd419db0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3605750675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3605750675
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1213336672
Short name T124
Test name
Test status
Simulation time 32357249640 ps
CPU time 305.41 seconds
Started Jun 21 07:01:54 PM PDT 24
Finished Jun 21 07:07:08 PM PDT 24
Peak memory 251520 kb
Host smart-f54bd1c4-4c52-4bab-b9b4-dd82c01fd202
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213336672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1213336672
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3214485974
Short name T692
Test name
Test status
Simulation time 9753482205 ps
CPU time 42.62 seconds
Started Jun 21 07:01:58 PM PDT 24
Finished Jun 21 07:02:47 PM PDT 24
Peak memory 216488 kb
Host smart-8ac1762d-6558-419a-8151-048ab0ca1383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214485974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3214485974
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2453728261
Short name T26
Test name
Test status
Simulation time 1758844096 ps
CPU time 7.52 seconds
Started Jun 21 07:01:53 PM PDT 24
Finished Jun 21 07:02:10 PM PDT 24
Peak memory 216440 kb
Host smart-6dadbbb9-ae8d-46e8-a236-3f2b8cf9a721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453728261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2453728261
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1951429863
Short name T520
Test name
Test status
Simulation time 193694398 ps
CPU time 3.19 seconds
Started Jun 21 07:01:53 PM PDT 24
Finished Jun 21 07:02:05 PM PDT 24
Peak memory 216408 kb
Host smart-2a35b705-f377-4fa9-87c3-62f0884205ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951429863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1951429863
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2848198132
Short name T566
Test name
Test status
Simulation time 554823276 ps
CPU time 0.95 seconds
Started Jun 21 07:01:54 PM PDT 24
Finished Jun 21 07:02:04 PM PDT 24
Peak memory 206100 kb
Host smart-928a250f-6075-4623-8e39-b1368b8f008b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848198132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2848198132
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3900239611
Short name T201
Test name
Test status
Simulation time 1368216401 ps
CPU time 5.59 seconds
Started Jun 21 07:01:54 PM PDT 24
Finished Jun 21 07:02:08 PM PDT 24
Peak memory 232840 kb
Host smart-333afecc-1f7d-42f7-90b2-78d8c9c49af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900239611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3900239611
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2480379785
Short name T738
Test name
Test status
Simulation time 14023970 ps
CPU time 0.74 seconds
Started Jun 21 07:02:02 PM PDT 24
Finished Jun 21 07:02:07 PM PDT 24
Peak memory 204940 kb
Host smart-42afe315-da54-4c70-bd98-77d6347ce270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480379785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2480379785
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.173174934
Short name T845
Test name
Test status
Simulation time 3490622452 ps
CPU time 7.71 seconds
Started Jun 21 07:01:54 PM PDT 24
Finished Jun 21 07:02:10 PM PDT 24
Peak memory 232976 kb
Host smart-615d19db-35b3-4891-b3de-cfd9518f9e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173174934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.173174934
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2937433116
Short name T348
Test name
Test status
Simulation time 18620895 ps
CPU time 0.79 seconds
Started Jun 21 07:01:53 PM PDT 24
Finished Jun 21 07:02:03 PM PDT 24
Peak memory 207072 kb
Host smart-f38af06e-7475-4178-8d54-9d1188b5442f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937433116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2937433116
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2107162540
Short name T723
Test name
Test status
Simulation time 34590881675 ps
CPU time 149.34 seconds
Started Jun 21 07:01:54 PM PDT 24
Finished Jun 21 07:04:32 PM PDT 24
Peak memory 256476 kb
Host smart-f219fa86-ab18-4829-b98b-ea3664fb67a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107162540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2107162540
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1622467207
Short name T178
Test name
Test status
Simulation time 2370297764 ps
CPU time 43.7 seconds
Started Jun 21 07:01:54 PM PDT 24
Finished Jun 21 07:02:46 PM PDT 24
Peak memory 253800 kb
Host smart-3ad64ea4-e535-4ff3-9d6f-b907f8ec9dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622467207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1622467207
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.764672601
Short name T263
Test name
Test status
Simulation time 20219086033 ps
CPU time 220.12 seconds
Started Jun 21 07:02:01 PM PDT 24
Finished Jun 21 07:05:46 PM PDT 24
Peak memory 254584 kb
Host smart-d1d6e162-e130-4410-a855-104864480fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764672601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.764672601
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1812926899
Short name T314
Test name
Test status
Simulation time 1246495932 ps
CPU time 13.53 seconds
Started Jun 21 07:01:53 PM PDT 24
Finished Jun 21 07:02:15 PM PDT 24
Peak memory 224680 kb
Host smart-17a503a2-09b8-4eb1-830c-85409b87d75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812926899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1812926899
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3710959318
Short name T585
Test name
Test status
Simulation time 160437107 ps
CPU time 2.49 seconds
Started Jun 21 07:01:53 PM PDT 24
Finished Jun 21 07:02:05 PM PDT 24
Peak memory 224408 kb
Host smart-d4fbe0f0-46c5-4f7a-96d4-dbbf1f9024ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710959318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3710959318
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.4188327350
Short name T310
Test name
Test status
Simulation time 1522601966 ps
CPU time 19.68 seconds
Started Jun 21 07:01:54 PM PDT 24
Finished Jun 21 07:02:22 PM PDT 24
Peak memory 224628 kb
Host smart-ccea82ee-a69d-4b4a-bbf4-732245ad496b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188327350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.4188327350
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.4229992043
Short name T41
Test name
Test status
Simulation time 782698170 ps
CPU time 6.92 seconds
Started Jun 21 07:01:54 PM PDT 24
Finished Jun 21 07:02:09 PM PDT 24
Peak memory 232840 kb
Host smart-85904a51-1866-40db-a788-ca4310b4e4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229992043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.4229992043
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.344986873
Short name T869
Test name
Test status
Simulation time 288726690 ps
CPU time 4.66 seconds
Started Jun 21 07:01:53 PM PDT 24
Finished Jun 21 07:02:06 PM PDT 24
Peak memory 232868 kb
Host smart-3ec422bf-704f-46d0-971d-32a9167ebc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344986873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.344986873
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.202451853
Short name T400
Test name
Test status
Simulation time 4189156286 ps
CPU time 11.92 seconds
Started Jun 21 07:01:55 PM PDT 24
Finished Jun 21 07:02:15 PM PDT 24
Peak memory 220424 kb
Host smart-7b9a00ba-048f-456f-918a-519a1f46adbb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=202451853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.202451853
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1124074336
Short name T496
Test name
Test status
Simulation time 162602955 ps
CPU time 1.02 seconds
Started Jun 21 07:02:12 PM PDT 24
Finished Jun 21 07:02:17 PM PDT 24
Peak memory 206896 kb
Host smart-218414bc-f40e-42a3-a557-8ca5b9ff3538
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124074336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1124074336
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2439409158
Short name T324
Test name
Test status
Simulation time 2144033969 ps
CPU time 9.34 seconds
Started Jun 21 07:01:52 PM PDT 24
Finished Jun 21 07:02:10 PM PDT 24
Peak memory 216380 kb
Host smart-afafb64f-701c-4955-bb6b-a924f91a02c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439409158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2439409158
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1997848720
Short name T583
Test name
Test status
Simulation time 506715606 ps
CPU time 2.79 seconds
Started Jun 21 07:01:54 PM PDT 24
Finished Jun 21 07:02:06 PM PDT 24
Peak memory 216432 kb
Host smart-898e2522-0d91-4433-a7fe-436f0e83f3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997848720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1997848720
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1989591982
Short name T10
Test name
Test status
Simulation time 47555791 ps
CPU time 0.78 seconds
Started Jun 21 07:01:57 PM PDT 24
Finished Jun 21 07:02:05 PM PDT 24
Peak memory 206116 kb
Host smart-7b30e9ef-d038-4f87-b63f-a3ad71b8ac9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989591982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1989591982
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.95217795
Short name T781
Test name
Test status
Simulation time 1440390652 ps
CPU time 0.92 seconds
Started Jun 21 07:01:54 PM PDT 24
Finished Jun 21 07:02:03 PM PDT 24
Peak memory 206036 kb
Host smart-152d2785-6ebd-4056-b3c4-d2244c57fd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95217795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.95217795
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.734765603
Short name T846
Test name
Test status
Simulation time 11011852346 ps
CPU time 6.01 seconds
Started Jun 21 07:01:57 PM PDT 24
Finished Jun 21 07:02:10 PM PDT 24
Peak memory 224792 kb
Host smart-11d8a584-5465-42b2-b80b-b1325a0b12b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734765603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.734765603
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2362846194
Short name T500
Test name
Test status
Simulation time 40846068 ps
CPU time 0.66 seconds
Started Jun 21 07:02:08 PM PDT 24
Finished Jun 21 07:02:12 PM PDT 24
Peak memory 205512 kb
Host smart-d1270004-0a8f-4563-969e-5497627f54b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362846194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2362846194
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3953610900
Short name T852
Test name
Test status
Simulation time 1091936247 ps
CPU time 3.3 seconds
Started Jun 21 07:02:21 PM PDT 24
Finished Jun 21 07:02:28 PM PDT 24
Peak memory 224628 kb
Host smart-657e8564-600b-4f0a-8974-aa85984a225b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953610900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3953610900
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3817826820
Short name T335
Test name
Test status
Simulation time 22002631 ps
CPU time 0.76 seconds
Started Jun 21 07:02:12 PM PDT 24
Finished Jun 21 07:02:17 PM PDT 24
Peak memory 206752 kb
Host smart-8da06e4a-13bf-4c17-a762-ceed21f67462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817826820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3817826820
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1587260913
Short name T74
Test name
Test status
Simulation time 6163299675 ps
CPU time 62.1 seconds
Started Jun 21 07:02:05 PM PDT 24
Finished Jun 21 07:03:10 PM PDT 24
Peak memory 256504 kb
Host smart-36ef9969-5241-41a2-a56b-59f15bd1ce75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587260913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1587260913
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1581952444
Short name T839
Test name
Test status
Simulation time 1566279416 ps
CPU time 11.19 seconds
Started Jun 21 07:02:02 PM PDT 24
Finished Jun 21 07:02:18 PM PDT 24
Peak memory 224808 kb
Host smart-718bdab4-fbf6-48f6-a951-831421bf3e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581952444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1581952444
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2029459121
Short name T215
Test name
Test status
Simulation time 5111253169 ps
CPU time 107.71 seconds
Started Jun 21 07:02:10 PM PDT 24
Finished Jun 21 07:04:01 PM PDT 24
Peak memory 256656 kb
Host smart-d4c8fd32-d78b-4222-be77-10b7543aa9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029459121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2029459121
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1236819956
Short name T426
Test name
Test status
Simulation time 316489125 ps
CPU time 6.01 seconds
Started Jun 21 07:02:02 PM PDT 24
Finished Jun 21 07:02:13 PM PDT 24
Peak memory 224672 kb
Host smart-a9e67b91-db45-4ab0-ac31-b5937613e822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236819956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1236819956
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1387288803
Short name T402
Test name
Test status
Simulation time 237942189 ps
CPU time 2.91 seconds
Started Jun 21 07:02:10 PM PDT 24
Finished Jun 21 07:02:17 PM PDT 24
Peak memory 232904 kb
Host smart-f655995a-1733-4416-8617-c317850bad2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387288803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1387288803
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3508552876
Short name T934
Test name
Test status
Simulation time 358787445 ps
CPU time 7.24 seconds
Started Jun 21 07:02:03 PM PDT 24
Finished Jun 21 07:02:14 PM PDT 24
Peak memory 232892 kb
Host smart-03760282-c8b5-4c33-8c34-357aeb621cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508552876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3508552876
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.49035692
Short name T750
Test name
Test status
Simulation time 12351615041 ps
CPU time 8.53 seconds
Started Jun 21 07:02:11 PM PDT 24
Finished Jun 21 07:02:24 PM PDT 24
Peak memory 240600 kb
Host smart-2221bacb-cddd-4c9e-8658-2c69a39f05b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49035692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.49035692
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3125250216
Short name T688
Test name
Test status
Simulation time 3589242824 ps
CPU time 5.09 seconds
Started Jun 21 07:02:10 PM PDT 24
Finished Jun 21 07:02:20 PM PDT 24
Peak memory 232952 kb
Host smart-fa65e4e0-2b91-45f9-87ca-bba37ed06384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125250216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3125250216
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.4055323513
Short name T698
Test name
Test status
Simulation time 256161588 ps
CPU time 3.41 seconds
Started Jun 21 07:02:03 PM PDT 24
Finished Jun 21 07:02:11 PM PDT 24
Peak memory 222808 kb
Host smart-204948db-087a-4e00-be2d-2326135c74bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4055323513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.4055323513
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2307458875
Short name T469
Test name
Test status
Simulation time 14880717068 ps
CPU time 38.59 seconds
Started Jun 21 07:02:11 PM PDT 24
Finished Jun 21 07:02:54 PM PDT 24
Peak memory 216556 kb
Host smart-ee90b206-2e5c-4a3f-9ebf-8405611fc14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307458875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2307458875
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2921225445
Short name T638
Test name
Test status
Simulation time 1290418288 ps
CPU time 5.22 seconds
Started Jun 21 07:02:10 PM PDT 24
Finished Jun 21 07:02:19 PM PDT 24
Peak memory 216388 kb
Host smart-d6e6f069-9b79-4b6b-a3f3-517883d7cb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921225445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2921225445
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1813551677
Short name T721
Test name
Test status
Simulation time 247135817 ps
CPU time 0.83 seconds
Started Jun 21 07:02:11 PM PDT 24
Finished Jun 21 07:02:16 PM PDT 24
Peak memory 207004 kb
Host smart-6b5b4bc8-0fcc-4d28-b27c-98986c2c7e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813551677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1813551677
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.243869943
Short name T912
Test name
Test status
Simulation time 20799735 ps
CPU time 0.73 seconds
Started Jun 21 07:02:05 PM PDT 24
Finished Jun 21 07:02:08 PM PDT 24
Peak memory 206088 kb
Host smart-2a81728c-c52f-463d-b283-37e68f283718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243869943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.243869943
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2866089613
Short name T483
Test name
Test status
Simulation time 8528407066 ps
CPU time 10.27 seconds
Started Jun 21 07:02:09 PM PDT 24
Finished Jun 21 07:02:23 PM PDT 24
Peak memory 224780 kb
Host smart-9f9c4921-4312-4e44-a321-c0296a806d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866089613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2866089613
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2065410910
Short name T718
Test name
Test status
Simulation time 128939602 ps
CPU time 0.74 seconds
Started Jun 21 07:02:11 PM PDT 24
Finished Jun 21 07:02:16 PM PDT 24
Peak memory 204936 kb
Host smart-df39ef1e-c7ec-4ee2-9147-96f41f068625
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065410910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2065410910
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.202055091
Short name T538
Test name
Test status
Simulation time 1489530968 ps
CPU time 6.56 seconds
Started Jun 21 07:02:05 PM PDT 24
Finished Jun 21 07:02:15 PM PDT 24
Peak memory 224688 kb
Host smart-0505a52b-7cd2-42d1-be0b-e60362a33803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202055091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.202055091
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1583673436
Short name T601
Test name
Test status
Simulation time 17563708 ps
CPU time 0.76 seconds
Started Jun 21 07:02:08 PM PDT 24
Finished Jun 21 07:02:11 PM PDT 24
Peak memory 206716 kb
Host smart-e2b4a629-dd3e-4a2c-841b-1c0ac56a8b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583673436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1583673436
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3152322271
Short name T747
Test name
Test status
Simulation time 21545297565 ps
CPU time 152.79 seconds
Started Jun 21 07:02:09 PM PDT 24
Finished Jun 21 07:04:46 PM PDT 24
Peak memory 253520 kb
Host smart-933b77b4-f768-45d5-a615-ff82d0d868dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152322271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3152322271
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.877451995
Short name T114
Test name
Test status
Simulation time 227843954 ps
CPU time 8.52 seconds
Started Jun 21 07:02:05 PM PDT 24
Finished Jun 21 07:02:16 PM PDT 24
Peak memory 238464 kb
Host smart-4f2bf175-5ce7-4435-86b3-17556269c964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877451995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.877451995
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2248882180
Short name T11
Test name
Test status
Simulation time 612121578 ps
CPU time 7.69 seconds
Started Jun 21 07:02:12 PM PDT 24
Finished Jun 21 07:02:24 PM PDT 24
Peak memory 224632 kb
Host smart-39f4ccf6-8af1-4db3-aa03-7a2815951b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248882180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2248882180
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3332070851
Short name T910
Test name
Test status
Simulation time 73452166899 ps
CPU time 37.74 seconds
Started Jun 21 07:02:07 PM PDT 24
Finished Jun 21 07:02:48 PM PDT 24
Peak memory 233000 kb
Host smart-7c848d8a-2e57-4037-b827-5e476c4c5730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332070851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3332070851
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3864975143
Short name T193
Test name
Test status
Simulation time 180195673 ps
CPU time 2.49 seconds
Started Jun 21 07:02:04 PM PDT 24
Finished Jun 21 07:02:10 PM PDT 24
Peak memory 232836 kb
Host smart-265cb0b7-8637-4348-a89f-d1f1f77ef09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864975143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3864975143
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1628088334
Short name T654
Test name
Test status
Simulation time 374980001 ps
CPU time 3.06 seconds
Started Jun 21 07:02:02 PM PDT 24
Finished Jun 21 07:02:10 PM PDT 24
Peak memory 224660 kb
Host smart-9de8c488-bf7e-4916-b5a7-81db9534f733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628088334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1628088334
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2072109886
Short name T472
Test name
Test status
Simulation time 2884156410 ps
CPU time 10.8 seconds
Started Jun 21 07:02:11 PM PDT 24
Finished Jun 21 07:02:26 PM PDT 24
Peak memory 219608 kb
Host smart-62816840-7bcc-4a2c-a7e2-6865f4c0422e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2072109886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2072109886
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.150836115
Short name T946
Test name
Test status
Simulation time 4426923684 ps
CPU time 3.62 seconds
Started Jun 21 07:02:11 PM PDT 24
Finished Jun 21 07:02:19 PM PDT 24
Peak memory 219824 kb
Host smart-85c16d1b-16bf-4a44-8567-95a4f0fdce3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150836115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.150836115
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1149415111
Short name T593
Test name
Test status
Simulation time 4155846529 ps
CPU time 8.33 seconds
Started Jun 21 07:02:08 PM PDT 24
Finished Jun 21 07:02:19 PM PDT 24
Peak memory 216524 kb
Host smart-b7d1f9c6-c2b5-424b-bd8a-8726223123da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149415111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1149415111
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3892305855
Short name T647
Test name
Test status
Simulation time 236738833 ps
CPU time 2.46 seconds
Started Jun 21 07:02:10 PM PDT 24
Finished Jun 21 07:02:17 PM PDT 24
Peak memory 216384 kb
Host smart-bf2dd0cb-1068-4aa2-9bad-64fe579228c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892305855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3892305855
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.180448598
Short name T502
Test name
Test status
Simulation time 47444597 ps
CPU time 0.79 seconds
Started Jun 21 07:02:09 PM PDT 24
Finished Jun 21 07:02:13 PM PDT 24
Peak memory 205992 kb
Host smart-7ea11fbd-c1d9-4a9a-b39f-3807f40d6ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180448598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.180448598
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2982646925
Short name T445
Test name
Test status
Simulation time 177120961 ps
CPU time 3.75 seconds
Started Jun 21 07:02:10 PM PDT 24
Finished Jun 21 07:02:18 PM PDT 24
Peak memory 232812 kb
Host smart-4482bf8c-b8d6-41d1-8106-8495d0dff7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982646925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2982646925
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1086520168
Short name T668
Test name
Test status
Simulation time 12195489 ps
CPU time 0.71 seconds
Started Jun 21 07:02:09 PM PDT 24
Finished Jun 21 07:02:13 PM PDT 24
Peak memory 205540 kb
Host smart-3fea0a71-24aa-41d3-a10e-1181db8cbc36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086520168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1086520168
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1328152388
Short name T834
Test name
Test status
Simulation time 32306552 ps
CPU time 2.24 seconds
Started Jun 21 07:02:13 PM PDT 24
Finished Jun 21 07:02:19 PM PDT 24
Peak memory 224672 kb
Host smart-67f06976-80e2-4f80-81d4-dc6c6d596ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328152388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1328152388
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.428367251
Short name T342
Test name
Test status
Simulation time 53363370 ps
CPU time 0.74 seconds
Started Jun 21 07:02:12 PM PDT 24
Finished Jun 21 07:02:17 PM PDT 24
Peak memory 206040 kb
Host smart-610ced5d-cf73-4074-a697-a6a1673ea1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428367251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.428367251
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.185289737
Short name T147
Test name
Test status
Simulation time 5453768266 ps
CPU time 65.16 seconds
Started Jun 21 07:02:19 PM PDT 24
Finished Jun 21 07:03:27 PM PDT 24
Peak memory 252544 kb
Host smart-2696366c-6964-4f15-9274-ef8859ca7a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185289737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.185289737
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1478783132
Short name T186
Test name
Test status
Simulation time 4323784247 ps
CPU time 93.67 seconds
Started Jun 21 07:02:12 PM PDT 24
Finished Jun 21 07:03:49 PM PDT 24
Peak memory 271912 kb
Host smart-eba61a11-28f2-4569-8666-57a4749c57aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478783132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1478783132
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2019154716
Short name T937
Test name
Test status
Simulation time 30617745627 ps
CPU time 219.91 seconds
Started Jun 21 07:02:18 PM PDT 24
Finished Jun 21 07:06:02 PM PDT 24
Peak memory 256444 kb
Host smart-53ce2633-a19b-42b7-a818-342b95e9866c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019154716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2019154716
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2268789563
Short name T609
Test name
Test status
Simulation time 614103461 ps
CPU time 12.67 seconds
Started Jun 21 07:02:10 PM PDT 24
Finished Jun 21 07:02:26 PM PDT 24
Peak memory 232824 kb
Host smart-bf2b1205-ccc8-43b2-9c85-0cfe899c507f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268789563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2268789563
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1310645870
Short name T817
Test name
Test status
Simulation time 983219468 ps
CPU time 11.31 seconds
Started Jun 21 07:02:16 PM PDT 24
Finished Jun 21 07:02:32 PM PDT 24
Peak memory 224584 kb
Host smart-97e364db-1cf8-4da7-bab5-45ddfd792087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310645870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1310645870
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1240176236
Short name T459
Test name
Test status
Simulation time 566116667 ps
CPU time 12.37 seconds
Started Jun 21 07:02:10 PM PDT 24
Finished Jun 21 07:02:27 PM PDT 24
Peak memory 249072 kb
Host smart-3cd8435a-a5c4-46eb-9e9d-000a634d462e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240176236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1240176236
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2448780185
Short name T794
Test name
Test status
Simulation time 5455690954 ps
CPU time 4.43 seconds
Started Jun 21 07:02:10 PM PDT 24
Finished Jun 21 07:02:19 PM PDT 24
Peak memory 232884 kb
Host smart-bafa5f70-b7aa-4180-a979-2e862b690dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448780185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2448780185
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1834526892
Short name T453
Test name
Test status
Simulation time 258808652 ps
CPU time 4.69 seconds
Started Jun 21 07:02:18 PM PDT 24
Finished Jun 21 07:02:26 PM PDT 24
Peak memory 224612 kb
Host smart-fed1ad8f-4c37-4272-8bb7-ba2f77b5f880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834526892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1834526892
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1300214574
Short name T858
Test name
Test status
Simulation time 651180501 ps
CPU time 4.01 seconds
Started Jun 21 07:02:16 PM PDT 24
Finished Jun 21 07:02:24 PM PDT 24
Peak memory 219432 kb
Host smart-08ac6ddc-e8f4-4aa8-aecb-8c279766034d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1300214574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1300214574
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3924834251
Short name T634
Test name
Test status
Simulation time 123008833 ps
CPU time 1 seconds
Started Jun 21 07:02:12 PM PDT 24
Finished Jun 21 07:02:17 PM PDT 24
Peak memory 208012 kb
Host smart-fff3bce3-2819-4729-87ed-6008592dcd09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924834251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3924834251
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3723808115
Short name T67
Test name
Test status
Simulation time 27903284236 ps
CPU time 38.63 seconds
Started Jun 21 07:02:18 PM PDT 24
Finished Jun 21 07:03:00 PM PDT 24
Peak memory 216504 kb
Host smart-c85fdb0f-b665-4552-9bf5-5827e7d21db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723808115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3723808115
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2643422241
Short name T954
Test name
Test status
Simulation time 179656734 ps
CPU time 1.02 seconds
Started Jun 21 07:02:12 PM PDT 24
Finished Jun 21 07:02:17 PM PDT 24
Peak memory 208080 kb
Host smart-27326170-3587-430e-bc17-29dfd41effd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643422241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2643422241
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.549201147
Short name T619
Test name
Test status
Simulation time 213776653 ps
CPU time 7.42 seconds
Started Jun 21 07:02:10 PM PDT 24
Finished Jun 21 07:02:22 PM PDT 24
Peak memory 216348 kb
Host smart-d76ba87f-fcaa-45a7-a81d-0ab7f43b0a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549201147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.549201147
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.99261486
Short name T359
Test name
Test status
Simulation time 30675300 ps
CPU time 0.73 seconds
Started Jun 21 07:02:10 PM PDT 24
Finished Jun 21 07:02:15 PM PDT 24
Peak memory 206108 kb
Host smart-d0a564de-f4c6-4431-a0c1-b85fb93f04b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99261486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.99261486
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.996254007
Short name T64
Test name
Test status
Simulation time 348913263 ps
CPU time 2.58 seconds
Started Jun 21 07:02:11 PM PDT 24
Finished Jun 21 07:02:18 PM PDT 24
Peak memory 234296 kb
Host smart-f519f246-cb11-4900-ab31-5af48da7ae60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996254007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.996254007
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1267087805
Short name T789
Test name
Test status
Simulation time 35818157 ps
CPU time 0.69 seconds
Started Jun 21 07:02:21 PM PDT 24
Finished Jun 21 07:02:25 PM PDT 24
Peak memory 205876 kb
Host smart-589bf5aa-459e-41bb-b7d6-f43554086e4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267087805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1267087805
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.4051432348
Short name T933
Test name
Test status
Simulation time 15562508 ps
CPU time 0.75 seconds
Started Jun 21 07:02:11 PM PDT 24
Finished Jun 21 07:02:16 PM PDT 24
Peak memory 207056 kb
Host smart-bfa1d0c8-af9a-4210-a23d-63526b83cb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051432348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.4051432348
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2818835191
Short name T795
Test name
Test status
Simulation time 30741266510 ps
CPU time 207.59 seconds
Started Jun 21 07:02:23 PM PDT 24
Finished Jun 21 07:05:54 PM PDT 24
Peak memory 249580 kb
Host smart-4c1dd71a-f2fb-472a-a339-a4676f45cfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818835191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2818835191
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2760481421
Short name T765
Test name
Test status
Simulation time 4115418691 ps
CPU time 6.88 seconds
Started Jun 21 07:02:25 PM PDT 24
Finished Jun 21 07:02:38 PM PDT 24
Peak memory 217848 kb
Host smart-8735d05a-b9e9-466d-a8ba-0b93ee2c3a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760481421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2760481421
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2320182014
Short name T327
Test name
Test status
Simulation time 40712554581 ps
CPU time 39.66 seconds
Started Jun 21 07:02:22 PM PDT 24
Finished Jun 21 07:03:06 PM PDT 24
Peak memory 217812 kb
Host smart-e178f4f2-1a4a-4f60-8c9b-2f331b11579c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320182014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2320182014
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1923354194
Short name T551
Test name
Test status
Simulation time 829285981 ps
CPU time 7.52 seconds
Started Jun 21 07:02:10 PM PDT 24
Finished Jun 21 07:02:21 PM PDT 24
Peak memory 232816 kb
Host smart-811c87a7-1b53-4863-b489-c7a1999426f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923354194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1923354194
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1121356461
Short name T730
Test name
Test status
Simulation time 1596944938 ps
CPU time 5.3 seconds
Started Jun 21 07:02:14 PM PDT 24
Finished Jun 21 07:02:24 PM PDT 24
Peak memory 232884 kb
Host smart-d2fb069f-96c6-42cf-a68c-941a9dd21e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121356461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1121356461
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2703453254
Short name T411
Test name
Test status
Simulation time 2556452117 ps
CPU time 3.01 seconds
Started Jun 21 07:02:10 PM PDT 24
Finished Jun 21 07:02:17 PM PDT 24
Peak memory 224744 kb
Host smart-b5eb7759-85bd-4d9e-babc-9ce18b8df01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703453254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2703453254
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3169835141
Short name T663
Test name
Test status
Simulation time 240921360 ps
CPU time 2.9 seconds
Started Jun 21 07:02:11 PM PDT 24
Finished Jun 21 07:02:18 PM PDT 24
Peak memory 232876 kb
Host smart-2e084050-d587-468b-a2a5-a16f7dad42f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169835141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3169835141
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.4074601374
Short name T878
Test name
Test status
Simulation time 1747142022 ps
CPU time 4.34 seconds
Started Jun 21 07:02:11 PM PDT 24
Finished Jun 21 07:02:20 PM PDT 24
Peak memory 232888 kb
Host smart-55d0e9f1-1a2a-4f31-8246-030469f6f985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074601374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.4074601374
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3734850493
Short name T895
Test name
Test status
Simulation time 78841804 ps
CPU time 3.66 seconds
Started Jun 21 07:02:10 PM PDT 24
Finished Jun 21 07:02:18 PM PDT 24
Peak memory 219100 kb
Host smart-a8aa2888-0dd2-4cca-b402-0650ee5f2c2d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3734850493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3734850493
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3082760648
Short name T458
Test name
Test status
Simulation time 27885066864 ps
CPU time 216.53 seconds
Started Jun 21 07:02:23 PM PDT 24
Finished Jun 21 07:06:03 PM PDT 24
Peak memory 249468 kb
Host smart-02ac58b7-ba15-49cb-bbdc-3d259e0ebcb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082760648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3082760648
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1885137622
Short name T512
Test name
Test status
Simulation time 2238723428 ps
CPU time 17.41 seconds
Started Jun 21 07:02:12 PM PDT 24
Finished Jun 21 07:02:33 PM PDT 24
Peak memory 216536 kb
Host smart-7bac7d44-a7be-4868-b971-7afca773570b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885137622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1885137622
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.901455597
Short name T505
Test name
Test status
Simulation time 921734215 ps
CPU time 2.55 seconds
Started Jun 21 07:02:11 PM PDT 24
Finished Jun 21 07:02:18 PM PDT 24
Peak memory 216468 kb
Host smart-6826dc26-000d-42bd-9e00-c4a776c0c3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901455597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.901455597
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1381775415
Short name T948
Test name
Test status
Simulation time 109412742 ps
CPU time 1.96 seconds
Started Jun 21 07:02:12 PM PDT 24
Finished Jun 21 07:02:18 PM PDT 24
Peak memory 216380 kb
Host smart-b8214cae-f621-4970-9a87-1fa793b175b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381775415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1381775415
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1222941312
Short name T753
Test name
Test status
Simulation time 99945369 ps
CPU time 1.05 seconds
Started Jun 21 07:02:13 PM PDT 24
Finished Jun 21 07:02:18 PM PDT 24
Peak memory 206100 kb
Host smart-de34e24c-cb34-45b6-96dd-c2f19a7b14d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222941312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1222941312
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.684396686
Short name T576
Test name
Test status
Simulation time 477885658 ps
CPU time 3.83 seconds
Started Jun 21 07:02:14 PM PDT 24
Finished Jun 21 07:02:21 PM PDT 24
Peak memory 224692 kb
Host smart-ad5589eb-464a-4fe0-a0da-da498d638fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684396686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.684396686
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.405224492
Short name T493
Test name
Test status
Simulation time 13122156 ps
CPU time 0.72 seconds
Started Jun 21 07:02:24 PM PDT 24
Finished Jun 21 07:02:29 PM PDT 24
Peak memory 204948 kb
Host smart-e86babbf-1fee-4719-a6a8-5ab575a56fa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405224492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.405224492
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3778627223
Short name T259
Test name
Test status
Simulation time 37177031 ps
CPU time 2.63 seconds
Started Jun 21 07:02:21 PM PDT 24
Finished Jun 21 07:02:27 PM PDT 24
Peak memory 232804 kb
Host smart-cb6bba45-8743-450c-9ce9-6f3a3ec2da06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778627223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3778627223
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3843161016
Short name T744
Test name
Test status
Simulation time 19668645 ps
CPU time 0.79 seconds
Started Jun 21 07:02:22 PM PDT 24
Finished Jun 21 07:02:26 PM PDT 24
Peak memory 206720 kb
Host smart-73481b93-962b-4e92-ac30-61b02a274990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843161016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3843161016
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2111157420
Short name T226
Test name
Test status
Simulation time 8509457299 ps
CPU time 40.64 seconds
Started Jun 21 07:02:22 PM PDT 24
Finished Jun 21 07:03:07 PM PDT 24
Peak memory 251356 kb
Host smart-7d63ce82-ee91-4608-97ae-bf80029d7814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111157420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2111157420
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1844271547
Short name T810
Test name
Test status
Simulation time 950855967 ps
CPU time 5.11 seconds
Started Jun 21 07:02:22 PM PDT 24
Finished Jun 21 07:02:31 PM PDT 24
Peak memory 224656 kb
Host smart-afb31ffb-e666-431a-b7c8-1a109789e538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844271547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1844271547
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2464094208
Short name T822
Test name
Test status
Simulation time 2457223593 ps
CPU time 6.68 seconds
Started Jun 21 07:02:20 PM PDT 24
Finished Jun 21 07:02:30 PM PDT 24
Peak memory 224756 kb
Host smart-7b33b317-594e-4454-a5b6-2e7838fdf6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464094208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2464094208
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1619449742
Short name T174
Test name
Test status
Simulation time 1245721402 ps
CPU time 12.43 seconds
Started Jun 21 07:02:19 PM PDT 24
Finished Jun 21 07:02:35 PM PDT 24
Peak memory 232844 kb
Host smart-f65c0e5a-0503-413e-ad98-22ad0c658836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619449742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1619449742
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.4216073548
Short name T217
Test name
Test status
Simulation time 3038173915 ps
CPU time 8.14 seconds
Started Jun 21 07:02:19 PM PDT 24
Finished Jun 21 07:02:30 PM PDT 24
Peak memory 233940 kb
Host smart-43797178-5216-4bc1-b0b2-dcd7cf8731e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216073548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.4216073548
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3984679466
Short name T188
Test name
Test status
Simulation time 112858333409 ps
CPU time 29.6 seconds
Started Jun 21 07:02:23 PM PDT 24
Finished Jun 21 07:02:56 PM PDT 24
Peak memory 232972 kb
Host smart-5df983b5-a5f0-4d42-a5b5-fd7e3eeba2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984679466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3984679466
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1472824436
Short name T381
Test name
Test status
Simulation time 351991114 ps
CPU time 5.82 seconds
Started Jun 21 07:02:20 PM PDT 24
Finished Jun 21 07:02:29 PM PDT 24
Peak memory 220644 kb
Host smart-3e00eb19-e5d4-4702-8a8f-c27d8e9c6692
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1472824436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1472824436
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3035863160
Short name T208
Test name
Test status
Simulation time 27672705930 ps
CPU time 216.32 seconds
Started Jun 21 07:02:20 PM PDT 24
Finished Jun 21 07:06:00 PM PDT 24
Peak memory 269580 kb
Host smart-2bc456d7-05c1-4313-99ea-365aa055627b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035863160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3035863160
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2805755874
Short name T633
Test name
Test status
Simulation time 11507158332 ps
CPU time 23.98 seconds
Started Jun 21 07:02:18 PM PDT 24
Finished Jun 21 07:02:46 PM PDT 24
Peak memory 216800 kb
Host smart-5caa0fae-2feb-4c14-b642-f17a9fe77939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805755874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2805755874
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1663044971
Short name T560
Test name
Test status
Simulation time 3116609561 ps
CPU time 5.43 seconds
Started Jun 21 07:02:17 PM PDT 24
Finished Jun 21 07:02:26 PM PDT 24
Peak memory 216564 kb
Host smart-553145fe-2b24-45f1-a0f7-50feec03bb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663044971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1663044971
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2841981710
Short name T953
Test name
Test status
Simulation time 114028716 ps
CPU time 4.26 seconds
Started Jun 21 07:02:19 PM PDT 24
Finished Jun 21 07:02:27 PM PDT 24
Peak memory 216440 kb
Host smart-319deb3f-d0d5-41c6-91a4-47d3cf4bf35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841981710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2841981710
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3368940099
Short name T383
Test name
Test status
Simulation time 51879602 ps
CPU time 0.86 seconds
Started Jun 21 07:02:22 PM PDT 24
Finished Jun 21 07:02:27 PM PDT 24
Peak memory 206112 kb
Host smart-ac8156d0-1b69-4378-b696-49f7146b0eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368940099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3368940099
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2549089621
Short name T161
Test name
Test status
Simulation time 810491963 ps
CPU time 4.79 seconds
Started Jun 21 07:02:21 PM PDT 24
Finished Jun 21 07:02:29 PM PDT 24
Peak memory 224676 kb
Host smart-72fed512-63b9-4aa6-b097-6cc6e6b5e64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549089621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2549089621
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.615746210
Short name T628
Test name
Test status
Simulation time 33418825 ps
CPU time 0.74 seconds
Started Jun 21 07:02:23 PM PDT 24
Finished Jun 21 07:02:29 PM PDT 24
Peak memory 205856 kb
Host smart-42f046a0-3398-48e2-9868-987940ac7a4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615746210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.615746210
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1805458893
Short name T786
Test name
Test status
Simulation time 239883080 ps
CPU time 3.54 seconds
Started Jun 21 07:02:23 PM PDT 24
Finished Jun 21 07:02:31 PM PDT 24
Peak memory 224636 kb
Host smart-42af9711-b009-45fa-9637-1861de0d3d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805458893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1805458893
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3950834819
Short name T364
Test name
Test status
Simulation time 20122481 ps
CPU time 0.75 seconds
Started Jun 21 07:02:19 PM PDT 24
Finished Jun 21 07:02:23 PM PDT 24
Peak memory 206740 kb
Host smart-cec9a2e9-ff94-40bc-8505-5156a1eb0193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950834819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3950834819
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1711040119
Short name T35
Test name
Test status
Simulation time 53845846744 ps
CPU time 354.24 seconds
Started Jun 21 07:02:22 PM PDT 24
Finished Jun 21 07:08:20 PM PDT 24
Peak memory 253768 kb
Host smart-1034e532-458c-44ea-97e0-9c42b49058a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711040119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1711040119
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.328799308
Short name T391
Test name
Test status
Simulation time 14944111387 ps
CPU time 124.78 seconds
Started Jun 21 07:02:18 PM PDT 24
Finished Jun 21 07:04:26 PM PDT 24
Peak memory 249396 kb
Host smart-d661177c-a7be-4b74-af2c-69d954fcd4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328799308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.328799308
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1472116335
Short name T273
Test name
Test status
Simulation time 32806099936 ps
CPU time 236.97 seconds
Started Jun 21 07:02:26 PM PDT 24
Finished Jun 21 07:06:28 PM PDT 24
Peak memory 250552 kb
Host smart-12e7840b-fadd-4d5a-a836-9b0f78221f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472116335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1472116335
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3494956738
Short name T715
Test name
Test status
Simulation time 249229179 ps
CPU time 3.24 seconds
Started Jun 21 07:02:26 PM PDT 24
Finished Jun 21 07:02:34 PM PDT 24
Peak memory 224616 kb
Host smart-5386c1bf-0d93-4b86-bbb9-2997fd48c0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494956738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3494956738
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.253941638
Short name T468
Test name
Test status
Simulation time 218871865 ps
CPU time 4.15 seconds
Started Jun 21 07:02:20 PM PDT 24
Finished Jun 21 07:02:27 PM PDT 24
Peak memory 232896 kb
Host smart-fa169956-24a4-4248-8b9d-41cf81b56cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253941638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.253941638
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2278841448
Short name T626
Test name
Test status
Simulation time 6389600926 ps
CPU time 16.5 seconds
Started Jun 21 07:02:20 PM PDT 24
Finished Jun 21 07:02:40 PM PDT 24
Peak memory 224764 kb
Host smart-6df82d8f-e2c2-4297-a319-d60c3fbd9001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278841448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2278841448
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1379843108
Short name T279
Test name
Test status
Simulation time 4985253598 ps
CPU time 11.37 seconds
Started Jun 21 07:02:21 PM PDT 24
Finished Jun 21 07:02:36 PM PDT 24
Peak memory 224772 kb
Host smart-639b325c-8e7b-4a23-9239-4fa00e5c68f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379843108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1379843108
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1360577125
Short name T887
Test name
Test status
Simulation time 569730356 ps
CPU time 7.82 seconds
Started Jun 21 07:02:18 PM PDT 24
Finished Jun 21 07:02:30 PM PDT 24
Peak memory 223224 kb
Host smart-8a6b9740-2624-4b09-bc02-6cd02b5b4144
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1360577125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1360577125
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2556946553
Short name T127
Test name
Test status
Simulation time 179330823 ps
CPU time 1.04 seconds
Started Jun 21 07:02:19 PM PDT 24
Finished Jun 21 07:02:24 PM PDT 24
Peak memory 207120 kb
Host smart-4b562cc9-f467-4afb-9662-45233368321f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556946553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2556946553
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3390467391
Short name T444
Test name
Test status
Simulation time 4608067166 ps
CPU time 20.23 seconds
Started Jun 21 07:02:20 PM PDT 24
Finished Jun 21 07:02:44 PM PDT 24
Peak memory 216532 kb
Host smart-18e74420-67ec-457c-bf26-df76c9faceb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390467391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3390467391
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2883433899
Short name T559
Test name
Test status
Simulation time 5197949957 ps
CPU time 4.12 seconds
Started Jun 21 07:02:19 PM PDT 24
Finished Jun 21 07:02:27 PM PDT 24
Peak memory 216560 kb
Host smart-79625ba1-1965-4cd3-ac75-4f6502139fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883433899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2883433899
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.224393716
Short name T410
Test name
Test status
Simulation time 301684981 ps
CPU time 1.77 seconds
Started Jun 21 07:02:18 PM PDT 24
Finished Jun 21 07:02:23 PM PDT 24
Peak memory 216276 kb
Host smart-6f7a371d-7772-490a-a65f-186c4bfd44b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224393716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.224393716
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.572276287
Short name T424
Test name
Test status
Simulation time 46011370 ps
CPU time 0.85 seconds
Started Jun 21 07:02:27 PM PDT 24
Finished Jun 21 07:02:32 PM PDT 24
Peak memory 206084 kb
Host smart-66f85fee-1117-4e40-91c6-4323a07216df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572276287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.572276287
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1053272657
Short name T278
Test name
Test status
Simulation time 603654301 ps
CPU time 6.71 seconds
Started Jun 21 07:02:19 PM PDT 24
Finished Jun 21 07:02:29 PM PDT 24
Peak memory 232884 kb
Host smart-845a31bb-8bb0-4b66-ad8b-0581f1db17fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053272657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1053272657
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.921943703
Short name T429
Test name
Test status
Simulation time 21385281 ps
CPU time 0.72 seconds
Started Jun 21 06:59:59 PM PDT 24
Finished Jun 21 07:00:03 PM PDT 24
Peak memory 205496 kb
Host smart-757d38f6-0b4a-4dc4-ba14-5b37d8f2e748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921943703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.921943703
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.4247613861
Short name T386
Test name
Test status
Simulation time 3197615685 ps
CPU time 23.28 seconds
Started Jun 21 06:59:57 PM PDT 24
Finished Jun 21 07:00:23 PM PDT 24
Peak memory 224848 kb
Host smart-aa5d823e-9dfc-447e-ad0f-8cf5c4bac4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247613861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.4247613861
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3597246141
Short name T352
Test name
Test status
Simulation time 23659470 ps
CPU time 0.81 seconds
Started Jun 21 06:59:52 PM PDT 24
Finished Jun 21 06:59:56 PM PDT 24
Peak memory 206724 kb
Host smart-387c061f-0255-4a76-a18a-a397855e9286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597246141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3597246141
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1980080782
Short name T270
Test name
Test status
Simulation time 10381622533 ps
CPU time 45.71 seconds
Started Jun 21 06:59:51 PM PDT 24
Finished Jun 21 07:00:40 PM PDT 24
Peak memory 249472 kb
Host smart-1d9c75b4-1ccf-4f55-af01-1804116df93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980080782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1980080782
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1191262285
Short name T399
Test name
Test status
Simulation time 9792449771 ps
CPU time 77.98 seconds
Started Jun 21 06:59:51 PM PDT 24
Finished Jun 21 07:01:12 PM PDT 24
Peak memory 249524 kb
Host smart-92da2988-00b2-4b50-85d7-eeb2ba562cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191262285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1191262285
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2210968147
Short name T650
Test name
Test status
Simulation time 14030318001 ps
CPU time 146.88 seconds
Started Jun 21 06:59:57 PM PDT 24
Finished Jun 21 07:02:27 PM PDT 24
Peak memory 249736 kb
Host smart-6e199063-f082-4645-a581-67e7c9be6d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210968147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2210968147
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.968371563
Short name T317
Test name
Test status
Simulation time 3156831562 ps
CPU time 23.22 seconds
Started Jun 21 06:59:52 PM PDT 24
Finished Jun 21 07:00:18 PM PDT 24
Peak memory 233012 kb
Host smart-11b10351-a374-4e31-82ee-7b1c7caac020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968371563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.968371563
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.4092229637
Short name T305
Test name
Test status
Simulation time 168424266 ps
CPU time 3.64 seconds
Started Jun 21 06:59:52 PM PDT 24
Finished Jun 21 06:59:59 PM PDT 24
Peak memory 232848 kb
Host smart-910ca1ea-875b-4d7e-978c-0d96ea5e2548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092229637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4092229637
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3306102474
Short name T705
Test name
Test status
Simulation time 478014637 ps
CPU time 5.14 seconds
Started Jun 21 06:59:54 PM PDT 24
Finished Jun 21 07:00:02 PM PDT 24
Peak memory 232884 kb
Host smart-fa59007f-32ea-4db9-b5b4-6e94ee934aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306102474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3306102474
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1961031109
Short name T849
Test name
Test status
Simulation time 1928329925 ps
CPU time 4.93 seconds
Started Jun 21 06:59:52 PM PDT 24
Finished Jun 21 07:00:00 PM PDT 24
Peak memory 224540 kb
Host smart-f46ce717-15ce-4b4a-8b7e-feb82e32fef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961031109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1961031109
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3690096805
Short name T799
Test name
Test status
Simulation time 428489707 ps
CPU time 3.62 seconds
Started Jun 21 06:59:52 PM PDT 24
Finished Jun 21 06:59:58 PM PDT 24
Peak memory 224660 kb
Host smart-70f738ba-fad9-4031-b5d2-eff5c62cccd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690096805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3690096805
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3521988041
Short name T546
Test name
Test status
Simulation time 1096396511 ps
CPU time 3.74 seconds
Started Jun 21 07:00:02 PM PDT 24
Finished Jun 21 07:00:10 PM PDT 24
Peak memory 219596 kb
Host smart-8db088b4-f88e-45d1-9576-6cf407a0166f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3521988041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3521988041
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.4150277459
Short name T389
Test name
Test status
Simulation time 12427619906 ps
CPU time 42.52 seconds
Started Jun 21 06:59:57 PM PDT 24
Finished Jun 21 07:00:43 PM PDT 24
Peak memory 241300 kb
Host smart-f7146207-9f39-4a24-aad8-1683f9a88834
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150277459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.4150277459
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2189162852
Short name T523
Test name
Test status
Simulation time 32429029226 ps
CPU time 42.14 seconds
Started Jun 21 06:59:52 PM PDT 24
Finished Jun 21 07:00:37 PM PDT 24
Peak memory 216444 kb
Host smart-b99e1966-646f-4713-8f8e-ca2dc36f5fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189162852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2189162852
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3894042745
Short name T694
Test name
Test status
Simulation time 17343722 ps
CPU time 0.73 seconds
Started Jun 21 06:59:52 PM PDT 24
Finished Jun 21 06:59:56 PM PDT 24
Peak memory 205724 kb
Host smart-ef8f6dbc-095a-4244-93c4-c3cf8be7388e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894042745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3894042745
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2163137783
Short name T340
Test name
Test status
Simulation time 36587331 ps
CPU time 0.75 seconds
Started Jun 21 07:00:02 PM PDT 24
Finished Jun 21 07:00:07 PM PDT 24
Peak memory 206120 kb
Host smart-7056ab2e-a5da-41ce-81c5-420fcebb3aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163137783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2163137783
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3315603654
Short name T658
Test name
Test status
Simulation time 52274402 ps
CPU time 0.76 seconds
Started Jun 21 06:59:51 PM PDT 24
Finished Jun 21 06:59:55 PM PDT 24
Peak memory 206100 kb
Host smart-06fa2e46-a409-4727-9c7f-a58456356dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315603654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3315603654
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3687509954
Short name T366
Test name
Test status
Simulation time 39841895 ps
CPU time 2.51 seconds
Started Jun 21 06:59:58 PM PDT 24
Finished Jun 21 07:00:03 PM PDT 24
Peak memory 232544 kb
Host smart-68b38aec-0cd2-492e-89ef-a786124ea653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687509954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3687509954
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2829989474
Short name T597
Test name
Test status
Simulation time 149733686 ps
CPU time 0.74 seconds
Started Jun 21 07:00:06 PM PDT 24
Finished Jun 21 07:00:11 PM PDT 24
Peak memory 205532 kb
Host smart-438371f8-a21a-42a3-8734-a2991398cf13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829989474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
829989474
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.4096068472
Short name T659
Test name
Test status
Simulation time 298584970 ps
CPU time 6.31 seconds
Started Jun 21 07:00:00 PM PDT 24
Finished Jun 21 07:00:10 PM PDT 24
Peak memory 224692 kb
Host smart-83e931d9-4664-4274-9c12-97e879acc283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096068472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.4096068472
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.325004160
Short name T661
Test name
Test status
Simulation time 14813511 ps
CPU time 0.76 seconds
Started Jun 21 06:59:59 PM PDT 24
Finished Jun 21 07:00:03 PM PDT 24
Peak memory 205728 kb
Host smart-2d169320-1da8-4e07-bea9-32c48db1e3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325004160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.325004160
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.303885493
Short name T828
Test name
Test status
Simulation time 22905421003 ps
CPU time 89.83 seconds
Started Jun 21 07:00:01 PM PDT 24
Finished Jun 21 07:01:34 PM PDT 24
Peak memory 251580 kb
Host smart-6967d61c-544a-4e53-b3c7-5ccd064e073d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303885493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.303885493
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.4141285529
Short name T239
Test name
Test status
Simulation time 8821928655 ps
CPU time 101.86 seconds
Started Jun 21 06:59:58 PM PDT 24
Finished Jun 21 07:01:43 PM PDT 24
Peak memory 256712 kb
Host smart-338b6a69-52b5-41fa-a615-221d1c55afef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141285529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.4141285529
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3281910526
Short name T874
Test name
Test status
Simulation time 271680836 ps
CPU time 6.36 seconds
Started Jun 21 07:00:04 PM PDT 24
Finished Jun 21 07:00:14 PM PDT 24
Peak memory 224684 kb
Host smart-83ba4d79-e340-4b54-9852-3b8f0b7b9b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281910526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3281910526
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3186786339
Short name T843
Test name
Test status
Simulation time 1608399254 ps
CPU time 11.17 seconds
Started Jun 21 07:00:05 PM PDT 24
Finished Jun 21 07:00:21 PM PDT 24
Peak memory 228332 kb
Host smart-82726819-7841-4a38-b723-c0150e6733fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186786339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3186786339
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2425444658
Short name T510
Test name
Test status
Simulation time 58797826282 ps
CPU time 134.25 seconds
Started Jun 21 07:00:02 PM PDT 24
Finished Jun 21 07:02:20 PM PDT 24
Peak memory 252640 kb
Host smart-1455adfc-069d-47dd-aebe-87d95129f0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425444658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2425444658
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3710815582
Short name T788
Test name
Test status
Simulation time 980357752 ps
CPU time 5.04 seconds
Started Jun 21 07:00:05 PM PDT 24
Finished Jun 21 07:00:14 PM PDT 24
Peak memory 224656 kb
Host smart-77269347-9803-47c9-9526-71fe4bfef612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710815582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3710815582
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2134575640
Short name T745
Test name
Test status
Simulation time 361428685 ps
CPU time 3.39 seconds
Started Jun 21 07:00:00 PM PDT 24
Finished Jun 21 07:00:07 PM PDT 24
Peak memory 232852 kb
Host smart-37f0e10c-40e7-4724-9983-08bebc28858a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134575640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2134575640
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1484385196
Short name T430
Test name
Test status
Simulation time 1110809364 ps
CPU time 5.14 seconds
Started Jun 21 07:00:00 PM PDT 24
Finished Jun 21 07:00:09 PM PDT 24
Peak memory 223228 kb
Host smart-5498914d-4f23-4964-a177-bbeb5dd884aa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1484385196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1484385196
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1705093004
Short name T943
Test name
Test status
Simulation time 3267519712 ps
CPU time 26.98 seconds
Started Jun 21 06:59:54 PM PDT 24
Finished Jun 21 07:00:24 PM PDT 24
Peak memory 216724 kb
Host smart-407b92e9-43d6-44d5-9770-9196d31d3871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705093004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1705093004
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3610973435
Short name T403
Test name
Test status
Simulation time 368025586 ps
CPU time 3.32 seconds
Started Jun 21 06:59:52 PM PDT 24
Finished Jun 21 06:59:59 PM PDT 24
Peak memory 216416 kb
Host smart-0b66ddb0-ebcd-489e-8095-ff2faa9c3632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610973435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3610973435
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1712938378
Short name T357
Test name
Test status
Simulation time 15667430 ps
CPU time 0.76 seconds
Started Jun 21 07:00:00 PM PDT 24
Finished Jun 21 07:00:05 PM PDT 24
Peak memory 206128 kb
Host smart-2441d14c-5eba-4710-baa4-1a8c702b5120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712938378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1712938378
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1175801468
Short name T526
Test name
Test status
Simulation time 119994480 ps
CPU time 0.78 seconds
Started Jun 21 07:00:05 PM PDT 24
Finished Jun 21 07:00:11 PM PDT 24
Peak memory 206100 kb
Host smart-6bab097c-0fbe-45ab-9313-20ed2aeb510d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175801468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1175801468
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.854081152
Short name T921
Test name
Test status
Simulation time 197311330 ps
CPU time 2.43 seconds
Started Jun 21 07:00:02 PM PDT 24
Finished Jun 21 07:00:09 PM PDT 24
Peak memory 232528 kb
Host smart-8000a35a-1886-4311-9628-c3b8eac3e59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854081152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.854081152
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1721983819
Short name T456
Test name
Test status
Simulation time 19592983 ps
CPU time 0.67 seconds
Started Jun 21 07:00:04 PM PDT 24
Finished Jun 21 07:00:09 PM PDT 24
Peak memory 205512 kb
Host smart-a370f47d-6dcf-42c5-8ce5-63b9aea2b6fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721983819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
721983819
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2510037333
Short name T157
Test name
Test status
Simulation time 33990681 ps
CPU time 2.05 seconds
Started Jun 21 07:00:03 PM PDT 24
Finished Jun 21 07:00:09 PM PDT 24
Peak memory 224628 kb
Host smart-3426ce83-9b2c-4c07-a260-4a2669486396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510037333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2510037333
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2866482309
Short name T418
Test name
Test status
Simulation time 58482833 ps
CPU time 0.79 seconds
Started Jun 21 07:00:06 PM PDT 24
Finished Jun 21 07:00:12 PM PDT 24
Peak memory 205724 kb
Host smart-49091080-4605-4679-8530-7a9d60f8b6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866482309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2866482309
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2734870311
Short name T289
Test name
Test status
Simulation time 1824996931 ps
CPU time 18 seconds
Started Jun 21 07:00:05 PM PDT 24
Finished Jun 21 07:00:27 PM PDT 24
Peak memory 233884 kb
Host smart-9db50063-be1f-48d0-8263-db8da62ba792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734870311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2734870311
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1662843224
Short name T242
Test name
Test status
Simulation time 119097706058 ps
CPU time 517.99 seconds
Started Jun 21 06:59:59 PM PDT 24
Finished Jun 21 07:08:41 PM PDT 24
Peak memory 269356 kb
Host smart-42af6068-ba15-46ee-b0b7-9da50a686450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662843224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1662843224
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2619598348
Short name T529
Test name
Test status
Simulation time 6649593140 ps
CPU time 79.98 seconds
Started Jun 21 07:00:04 PM PDT 24
Finished Jun 21 07:01:29 PM PDT 24
Peak memory 256780 kb
Host smart-38d93775-d02b-4042-aae7-7726569217e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619598348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2619598348
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.749833287
Short name T71
Test name
Test status
Simulation time 544875272 ps
CPU time 6.15 seconds
Started Jun 21 07:00:07 PM PDT 24
Finished Jun 21 07:00:19 PM PDT 24
Peak memory 224684 kb
Host smart-c629adc9-5e27-46f2-9479-024dc2a12020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749833287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.749833287
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3638135433
Short name T191
Test name
Test status
Simulation time 56447796 ps
CPU time 2.51 seconds
Started Jun 21 06:59:59 PM PDT 24
Finished Jun 21 07:00:05 PM PDT 24
Peak memory 232900 kb
Host smart-a87c3617-b2c4-437a-8738-d1efa6150491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638135433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3638135433
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3773170618
Short name T735
Test name
Test status
Simulation time 18416633536 ps
CPU time 17.26 seconds
Started Jun 21 06:59:57 PM PDT 24
Finished Jun 21 07:00:18 PM PDT 24
Peak memory 224772 kb
Host smart-ed660cfc-e522-4324-815d-c3188ee81dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773170618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3773170618
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3560910946
Short name T199
Test name
Test status
Simulation time 3586426895 ps
CPU time 3.29 seconds
Started Jun 21 07:00:04 PM PDT 24
Finished Jun 21 07:00:12 PM PDT 24
Peak memory 224764 kb
Host smart-f56e3bb0-5adb-42a0-ac35-58a48ffabea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560910946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3560910946
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1027840809
Short name T398
Test name
Test status
Simulation time 75457200 ps
CPU time 2.07 seconds
Started Jun 21 07:00:06 PM PDT 24
Finished Jun 21 07:00:13 PM PDT 24
Peak memory 223200 kb
Host smart-a934d629-03bc-464b-950e-ec132e8352af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027840809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1027840809
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.817368406
Short name T461
Test name
Test status
Simulation time 287454651 ps
CPU time 3.53 seconds
Started Jun 21 07:00:06 PM PDT 24
Finished Jun 21 07:00:15 PM PDT 24
Peak memory 220228 kb
Host smart-02d6c2e5-5702-4936-8da1-151830ab2d67
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=817368406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.817368406
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2515940267
Short name T630
Test name
Test status
Simulation time 34153159 ps
CPU time 1.01 seconds
Started Jun 21 07:00:05 PM PDT 24
Finished Jun 21 07:00:10 PM PDT 24
Peak memory 207040 kb
Host smart-822f2381-a15a-482d-a4f3-ec29973920dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515940267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2515940267
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1977837159
Short name T464
Test name
Test status
Simulation time 70059464 ps
CPU time 0.72 seconds
Started Jun 21 06:59:59 PM PDT 24
Finished Jun 21 07:00:03 PM PDT 24
Peak memory 205800 kb
Host smart-04d8fc97-f6f8-432b-845c-14df0039b637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977837159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1977837159
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1707500952
Short name T370
Test name
Test status
Simulation time 41389489 ps
CPU time 0.76 seconds
Started Jun 21 07:00:03 PM PDT 24
Finished Jun 21 07:00:08 PM PDT 24
Peak memory 205784 kb
Host smart-a19364d8-9d3c-45cf-ae9b-e5c6ae5610a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707500952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1707500952
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3988817915
Short name T676
Test name
Test status
Simulation time 36283253 ps
CPU time 1.27 seconds
Started Jun 21 07:00:04 PM PDT 24
Finished Jun 21 07:00:09 PM PDT 24
Peak memory 216420 kb
Host smart-44dab53d-5756-4e89-bca6-aaa064259bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988817915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3988817915
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.4035921303
Short name T714
Test name
Test status
Simulation time 23244423 ps
CPU time 0.78 seconds
Started Jun 21 07:00:05 PM PDT 24
Finished Jun 21 07:00:10 PM PDT 24
Peak memory 206096 kb
Host smart-d6065925-5599-4786-9433-d60fb110096c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035921303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.4035921303
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.4027085481
Short name T488
Test name
Test status
Simulation time 458063716 ps
CPU time 3.23 seconds
Started Jun 21 07:00:03 PM PDT 24
Finished Jun 21 07:00:11 PM PDT 24
Peak memory 232868 kb
Host smart-799c98d2-4961-4613-a010-b563623bce70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027085481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.4027085481
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1560440858
Short name T607
Test name
Test status
Simulation time 12663075 ps
CPU time 0.75 seconds
Started Jun 21 07:00:05 PM PDT 24
Finished Jun 21 07:00:10 PM PDT 24
Peak memory 204892 kb
Host smart-a294b232-f342-422e-9236-16ce33c5eb0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560440858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
560440858
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.608194167
Short name T707
Test name
Test status
Simulation time 449189645 ps
CPU time 3.89 seconds
Started Jun 21 07:00:06 PM PDT 24
Finished Jun 21 07:00:15 PM PDT 24
Peak memory 224688 kb
Host smart-8d217336-4e2f-428a-b554-7fa189728a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608194167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.608194167
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3955146217
Short name T484
Test name
Test status
Simulation time 14799068 ps
CPU time 0.77 seconds
Started Jun 21 07:00:04 PM PDT 24
Finished Jun 21 07:00:09 PM PDT 24
Peak memory 206036 kb
Host smart-df1256ef-b76f-418a-a5e1-9354e986f59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955146217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3955146217
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.338802249
Short name T535
Test name
Test status
Simulation time 116657128223 ps
CPU time 249.7 seconds
Started Jun 21 07:00:04 PM PDT 24
Finished Jun 21 07:04:18 PM PDT 24
Peak memory 251788 kb
Host smart-5bfbea99-931b-440a-8138-fde91614a694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338802249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.338802249
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2810875865
Short name T563
Test name
Test status
Simulation time 17433923834 ps
CPU time 164.77 seconds
Started Jun 21 07:00:04 PM PDT 24
Finished Jun 21 07:02:54 PM PDT 24
Peak memory 263484 kb
Host smart-ce9e5280-2620-4d56-b50c-9428b35bf118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810875865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2810875865
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1459800614
Short name T490
Test name
Test status
Simulation time 390937177 ps
CPU time 5.49 seconds
Started Jun 21 07:00:05 PM PDT 24
Finished Jun 21 07:00:16 PM PDT 24
Peak memory 224680 kb
Host smart-02497524-4452-40c6-b9ab-2213e626300e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459800614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1459800614
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2598580995
Short name T528
Test name
Test status
Simulation time 145413750 ps
CPU time 4.38 seconds
Started Jun 21 07:00:06 PM PDT 24
Finished Jun 21 07:00:15 PM PDT 24
Peak memory 232892 kb
Host smart-0bf9f55f-9e4e-42e3-82a8-b663e3ee4f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598580995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2598580995
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.654413250
Short name T374
Test name
Test status
Simulation time 1012615749 ps
CPU time 5.47 seconds
Started Jun 21 07:00:05 PM PDT 24
Finished Jun 21 07:00:16 PM PDT 24
Peak memory 224620 kb
Host smart-625b8507-6152-482d-91c3-4f218d5cda07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654413250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.654413250
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.4257888385
Short name T802
Test name
Test status
Simulation time 10232993718 ps
CPU time 6.24 seconds
Started Jun 21 07:00:03 PM PDT 24
Finished Jun 21 07:00:13 PM PDT 24
Peak memory 233032 kb
Host smart-5f2d6e43-4ca7-47ce-9656-0671bdf09cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257888385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.4257888385
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1171275209
Short name T146
Test name
Test status
Simulation time 208956666 ps
CPU time 2.36 seconds
Started Jun 21 07:00:04 PM PDT 24
Finished Jun 21 07:00:11 PM PDT 24
Peak memory 224600 kb
Host smart-9f978cff-6418-4a23-ab48-65f2d8bf0e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171275209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1171275209
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2822496149
Short name T847
Test name
Test status
Simulation time 949467090 ps
CPU time 10.4 seconds
Started Jun 21 07:00:04 PM PDT 24
Finished Jun 21 07:00:19 PM PDT 24
Peak memory 220864 kb
Host smart-cd469c87-a204-4413-ae1d-d2ac5e9397d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2822496149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2822496149
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2938882041
Short name T859
Test name
Test status
Simulation time 34282418802 ps
CPU time 176.23 seconds
Started Jun 21 07:00:02 PM PDT 24
Finished Jun 21 07:03:02 PM PDT 24
Peak memory 252228 kb
Host smart-0179ae31-6974-43bb-babb-1f42a53a5396
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938882041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2938882041
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3042879390
Short name T332
Test name
Test status
Simulation time 7783230854 ps
CPU time 23.85 seconds
Started Jun 21 07:00:07 PM PDT 24
Finished Jun 21 07:00:36 PM PDT 24
Peak memory 216516 kb
Host smart-30a6987b-40ba-4a65-9ce5-803cf287c81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042879390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3042879390
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1298455403
Short name T711
Test name
Test status
Simulation time 4985971203 ps
CPU time 13.47 seconds
Started Jun 21 07:00:01 PM PDT 24
Finished Jun 21 07:00:18 PM PDT 24
Peak memory 216528 kb
Host smart-a0008d4a-fcb6-44df-a240-a01545038a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298455403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1298455403
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2632448293
Short name T864
Test name
Test status
Simulation time 23035912 ps
CPU time 0.93 seconds
Started Jun 21 07:00:03 PM PDT 24
Finished Jun 21 07:00:08 PM PDT 24
Peak memory 206816 kb
Host smart-9dc7fb50-e10d-47d7-a471-042de8eca8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632448293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2632448293
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.676045798
Short name T916
Test name
Test status
Simulation time 73835312 ps
CPU time 0.92 seconds
Started Jun 21 07:00:04 PM PDT 24
Finished Jun 21 07:00:09 PM PDT 24
Peak memory 206076 kb
Host smart-7914408a-6131-46d4-aa50-42a3b99a2f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676045798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.676045798
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.4225483962
Short name T590
Test name
Test status
Simulation time 5324902641 ps
CPU time 6.46 seconds
Started Jun 21 07:00:03 PM PDT 24
Finished Jun 21 07:00:14 PM PDT 24
Peak memory 238112 kb
Host smart-614ac862-1e19-478a-9953-3c17f91ae003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225483962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.4225483962
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2830699786
Short name T710
Test name
Test status
Simulation time 16483852 ps
CPU time 0.73 seconds
Started Jun 21 07:00:13 PM PDT 24
Finished Jun 21 07:00:21 PM PDT 24
Peak memory 204920 kb
Host smart-c29fe979-bc76-4e74-96d6-e1b467444dab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830699786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
830699786
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.408904643
Short name T401
Test name
Test status
Simulation time 355928250 ps
CPU time 3.13 seconds
Started Jun 21 07:00:10 PM PDT 24
Finished Jun 21 07:00:20 PM PDT 24
Peak memory 232864 kb
Host smart-c4f22061-fd6b-4cad-a794-6422694e31ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408904643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.408904643
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3916833541
Short name T886
Test name
Test status
Simulation time 15005779 ps
CPU time 0.76 seconds
Started Jun 21 07:00:00 PM PDT 24
Finished Jun 21 07:00:04 PM PDT 24
Peak memory 205716 kb
Host smart-8e65ad44-3017-49cd-b4f5-e1b7c6d3fc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916833541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3916833541
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1183005683
Short name T225
Test name
Test status
Simulation time 69456128527 ps
CPU time 320.79 seconds
Started Jun 21 07:00:11 PM PDT 24
Finished Jun 21 07:05:38 PM PDT 24
Peak memory 256256 kb
Host smart-26f9daf5-b014-4e37-b497-f80d66896bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183005683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1183005683
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1762232707
Short name T880
Test name
Test status
Simulation time 357447609 ps
CPU time 7.62 seconds
Started Jun 21 07:00:13 PM PDT 24
Finished Jun 21 07:00:27 PM PDT 24
Peak memory 241132 kb
Host smart-105ee28c-9faa-4781-9699-05f9a5b9eff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762232707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1762232707
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.456438644
Short name T441
Test name
Test status
Simulation time 1777761432 ps
CPU time 11.39 seconds
Started Jun 21 07:00:10 PM PDT 24
Finished Jun 21 07:00:28 PM PDT 24
Peak memory 233368 kb
Host smart-700ddc28-8fb9-4118-8bf5-0afc2ed7a491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456438644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.456438644
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1273183403
Short name T532
Test name
Test status
Simulation time 2793166580 ps
CPU time 14.9 seconds
Started Jun 21 07:00:10 PM PDT 24
Finished Jun 21 07:00:32 PM PDT 24
Peak memory 224712 kb
Host smart-3f050dd4-44d8-46fd-96c9-74b2017510ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273183403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1273183403
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2331873919
Short name T417
Test name
Test status
Simulation time 287337337 ps
CPU time 2.03 seconds
Started Jun 21 07:00:12 PM PDT 24
Finished Jun 21 07:00:21 PM PDT 24
Peak memory 222972 kb
Host smart-fa798155-4217-47b0-a636-ec9237791d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331873919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2331873919
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.960564345
Short name T708
Test name
Test status
Simulation time 241090851 ps
CPU time 3.74 seconds
Started Jun 21 07:00:10 PM PDT 24
Finished Jun 21 07:00:21 PM PDT 24
Peak memory 232836 kb
Host smart-e2dfb7a8-d297-42d8-b34a-6eacfd3ed3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960564345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
960564345
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2035646295
Short name T508
Test name
Test status
Simulation time 247444483 ps
CPU time 4.83 seconds
Started Jun 21 07:00:18 PM PDT 24
Finished Jun 21 07:00:32 PM PDT 24
Peak memory 232892 kb
Host smart-1223ce89-4802-43b0-9bfe-999783d36684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035646295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2035646295
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1988131132
Short name T651
Test name
Test status
Simulation time 244025298 ps
CPU time 4.84 seconds
Started Jun 21 07:00:09 PM PDT 24
Finished Jun 21 07:00:21 PM PDT 24
Peak memory 219500 kb
Host smart-73e59fea-b318-4da2-a702-e67f6aa3f80a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1988131132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1988131132
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.986587298
Short name T46
Test name
Test status
Simulation time 36263079935 ps
CPU time 320.37 seconds
Started Jun 21 07:00:20 PM PDT 24
Finished Jun 21 07:05:48 PM PDT 24
Peak memory 249836 kb
Host smart-642b8ef3-1539-4b09-b99e-ae169518912c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986587298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.986587298
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.712437802
Short name T770
Test name
Test status
Simulation time 35274801143 ps
CPU time 40.19 seconds
Started Jun 21 07:00:14 PM PDT 24
Finished Jun 21 07:01:02 PM PDT 24
Peak memory 216520 kb
Host smart-3b422345-740b-4251-b267-91625b3ee3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712437802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.712437802
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3096955957
Short name T4
Test name
Test status
Simulation time 1230781419 ps
CPU time 5.25 seconds
Started Jun 21 07:00:01 PM PDT 24
Finished Jun 21 07:00:10 PM PDT 24
Peak memory 216388 kb
Host smart-21103e23-8b91-4ce0-801a-f705bc9dd678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096955957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3096955957
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2899956898
Short name T949
Test name
Test status
Simulation time 91427329 ps
CPU time 0.79 seconds
Started Jun 21 07:00:13 PM PDT 24
Finished Jun 21 07:00:20 PM PDT 24
Peak memory 206100 kb
Host smart-4888e430-54ee-42dc-8815-e2bfcf4f672b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899956898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2899956898
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.428256669
Short name T539
Test name
Test status
Simulation time 22322828 ps
CPU time 0.72 seconds
Started Jun 21 07:00:11 PM PDT 24
Finished Jun 21 07:00:18 PM PDT 24
Peak memory 206004 kb
Host smart-8393462a-88d6-49bb-bd58-43b24c22923c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428256669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.428256669
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2389195199
Short name T542
Test name
Test status
Simulation time 211250041 ps
CPU time 2.16 seconds
Started Jun 21 07:00:11 PM PDT 24
Finished Jun 21 07:00:20 PM PDT 24
Peak memory 224008 kb
Host smart-7a0c3d64-9c75-46c9-b344-060e5d2d68ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389195199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2389195199
Directory /workspace/9.spi_device_upload/latest
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