Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3419220	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3857620

1

T1

4671

T2

2033

T3

924

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4068453	1			T1	543		T2	435		T3	81
values[0x0]	1603106	1			T1	2243		T2	892		T3	442
values[0x1]	1605281	1			T1	2162		T2	881		T3	439

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2423672	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4853168

1

T1

4723

T2

2068

T3

934

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	47166	1			T2	1		T5	7		T6	1
valid_sources[0x01]	28120	1			T2	18		T4	6		T5	2
valid_sources[0x02]	27335	1			T2	32		T5	5		T6	5
valid_sources[0x03]	26807	1			T2	13		T5	7		T7	9
valid_sources[0x04]	30873	1			T5	5		T6	8		T7	9
valid_sources[0x05]	28120	1			T1	1		T5	6		T6	1
valid_sources[0x06]	26700	1			T5	7		T6	3		T7	3
valid_sources[0x07]	30114	1			T1	608		T2	3		T5	3
valid_sources[0x08]	25706	1			T2	10		T5	2		T7	1
valid_sources[0x09]	28012	1			T2	9		T5	5		T7	5
valid_sources[0x0a]	26568	1			T2	13		T5	4		T7	5
valid_sources[0x0b]	34240	1			T5	7		T6	3		T7	6
valid_sources[0x0c]	35330	1			T1	1		T5	4		T7	6
valid_sources[0x0d]	27224	1			T2	11		T5	3		T6	1
valid_sources[0x0e]	26373	1			T5	3		T6	9		T7	7
valid_sources[0x0f]	33298	1			T5	4		T6	29		T7	7
valid_sources[0x10]	26898	1			T5	7		T7	7		T9	24
valid_sources[0x11]	27337	1			T1	1		T2	8		T5	2
valid_sources[0x12]	27729	1			T1	1		T2	2		T5	5
valid_sources[0x13]	27224	1			T5	9		T6	1		T7	9
valid_sources[0x14]	29359	1			T2	7		T6	12		T7	11
valid_sources[0x15]	25737	1			T2	4		T5	4		T6	17
valid_sources[0x16]	32722	1			T1	1		T2	20		T5	7
valid_sources[0x17]	27913	1			T1	1		T5	6		T6	7
valid_sources[0x18]	27889	1			T1	1		T2	5		T5	3
valid_sources[0x19]	26963	1			T2	17		T5	5		T6	20
valid_sources[0x1a]	25718	1			T2	33		T5	3		T6	2
valid_sources[0x1b]	30369	1			T5	7		T6	2		T7	5
valid_sources[0x1c]	28098	1			T1	1		T2	32		T5	1
valid_sources[0x1d]	26516	1			T2	26		T5	5		T7	8
valid_sources[0x1e]	27462	1			T2	2		T5	4		T7	6
valid_sources[0x1f]	26185	1			T2	1		T5	10		T6	2
valid_sources[0x20]	26124	1			T5	6		T7	5		T8	2
valid_sources[0x21]	28338	1			T2	36		T5	4		T6	2
valid_sources[0x22]	27468	1			T2	3		T5	2		T6	1
valid_sources[0x23]	27380	1			T2	16		T5	3		T6	3
valid_sources[0x24]	24615	1			T2	15		T5	3		T6	3
valid_sources[0x25]	26017	1			T2	4		T5	4		T7	3
valid_sources[0x26]	25564	1			T1	1		T2	5		T5	2
valid_sources[0x27]	27225	1			T2	16		T5	4		T6	1
valid_sources[0x28]	53046	1			T2	3		T5	4		T6	7
valid_sources[0x29]	27319	1			T2	18		T5	4		T6	2
valid_sources[0x2a]	29203	1			T2	19		T5	2		T6	2
valid_sources[0x2b]	29738	1			T2	4		T5	5		T7	4
valid_sources[0x2c]	25845	1			T2	32		T5	4		T6	7
valid_sources[0x2d]	29175	1			T1	6		T2	4		T5	4
valid_sources[0x2e]	25198	1			T2	13		T5	6		T6	8
valid_sources[0x2f]	26632	1			T2	24		T5	4		T7	6
valid_sources[0x30]	32422	1			T2	6		T5	9		T7	1
valid_sources[0x31]	27982	1			T2	2		T4	8		T5	6
valid_sources[0x32]	27115	1			T4	1		T5	11		T6	5
valid_sources[0x33]	27201	1			T2	10		T5	2		T7	9
valid_sources[0x34]	27017	1			T2	12		T5	10		T6	2
valid_sources[0x35]	41209	1			T5	3		T6	8		T7	6
valid_sources[0x36]	29128	1			T1	1		T5	8		T7	10
valid_sources[0x37]	25709	1			T2	9		T5	2		T6	8
valid_sources[0x38]	26561	1			T1	2		T2	28		T5	5
valid_sources[0x39]	26828	1			T2	21		T5	3		T7	6
valid_sources[0x3a]	27643	1			T2	10		T5	4		T6	1
valid_sources[0x3b]	27164	1			T2	4		T4	2		T5	5
valid_sources[0x3c]	25764	1			T2	3		T5	2		T6	6
valid_sources[0x3d]	26201	1			T5	4		T7	6		T8	3
valid_sources[0x3e]	26007	1			T5	3		T6	5		T7	5
valid_sources[0x3f]	26535	1			T5	2		T6	10		T7	3
valid_sources[0x40]	28867	1			T2	7		T5	3		T6	8
valid_sources[0x41]	27463	1			T2	2		T7	10		T8	18
valid_sources[0x42]	28267	1			T2	17		T5	5		T7	10
valid_sources[0x43]	29480	1			T2	7		T5	13		T6	2
valid_sources[0x44]	26144	1			T5	9		T6	7		T7	10
valid_sources[0x45]	27810	1			T5	2		T6	4		T7	4
valid_sources[0x46]	27775	1			T5	4		T6	11		T7	6
valid_sources[0x47]	27480	1			T5	10		T7	7		T8	10
valid_sources[0x48]	26889	1			T2	4		T5	4		T7	12
valid_sources[0x49]	24918	1			T2	16		T5	5		T6	1
valid_sources[0x4a]	26779	1			T2	11		T5	6		T6	3
valid_sources[0x4b]	26416	1			T2	19		T5	4		T6	8
valid_sources[0x4c]	27295	1			T5	4		T6	4		T7	8
valid_sources[0x4d]	28062	1			T2	15		T5	5		T6	5
valid_sources[0x4e]	25939	1			T2	3		T5	2		T6	7
valid_sources[0x4f]	30779	1			T2	2		T5	9		T7	7
valid_sources[0x50]	28097	1			T2	2		T5	2		T6	6
valid_sources[0x51]	27571	1			T2	2		T5	10		T6	5
valid_sources[0x52]	26234	1			T2	3		T5	1		T6	7
valid_sources[0x53]	29884	1			T2	18		T5	1		T6	1
valid_sources[0x54]	28404	1			T5	10		T7	4		T9	19
valid_sources[0x55]	27107	1			T1	1		T2	35		T5	3
valid_sources[0x56]	28966	1			T2	6		T5	9		T6	1
valid_sources[0x57]	26913	1			T5	2		T6	1		T7	6
valid_sources[0x58]	28768	1			T2	4		T5	3		T6	4
valid_sources[0x59]	29050	1			T1	1		T2	5		T4	7
valid_sources[0x5a]	28834	1			T5	1		T6	2		T7	9
valid_sources[0x5b]	30334	1			T2	5		T5	3		T7	3
valid_sources[0x5c]	26633	1			T1	2		T2	32		T5	3
valid_sources[0x5d]	28567	1			T2	1		T5	6		T6	6
valid_sources[0x5e]	28467	1			T4	1		T5	2		T6	4
valid_sources[0x5f]	26368	1			T5	3		T6	3		T7	4
valid_sources[0x60]	27312	1			T2	2		T5	2		T6	1
valid_sources[0x61]	29664	1			T2	3		T5	11		T7	3
valid_sources[0x62]	29714	1			T5	11		T6	4		T7	3
valid_sources[0x63]	31215	1			T1	1		T2	40		T5	1
valid_sources[0x64]	28121	1			T2	24		T5	3		T7	11
valid_sources[0x65]	27636	1			T2	8		T5	5		T6	6
valid_sources[0x66]	26070	1			T2	5		T5	4		T6	4
valid_sources[0x67]	29298	1			T2	13		T5	5		T7	8
valid_sources[0x68]	29588	1			T1	1		T6	1		T7	6
valid_sources[0x69]	25573	1			T2	4		T5	5		T7	8
valid_sources[0x6a]	31681	1			T1	1		T2	7		T5	3
valid_sources[0x6b]	27582	1			T2	13		T4	7		T5	5
valid_sources[0x6c]	32198	1			T2	4		T5	6		T6	1
valid_sources[0x6d]	24798	1			T2	22		T5	3		T6	1
valid_sources[0x6e]	27329	1			T1	65		T5	10		T6	12
valid_sources[0x6f]	28913	1			T1	4		T5	1		T6	10
valid_sources[0x70]	24963	1			T2	13		T5	2		T7	7
valid_sources[0x71]	25532	1			T1	2		T5	5		T7	6
valid_sources[0x72]	26339	1			T1	1		T2	12		T5	2
valid_sources[0x73]	26497	1			T5	4		T7	6		T9	27
valid_sources[0x74]	30250	1			T2	1		T6	7		T7	13
valid_sources[0x75]	27272	1			T2	5		T5	10		T6	1
valid_sources[0x76]	26038	1			T5	5		T7	8		T8	7
valid_sources[0x77]	28327	1			T2	13		T5	12		T6	4
valid_sources[0x78]	26101	1			T5	7		T6	1		T7	13
valid_sources[0x79]	25829	1			T2	20		T5	5		T6	11
valid_sources[0x7a]	27228	1			T1	2		T5	1		T6	4
valid_sources[0x7b]	27852	1			T1	1		T2	2		T5	3
valid_sources[0x7c]	26135	1			T2	15		T5	4		T7	3
valid_sources[0x7d]	27509	1			T2	25		T5	6		T7	8
valid_sources[0x7e]	26323	1			T1	635		T2	7		T5	8
valid_sources[0x7f]	25351	1			T5	2		T6	3		T7	4
valid_sources[0x80]	26712	1			T2	5		T5	7		T7	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

974119

1

T1

282

T2

272

T3

47

values[0x0]

all_enables

biggest_size

1452670

1

T1

2238

T2

888

T3

440

values[0x1]

all_enables

biggest_size

1430831

1

T1

2151

T2

873

T3

437