Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3439701

1

T1

277

T2

175

T3

38

full_word

3858747

1

T1

4671

T2

2033

T3

924

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7298048	1			T1	4948		T2	2208		T3	962
auto[TlIntgErrCmd]	135	1			T99	9		T101	5		T102	5
auto[TlIntgErrData]	130	1			T99	11		T101	3		T102	7
auto[TlIntgErrBoth]	135	1			T99	10		T101	2		T102	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4071725

1

T1

543

T2

435

T3

81

auto[1]

3226723

1

T1

4405

T2

1773

T3

881

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3097158	1			T1	261		T2	163		T3	34
auto[TlIntgErrNone]	partial	auto[1]	342178	1			T1	16		T2	12		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	974373	1			T1	282		T2	272		T3	47
auto[TlIntgErrNone]	full_word	auto[1]	2884339	1			T1	4389		T2	1761		T3	877
auto[TlIntgErrCmd]	partial	auto[0]	59	1			T99	4		T101	4		T116	3
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T99	5		T101	1		T102	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T184	2		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T116	1		T185	1		T186	1
auto[TlIntgErrData]	partial	auto[0]	66	1			T99	5		T101	1		T102	3
auto[TlIntgErrData]	partial	auto[1]	52	1			T99	6		T102	3		T116	4
auto[TlIntgErrData]	full_word	auto[0]	7	1			T101	2		T187	1		T184	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T102	1		T185	1		T188	2
auto[TlIntgErrBoth]	partial	auto[0]	54	1			T99	2		T101	1		T102	5
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T99	7		T102	1		T116	7
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T99	1		T101	1		T102	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T102	1		T116	2		T180	1