Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	500003347	2957313	0	0
gen_wmask[1].MaskCheckPortA_A	500003347	2957313	0	0
gen_wmask[2].MaskCheckPortA_A	500003347	2957313	0	0
gen_wmask[3].MaskCheckPortA_A	500003347	2957313	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500003347	2957313	0	0
T1	713544	6388	0	0
T2	230019	2196	0	0
T3	7701	832	0	0
T4	1501	0	0	0
T5	26422	832	0	0
T6	231094	832	0	0
T7	32438	1088	0	0
T8	20527	832	0	0
T9	163777	1088	0	0
T10	122894	832	0	0
T11	90048	832	0	0
T27	0	1047	0	0
T32	0	8209	0	0
T35	0	6855	0	0
T36	0	2087	0	0
T37	0	6088	0	0
T39	0	3691	0	0
T43	0	6068	0	0
T44	0	16305	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500003347	2957313	0	0
T1	713544	6388	0	0
T2	230019	2196	0	0
T3	7701	832	0	0
T4	1501	0	0	0
T5	26422	832	0	0
T6	231094	832	0	0
T7	32438	1088	0	0
T8	20527	832	0	0
T9	163777	1088	0	0
T10	122894	832	0	0
T11	90048	832	0	0
T27	0	1047	0	0
T32	0	8209	0	0
T35	0	6855	0	0
T36	0	2087	0	0
T37	0	6088	0	0
T39	0	3691	0	0
T43	0	6068	0	0
T44	0	16305	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500003347	2957313	0	0
T1	713544	6388	0	0
T2	230019	2196	0	0
T3	7701	832	0	0
T4	1501	0	0	0
T5	26422	832	0	0
T6	231094	832	0	0
T7	32438	1088	0	0
T8	20527	832	0	0
T9	163777	1088	0	0
T10	122894	832	0	0
T11	90048	832	0	0
T27	0	1047	0	0
T32	0	8209	0	0
T35	0	6855	0	0
T36	0	2087	0	0
T37	0	6088	0	0
T39	0	3691	0	0
T43	0	6068	0	0
T44	0	16305	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500003347	2957313	0	0
T1	713544	6388	0	0
T2	230019	2196	0	0
T3	7701	832	0	0
T4	1501	0	0	0
T5	26422	832	0	0
T6	231094	832	0	0
T7	32438	1088	0	0
T8	20527	832	0	0
T9	163777	1088	0	0
T10	122894	832	0	0
T11	90048	832	0	0
T27	0	1047	0	0
T32	0	8209	0	0
T35	0	6855	0	0
T36	0	2087	0	0
T37	0	6088	0	0
T39	0	3691	0	0
T43	0	6068	0	0
T44	0	16305	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	366779948	1824330	0	0
gen_wmask[1].MaskCheckPortA_A	366779948	1824330	0	0
gen_wmask[2].MaskCheckPortA_A	366779948	1824330	0	0
gen_wmask[3].MaskCheckPortA_A	366779948	1824330	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366779948	1824330	0	0
T1	278817	4160	0	0
T2	157563	1664	0	0
T3	4473	832	0	0
T4	1501	0	0	0
T5	15149	832	0	0
T6	117853	832	0	0
T7	10696	1088	0	0
T8	11931	832	0	0
T9	143765	1088	0	0
T10	100366	832	0	0
T11	0	832	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366779948	1824330	0	0
T1	278817	4160	0	0
T2	157563	1664	0	0
T3	4473	832	0	0
T4	1501	0	0	0
T5	15149	832	0	0
T6	117853	832	0	0
T7	10696	1088	0	0
T8	11931	832	0	0
T9	143765	1088	0	0
T10	100366	832	0	0
T11	0	832	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366779948	1824330	0	0
T1	278817	4160	0	0
T2	157563	1664	0	0
T3	4473	832	0	0
T4	1501	0	0	0
T5	15149	832	0	0
T6	117853	832	0	0
T7	10696	1088	0	0
T8	11931	832	0	0
T9	143765	1088	0	0
T10	100366	832	0	0
T11	0	832	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366779948	1824330	0	0
T1	278817	4160	0	0
T2	157563	1664	0	0
T3	4473	832	0	0
T4	1501	0	0	0
T5	15149	832	0	0
T6	117853	832	0	0
T7	10696	1088	0	0
T8	11931	832	0	0
T9	143765	1088	0	0
T10	100366	832	0	0
T11	0	832	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T39
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T39
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	133223399	1132983	0	0
gen_wmask[1].MaskCheckPortA_A	133223399	1132983	0	0
gen_wmask[2].MaskCheckPortA_A	133223399	1132983	0	0
gen_wmask[3].MaskCheckPortA_A	133223399	1132983	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	1132983	0	0
T1	434727	2228	0	0
T2	72456	532	0	0
T3	3228	0	0	0
T5	11273	0	0	0
T6	113241	0	0	0
T7	21742	0	0	0
T8	8596	0	0	0
T9	20012	0	0	0
T10	22528	0	0	0
T11	90048	0	0	0
T27	0	1047	0	0
T32	0	8209	0	0
T35	0	6855	0	0
T36	0	2087	0	0
T37	0	6088	0	0
T39	0	3691	0	0
T43	0	6068	0	0
T44	0	16305	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	1132983	0	0
T1	434727	2228	0	0
T2	72456	532	0	0
T3	3228	0	0	0
T5	11273	0	0	0
T6	113241	0	0	0
T7	21742	0	0	0
T8	8596	0	0	0
T9	20012	0	0	0
T10	22528	0	0	0
T11	90048	0	0	0
T27	0	1047	0	0
T32	0	8209	0	0
T35	0	6855	0	0
T36	0	2087	0	0
T37	0	6088	0	0
T39	0	3691	0	0
T43	0	6068	0	0
T44	0	16305	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	1132983	0	0
T1	434727	2228	0	0
T2	72456	532	0	0
T3	3228	0	0	0
T5	11273	0	0	0
T6	113241	0	0	0
T7	21742	0	0	0
T8	8596	0	0	0
T9	20012	0	0	0
T10	22528	0	0	0
T11	90048	0	0	0
T27	0	1047	0	0
T32	0	8209	0	0
T35	0	6855	0	0
T36	0	2087	0	0
T37	0	6088	0	0
T39	0	3691	0	0
T43	0	6068	0	0
T44	0	16305	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	1132983	0	0
T1	434727	2228	0	0
T2	72456	532	0	0
T3	3228	0	0	0
T5	11273	0	0	0
T6	113241	0	0	0
T7	21742	0	0	0
T8	8596	0	0	0
T9	20012	0	0	0
T10	22528	0	0	0
T11	90048	0	0	0
T27	0	1047	0	0
T32	0	8209	0	0
T35	0	6855	0	0
T36	0	2087	0	0
T37	0	6088	0	0
T39	0	3691	0	0
T43	0	6068	0	0
T44	0	16305	0	0