Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T32,T35,T36
1	0	Covered	T32,T35,T36

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T33
1	0	Unreachable
1	1	Covered	T32,T35,T36

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T39

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T39
1	0	Covered	T1,T2,T39

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T39

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T39

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T39
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T39
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	633226746	498645616	0	0
CheckNGreaterZero_A	2718	2718	0	0
GntImpliesReady_A	633226746	3337014	0	0
GntImpliesValid_A	633226746	3337014	0	0
GrantKnown_A	633226746	498645616	0	0
IdxKnown_A	633226746	498645616	0	0
IndexIsCorrect_A	633226746	3337014	0	0
LockArbDecision_A	633226746	0	0	0
NoReadyValidNoGrant_A	633226746	0	0	0
ReadyAndValidImplyGrant_A	633226746	3337014	0	0
ReqAndReadyImplyGrant_A	633226746	3337014	0	0
ReqImpliesValid_A	633226746	3337014	0	0
ReqStaysHighUntilGranted0_M	633226746	0	0	0
RoundRobin_A	633226746	2	0	906
ValidKnown_A	633226746	498645616	0	0
gen_data_port_assertion.DataFlow_A	633226746	3337014	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633226746	498645616	0	0
T1	713544	712478	0	0
T2	230019	229942	0	0
T3	7701	7611	0	0
T4	1501	1436	0	0
T5	26422	26172	0	0
T6	231094	229960	0	0
T7	32438	32362	0	0
T8	20527	20470	0	0
T9	163777	163698	0	0
T10	122894	122805	0	0
T11	90048	90048	0	0
T29	0	56728	0	0
T30	0	3016	0	0
T31	9340	8912	0	0
T32	334117	126464	0	0
T33	89259	82824	0	0
T34	549	360	0	0
T35	736582	306624	0	0
T36	0	71760	0	0
T37	0	65592	0	0
T38	0	48384	0	0
T39	345868	0	0	0
T43	148797	0	0	0
T44	854188	0	0	0
T46	13426	0	0	0
T57	16480	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2718	2718	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633226746	3337014	0	0
T1	713544	6465	0	0
T2	230019	2339	0	0
T3	7701	832	0	0
T4	1501	0	0	0
T5	26422	832	0	0
T6	231094	832	0	0
T7	32438	1088	0	0
T8	20527	832	0	0
T9	163777	1088	0	0
T10	122894	832	0	0
T11	90048	832	0	0
T13	0	3702	0	0
T29	0	2826	0	0
T32	334117	10306	0	0
T33	89259	0	0	0
T34	549	0	0	0
T35	736582	8283	0	0
T36	230557	2991	0	0
T37	461761	6861	0	0
T38	0	2246	0	0
T39	0	3691	0	0
T43	148797	0	0	0
T44	854188	0	0	0
T47	25633	0	0	0
T52	0	4069	0	0
T58	21616	0	0	0
T59	0	114	0	0
T60	0	6162	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633226746	3337014	0	0
T1	713544	6465	0	0
T2	230019	2339	0	0
T3	7701	832	0	0
T4	1501	0	0	0
T5	26422	832	0	0
T6	231094	832	0	0
T7	32438	1088	0	0
T8	20527	832	0	0
T9	163777	1088	0	0
T10	122894	832	0	0
T11	90048	832	0	0
T13	0	3702	0	0
T29	0	2826	0	0
T32	334117	10306	0	0
T33	89259	0	0	0
T34	549	0	0	0
T35	736582	8283	0	0
T36	230557	2991	0	0
T37	461761	6861	0	0
T38	0	2246	0	0
T39	0	3691	0	0
T43	148797	0	0	0
T44	854188	0	0	0
T47	25633	0	0	0
T52	0	4069	0	0
T58	21616	0	0	0
T59	0	114	0	0
T60	0	6162	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633226746	498645616	0	0
T1	713544	712478	0	0
T2	230019	229942	0	0
T3	7701	7611	0	0
T4	1501	1436	0	0
T5	26422	26172	0	0
T6	231094	229960	0	0
T7	32438	32362	0	0
T8	20527	20470	0	0
T9	163777	163698	0	0
T10	122894	122805	0	0
T11	90048	90048	0	0
T29	0	56728	0	0
T30	0	3016	0	0
T31	9340	8912	0	0
T32	334117	126464	0	0
T33	89259	82824	0	0
T34	549	360	0	0
T35	736582	306624	0	0
T36	0	71760	0	0
T37	0	65592	0	0
T38	0	48384	0	0
T39	345868	0	0	0
T43	148797	0	0	0
T44	854188	0	0	0
T46	13426	0	0	0
T57	16480	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633226746	498645616	0	0
T1	713544	712478	0	0
T2	230019	229942	0	0
T3	7701	7611	0	0
T4	1501	1436	0	0
T5	26422	26172	0	0
T6	231094	229960	0	0
T7	32438	32362	0	0
T8	20527	20470	0	0
T9	163777	163698	0	0
T10	122894	122805	0	0
T11	90048	90048	0	0
T29	0	56728	0	0
T30	0	3016	0	0
T31	9340	8912	0	0
T32	334117	126464	0	0
T33	89259	82824	0	0
T34	549	360	0	0
T35	736582	306624	0	0
T36	0	71760	0	0
T37	0	65592	0	0
T38	0	48384	0	0
T39	345868	0	0	0
T43	148797	0	0	0
T44	854188	0	0	0
T46	13426	0	0	0
T57	16480	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633226746	3337014	0	0
T1	713544	6465	0	0
T2	230019	2339	0	0
T3	7701	832	0	0
T4	1501	0	0	0
T5	26422	832	0	0
T6	231094	832	0	0
T7	32438	1088	0	0
T8	20527	832	0	0
T9	163777	1088	0	0
T10	122894	832	0	0
T11	90048	832	0	0
T13	0	3702	0	0
T29	0	2826	0	0
T32	334117	10306	0	0
T33	89259	0	0	0
T34	549	0	0	0
T35	736582	8283	0	0
T36	230557	2991	0	0
T37	461761	6861	0	0
T38	0	2246	0	0
T39	0	3691	0	0
T43	148797	0	0	0
T44	854188	0	0	0
T47	25633	0	0	0
T52	0	4069	0	0
T58	21616	0	0	0
T59	0	114	0	0
T60	0	6162	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633226746	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633226746	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633226746	3337014	0	0
T1	713544	6465	0	0
T2	230019	2339	0	0
T3	7701	832	0	0
T4	1501	0	0	0
T5	26422	832	0	0
T6	231094	832	0	0
T7	32438	1088	0	0
T8	20527	832	0	0
T9	163777	1088	0	0
T10	122894	832	0	0
T11	90048	832	0	0
T13	0	3702	0	0
T29	0	2826	0	0
T32	334117	10306	0	0
T33	89259	0	0	0
T34	549	0	0	0
T35	736582	8283	0	0
T36	230557	2991	0	0
T37	461761	6861	0	0
T38	0	2246	0	0
T39	0	3691	0	0
T43	148797	0	0	0
T44	854188	0	0	0
T47	25633	0	0	0
T52	0	4069	0	0
T58	21616	0	0	0
T59	0	114	0	0
T60	0	6162	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633226746	3337014	0	0
T1	713544	6465	0	0
T2	230019	2339	0	0
T3	7701	832	0	0
T4	1501	0	0	0
T5	26422	832	0	0
T6	231094	832	0	0
T7	32438	1088	0	0
T8	20527	832	0	0
T9	163777	1088	0	0
T10	122894	832	0	0
T11	90048	832	0	0
T13	0	3702	0	0
T29	0	2826	0	0
T32	334117	10306	0	0
T33	89259	0	0	0
T34	549	0	0	0
T35	736582	8283	0	0
T36	230557	2991	0	0
T37	461761	6861	0	0
T38	0	2246	0	0
T39	0	3691	0	0
T43	148797	0	0	0
T44	854188	0	0	0
T47	25633	0	0	0
T52	0	4069	0	0
T58	21616	0	0	0
T59	0	114	0	0
T60	0	6162	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633226746	3337014	0	0
T1	713544	6465	0	0
T2	230019	2339	0	0
T3	7701	832	0	0
T4	1501	0	0	0
T5	26422	832	0	0
T6	231094	832	0	0
T7	32438	1088	0	0
T8	20527	832	0	0
T9	163777	1088	0	0
T10	122894	832	0	0
T11	90048	832	0	0
T13	0	3702	0	0
T29	0	2826	0	0
T32	334117	10306	0	0
T33	89259	0	0	0
T34	549	0	0	0
T35	736582	8283	0	0
T36	230557	2991	0	0
T37	461761	6861	0	0
T38	0	2246	0	0
T39	0	3691	0	0
T43	148797	0	0	0
T44	854188	0	0	0
T47	25633	0	0	0
T52	0	4069	0	0
T58	21616	0	0	0
T59	0	114	0	0
T60	0	6162	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	633226746	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633226746	2	0	906
T61	139968	1	0	1
T62	0	1	0	0
T63	495245	0	0	1
T64	15230	0	0	1
T65	604814	0	0	1
T66	793	0	0	1
T67	51740	0	0	1
T68	24195	0	0	1
T69	967440	0	0	1
T70	243670	0	0	1
T71	3810	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633226746	498645616	0	0
T1	713544	712478	0	0
T2	230019	229942	0	0
T3	7701	7611	0	0
T4	1501	1436	0	0
T5	26422	26172	0	0
T6	231094	229960	0	0
T7	32438	32362	0	0
T8	20527	20470	0	0
T9	163777	163698	0	0
T10	122894	122805	0	0
T11	90048	90048	0	0
T29	0	56728	0	0
T30	0	3016	0	0
T31	9340	8912	0	0
T32	334117	126464	0	0
T33	89259	82824	0	0
T34	549	360	0	0
T35	736582	306624	0	0
T36	0	71760	0	0
T37	0	65592	0	0
T38	0	48384	0	0
T39	345868	0	0	0
T43	148797	0	0	0
T44	854188	0	0	0
T46	13426	0	0	0
T57	16480	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633226746	3337014	0	0
T1	713544	6465	0	0
T2	230019	2339	0	0
T3	7701	832	0	0
T4	1501	0	0	0
T5	26422	832	0	0
T6	231094	832	0	0
T7	32438	1088	0	0
T8	20527	832	0	0
T9	163777	1088	0	0
T10	122894	832	0	0
T11	90048	832	0	0
T13	0	3702	0	0
T29	0	2826	0	0
T32	334117	10306	0	0
T33	89259	0	0	0
T34	549	0	0	0
T35	736582	8283	0	0
T36	230557	2991	0	0
T37	461761	6861	0	0
T38	0	2246	0	0
T39	0	3691	0	0
T43	148797	0	0	0
T44	854188	0	0	0
T47	25633	0	0	0
T52	0	4069	0	0
T58	21616	0	0	0
T59	0	114	0	0
T60	0	6162	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T32,T35,T36
1	0	Covered	T32,T35,T36

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T33
1	0	Unreachable
1	1	Covered	T32,T35,T36

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T32,T35,T36
0	0	1	Unreachable
0	0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T32,T35,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T32,T35,T36
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	133223399	29165584	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	133223399	643051	0	0
GntImpliesValid_A	133223399	643051	0	0
GrantKnown_A	133223399	29165584	0	0
IdxKnown_A	133223399	29165584	0	0
IndexIsCorrect_A	133223399	643051	0	0
LockArbDecision_A	133223399	0	0	0
NoReadyValidNoGrant_A	133223399	0	0	0
ReadyAndValidImplyGrant_A	133223399	643051	0	0
ReqAndReadyImplyGrant_A	133223399	643051	0	0
ReqImpliesValid_A	133223399	643051	0	0
ReqStaysHighUntilGranted0_M	133223399	0	0	0
RoundRobin_A	133223399	0	0	0
ValidKnown_A	133223399	29165584	0	0
gen_data_port_assertion.DataFlow_A	133223399	643051	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	29165584	0	0
T29	0	56728	0	0
T30	0	3016	0	0
T31	9340	8912	0	0
T32	334117	126464	0	0
T33	89259	82824	0	0
T34	549	360	0	0
T35	736582	306624	0	0
T36	0	71760	0	0
T37	0	65592	0	0
T38	0	48384	0	0
T39	345868	0	0	0
T43	148797	0	0	0
T44	854188	0	0	0
T46	13426	0	0	0
T57	16480	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	643051	0	0
T13	0	3702	0	0
T29	0	2826	0	0
T32	334117	5868	0	0
T33	89259	0	0	0
T34	549	0	0	0
T35	736582	5159	0	0
T36	230557	2983	0	0
T37	461761	2160	0	0
T38	0	2246	0	0
T43	148797	0	0	0
T44	854188	0	0	0
T47	25633	0	0	0
T52	0	4069	0	0
T58	21616	0	0	0
T59	0	114	0	0
T60	0	6162	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	643051	0	0
T13	0	3702	0	0
T29	0	2826	0	0
T32	334117	5868	0	0
T33	89259	0	0	0
T34	549	0	0	0
T35	736582	5159	0	0
T36	230557	2983	0	0
T37	461761	2160	0	0
T38	0	2246	0	0
T43	148797	0	0	0
T44	854188	0	0	0
T47	25633	0	0	0
T52	0	4069	0	0
T58	21616	0	0	0
T59	0	114	0	0
T60	0	6162	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	29165584	0	0
T29	0	56728	0	0
T30	0	3016	0	0
T31	9340	8912	0	0
T32	334117	126464	0	0
T33	89259	82824	0	0
T34	549	360	0	0
T35	736582	306624	0	0
T36	0	71760	0	0
T37	0	65592	0	0
T38	0	48384	0	0
T39	345868	0	0	0
T43	148797	0	0	0
T44	854188	0	0	0
T46	13426	0	0	0
T57	16480	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	29165584	0	0
T29	0	56728	0	0
T30	0	3016	0	0
T31	9340	8912	0	0
T32	334117	126464	0	0
T33	89259	82824	0	0
T34	549	360	0	0
T35	736582	306624	0	0
T36	0	71760	0	0
T37	0	65592	0	0
T38	0	48384	0	0
T39	345868	0	0	0
T43	148797	0	0	0
T44	854188	0	0	0
T46	13426	0	0	0
T57	16480	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	643051	0	0
T13	0	3702	0	0
T29	0	2826	0	0
T32	334117	5868	0	0
T33	89259	0	0	0
T34	549	0	0	0
T35	736582	5159	0	0
T36	230557	2983	0	0
T37	461761	2160	0	0
T38	0	2246	0	0
T43	148797	0	0	0
T44	854188	0	0	0
T47	25633	0	0	0
T52	0	4069	0	0
T58	21616	0	0	0
T59	0	114	0	0
T60	0	6162	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	643051	0	0
T13	0	3702	0	0
T29	0	2826	0	0
T32	334117	5868	0	0
T33	89259	0	0	0
T34	549	0	0	0
T35	736582	5159	0	0
T36	230557	2983	0	0
T37	461761	2160	0	0
T38	0	2246	0	0
T43	148797	0	0	0
T44	854188	0	0	0
T47	25633	0	0	0
T52	0	4069	0	0
T58	21616	0	0	0
T59	0	114	0	0
T60	0	6162	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	643051	0	0
T13	0	3702	0	0
T29	0	2826	0	0
T32	334117	5868	0	0
T33	89259	0	0	0
T34	549	0	0	0
T35	736582	5159	0	0
T36	230557	2983	0	0
T37	461761	2160	0	0
T38	0	2246	0	0
T43	148797	0	0	0
T44	854188	0	0	0
T47	25633	0	0	0
T52	0	4069	0	0
T58	21616	0	0	0
T59	0	114	0	0
T60	0	6162	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	643051	0	0
T13	0	3702	0	0
T29	0	2826	0	0
T32	334117	5868	0	0
T33	89259	0	0	0
T34	549	0	0	0
T35	736582	5159	0	0
T36	230557	2983	0	0
T37	461761	2160	0	0
T38	0	2246	0	0
T43	148797	0	0	0
T44	854188	0	0	0
T47	25633	0	0	0
T52	0	4069	0	0
T58	21616	0	0	0
T59	0	114	0	0
T60	0	6162	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	29165584	0	0
T29	0	56728	0	0
T30	0	3016	0	0
T31	9340	8912	0	0
T32	334117	126464	0	0
T33	89259	82824	0	0
T34	549	360	0	0
T35	736582	306624	0	0
T36	0	71760	0	0
T37	0	65592	0	0
T38	0	48384	0	0
T39	345868	0	0	0
T43	148797	0	0	0
T44	854188	0	0	0
T46	13426	0	0	0
T57	16480	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	643051	0	0
T13	0	3702	0	0
T29	0	2826	0	0
T32	334117	5868	0	0
T33	89259	0	0	0
T34	549	0	0	0
T35	736582	5159	0	0
T36	230557	2983	0	0
T37	461761	2160	0	0
T38	0	2246	0	0
T43	148797	0	0	0
T44	854188	0	0	0
T47	25633	0	0	0
T52	0	4069	0	0
T58	21616	0	0	0
T59	0	114	0	0
T60	0	6162	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T39

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T39
1	0	Covered	T1,T2,T39

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T39

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T39
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T39
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T39
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T39
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	133223399	102781728	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	133223399	700895	0	0
GntImpliesValid_A	133223399	700895	0	0
GrantKnown_A	133223399	102781728	0	0
IdxKnown_A	133223399	102781728	0	0
IndexIsCorrect_A	133223399	700895	0	0
LockArbDecision_A	133223399	0	0	0
NoReadyValidNoGrant_A	133223399	0	0	0
ReadyAndValidImplyGrant_A	133223399	700895	0	0
ReqAndReadyImplyGrant_A	133223399	700895	0	0
ReqImpliesValid_A	133223399	700895	0	0
ReqStaysHighUntilGranted0_M	133223399	0	0	0
RoundRobin_A	133223399	0	0	0
ValidKnown_A	133223399	102781728	0	0
gen_data_port_assertion.DataFlow_A	133223399	700895	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	102781728	0	0
T1	434727	433759	0	0
T2	72456	72456	0	0
T3	3228	3228	0	0
T5	11273	11100	0	0
T6	113241	112158	0	0
T7	21742	21742	0	0
T8	8596	8596	0	0
T9	20012	20012	0	0
T10	22528	22528	0	0
T11	90048	90048	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	700895	0	0
T1	434727	2228	0	0
T2	72456	532	0	0
T3	3228	0	0	0
T5	11273	0	0	0
T6	113241	0	0	0
T7	21742	0	0	0
T8	8596	0	0	0
T9	20012	0	0	0
T10	22528	0	0	0
T11	90048	0	0	0
T27	0	1047	0	0
T32	0	4438	0	0
T35	0	3124	0	0
T36	0	8	0	0
T37	0	4701	0	0
T39	0	3691	0	0
T43	0	6068	0	0
T44	0	16305	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	700895	0	0
T1	434727	2228	0	0
T2	72456	532	0	0
T3	3228	0	0	0
T5	11273	0	0	0
T6	113241	0	0	0
T7	21742	0	0	0
T8	8596	0	0	0
T9	20012	0	0	0
T10	22528	0	0	0
T11	90048	0	0	0
T27	0	1047	0	0
T32	0	4438	0	0
T35	0	3124	0	0
T36	0	8	0	0
T37	0	4701	0	0
T39	0	3691	0	0
T43	0	6068	0	0
T44	0	16305	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	102781728	0	0
T1	434727	433759	0	0
T2	72456	72456	0	0
T3	3228	3228	0	0
T5	11273	11100	0	0
T6	113241	112158	0	0
T7	21742	21742	0	0
T8	8596	8596	0	0
T9	20012	20012	0	0
T10	22528	22528	0	0
T11	90048	90048	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	102781728	0	0
T1	434727	433759	0	0
T2	72456	72456	0	0
T3	3228	3228	0	0
T5	11273	11100	0	0
T6	113241	112158	0	0
T7	21742	21742	0	0
T8	8596	8596	0	0
T9	20012	20012	0	0
T10	22528	22528	0	0
T11	90048	90048	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	700895	0	0
T1	434727	2228	0	0
T2	72456	532	0	0
T3	3228	0	0	0
T5	11273	0	0	0
T6	113241	0	0	0
T7	21742	0	0	0
T8	8596	0	0	0
T9	20012	0	0	0
T10	22528	0	0	0
T11	90048	0	0	0
T27	0	1047	0	0
T32	0	4438	0	0
T35	0	3124	0	0
T36	0	8	0	0
T37	0	4701	0	0
T39	0	3691	0	0
T43	0	6068	0	0
T44	0	16305	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	700895	0	0
T1	434727	2228	0	0
T2	72456	532	0	0
T3	3228	0	0	0
T5	11273	0	0	0
T6	113241	0	0	0
T7	21742	0	0	0
T8	8596	0	0	0
T9	20012	0	0	0
T10	22528	0	0	0
T11	90048	0	0	0
T27	0	1047	0	0
T32	0	4438	0	0
T35	0	3124	0	0
T36	0	8	0	0
T37	0	4701	0	0
T39	0	3691	0	0
T43	0	6068	0	0
T44	0	16305	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	700895	0	0
T1	434727	2228	0	0
T2	72456	532	0	0
T3	3228	0	0	0
T5	11273	0	0	0
T6	113241	0	0	0
T7	21742	0	0	0
T8	8596	0	0	0
T9	20012	0	0	0
T10	22528	0	0	0
T11	90048	0	0	0
T27	0	1047	0	0
T32	0	4438	0	0
T35	0	3124	0	0
T36	0	8	0	0
T37	0	4701	0	0
T39	0	3691	0	0
T43	0	6068	0	0
T44	0	16305	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	700895	0	0
T1	434727	2228	0	0
T2	72456	532	0	0
T3	3228	0	0	0
T5	11273	0	0	0
T6	113241	0	0	0
T7	21742	0	0	0
T8	8596	0	0	0
T9	20012	0	0	0
T10	22528	0	0	0
T11	90048	0	0	0
T27	0	1047	0	0
T32	0	4438	0	0
T35	0	3124	0	0
T36	0	8	0	0
T37	0	4701	0	0
T39	0	3691	0	0
T43	0	6068	0	0
T44	0	16305	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	102781728	0	0
T1	434727	433759	0	0
T2	72456	72456	0	0
T3	3228	3228	0	0
T5	11273	11100	0	0
T6	113241	112158	0	0
T7	21742	21742	0	0
T8	8596	8596	0	0
T9	20012	20012	0	0
T10	22528	22528	0	0
T11	90048	90048	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133223399	700895	0	0
T1	434727	2228	0	0
T2	72456	532	0	0
T3	3228	0	0	0
T5	11273	0	0	0
T6	113241	0	0	0
T7	21742	0	0	0
T8	8596	0	0	0
T9	20012	0	0	0
T10	22528	0	0	0
T11	90048	0	0	0
T27	0	1047	0	0
T32	0	4438	0	0
T35	0	3124	0	0
T36	0	8	0	0
T37	0	4701	0	0
T39	0	3691	0	0
T43	0	6068	0	0
T44	0	16305	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T39

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T39
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T39
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	366779948	366698304	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	366779948	1993068	0	0
GntImpliesValid_A	366779948	1993068	0	0
GrantKnown_A	366779948	366698304	0	0
IdxKnown_A	366779948	366698304	0	0
IndexIsCorrect_A	366779948	1993068	0	0
LockArbDecision_A	366779948	0	0	0
NoReadyValidNoGrant_A	366779948	0	0	0
ReadyAndValidImplyGrant_A	366779948	1993068	0	0
ReqAndReadyImplyGrant_A	366779948	1993068	0	0
ReqImpliesValid_A	366779948	1993068	0	0
ReqStaysHighUntilGranted0_M	366779948	0	0	0
RoundRobin_A	366779948	2	0	906
ValidKnown_A	366779948	366698304	0	0
gen_data_port_assertion.DataFlow_A	366779948	1993068	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366779948	366698304	0	0
T1	278817	278719	0	0
T2	157563	157486	0	0
T3	4473	4383	0	0
T4	1501	1436	0	0
T5	15149	15072	0	0
T6	117853	117802	0	0
T7	10696	10620	0	0
T8	11931	11874	0	0
T9	143765	143686	0	0
T10	100366	100277	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366779948	1993068	0	0
T1	278817	4237	0	0
T2	157563	1807	0	0
T3	4473	832	0	0
T4	1501	0	0	0
T5	15149	832	0	0
T6	117853	832	0	0
T7	10696	1088	0	0
T8	11931	832	0	0
T9	143765	1088	0	0
T10	100366	832	0	0
T11	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366779948	1993068	0	0
T1	278817	4237	0	0
T2	157563	1807	0	0
T3	4473	832	0	0
T4	1501	0	0	0
T5	15149	832	0	0
T6	117853	832	0	0
T7	10696	1088	0	0
T8	11931	832	0	0
T9	143765	1088	0	0
T10	100366	832	0	0
T11	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366779948	366698304	0	0
T1	278817	278719	0	0
T2	157563	157486	0	0
T3	4473	4383	0	0
T4	1501	1436	0	0
T5	15149	15072	0	0
T6	117853	117802	0	0
T7	10696	10620	0	0
T8	11931	11874	0	0
T9	143765	143686	0	0
T10	100366	100277	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366779948	366698304	0	0
T1	278817	278719	0	0
T2	157563	157486	0	0
T3	4473	4383	0	0
T4	1501	1436	0	0
T5	15149	15072	0	0
T6	117853	117802	0	0
T7	10696	10620	0	0
T8	11931	11874	0	0
T9	143765	143686	0	0
T10	100366	100277	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366779948	1993068	0	0
T1	278817	4237	0	0
T2	157563	1807	0	0
T3	4473	832	0	0
T4	1501	0	0	0
T5	15149	832	0	0
T6	117853	832	0	0
T7	10696	1088	0	0
T8	11931	832	0	0
T9	143765	1088	0	0
T10	100366	832	0	0
T11	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366779948	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366779948	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366779948	1993068	0	0
T1	278817	4237	0	0
T2	157563	1807	0	0
T3	4473	832	0	0
T4	1501	0	0	0
T5	15149	832	0	0
T6	117853	832	0	0
T7	10696	1088	0	0
T8	11931	832	0	0
T9	143765	1088	0	0
T10	100366	832	0	0
T11	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366779948	1993068	0	0
T1	278817	4237	0	0
T2	157563	1807	0	0
T3	4473	832	0	0
T4	1501	0	0	0
T5	15149	832	0	0
T6	117853	832	0	0
T7	10696	1088	0	0
T8	11931	832	0	0
T9	143765	1088	0	0
T10	100366	832	0	0
T11	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366779948	1993068	0	0
T1	278817	4237	0	0
T2	157563	1807	0	0
T3	4473	832	0	0
T4	1501	0	0	0
T5	15149	832	0	0
T6	117853	832	0	0
T7	10696	1088	0	0
T8	11931	832	0	0
T9	143765	1088	0	0
T10	100366	832	0	0
T11	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	366779948	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366779948	2	0	906
T61	139968	1	0	1
T62	0	1	0	0
T63	495245	0	0	1
T64	15230	0	0	1
T65	604814	0	0	1
T66	793	0	0	1
T67	51740	0	0	1
T68	24195	0	0	1
T69	967440	0	0	1
T70	243670	0	0	1
T71	3810	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366779948	366698304	0	0
T1	278817	278719	0	0
T2	157563	157486	0	0
T3	4473	4383	0	0
T4	1501	1436	0	0
T5	15149	15072	0	0
T6	117853	117802	0	0
T7	10696	10620	0	0
T8	11931	11874	0	0
T9	143765	143686	0	0
T10	100366	100277	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	366779948	1993068	0	0
T1	278817	4237	0	0
T2	157563	1807	0	0
T3	4473	832	0	0
T4	1501	0	0	0
T5	15149	832	0	0
T6	117853	832	0	0
T7	10696	1088	0	0
T8	11931	832	0	0
T9	143765	1088	0	0
T10	100366	832	0	0
T11	0	832	0	0