Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3602137	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4048303

1

T1

894

T2

8166

T3

15930

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4266612	1			T1	4		T2	3504		T3	17788
values[0x0]	1690298	1			T1	451		T2	3135		T3	8027
values[0x1]	1693530	1			T1	441		T2	3036		T3	7976

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2550725	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5099715

1

T1

895

T2

8475

T3

21337

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28244	1			T2	20		T3	152		T7	49
valid_sources[0x01]	31449	1			T1	445		T2	68		T3	168
valid_sources[0x02]	31758	1			T2	27		T3	135		T7	43
valid_sources[0x03]	30633	1			T2	53		T3	152		T7	12
valid_sources[0x04]	30561	1			T2	55		T3	119		T7	36
valid_sources[0x05]	33001	1			T2	11		T3	92		T7	25
valid_sources[0x06]	30681	1			T2	137		T3	135		T7	32
valid_sources[0x07]	27886	1			T2	67		T3	126		T7	29
valid_sources[0x08]	29810	1			T2	45		T3	113		T7	5
valid_sources[0x09]	30700	1			T2	45		T3	123		T7	2
valid_sources[0x0a]	27546	1			T2	36		T3	115		T7	14
valid_sources[0x0b]	49916	1			T2	39		T3	124		T7	8
valid_sources[0x0c]	30511	1			T2	89		T3	132		T7	3
valid_sources[0x0d]	27471	1			T2	8		T3	121		T7	17
valid_sources[0x0e]	31287	1			T2	76		T3	148		T7	41
valid_sources[0x0f]	31388	1			T2	40		T3	125		T7	56
valid_sources[0x10]	25967	1			T2	84		T3	145		T7	32
valid_sources[0x11]	29852	1			T2	47		T3	143		T7	47
valid_sources[0x12]	30086	1			T2	37		T3	143		T7	5
valid_sources[0x13]	32406	1			T2	34		T3	155		T7	11
valid_sources[0x14]	28373	1			T2	62		T3	114		T7	27
valid_sources[0x15]	24783	1			T2	34		T3	90		T7	20
valid_sources[0x16]	28247	1			T2	10		T3	136		T7	2
valid_sources[0x17]	27223	1			T2	25		T3	110		T7	22
valid_sources[0x18]	29339	1			T2	54		T3	86		T7	51
valid_sources[0x19]	29085	1			T2	28		T3	146		T7	8
valid_sources[0x1a]	29045	1			T2	95		T3	118		T7	36
valid_sources[0x1b]	29170	1			T2	25		T3	129		T7	52
valid_sources[0x1c]	27437	1			T3	154		T7	14		T8	3
valid_sources[0x1d]	30371	1			T2	113		T3	106		T7	3
valid_sources[0x1e]	30205	1			T2	25		T3	140		T7	102
valid_sources[0x1f]	25590	1			T2	57		T3	155		T5	1
valid_sources[0x20]	29092	1			T2	41		T3	98		T7	20
valid_sources[0x21]	27893	1			T2	38		T3	110		T7	18
valid_sources[0x22]	47793	1			T2	30		T3	87		T8	1
valid_sources[0x23]	28907	1			T2	6		T3	136		T7	62
valid_sources[0x24]	31854	1			T2	15		T3	128		T7	64
valid_sources[0x25]	40681	1			T2	86		T3	140		T7	28
valid_sources[0x26]	27290	1			T2	4		T3	114		T7	61
valid_sources[0x27]	27982	1			T2	36		T3	118		T7	16
valid_sources[0x28]	34660	1			T2	56		T3	166		T7	9
valid_sources[0x29]	28241	1			T2	68		T3	119		T7	32
valid_sources[0x2a]	28089	1			T2	25		T3	135		T7	25
valid_sources[0x2b]	28268	1			T2	88		T3	140		T5	2
valid_sources[0x2c]	33142	1			T2	26		T3	134		T7	87
valid_sources[0x2d]	28997	1			T2	38		T3	161		T7	3
valid_sources[0x2e]	28750	1			T2	33		T3	155		T7	10
valid_sources[0x2f]	26513	1			T2	22		T3	135		T7	25
valid_sources[0x30]	30386	1			T2	47		T3	123		T7	14
valid_sources[0x31]	28444	1			T2	20		T3	120		T7	5
valid_sources[0x32]	28274	1			T2	77		T3	150		T7	3
valid_sources[0x33]	35764	1			T2	15		T3	123		T7	8
valid_sources[0x34]	25748	1			T2	18		T3	137		T7	53
valid_sources[0x35]	33709	1			T2	29		T3	128		T7	9
valid_sources[0x36]	27676	1			T2	30		T3	105		T7	49
valid_sources[0x37]	27545	1			T2	34		T3	114		T7	20
valid_sources[0x38]	33380	1			T2	39		T3	163		T7	48
valid_sources[0x39]	29157	1			T2	13		T3	123		T7	34
valid_sources[0x3a]	28045	1			T2	42		T3	117		T7	55
valid_sources[0x3b]	28309	1			T2	28		T3	145		T7	28
valid_sources[0x3c]	32443	1			T2	62		T3	107		T7	1
valid_sources[0x3d]	29612	1			T2	69		T3	127		T7	1
valid_sources[0x3e]	29894	1			T2	68		T3	146		T6	451
valid_sources[0x3f]	28667	1			T2	8		T3	137		T7	12
valid_sources[0x40]	26012	1			T2	30		T3	100		T7	27
valid_sources[0x41]	28686	1			T2	29		T3	147		T7	7
valid_sources[0x42]	33637	1			T2	36		T3	142		T7	7
valid_sources[0x43]	27761	1			T2	47		T3	138		T7	27
valid_sources[0x44]	28730	1			T2	62		T3	145		T7	3
valid_sources[0x45]	25655	1			T2	15		T3	112		T7	3
valid_sources[0x46]	26786	1			T2	27		T3	133		T7	24
valid_sources[0x47]	30288	1			T2	26		T3	148		T7	23
valid_sources[0x48]	24618	1			T2	20		T3	153		T7	37
valid_sources[0x49]	27566	1			T2	13		T3	148		T7	49
valid_sources[0x4a]	29942	1			T2	40		T3	180		T7	42
valid_sources[0x4b]	27791	1			T2	52		T3	152		T7	41
valid_sources[0x4c]	27002	1			T2	60		T3	123		T7	26
valid_sources[0x4d]	29697	1			T2	19		T3	137		T7	28
valid_sources[0x4e]	29297	1			T2	56		T3	141		T8	1
valid_sources[0x4f]	29418	1			T2	22		T3	170		T7	26
valid_sources[0x50]	31741	1			T2	54		T3	101		T7	60
valid_sources[0x51]	26007	1			T2	23		T3	139		T7	31
valid_sources[0x52]	28094	1			T2	42		T3	129		T7	2
valid_sources[0x53]	28379	1			T2	11		T3	115		T7	16
valid_sources[0x54]	28933	1			T2	36		T3	118		T7	51
valid_sources[0x55]	28080	1			T2	18		T3	173		T7	1
valid_sources[0x56]	27839	1			T2	35		T3	167		T7	15
valid_sources[0x57]	30428	1			T2	81		T3	111		T7	9
valid_sources[0x58]	29685	1			T2	20		T3	163		T7	33
valid_sources[0x59]	27968	1			T2	3		T3	114		T7	15
valid_sources[0x5a]	27736	1			T2	19		T3	125		T7	43
valid_sources[0x5b]	30964	1			T2	7		T3	135		T7	88
valid_sources[0x5c]	30608	1			T2	21		T3	136		T7	57
valid_sources[0x5d]	28401	1			T2	3		T3	155		T9	14
valid_sources[0x5e]	27784	1			T2	52		T3	128		T5	2
valid_sources[0x5f]	26777	1			T2	81		T3	136		T6	451
valid_sources[0x60]	28220	1			T2	103		T3	156		T5	1
valid_sources[0x61]	26719	1			T2	16		T3	109		T7	1
valid_sources[0x62]	30175	1			T2	18		T3	140		T7	17
valid_sources[0x63]	28603	1			T2	24		T3	141		T5	2
valid_sources[0x64]	29548	1			T2	2		T3	142		T7	5
valid_sources[0x65]	29152	1			T2	22		T3	164		T7	23
valid_sources[0x66]	27721	1			T2	11		T3	133		T7	49
valid_sources[0x67]	36301	1			T2	36		T3	101		T7	40
valid_sources[0x68]	29716	1			T2	65		T3	186		T7	30
valid_sources[0x69]	28594	1			T2	31		T3	110		T7	36
valid_sources[0x6a]	30523	1			T2	62		T3	157		T7	11
valid_sources[0x6b]	27621	1			T2	51		T3	107		T7	67
valid_sources[0x6c]	29515	1			T2	42		T3	153		T7	38
valid_sources[0x6d]	29710	1			T2	57		T3	110		T7	32
valid_sources[0x6e]	26837	1			T2	14		T3	100		T7	30
valid_sources[0x6f]	29267	1			T2	33		T3	131		T7	18
valid_sources[0x70]	34896	1			T2	80		T3	122		T7	55
valid_sources[0x71]	40205	1			T2	8		T3	136		T7	9
valid_sources[0x72]	27874	1			T2	18		T3	149		T7	12
valid_sources[0x73]	29504	1			T2	38		T3	127		T7	18
valid_sources[0x74]	28729	1			T2	30		T3	132		T7	26
valid_sources[0x75]	30318	1			T2	28		T3	137		T7	11
valid_sources[0x76]	27263	1			T2	34		T3	124		T7	30
valid_sources[0x77]	28254	1			T2	66		T3	168		T7	10
valid_sources[0x78]	27815	1			T2	44		T3	106		T7	10
valid_sources[0x79]	28574	1			T2	96		T3	120		T7	14
valid_sources[0x7a]	27749	1			T2	24		T3	91		T7	32
valid_sources[0x7b]	29917	1			T2	31		T3	159		T7	36
valid_sources[0x7c]	29241	1			T2	72		T3	137		T7	31
valid_sources[0x7d]	28475	1			T2	39		T3	167		T7	7
valid_sources[0x7e]	25903	1			T2	87		T3	136		T7	39
valid_sources[0x7f]	28332	1			T2	81		T3	147		T4	1025
valid_sources[0x80]	31200	1			T2	36		T3	147		T7	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1009736

1

T1

4

T2

2020

T3

2505

values[0x0]

all_enables

biggest_size

1530370

1

T1

451

T2

3123

T3

6856

values[0x1]

all_enables

biggest_size

1508197

1

T1

439

T2

3023

T3

6569