Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3621506

1

T1

2

T2

1509

T3

17861

full_word

4049444

1

T1

894

T2

8166

T3

15930

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7670600	1			T1	896		T2	9675		T3	33791
auto[TlIntgErrCmd]	136	1			T97	11		T98	9		T99	7
auto[TlIntgErrData]	102	1			T97	12		T98	6		T99	4
auto[TlIntgErrBoth]	112	1			T97	7		T98	5		T99	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4269906

1

T1

4

T2

3504

T3

17788

auto[1]

3401044

1

T1

892

T2

6171

T3

16003

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3259764	1			T2	1484		T3	15283		T4	66
auto[TlIntgErrNone]	partial	auto[1]	361425	1			T1	2		T2	25		T3	2578
auto[TlIntgErrNone]	full_word	auto[0]	1009996	1			T1	4		T2	2020		T3	2505
auto[TlIntgErrNone]	full_word	auto[1]	3039415	1			T1	890		T2	6146		T3	13425
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T97	3		T98	1		T173	3
auto[TlIntgErrCmd]	partial	auto[1]	71	1			T97	6		T98	8		T99	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T97	1		T176	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	13	1			T97	1		T99	3		T171	2
auto[TlIntgErrData]	partial	auto[0]	45	1			T97	4		T98	3		T173	1
auto[TlIntgErrData]	partial	auto[1]	46	1			T97	7		T98	2		T99	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T97	1		T98	1		T99	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T173	1		T174	1		T177	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T97	3		T98	2		T99	1
auto[TlIntgErrBoth]	partial	auto[1]	66	1			T97	3		T98	3		T99	8
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T97	1		T178	2		T108	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T174	1		T175	1		T178	1