Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412910339	2582661	0	0
DepthKnown_A	412910339	412785456	0	0
RvalidKnown_A	412910339	412785456	0	0
WreadyKnown_A	412910339	412785456	0	0
gen_passthru_fifo.paramCheckPass	1080	1080	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	2582661	0	0
T1	166631	1663	0	0
T2	208991	8332	0	0
T3	132950	6654	0	0
T4	4518	832	0	0
T5	1491	0	0	0
T6	275880	1663	0	0
T7	171603	9979	0	0
T8	470582	832	0	0
T9	522388	832	0	0
T10	161686	1663	0	0
T11	0	4410	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	412785456	0	0
T1	166631	166564	0	0
T2	208991	208985	0	0
T3	132950	132926	0	0
T4	4518	4449	0	0
T5	1491	1433	0	0
T6	275880	275801	0	0
T7	171603	171517	0	0
T8	470582	470492	0	0
T9	522388	522300	0	0
T10	161686	161602	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	412785456	0	0
T1	166631	166564	0	0
T2	208991	208985	0	0
T3	132950	132926	0	0
T4	4518	4449	0	0
T5	1491	1433	0	0
T6	275880	275801	0	0
T7	171603	171517	0	0
T8	470582	470492	0	0
T9	522388	522300	0	0
T10	161686	161602	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	412785456	0	0
T1	166631	166564	0	0
T2	208991	208985	0	0
T3	132950	132926	0	0
T4	4518	4449	0	0
T5	1491	1433	0	0
T6	275880	275801	0	0
T7	171603	171517	0	0
T8	470582	470492	0	0
T9	522388	522300	0	0
T10	161686	161602	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1080	1080	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412910339	2755877	0	0
DepthKnown_A	412910339	412785456	0	0
RvalidKnown_A	412910339	412785456	0	0
WreadyKnown_A	412910339	412785456	0	0
gen_passthru_fifo.paramCheckPass	1080	1080	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	2755877	0	0
T1	166631	832	0	0
T2	208991	17632	0	0
T3	132950	12008	0	0
T4	4518	832	0	0
T5	1491	0	0	0
T6	275880	832	0	0
T7	171603	5824	0	0
T8	470582	2621	0	0
T9	522388	3665	0	0
T10	161686	832	0	0
T11	0	4364	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	412785456	0	0
T1	166631	166564	0	0
T2	208991	208985	0	0
T3	132950	132926	0	0
T4	4518	4449	0	0
T5	1491	1433	0	0
T6	275880	275801	0	0
T7	171603	171517	0	0
T8	470582	470492	0	0
T9	522388	522300	0	0
T10	161686	161602	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	412785456	0	0
T1	166631	166564	0	0
T2	208991	208985	0	0
T3	132950	132926	0	0
T4	4518	4449	0	0
T5	1491	1433	0	0
T6	275880	275801	0	0
T7	171603	171517	0	0
T8	470582	470492	0	0
T9	522388	522300	0	0
T10	161686	161602	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	412785456	0	0
T1	166631	166564	0	0
T2	208991	208985	0	0
T3	132950	132926	0	0
T4	4518	4449	0	0
T5	1491	1433	0	0
T6	275880	275801	0	0
T7	171603	171517	0	0
T8	470582	470492	0	0
T9	522388	522300	0	0
T10	161686	161602	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1080	1080	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412910339	191412	0	0
DepthKnown_A	412910339	412785456	0	0
RvalidKnown_A	412910339	412785456	0	0
WreadyKnown_A	412910339	412785456	0	0
gen_passthru_fifo.paramCheckPass	1080	1080	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	191412	0	0
T2	208991	514	0	0
T3	132950	1525	0	0
T4	4518	0	0	0
T5	1491	0	0	0
T6	275880	0	0	0
T7	171603	128	0	0
T8	470582	0	0	0
T9	522388	0	0	0
T10	161686	0	0	0
T13	0	18	0	0
T23	1234	0	0	0
T27	0	852	0	0
T28	0	404	0	0
T29	0	1113	0	0
T30	0	1140	0	0
T31	0	1300	0	0
T33	0	65	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	412785456	0	0
T1	166631	166564	0	0
T2	208991	208985	0	0
T3	132950	132926	0	0
T4	4518	4449	0	0
T5	1491	1433	0	0
T6	275880	275801	0	0
T7	171603	171517	0	0
T8	470582	470492	0	0
T9	522388	522300	0	0
T10	161686	161602	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	412785456	0	0
T1	166631	166564	0	0
T2	208991	208985	0	0
T3	132950	132926	0	0
T4	4518	4449	0	0
T5	1491	1433	0	0
T6	275880	275801	0	0
T7	171603	171517	0	0
T8	470582	470492	0	0
T9	522388	522300	0	0
T10	161686	161602	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	412785456	0	0
T1	166631	166564	0	0
T2	208991	208985	0	0
T3	132950	132926	0	0
T4	4518	4449	0	0
T5	1491	1433	0	0
T6	275880	275801	0	0
T7	171603	171517	0	0
T8	470582	470492	0	0
T9	522388	522300	0	0
T10	161686	161602	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1080	1080	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412910339	434502	0	0
DepthKnown_A	412910339	412785456	0	0
RvalidKnown_A	412910339	412785456	0	0
WreadyKnown_A	412910339	412785456	0	0
gen_passthru_fifo.paramCheckPass	1080	1080	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	434502	0	0
T2	208991	2420	0	0
T3	132950	4826	0	0
T4	4518	0	0	0
T5	1491	0	0	0
T6	275880	0	0	0
T7	171603	128	0	0
T8	470582	0	0	0
T9	522388	0	0	0
T10	161686	0	0	0
T13	0	18	0	0
T23	1234	0	0	0
T27	0	852	0	0
T28	0	404	0	0
T29	0	1113	0	0
T30	0	5237	0	0
T31	0	1300	0	0
T33	0	279	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	412785456	0	0
T1	166631	166564	0	0
T2	208991	208985	0	0
T3	132950	132926	0	0
T4	4518	4449	0	0
T5	1491	1433	0	0
T6	275880	275801	0	0
T7	171603	171517	0	0
T8	470582	470492	0	0
T9	522388	522300	0	0
T10	161686	161602	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	412785456	0	0
T1	166631	166564	0	0
T2	208991	208985	0	0
T3	132950	132926	0	0
T4	4518	4449	0	0
T5	1491	1433	0	0
T6	275880	275801	0	0
T7	171603	171517	0	0
T8	470582	470492	0	0
T9	522388	522300	0	0
T10	161686	161602	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	412785456	0	0
T1	166631	166564	0	0
T2	208991	208985	0	0
T3	132950	132926	0	0
T4	4518	4449	0	0
T5	1491	1433	0	0
T6	275880	275801	0	0
T7	171603	171517	0	0
T8	470582	470492	0	0
T9	522388	522300	0	0
T10	161686	161602	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1080	1080	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412910339	6180531	0	0
DepthKnown_A	412910339	412785456	0	0
RvalidKnown_A	412910339	412785456	0	0
WreadyKnown_A	412910339	412785456	0	0
gen_passthru_fifo.paramCheckPass	1080	1080	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	6180531	0	0
T1	166631	64	0	0
T2	208991	3377	0	0
T3	132950	28706	0	0
T4	4518	193	0	0
T5	1491	12	0	0
T6	275880	70	0	0
T7	171603	677	0	0
T8	470582	73	0	0
T9	522388	841	0	0
T10	161686	7378	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	412785456	0	0
T1	166631	166564	0	0
T2	208991	208985	0	0
T3	132950	132926	0	0
T4	4518	4449	0	0
T5	1491	1433	0	0
T6	275880	275801	0	0
T7	171603	171517	0	0
T8	470582	470492	0	0
T9	522388	522300	0	0
T10	161686	161602	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	412785456	0	0
T1	166631	166564	0	0
T2	208991	208985	0	0
T3	132950	132926	0	0
T4	4518	4449	0	0
T5	1491	1433	0	0
T6	275880	275801	0	0
T7	171603	171517	0	0
T8	470582	470492	0	0
T9	522388	522300	0	0
T10	161686	161602	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	412785456	0	0
T1	166631	166564	0	0
T2	208991	208985	0	0
T3	132950	132926	0	0
T4	4518	4449	0	0
T5	1491	1433	0	0
T6	275880	275801	0	0
T7	171603	171517	0	0
T8	470582	470492	0	0
T9	522388	522300	0	0
T10	161686	161602	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1080	1080	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412910339	12563473	0	0
DepthKnown_A	412910339	412785456	0	0
RvalidKnown_A	412910339	412785456	0	0
WreadyKnown_A	412910339	412785456	0	0
gen_passthru_fifo.paramCheckPass	1080	1080	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	12563473	0	0
T1	166631	64	0	0
T2	208991	14664	0	0
T3	132950	84075	0	0
T4	4518	193	0	0
T5	1491	12	0	0
T6	275880	216	0	0
T7	171603	676	0	0
T8	470582	223	0	0
T9	522388	3765	0	0
T10	161686	32127	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	412785456	0	0
T1	166631	166564	0	0
T2	208991	208985	0	0
T3	132950	132926	0	0
T4	4518	4449	0	0
T5	1491	1433	0	0
T6	275880	275801	0	0
T7	171603	171517	0	0
T8	470582	470492	0	0
T9	522388	522300	0	0
T10	161686	161602	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	412785456	0	0
T1	166631	166564	0	0
T2	208991	208985	0	0
T3	132950	132926	0	0
T4	4518	4449	0	0
T5	1491	1433	0	0
T6	275880	275801	0	0
T7	171603	171517	0	0
T8	470582	470492	0	0
T9	522388	522300	0	0
T10	161686	161602	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412910339	412785456	0	0
T1	166631	166564	0	0
T2	208991	208985	0	0
T3	132950	132926	0	0
T4	4518	4449	0	0
T5	1491	1433	0	0
T6	275880	275801	0	0
T7	171603	171517	0	0
T8	470582	470492	0	0
T9	522388	522300	0	0
T10	161686	161602	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1080	1080	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0