Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T13,T27
1	0	Covered	T3,T13,T26

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T13
1	0	Unreachable
1	1	Covered	T3,T13,T26

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	680701681	544134527	0	0
CheckNGreaterZero_A	2715	2715	0	0
GntImpliesReady_A	680701681	3561500	0	0
GntImpliesValid_A	680701681	3561500	0	0
GrantKnown_A	680701681	544134527	0	0
IdxKnown_A	680701681	544134527	0	0
IndexIsCorrect_A	680701681	3561500	0	0
LockArbDecision_A	680701681	0	0	0
NoReadyValidNoGrant_A	680701681	0	0	0
ReadyAndValidImplyGrant_A	680701681	3561500	0	0
ReqAndReadyImplyGrant_A	680701681	3561500	0	0
ReqImpliesValid_A	680701681	3561500	0	0
ReqStaysHighUntilGranted0_M	680701681	0	0	0
RoundRobin_A	680701681	11	0	905
ValidKnown_A	680701681	544134527	0	0
gen_data_port_assertion.DataFlow_A	680701681	3561500	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680701681	544134527	0	0
T1	221305	221048	0	0
T2	717163	716038	0	0
T3	1052118	579327	0	0
T4	8646	6513	0	0
T5	1491	1433	0	0
T6	455474	365219	0	0
T7	1251669	711235	0	0
T8	602758	536230	0	0
T9	776600	649276	0	0
T10	214638	188078	0	0
T11	136816	68314	0	0
T12	0	648	0	0
T13	0	2400	0	0
T25	0	59168	0	0
T26	0	680	0	0
T27	0	170272	0	0
T28	0	19600	0	0
T29	0	544560	0	0
T30	0	127824	0	0
T31	0	63936	0	0
T37	82749	0	0	0
T42	26424	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2715	2715	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680701681	3561500	0	0
T1	166631	832	0	0
T2	717163	12806	0	0
T3	1052118	20867	0	0
T4	8646	832	0	0
T5	1491	0	0	0
T6	455474	832	0	0
T7	1251669	8543	0	0
T8	602758	832	0	0
T9	776600	832	0	0
T10	214638	832	0	0
T11	136816	2624	0	0
T13	0	119	0	0
T14	0	4085	0	0
T26	0	19	0	0
T27	0	4487	0	0
T28	0	5285	0	0
T29	0	11456	0	0
T30	0	5920	0	0
T31	0	12892	0	0
T33	0	263	0	0
T37	165498	0	0	0
T42	26424	0	0	0
T43	0	9858	0	0
T44	0	4322	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680701681	3561500	0	0
T1	166631	832	0	0
T2	717163	12806	0	0
T3	1052118	20867	0	0
T4	8646	832	0	0
T5	1491	0	0	0
T6	455474	832	0	0
T7	1251669	8543	0	0
T8	602758	832	0	0
T9	776600	832	0	0
T10	214638	832	0	0
T11	136816	2624	0	0
T13	0	119	0	0
T14	0	4085	0	0
T26	0	19	0	0
T27	0	4487	0	0
T28	0	5285	0	0
T29	0	11456	0	0
T30	0	5920	0	0
T31	0	12892	0	0
T33	0	263	0	0
T37	165498	0	0	0
T42	26424	0	0	0
T43	0	9858	0	0
T44	0	4322	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680701681	544134527	0	0
T1	221305	221048	0	0
T2	717163	716038	0	0
T3	1052118	579327	0	0
T4	8646	6513	0	0
T5	1491	1433	0	0
T6	455474	365219	0	0
T7	1251669	711235	0	0
T8	602758	536230	0	0
T9	776600	649276	0	0
T10	214638	188078	0	0
T11	136816	68314	0	0
T12	0	648	0	0
T13	0	2400	0	0
T25	0	59168	0	0
T26	0	680	0	0
T27	0	170272	0	0
T28	0	19600	0	0
T29	0	544560	0	0
T30	0	127824	0	0
T31	0	63936	0	0
T37	82749	0	0	0
T42	26424	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680701681	544134527	0	0
T1	221305	221048	0	0
T2	717163	716038	0	0
T3	1052118	579327	0	0
T4	8646	6513	0	0
T5	1491	1433	0	0
T6	455474	365219	0	0
T7	1251669	711235	0	0
T8	602758	536230	0	0
T9	776600	649276	0	0
T10	214638	188078	0	0
T11	136816	68314	0	0
T12	0	648	0	0
T13	0	2400	0	0
T25	0	59168	0	0
T26	0	680	0	0
T27	0	170272	0	0
T28	0	19600	0	0
T29	0	544560	0	0
T30	0	127824	0	0
T31	0	63936	0	0
T37	82749	0	0	0
T42	26424	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680701681	3561500	0	0
T1	166631	832	0	0
T2	717163	12806	0	0
T3	1052118	20867	0	0
T4	8646	832	0	0
T5	1491	0	0	0
T6	455474	832	0	0
T7	1251669	8543	0	0
T8	602758	832	0	0
T9	776600	832	0	0
T10	214638	832	0	0
T11	136816	2624	0	0
T13	0	119	0	0
T14	0	4085	0	0
T26	0	19	0	0
T27	0	4487	0	0
T28	0	5285	0	0
T29	0	11456	0	0
T30	0	5920	0	0
T31	0	12892	0	0
T33	0	263	0	0
T37	165498	0	0	0
T42	26424	0	0	0
T43	0	9858	0	0
T44	0	4322	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680701681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680701681	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680701681	3561500	0	0
T1	166631	832	0	0
T2	717163	12806	0	0
T3	1052118	20867	0	0
T4	8646	832	0	0
T5	1491	0	0	0
T6	455474	832	0	0
T7	1251669	8543	0	0
T8	602758	832	0	0
T9	776600	832	0	0
T10	214638	832	0	0
T11	136816	2624	0	0
T13	0	119	0	0
T14	0	4085	0	0
T26	0	19	0	0
T27	0	4487	0	0
T28	0	5285	0	0
T29	0	11456	0	0
T30	0	5920	0	0
T31	0	12892	0	0
T33	0	263	0	0
T37	165498	0	0	0
T42	26424	0	0	0
T43	0	9858	0	0
T44	0	4322	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680701681	3561500	0	0
T1	166631	832	0	0
T2	717163	12806	0	0
T3	1052118	20867	0	0
T4	8646	832	0	0
T5	1491	0	0	0
T6	455474	832	0	0
T7	1251669	8543	0	0
T8	602758	832	0	0
T9	776600	832	0	0
T10	214638	832	0	0
T11	136816	2624	0	0
T13	0	119	0	0
T14	0	4085	0	0
T26	0	19	0	0
T27	0	4487	0	0
T28	0	5285	0	0
T29	0	11456	0	0
T30	0	5920	0	0
T31	0	12892	0	0
T33	0	263	0	0
T37	165498	0	0	0
T42	26424	0	0	0
T43	0	9858	0	0
T44	0	4322	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680701681	3561500	0	0
T1	166631	832	0	0
T2	717163	12806	0	0
T3	1052118	20867	0	0
T4	8646	832	0	0
T5	1491	0	0	0
T6	455474	832	0	0
T7	1251669	8543	0	0
T8	602758	832	0	0
T9	776600	832	0	0
T10	214638	832	0	0
T11	136816	2624	0	0
T13	0	119	0	0
T14	0	4085	0	0
T26	0	19	0	0
T27	0	4487	0	0
T28	0	5285	0	0
T29	0	11456	0	0
T30	0	5920	0	0
T31	0	12892	0	0
T33	0	263	0	0
T37	165498	0	0	0
T42	26424	0	0	0
T43	0	9858	0	0
T44	0	4322	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	680701681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680701681	11	0	905
T18	528192	1	0	1
T19	160764	0	0	1
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	272221	0	0	1
T54	332158	0	0	1
T55	275264	0	0	1
T56	887596	0	0	1
T57	916	0	0	1
T58	48313	0	0	1
T59	100241	0	0	1
T60	26594	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680701681	544134527	0	0
T1	221305	221048	0	0
T2	717163	716038	0	0
T3	1052118	579327	0	0
T4	8646	6513	0	0
T5	1491	1433	0	0
T6	455474	365219	0	0
T7	1251669	711235	0	0
T8	602758	536230	0	0
T9	776600	649276	0	0
T10	214638	188078	0	0
T11	136816	68314	0	0
T12	0	648	0	0
T13	0	2400	0	0
T25	0	59168	0	0
T26	0	680	0	0
T27	0	170272	0	0
T28	0	19600	0	0
T29	0	544560	0	0
T30	0	127824	0	0
T31	0	63936	0	0
T37	82749	0	0	0
T42	26424	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680701681	3561500	0	0
T1	166631	832	0	0
T2	717163	12806	0	0
T3	1052118	20867	0	0
T4	8646	832	0	0
T5	1491	0	0	0
T6	455474	832	0	0
T7	1251669	8543	0	0
T8	602758	832	0	0
T9	776600	832	0	0
T10	214638	832	0	0
T11	136816	2624	0	0
T13	0	119	0	0
T14	0	4085	0	0
T26	0	19	0	0
T27	0	4487	0	0
T28	0	5285	0	0
T29	0	11456	0	0
T30	0	5920	0	0
T31	0	12892	0	0
T33	0	263	0	0
T37	165498	0	0	0
T42	26424	0	0	0
T43	0	9858	0	0
T44	0	4322	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T13,T27
1	0	Covered	T3,T13,T26

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T13
1	0	Unreachable
1	1	Covered	T3,T13,T26

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T13,T26
0	0	1	Unreachable
0	0	0	Covered	T3,T12,T13

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T13,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T13,T26
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	135116846	30790534	0	0
CheckNGreaterZero_A	905	905	0	0
GntImpliesReady_A	135116846	695827	0	0
GntImpliesValid_A	135116846	695827	0	0
GrantKnown_A	135116846	30790534	0	0
IdxKnown_A	135116846	30790534	0	0
IndexIsCorrect_A	135116846	695827	0	0
LockArbDecision_A	135116846	0	0	0
NoReadyValidNoGrant_A	135116846	0	0	0
ReadyAndValidImplyGrant_A	135116846	695827	0	0
ReqAndReadyImplyGrant_A	135116846	695827	0	0
ReqImpliesValid_A	135116846	695827	0	0
ReqStaysHighUntilGranted0_M	135116846	0	0	0
RoundRobin_A	135116846	0	0	0
ValidKnown_A	135116846	30790534	0	0
gen_data_port_assertion.DataFlow_A	135116846	695827	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	30790534	0	0
T3	459584	247632	0	0
T4	2064	0	0	0
T6	89797	0	0	0
T7	540033	0	0	0
T8	66088	0	0	0
T9	127106	0	0	0
T10	26476	0	0	0
T11	68408	0	0	0
T12	0	648	0	0
T13	0	2400	0	0
T25	0	59168	0	0
T26	0	680	0	0
T27	0	170272	0	0
T28	0	19600	0	0
T29	0	544560	0	0
T30	0	127824	0	0
T31	0	63936	0	0
T37	82749	0	0	0
T42	26424	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	695827	0	0
T3	459584	8642	0	0
T4	2064	0	0	0
T6	89797	0	0	0
T7	540033	0	0	0
T8	66088	0	0	0
T9	127106	0	0	0
T10	26476	0	0	0
T11	68408	0	0	0
T13	0	119	0	0
T26	0	19	0	0
T27	0	4487	0	0
T28	0	174	0	0
T29	0	6038	0	0
T30	0	5920	0	0
T31	0	2646	0	0
T37	82749	0	0	0
T42	26424	0	0	0
T43	0	573	0	0
T44	0	4316	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	695827	0	0
T3	459584	8642	0	0
T4	2064	0	0	0
T6	89797	0	0	0
T7	540033	0	0	0
T8	66088	0	0	0
T9	127106	0	0	0
T10	26476	0	0	0
T11	68408	0	0	0
T13	0	119	0	0
T26	0	19	0	0
T27	0	4487	0	0
T28	0	174	0	0
T29	0	6038	0	0
T30	0	5920	0	0
T31	0	2646	0	0
T37	82749	0	0	0
T42	26424	0	0	0
T43	0	573	0	0
T44	0	4316	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	30790534	0	0
T3	459584	247632	0	0
T4	2064	0	0	0
T6	89797	0	0	0
T7	540033	0	0	0
T8	66088	0	0	0
T9	127106	0	0	0
T10	26476	0	0	0
T11	68408	0	0	0
T12	0	648	0	0
T13	0	2400	0	0
T25	0	59168	0	0
T26	0	680	0	0
T27	0	170272	0	0
T28	0	19600	0	0
T29	0	544560	0	0
T30	0	127824	0	0
T31	0	63936	0	0
T37	82749	0	0	0
T42	26424	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	30790534	0	0
T3	459584	247632	0	0
T4	2064	0	0	0
T6	89797	0	0	0
T7	540033	0	0	0
T8	66088	0	0	0
T9	127106	0	0	0
T10	26476	0	0	0
T11	68408	0	0	0
T12	0	648	0	0
T13	0	2400	0	0
T25	0	59168	0	0
T26	0	680	0	0
T27	0	170272	0	0
T28	0	19600	0	0
T29	0	544560	0	0
T30	0	127824	0	0
T31	0	63936	0	0
T37	82749	0	0	0
T42	26424	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	695827	0	0
T3	459584	8642	0	0
T4	2064	0	0	0
T6	89797	0	0	0
T7	540033	0	0	0
T8	66088	0	0	0
T9	127106	0	0	0
T10	26476	0	0	0
T11	68408	0	0	0
T13	0	119	0	0
T26	0	19	0	0
T27	0	4487	0	0
T28	0	174	0	0
T29	0	6038	0	0
T30	0	5920	0	0
T31	0	2646	0	0
T37	82749	0	0	0
T42	26424	0	0	0
T43	0	573	0	0
T44	0	4316	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	695827	0	0
T3	459584	8642	0	0
T4	2064	0	0	0
T6	89797	0	0	0
T7	540033	0	0	0
T8	66088	0	0	0
T9	127106	0	0	0
T10	26476	0	0	0
T11	68408	0	0	0
T13	0	119	0	0
T26	0	19	0	0
T27	0	4487	0	0
T28	0	174	0	0
T29	0	6038	0	0
T30	0	5920	0	0
T31	0	2646	0	0
T37	82749	0	0	0
T42	26424	0	0	0
T43	0	573	0	0
T44	0	4316	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	695827	0	0
T3	459584	8642	0	0
T4	2064	0	0	0
T6	89797	0	0	0
T7	540033	0	0	0
T8	66088	0	0	0
T9	127106	0	0	0
T10	26476	0	0	0
T11	68408	0	0	0
T13	0	119	0	0
T26	0	19	0	0
T27	0	4487	0	0
T28	0	174	0	0
T29	0	6038	0	0
T30	0	5920	0	0
T31	0	2646	0	0
T37	82749	0	0	0
T42	26424	0	0	0
T43	0	573	0	0
T44	0	4316	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	695827	0	0
T3	459584	8642	0	0
T4	2064	0	0	0
T6	89797	0	0	0
T7	540033	0	0	0
T8	66088	0	0	0
T9	127106	0	0	0
T10	26476	0	0	0
T11	68408	0	0	0
T13	0	119	0	0
T26	0	19	0	0
T27	0	4487	0	0
T28	0	174	0	0
T29	0	6038	0	0
T30	0	5920	0	0
T31	0	2646	0	0
T37	82749	0	0	0
T42	26424	0	0	0
T43	0	573	0	0
T44	0	4316	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	30790534	0	0
T3	459584	247632	0	0
T4	2064	0	0	0
T6	89797	0	0	0
T7	540033	0	0	0
T8	66088	0	0	0
T9	127106	0	0	0
T10	26476	0	0	0
T11	68408	0	0	0
T12	0	648	0	0
T13	0	2400	0	0
T25	0	59168	0	0
T26	0	680	0	0
T27	0	170272	0	0
T28	0	19600	0	0
T29	0	544560	0	0
T30	0	127824	0	0
T31	0	63936	0	0
T37	82749	0	0	0
T42	26424	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	695827	0	0
T3	459584	8642	0	0
T4	2064	0	0	0
T6	89797	0	0	0
T7	540033	0	0	0
T8	66088	0	0	0
T9	127106	0	0	0
T10	26476	0	0	0
T11	68408	0	0	0
T13	0	119	0	0
T26	0	19	0	0
T27	0	4487	0	0
T28	0	174	0	0
T29	0	6038	0	0
T30	0	5920	0	0
T31	0	2646	0	0
T37	82749	0	0	0
T42	26424	0	0	0
T43	0	573	0	0
T44	0	4316	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	135116846	102960114	0	0
CheckNGreaterZero_A	905	905	0	0
GntImpliesReady_A	135116846	770208	0	0
GntImpliesValid_A	135116846	770208	0	0
GrantKnown_A	135116846	102960114	0	0
IdxKnown_A	135116846	102960114	0	0
IndexIsCorrect_A	135116846	770208	0	0
LockArbDecision_A	135116846	0	0	0
NoReadyValidNoGrant_A	135116846	0	0	0
ReadyAndValidImplyGrant_A	135116846	770208	0	0
ReqAndReadyImplyGrant_A	135116846	770208	0	0
ReqImpliesValid_A	135116846	770208	0	0
ReqStaysHighUntilGranted0_M	135116846	0	0	0
RoundRobin_A	135116846	0	0	0
ValidKnown_A	135116846	102960114	0	0
gen_data_port_assertion.DataFlow_A	135116846	770208	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	102960114	0	0
T1	54674	54484	0	0
T2	508172	507053	0	0
T3	459584	198769	0	0
T4	2064	2064	0	0
T6	89797	89418	0	0
T7	540033	539718	0	0
T8	66088	65738	0	0
T9	127106	126976	0	0
T10	26476	26476	0	0
T11	68408	68314	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	770208	0	0
T2	508172	6447	0	0
T3	459584	2726	0	0
T4	2064	0	0	0
T6	89797	0	0	0
T7	540033	2588	0	0
T8	66088	0	0	0
T9	127106	0	0	0
T10	26476	0	0	0
T11	68408	0	0	0
T14	0	4085	0	0
T28	0	5111	0	0
T29	0	5418	0	0
T31	0	10246	0	0
T33	0	263	0	0
T37	82749	0	0	0
T43	0	9285	0	0
T44	0	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	770208	0	0
T2	508172	6447	0	0
T3	459584	2726	0	0
T4	2064	0	0	0
T6	89797	0	0	0
T7	540033	2588	0	0
T8	66088	0	0	0
T9	127106	0	0	0
T10	26476	0	0	0
T11	68408	0	0	0
T14	0	4085	0	0
T28	0	5111	0	0
T29	0	5418	0	0
T31	0	10246	0	0
T33	0	263	0	0
T37	82749	0	0	0
T43	0	9285	0	0
T44	0	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	102960114	0	0
T1	54674	54484	0	0
T2	508172	507053	0	0
T3	459584	198769	0	0
T4	2064	2064	0	0
T6	89797	89418	0	0
T7	540033	539718	0	0
T8	66088	65738	0	0
T9	127106	126976	0	0
T10	26476	26476	0	0
T11	68408	68314	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	102960114	0	0
T1	54674	54484	0	0
T2	508172	507053	0	0
T3	459584	198769	0	0
T4	2064	2064	0	0
T6	89797	89418	0	0
T7	540033	539718	0	0
T8	66088	65738	0	0
T9	127106	126976	0	0
T10	26476	26476	0	0
T11	68408	68314	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	770208	0	0
T2	508172	6447	0	0
T3	459584	2726	0	0
T4	2064	0	0	0
T6	89797	0	0	0
T7	540033	2588	0	0
T8	66088	0	0	0
T9	127106	0	0	0
T10	26476	0	0	0
T11	68408	0	0	0
T14	0	4085	0	0
T28	0	5111	0	0
T29	0	5418	0	0
T31	0	10246	0	0
T33	0	263	0	0
T37	82749	0	0	0
T43	0	9285	0	0
T44	0	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	770208	0	0
T2	508172	6447	0	0
T3	459584	2726	0	0
T4	2064	0	0	0
T6	89797	0	0	0
T7	540033	2588	0	0
T8	66088	0	0	0
T9	127106	0	0	0
T10	26476	0	0	0
T11	68408	0	0	0
T14	0	4085	0	0
T28	0	5111	0	0
T29	0	5418	0	0
T31	0	10246	0	0
T33	0	263	0	0
T37	82749	0	0	0
T43	0	9285	0	0
T44	0	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	770208	0	0
T2	508172	6447	0	0
T3	459584	2726	0	0
T4	2064	0	0	0
T6	89797	0	0	0
T7	540033	2588	0	0
T8	66088	0	0	0
T9	127106	0	0	0
T10	26476	0	0	0
T11	68408	0	0	0
T14	0	4085	0	0
T28	0	5111	0	0
T29	0	5418	0	0
T31	0	10246	0	0
T33	0	263	0	0
T37	82749	0	0	0
T43	0	9285	0	0
T44	0	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	770208	0	0
T2	508172	6447	0	0
T3	459584	2726	0	0
T4	2064	0	0	0
T6	89797	0	0	0
T7	540033	2588	0	0
T8	66088	0	0	0
T9	127106	0	0	0
T10	26476	0	0	0
T11	68408	0	0	0
T14	0	4085	0	0
T28	0	5111	0	0
T29	0	5418	0	0
T31	0	10246	0	0
T33	0	263	0	0
T37	82749	0	0	0
T43	0	9285	0	0
T44	0	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	102960114	0	0
T1	54674	54484	0	0
T2	508172	507053	0	0
T3	459584	198769	0	0
T4	2064	2064	0	0
T6	89797	89418	0	0
T7	540033	539718	0	0
T8	66088	65738	0	0
T9	127106	126976	0	0
T10	26476	26476	0	0
T11	68408	68314	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135116846	770208	0	0
T2	508172	6447	0	0
T3	459584	2726	0	0
T4	2064	0	0	0
T6	89797	0	0	0
T7	540033	2588	0	0
T8	66088	0	0	0
T9	127106	0	0	0
T10	26476	0	0	0
T11	68408	0	0	0
T14	0	4085	0	0
T28	0	5111	0	0
T29	0	5418	0	0
T31	0	10246	0	0
T33	0	263	0	0
T37	82749	0	0	0
T43	0	9285	0	0
T44	0	6	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410467989	410383879	0	0
CheckNGreaterZero_A	905	905	0	0
GntImpliesReady_A	410467989	2095465	0	0
GntImpliesValid_A	410467989	2095465	0	0
GrantKnown_A	410467989	410383879	0	0
IdxKnown_A	410467989	410383879	0	0
IndexIsCorrect_A	410467989	2095465	0	0
LockArbDecision_A	410467989	0	0	0
NoReadyValidNoGrant_A	410467989	0	0	0
ReadyAndValidImplyGrant_A	410467989	2095465	0	0
ReqAndReadyImplyGrant_A	410467989	2095465	0	0
ReqImpliesValid_A	410467989	2095465	0	0
ReqStaysHighUntilGranted0_M	410467989	0	0	0
RoundRobin_A	410467989	11	0	905
ValidKnown_A	410467989	410383879	0	0
gen_data_port_assertion.DataFlow_A	410467989	2095465	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410467989	410383879	0	0
T1	166631	166564	0	0
T2	208991	208985	0	0
T3	132950	132926	0	0
T4	4518	4449	0	0
T5	1491	1433	0	0
T6	275880	275801	0	0
T7	171603	171517	0	0
T8	470582	470492	0	0
T9	522388	522300	0	0
T10	161686	161602	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410467989	2095465	0	0
T1	166631	832	0	0
T2	208991	6359	0	0
T3	132950	9499	0	0
T4	4518	832	0	0
T5	1491	0	0	0
T6	275880	832	0	0
T7	171603	5955	0	0
T8	470582	832	0	0
T9	522388	832	0	0
T10	161686	832	0	0
T11	0	2624	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410467989	2095465	0	0
T1	166631	832	0	0
T2	208991	6359	0	0
T3	132950	9499	0	0
T4	4518	832	0	0
T5	1491	0	0	0
T6	275880	832	0	0
T7	171603	5955	0	0
T8	470582	832	0	0
T9	522388	832	0	0
T10	161686	832	0	0
T11	0	2624	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410467989	410383879	0	0
T1	166631	166564	0	0
T2	208991	208985	0	0
T3	132950	132926	0	0
T4	4518	4449	0	0
T5	1491	1433	0	0
T6	275880	275801	0	0
T7	171603	171517	0	0
T8	470582	470492	0	0
T9	522388	522300	0	0
T10	161686	161602	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410467989	410383879	0	0
T1	166631	166564	0	0
T2	208991	208985	0	0
T3	132950	132926	0	0
T4	4518	4449	0	0
T5	1491	1433	0	0
T6	275880	275801	0	0
T7	171603	171517	0	0
T8	470582	470492	0	0
T9	522388	522300	0	0
T10	161686	161602	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410467989	2095465	0	0
T1	166631	832	0	0
T2	208991	6359	0	0
T3	132950	9499	0	0
T4	4518	832	0	0
T5	1491	0	0	0
T6	275880	832	0	0
T7	171603	5955	0	0
T8	470582	832	0	0
T9	522388	832	0	0
T10	161686	832	0	0
T11	0	2624	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410467989	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410467989	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410467989	2095465	0	0
T1	166631	832	0	0
T2	208991	6359	0	0
T3	132950	9499	0	0
T4	4518	832	0	0
T5	1491	0	0	0
T6	275880	832	0	0
T7	171603	5955	0	0
T8	470582	832	0	0
T9	522388	832	0	0
T10	161686	832	0	0
T11	0	2624	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410467989	2095465	0	0
T1	166631	832	0	0
T2	208991	6359	0	0
T3	132950	9499	0	0
T4	4518	832	0	0
T5	1491	0	0	0
T6	275880	832	0	0
T7	171603	5955	0	0
T8	470582	832	0	0
T9	522388	832	0	0
T10	161686	832	0	0
T11	0	2624	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410467989	2095465	0	0
T1	166631	832	0	0
T2	208991	6359	0	0
T3	132950	9499	0	0
T4	4518	832	0	0
T5	1491	0	0	0
T6	275880	832	0	0
T7	171603	5955	0	0
T8	470582	832	0	0
T9	522388	832	0	0
T10	161686	832	0	0
T11	0	2624	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410467989	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410467989	11	0	905
T18	528192	1	0	1
T19	160764	0	0	1
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	272221	0	0	1
T54	332158	0	0	1
T55	275264	0	0	1
T56	887596	0	0	1
T57	916	0	0	1
T58	48313	0	0	1
T59	100241	0	0	1
T60	26594	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410467989	410383879	0	0
T1	166631	166564	0	0
T2	208991	208985	0	0
T3	132950	132926	0	0
T4	4518	4449	0	0
T5	1491	1433	0	0
T6	275880	275801	0	0
T7	171603	171517	0	0
T8	470582	470492	0	0
T9	522388	522300	0	0
T10	161686	161602	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410467989	2095465	0	0
T1	166631	832	0	0
T2	208991	6359	0	0
T3	132950	9499	0	0
T4	4518	832	0	0
T5	1491	0	0	0
T6	275880	832	0	0
T7	171603	5955	0	0
T8	470582	832	0	0
T9	522388	832	0	0
T10	161686	832	0	0
T11	0	2624	0	0