Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
3533 |
0 |
0 |
T64 |
2724 |
4 |
0 |
0 |
T65 |
10777 |
223 |
0 |
0 |
T66 |
8116 |
62 |
0 |
0 |
T96 |
8634 |
154 |
0 |
0 |
T97 |
102644 |
7 |
0 |
0 |
T98 |
72411 |
2 |
0 |
0 |
T101 |
7778 |
94 |
0 |
0 |
T110 |
12219 |
7 |
0 |
0 |
T111 |
13925 |
5 |
0 |
0 |
T112 |
10195 |
4 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
2826 |
0 |
0 |
T97 |
102644 |
108 |
0 |
0 |
T98 |
72411 |
80 |
0 |
0 |
T99 |
67222 |
76 |
0 |
0 |
T111 |
13925 |
23 |
0 |
0 |
T112 |
10195 |
18 |
0 |
0 |
T119 |
156714 |
307 |
0 |
0 |
T125 |
180184 |
473 |
0 |
0 |
T147 |
180243 |
463 |
0 |
0 |
T148 |
12118 |
12 |
0 |
0 |
T149 |
6865 |
7 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
2610 |
0 |
0 |
T97 |
102644 |
111 |
0 |
0 |
T98 |
72411 |
79 |
0 |
0 |
T99 |
67222 |
74 |
0 |
0 |
T111 |
13925 |
16 |
0 |
0 |
T112 |
10195 |
17 |
0 |
0 |
T118 |
3862 |
1 |
0 |
0 |
T119 |
156714 |
247 |
0 |
0 |
T125 |
180184 |
418 |
0 |
0 |
T147 |
180243 |
463 |
0 |
0 |
T148 |
12118 |
26 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
3474 |
0 |
0 |
T97 |
102644 |
250 |
0 |
0 |
T98 |
72411 |
173 |
0 |
0 |
T99 |
67222 |
176 |
0 |
0 |
T111 |
13925 |
26 |
0 |
0 |
T112 |
10195 |
19 |
0 |
0 |
T118 |
3862 |
11 |
0 |
0 |
T119 |
156714 |
233 |
0 |
0 |
T125 |
180184 |
421 |
0 |
0 |
T147 |
180243 |
411 |
0 |
0 |
T148 |
12118 |
47 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
12973 |
0 |
0 |
T97 |
102644 |
2302 |
0 |
0 |
T98 |
72411 |
1148 |
0 |
0 |
T99 |
67222 |
1453 |
0 |
0 |
T111 |
13925 |
16 |
0 |
0 |
T112 |
10195 |
124 |
0 |
0 |
T118 |
3862 |
9 |
0 |
0 |
T119 |
156714 |
297 |
0 |
0 |
T125 |
180184 |
443 |
0 |
0 |
T147 |
180243 |
495 |
0 |
0 |
T148 |
12118 |
17 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
13305 |
0 |
0 |
T97 |
102644 |
1851 |
0 |
0 |
T98 |
72411 |
1419 |
0 |
0 |
T99 |
67222 |
1619 |
0 |
0 |
T111 |
13925 |
126 |
0 |
0 |
T112 |
10195 |
22 |
0 |
0 |
T118 |
3862 |
4 |
0 |
0 |
T119 |
156714 |
288 |
0 |
0 |
T125 |
180184 |
424 |
0 |
0 |
T147 |
180243 |
438 |
0 |
0 |
T148 |
12118 |
7 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
12439 |
0 |
0 |
T97 |
102644 |
1932 |
0 |
0 |
T98 |
72411 |
868 |
0 |
0 |
T99 |
67222 |
1191 |
0 |
0 |
T111 |
13925 |
129 |
0 |
0 |
T112 |
10195 |
13 |
0 |
0 |
T118 |
3862 |
119 |
0 |
0 |
T119 |
156714 |
258 |
0 |
0 |
T125 |
180184 |
490 |
0 |
0 |
T147 |
180243 |
453 |
0 |
0 |
T148 |
12118 |
23 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
12296 |
0 |
0 |
T97 |
102644 |
1832 |
0 |
0 |
T98 |
72411 |
1543 |
0 |
0 |
T99 |
67222 |
889 |
0 |
0 |
T111 |
13925 |
117 |
0 |
0 |
T112 |
10195 |
169 |
0 |
0 |
T119 |
156714 |
291 |
0 |
0 |
T125 |
180184 |
478 |
0 |
0 |
T147 |
180243 |
494 |
0 |
0 |
T148 |
12118 |
29 |
0 |
0 |
T149 |
6865 |
16 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
14315 |
0 |
0 |
T97 |
102644 |
2482 |
0 |
0 |
T98 |
72411 |
1469 |
0 |
0 |
T99 |
67222 |
1422 |
0 |
0 |
T111 |
13925 |
288 |
0 |
0 |
T112 |
10195 |
205 |
0 |
0 |
T118 |
3862 |
2 |
0 |
0 |
T119 |
156714 |
246 |
0 |
0 |
T125 |
180184 |
481 |
0 |
0 |
T147 |
180243 |
441 |
0 |
0 |
T148 |
12118 |
24 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
13714 |
0 |
0 |
T97 |
102644 |
2155 |
0 |
0 |
T98 |
72411 |
1837 |
0 |
0 |
T99 |
67222 |
1421 |
0 |
0 |
T111 |
13925 |
156 |
0 |
0 |
T112 |
10195 |
289 |
0 |
0 |
T118 |
3862 |
113 |
0 |
0 |
T119 |
156714 |
299 |
0 |
0 |
T125 |
180184 |
466 |
0 |
0 |
T147 |
180243 |
421 |
0 |
0 |
T148 |
12118 |
27 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
12997 |
0 |
0 |
T97 |
102644 |
1966 |
0 |
0 |
T98 |
72411 |
876 |
0 |
0 |
T99 |
67222 |
1342 |
0 |
0 |
T111 |
13925 |
164 |
0 |
0 |
T112 |
10195 |
122 |
0 |
0 |
T118 |
3862 |
7 |
0 |
0 |
T119 |
156714 |
213 |
0 |
0 |
T125 |
180184 |
398 |
0 |
0 |
T147 |
180243 |
466 |
0 |
0 |
T148 |
12118 |
27 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
11886 |
0 |
0 |
T97 |
102644 |
1781 |
0 |
0 |
T98 |
72411 |
1286 |
0 |
0 |
T99 |
67222 |
1157 |
0 |
0 |
T111 |
13925 |
23 |
0 |
0 |
T112 |
10195 |
15 |
0 |
0 |
T118 |
3862 |
89 |
0 |
0 |
T119 |
156714 |
305 |
0 |
0 |
T125 |
180184 |
427 |
0 |
0 |
T147 |
180243 |
389 |
0 |
0 |
T148 |
12118 |
35 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
6534 |
0 |
0 |
T97 |
102644 |
681 |
0 |
0 |
T98 |
72411 |
516 |
0 |
0 |
T99 |
67222 |
711 |
0 |
0 |
T111 |
13925 |
92 |
0 |
0 |
T112 |
10195 |
125 |
0 |
0 |
T118 |
3862 |
54 |
0 |
0 |
T119 |
156714 |
268 |
0 |
0 |
T125 |
180184 |
469 |
0 |
0 |
T147 |
180243 |
411 |
0 |
0 |
T148 |
12118 |
40 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
6545 |
0 |
0 |
T97 |
102644 |
887 |
0 |
0 |
T98 |
72411 |
408 |
0 |
0 |
T99 |
67222 |
488 |
0 |
0 |
T111 |
13925 |
82 |
0 |
0 |
T112 |
10195 |
74 |
0 |
0 |
T118 |
3862 |
2 |
0 |
0 |
T119 |
156714 |
261 |
0 |
0 |
T125 |
180184 |
430 |
0 |
0 |
T147 |
180243 |
413 |
0 |
0 |
T148 |
12118 |
14 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
6877 |
0 |
0 |
T97 |
102644 |
784 |
0 |
0 |
T98 |
72411 |
570 |
0 |
0 |
T99 |
67222 |
434 |
0 |
0 |
T111 |
13925 |
62 |
0 |
0 |
T112 |
10195 |
26 |
0 |
0 |
T119 |
156714 |
310 |
0 |
0 |
T125 |
180184 |
491 |
0 |
0 |
T147 |
180243 |
418 |
0 |
0 |
T148 |
12118 |
16 |
0 |
0 |
T149 |
6865 |
14 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
6804 |
0 |
0 |
T97 |
102644 |
911 |
0 |
0 |
T98 |
72411 |
737 |
0 |
0 |
T99 |
67222 |
548 |
0 |
0 |
T111 |
13925 |
63 |
0 |
0 |
T112 |
10195 |
83 |
0 |
0 |
T118 |
3862 |
1 |
0 |
0 |
T119 |
156714 |
250 |
0 |
0 |
T125 |
180184 |
452 |
0 |
0 |
T147 |
180243 |
376 |
0 |
0 |
T148 |
12118 |
6 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
6777 |
0 |
0 |
T96 |
8634 |
1 |
0 |
0 |
T97 |
102644 |
904 |
0 |
0 |
T98 |
72411 |
548 |
0 |
0 |
T99 |
67222 |
433 |
0 |
0 |
T111 |
13925 |
46 |
0 |
0 |
T112 |
10195 |
67 |
0 |
0 |
T118 |
3862 |
36 |
0 |
0 |
T119 |
156714 |
276 |
0 |
0 |
T125 |
180184 |
499 |
0 |
0 |
T147 |
180243 |
401 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
6872 |
0 |
0 |
T97 |
102644 |
853 |
0 |
0 |
T98 |
72411 |
497 |
0 |
0 |
T99 |
67222 |
514 |
0 |
0 |
T111 |
13925 |
102 |
0 |
0 |
T112 |
10195 |
9 |
0 |
0 |
T118 |
3862 |
56 |
0 |
0 |
T119 |
156714 |
251 |
0 |
0 |
T125 |
180184 |
397 |
0 |
0 |
T147 |
180243 |
409 |
0 |
0 |
T148 |
12118 |
44 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
5901 |
0 |
0 |
T97 |
102644 |
534 |
0 |
0 |
T98 |
72411 |
340 |
0 |
0 |
T99 |
67222 |
512 |
0 |
0 |
T111 |
13925 |
125 |
0 |
0 |
T112 |
10195 |
100 |
0 |
0 |
T118 |
3862 |
2 |
0 |
0 |
T119 |
156714 |
232 |
0 |
0 |
T125 |
180184 |
410 |
0 |
0 |
T147 |
180243 |
474 |
0 |
0 |
T148 |
12118 |
22 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
6942 |
0 |
0 |
T97 |
102644 |
862 |
0 |
0 |
T98 |
72411 |
507 |
0 |
0 |
T99 |
67222 |
627 |
0 |
0 |
T111 |
13925 |
168 |
0 |
0 |
T112 |
10195 |
69 |
0 |
0 |
T118 |
3862 |
49 |
0 |
0 |
T119 |
156714 |
280 |
0 |
0 |
T125 |
180184 |
431 |
0 |
0 |
T147 |
180243 |
444 |
0 |
0 |
T148 |
12118 |
6 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
6650 |
0 |
0 |
T97 |
102644 |
598 |
0 |
0 |
T98 |
72411 |
514 |
0 |
0 |
T99 |
67222 |
543 |
0 |
0 |
T111 |
13925 |
78 |
0 |
0 |
T112 |
10195 |
12 |
0 |
0 |
T118 |
3862 |
30 |
0 |
0 |
T119 |
156714 |
256 |
0 |
0 |
T125 |
180184 |
472 |
0 |
0 |
T147 |
180243 |
455 |
0 |
0 |
T148 |
12118 |
8 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
6572 |
0 |
0 |
T97 |
102644 |
971 |
0 |
0 |
T98 |
72411 |
526 |
0 |
0 |
T99 |
67222 |
535 |
0 |
0 |
T111 |
13925 |
59 |
0 |
0 |
T112 |
10195 |
56 |
0 |
0 |
T119 |
156714 |
237 |
0 |
0 |
T125 |
180184 |
445 |
0 |
0 |
T147 |
180243 |
458 |
0 |
0 |
T148 |
12118 |
30 |
0 |
0 |
T149 |
6865 |
9 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
7756 |
0 |
0 |
T97 |
102644 |
1099 |
0 |
0 |
T98 |
72411 |
343 |
0 |
0 |
T99 |
67222 |
643 |
0 |
0 |
T111 |
13925 |
116 |
0 |
0 |
T112 |
10195 |
117 |
0 |
0 |
T119 |
156714 |
268 |
0 |
0 |
T125 |
180184 |
471 |
0 |
0 |
T147 |
180243 |
420 |
0 |
0 |
T148 |
12118 |
13 |
0 |
0 |
T149 |
6865 |
3 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
6765 |
0 |
0 |
T97 |
102644 |
968 |
0 |
0 |
T98 |
72411 |
652 |
0 |
0 |
T99 |
67222 |
417 |
0 |
0 |
T111 |
13925 |
111 |
0 |
0 |
T112 |
10195 |
81 |
0 |
0 |
T118 |
3862 |
6 |
0 |
0 |
T119 |
156714 |
293 |
0 |
0 |
T125 |
180184 |
438 |
0 |
0 |
T147 |
180243 |
393 |
0 |
0 |
T148 |
12118 |
34 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
6747 |
0 |
0 |
T97 |
102644 |
930 |
0 |
0 |
T98 |
72411 |
503 |
0 |
0 |
T99 |
67222 |
465 |
0 |
0 |
T111 |
13925 |
160 |
0 |
0 |
T112 |
10195 |
18 |
0 |
0 |
T118 |
3862 |
1 |
0 |
0 |
T119 |
156714 |
273 |
0 |
0 |
T125 |
180184 |
400 |
0 |
0 |
T147 |
180243 |
455 |
0 |
0 |
T148 |
12118 |
16 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
6333 |
0 |
0 |
T97 |
102644 |
704 |
0 |
0 |
T98 |
72411 |
464 |
0 |
0 |
T99 |
67222 |
463 |
0 |
0 |
T111 |
13925 |
71 |
0 |
0 |
T112 |
10195 |
119 |
0 |
0 |
T118 |
3862 |
57 |
0 |
0 |
T119 |
156714 |
284 |
0 |
0 |
T125 |
180184 |
426 |
0 |
0 |
T147 |
180243 |
438 |
0 |
0 |
T148 |
12118 |
31 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
6481 |
0 |
0 |
T97 |
102644 |
723 |
0 |
0 |
T98 |
72411 |
500 |
0 |
0 |
T99 |
67222 |
362 |
0 |
0 |
T111 |
13925 |
142 |
0 |
0 |
T112 |
10195 |
97 |
0 |
0 |
T118 |
3862 |
5 |
0 |
0 |
T119 |
156714 |
231 |
0 |
0 |
T125 |
180184 |
442 |
0 |
0 |
T147 |
180243 |
432 |
0 |
0 |
T148 |
12118 |
15 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
6927 |
0 |
0 |
T97 |
102644 |
832 |
0 |
0 |
T98 |
72411 |
502 |
0 |
0 |
T99 |
67222 |
537 |
0 |
0 |
T111 |
13925 |
82 |
0 |
0 |
T112 |
10195 |
119 |
0 |
0 |
T118 |
3862 |
62 |
0 |
0 |
T119 |
156714 |
315 |
0 |
0 |
T125 |
180184 |
473 |
0 |
0 |
T147 |
180243 |
481 |
0 |
0 |
T148 |
12118 |
35 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
6411 |
0 |
0 |
T97 |
102644 |
609 |
0 |
0 |
T98 |
72411 |
493 |
0 |
0 |
T99 |
67222 |
515 |
0 |
0 |
T111 |
13925 |
115 |
0 |
0 |
T112 |
10195 |
116 |
0 |
0 |
T118 |
3862 |
4 |
0 |
0 |
T119 |
156714 |
307 |
0 |
0 |
T125 |
180184 |
439 |
0 |
0 |
T147 |
180243 |
467 |
0 |
0 |
T148 |
12118 |
19 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
6854 |
0 |
0 |
T97 |
102644 |
952 |
0 |
0 |
T98 |
72411 |
596 |
0 |
0 |
T99 |
67222 |
560 |
0 |
0 |
T111 |
13925 |
84 |
0 |
0 |
T112 |
10195 |
57 |
0 |
0 |
T118 |
3862 |
4 |
0 |
0 |
T119 |
156714 |
246 |
0 |
0 |
T125 |
180184 |
519 |
0 |
0 |
T147 |
180243 |
462 |
0 |
0 |
T148 |
12118 |
27 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
6607 |
0 |
0 |
T97 |
102644 |
819 |
0 |
0 |
T98 |
72411 |
515 |
0 |
0 |
T99 |
67222 |
572 |
0 |
0 |
T111 |
13925 |
124 |
0 |
0 |
T112 |
10195 |
15 |
0 |
0 |
T119 |
156714 |
220 |
0 |
0 |
T125 |
180184 |
412 |
0 |
0 |
T147 |
180243 |
452 |
0 |
0 |
T148 |
12118 |
11 |
0 |
0 |
T149 |
6865 |
6 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
7262 |
0 |
0 |
T97 |
102644 |
1150 |
0 |
0 |
T98 |
72411 |
592 |
0 |
0 |
T99 |
67222 |
463 |
0 |
0 |
T111 |
13925 |
67 |
0 |
0 |
T112 |
10195 |
44 |
0 |
0 |
T119 |
156714 |
238 |
0 |
0 |
T125 |
180184 |
461 |
0 |
0 |
T147 |
180243 |
443 |
0 |
0 |
T148 |
12118 |
8 |
0 |
0 |
T149 |
6865 |
12 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
6863 |
0 |
0 |
T97 |
102644 |
799 |
0 |
0 |
T98 |
72411 |
609 |
0 |
0 |
T99 |
67222 |
549 |
0 |
0 |
T111 |
13925 |
137 |
0 |
0 |
T112 |
10195 |
69 |
0 |
0 |
T118 |
3862 |
7 |
0 |
0 |
T119 |
156714 |
258 |
0 |
0 |
T125 |
180184 |
409 |
0 |
0 |
T147 |
180243 |
423 |
0 |
0 |
T148 |
12118 |
12 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
6838 |
0 |
0 |
T97 |
102644 |
925 |
0 |
0 |
T98 |
72411 |
740 |
0 |
0 |
T99 |
67222 |
591 |
0 |
0 |
T111 |
13925 |
59 |
0 |
0 |
T112 |
10195 |
49 |
0 |
0 |
T118 |
3862 |
10 |
0 |
0 |
T119 |
156714 |
270 |
0 |
0 |
T125 |
180184 |
448 |
0 |
0 |
T147 |
180243 |
323 |
0 |
0 |
T148 |
12118 |
36 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
7001 |
0 |
0 |
T97 |
102644 |
659 |
0 |
0 |
T98 |
72411 |
530 |
0 |
0 |
T99 |
67222 |
569 |
0 |
0 |
T111 |
13925 |
121 |
0 |
0 |
T112 |
10195 |
62 |
0 |
0 |
T118 |
3862 |
43 |
0 |
0 |
T119 |
156714 |
253 |
0 |
0 |
T125 |
180184 |
407 |
0 |
0 |
T147 |
180243 |
452 |
0 |
0 |
T148 |
12118 |
10 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
6785 |
0 |
0 |
T97 |
102644 |
873 |
0 |
0 |
T98 |
72411 |
598 |
0 |
0 |
T99 |
67222 |
581 |
0 |
0 |
T111 |
13925 |
27 |
0 |
0 |
T112 |
10195 |
117 |
0 |
0 |
T118 |
3862 |
8 |
0 |
0 |
T119 |
156714 |
227 |
0 |
0 |
T125 |
180184 |
367 |
0 |
0 |
T147 |
180243 |
400 |
0 |
0 |
T148 |
12118 |
50 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
2839 |
0 |
0 |
T97 |
102644 |
133 |
0 |
0 |
T98 |
72411 |
102 |
0 |
0 |
T99 |
67222 |
130 |
0 |
0 |
T111 |
13925 |
19 |
0 |
0 |
T112 |
10195 |
19 |
0 |
0 |
T118 |
3862 |
6 |
0 |
0 |
T119 |
156714 |
290 |
0 |
0 |
T125 |
180184 |
402 |
0 |
0 |
T147 |
180243 |
394 |
0 |
0 |
T148 |
12118 |
7 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
3244 |
0 |
0 |
T97 |
102644 |
192 |
0 |
0 |
T98 |
72411 |
100 |
0 |
0 |
T99 |
67222 |
123 |
0 |
0 |
T111 |
13925 |
21 |
0 |
0 |
T112 |
10195 |
14 |
0 |
0 |
T118 |
3862 |
4 |
0 |
0 |
T119 |
156714 |
284 |
0 |
0 |
T125 |
180184 |
421 |
0 |
0 |
T147 |
180243 |
472 |
0 |
0 |
T148 |
12118 |
32 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
2905 |
0 |
0 |
T97 |
102644 |
179 |
0 |
0 |
T98 |
72411 |
103 |
0 |
0 |
T99 |
67222 |
157 |
0 |
0 |
T111 |
13925 |
29 |
0 |
0 |
T112 |
10195 |
6 |
0 |
0 |
T118 |
3862 |
2 |
0 |
0 |
T119 |
156714 |
255 |
0 |
0 |
T125 |
180184 |
389 |
0 |
0 |
T147 |
180243 |
448 |
0 |
0 |
T148 |
12118 |
24 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
3097 |
0 |
0 |
T97 |
102644 |
140 |
0 |
0 |
T98 |
72411 |
117 |
0 |
0 |
T99 |
67222 |
104 |
0 |
0 |
T111 |
13925 |
33 |
0 |
0 |
T112 |
10195 |
31 |
0 |
0 |
T118 |
3862 |
7 |
0 |
0 |
T119 |
156714 |
282 |
0 |
0 |
T125 |
180184 |
449 |
0 |
0 |
T147 |
180243 |
458 |
0 |
0 |
T148 |
12118 |
38 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
3741 |
0 |
0 |
T97 |
102644 |
290 |
0 |
0 |
T98 |
72411 |
241 |
0 |
0 |
T99 |
67222 |
135 |
0 |
0 |
T111 |
13925 |
74 |
0 |
0 |
T112 |
10195 |
11 |
0 |
0 |
T118 |
3862 |
3 |
0 |
0 |
T119 |
156714 |
302 |
0 |
0 |
T125 |
180184 |
418 |
0 |
0 |
T147 |
180243 |
465 |
0 |
0 |
T148 |
12118 |
30 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
6015 |
0 |
0 |
T14 |
293873 |
31 |
0 |
0 |
T16 |
0 |
32 |
0 |
0 |
T40 |
917206 |
0 |
0 |
0 |
T150 |
0 |
50 |
0 |
0 |
T151 |
0 |
1 |
0 |
0 |
T152 |
0 |
49 |
0 |
0 |
T153 |
0 |
47 |
0 |
0 |
T154 |
0 |
81 |
0 |
0 |
T155 |
0 |
10 |
0 |
0 |
T156 |
0 |
44 |
0 |
0 |
T157 |
0 |
14 |
0 |
0 |
T158 |
803697 |
0 |
0 |
0 |
T159 |
201537 |
0 |
0 |
0 |
T160 |
148224 |
0 |
0 |
0 |
T161 |
101427 |
0 |
0 |
0 |
T162 |
23862 |
0 |
0 |
0 |
T163 |
926 |
0 |
0 |
0 |
T164 |
1883 |
0 |
0 |
0 |
T165 |
799688 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
3027 |
0 |
0 |
T97 |
102644 |
176 |
0 |
0 |
T98 |
72411 |
110 |
0 |
0 |
T99 |
67222 |
125 |
0 |
0 |
T111 |
13925 |
33 |
0 |
0 |
T112 |
10195 |
22 |
0 |
0 |
T118 |
3862 |
4 |
0 |
0 |
T119 |
156714 |
259 |
0 |
0 |
T125 |
180184 |
398 |
0 |
0 |
T147 |
180243 |
410 |
0 |
0 |
T148 |
12118 |
31 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
2786 |
0 |
0 |
T97 |
102644 |
126 |
0 |
0 |
T98 |
72411 |
100 |
0 |
0 |
T99 |
67222 |
121 |
0 |
0 |
T111 |
13925 |
12 |
0 |
0 |
T112 |
10195 |
9 |
0 |
0 |
T118 |
3862 |
1 |
0 |
0 |
T119 |
156714 |
224 |
0 |
0 |
T125 |
180184 |
445 |
0 |
0 |
T147 |
180243 |
432 |
0 |
0 |
T148 |
12118 |
11 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
2864 |
0 |
0 |
T97 |
102644 |
133 |
0 |
0 |
T98 |
72411 |
66 |
0 |
0 |
T99 |
67222 |
91 |
0 |
0 |
T111 |
13925 |
26 |
0 |
0 |
T112 |
10195 |
10 |
0 |
0 |
T119 |
156714 |
290 |
0 |
0 |
T125 |
180184 |
434 |
0 |
0 |
T147 |
180243 |
437 |
0 |
0 |
T148 |
12118 |
30 |
0 |
0 |
T149 |
6865 |
10 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
2804 |
0 |
0 |
T97 |
102644 |
107 |
0 |
0 |
T98 |
72411 |
85 |
0 |
0 |
T99 |
67222 |
79 |
0 |
0 |
T111 |
13925 |
21 |
0 |
0 |
T112 |
10195 |
18 |
0 |
0 |
T119 |
156714 |
242 |
0 |
0 |
T125 |
180184 |
444 |
0 |
0 |
T147 |
180243 |
494 |
0 |
0 |
T148 |
12118 |
31 |
0 |
0 |
T149 |
6865 |
9 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
2864 |
0 |
0 |
T97 |
102644 |
139 |
0 |
0 |
T98 |
72411 |
66 |
0 |
0 |
T99 |
67222 |
92 |
0 |
0 |
T111 |
13925 |
25 |
0 |
0 |
T112 |
10195 |
27 |
0 |
0 |
T118 |
3862 |
5 |
0 |
0 |
T119 |
156714 |
278 |
0 |
0 |
T125 |
180184 |
407 |
0 |
0 |
T147 |
180243 |
462 |
0 |
0 |
T148 |
12118 |
16 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
2719 |
0 |
0 |
T97 |
102644 |
152 |
0 |
0 |
T98 |
72411 |
78 |
0 |
0 |
T99 |
67222 |
80 |
0 |
0 |
T111 |
13925 |
31 |
0 |
0 |
T112 |
10195 |
12 |
0 |
0 |
T118 |
3862 |
7 |
0 |
0 |
T119 |
156714 |
277 |
0 |
0 |
T125 |
180184 |
417 |
0 |
0 |
T147 |
180243 |
457 |
0 |
0 |
T148 |
12118 |
6 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
3785 |
0 |
0 |
T97 |
102644 |
319 |
0 |
0 |
T98 |
72411 |
159 |
0 |
0 |
T99 |
67222 |
178 |
0 |
0 |
T111 |
13925 |
76 |
0 |
0 |
T112 |
10195 |
21 |
0 |
0 |
T118 |
3862 |
1 |
0 |
0 |
T119 |
156714 |
321 |
0 |
0 |
T125 |
180184 |
449 |
0 |
0 |
T147 |
180243 |
456 |
0 |
0 |
T148 |
12118 |
17 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
2796 |
0 |
0 |
T97 |
102644 |
89 |
0 |
0 |
T98 |
72411 |
74 |
0 |
0 |
T99 |
67222 |
104 |
0 |
0 |
T111 |
13925 |
18 |
0 |
0 |
T112 |
10195 |
17 |
0 |
0 |
T118 |
3862 |
3 |
0 |
0 |
T119 |
156714 |
324 |
0 |
0 |
T125 |
180184 |
463 |
0 |
0 |
T147 |
180243 |
398 |
0 |
0 |
T148 |
12118 |
21 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
3910 |
0 |
0 |
T97 |
102644 |
339 |
0 |
0 |
T98 |
72411 |
238 |
0 |
0 |
T99 |
67222 |
270 |
0 |
0 |
T111 |
13925 |
55 |
0 |
0 |
T112 |
10195 |
27 |
0 |
0 |
T119 |
156714 |
288 |
0 |
0 |
T125 |
180184 |
440 |
0 |
0 |
T147 |
180243 |
429 |
0 |
0 |
T148 |
12118 |
27 |
0 |
0 |
T149 |
6865 |
8 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
3161 |
0 |
0 |
T97 |
102644 |
195 |
0 |
0 |
T98 |
72411 |
127 |
0 |
0 |
T99 |
67222 |
142 |
0 |
0 |
T111 |
13925 |
11 |
0 |
0 |
T112 |
10195 |
21 |
0 |
0 |
T119 |
156714 |
266 |
0 |
0 |
T122 |
42056 |
293 |
0 |
0 |
T125 |
180184 |
456 |
0 |
0 |
T147 |
180243 |
463 |
0 |
0 |
T148 |
12118 |
4 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
2807 |
0 |
0 |
T97 |
102644 |
135 |
0 |
0 |
T98 |
72411 |
65 |
0 |
0 |
T99 |
67222 |
75 |
0 |
0 |
T111 |
13925 |
30 |
0 |
0 |
T112 |
10195 |
18 |
0 |
0 |
T118 |
3862 |
3 |
0 |
0 |
T119 |
156714 |
294 |
0 |
0 |
T125 |
180184 |
446 |
0 |
0 |
T147 |
180243 |
444 |
0 |
0 |
T148 |
12118 |
8 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
2827 |
0 |
0 |
T97 |
102644 |
110 |
0 |
0 |
T98 |
72411 |
48 |
0 |
0 |
T99 |
67222 |
91 |
0 |
0 |
T111 |
13925 |
19 |
0 |
0 |
T112 |
10195 |
8 |
0 |
0 |
T118 |
3862 |
1 |
0 |
0 |
T119 |
156714 |
321 |
0 |
0 |
T125 |
180184 |
493 |
0 |
0 |
T147 |
180243 |
519 |
0 |
0 |
T148 |
12118 |
35 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
2779 |
0 |
0 |
T97 |
102644 |
91 |
0 |
0 |
T98 |
72411 |
81 |
0 |
0 |
T99 |
67222 |
75 |
0 |
0 |
T111 |
13925 |
25 |
0 |
0 |
T112 |
10195 |
12 |
0 |
0 |
T119 |
156714 |
248 |
0 |
0 |
T125 |
180184 |
419 |
0 |
0 |
T147 |
180243 |
496 |
0 |
0 |
T148 |
12118 |
23 |
0 |
0 |
T149 |
6865 |
22 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
2646 |
0 |
0 |
T97 |
102644 |
128 |
0 |
0 |
T98 |
72411 |
67 |
0 |
0 |
T99 |
67222 |
44 |
0 |
0 |
T111 |
13925 |
33 |
0 |
0 |
T112 |
10195 |
17 |
0 |
0 |
T118 |
3862 |
3 |
0 |
0 |
T119 |
156714 |
306 |
0 |
0 |
T125 |
180184 |
363 |
0 |
0 |
T147 |
180243 |
442 |
0 |
0 |
T148 |
12118 |
47 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
2632 |
0 |
0 |
T97 |
102644 |
106 |
0 |
0 |
T98 |
72411 |
111 |
0 |
0 |
T99 |
67222 |
91 |
0 |
0 |
T111 |
13925 |
22 |
0 |
0 |
T112 |
10195 |
10 |
0 |
0 |
T118 |
3862 |
4 |
0 |
0 |
T119 |
156714 |
219 |
0 |
0 |
T125 |
180184 |
408 |
0 |
0 |
T147 |
180243 |
376 |
0 |
0 |
T148 |
12118 |
11 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412910339 |
2796 |
0 |
0 |
T97 |
102644 |
119 |
0 |
0 |
T98 |
72411 |
74 |
0 |
0 |
T99 |
67222 |
70 |
0 |
0 |
T111 |
13925 |
34 |
0 |
0 |
T112 |
10195 |
9 |
0 |
0 |
T118 |
3862 |
6 |
0 |
0 |
T119 |
156714 |
261 |
0 |
0 |
T125 |
180184 |
408 |
0 |
0 |
T147 |
180243 |
479 |
0 |
0 |
T148 |
12118 |
12 |
0 |
0 |