Unified Coverage Report :: Module :: prim_ram_1r1w_async_adv

Module : prim_ram_1r1w_async_adv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	75.00			100.00		u_spid_dpram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_mem	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	75.00			100.00		u_spid_dpram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_mem	100.00	100.00				100.00	100.00

Line Coverage for Module : prim_ram_1r1w_async_adv

	Line No.	Total	Covered	Percent
TOTAL		28	28	100.00
ALWAYS	118	3	3	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
ALWAYS	180	8	8	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	261	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' or '../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
118	1	1
119	1	1
121	1	1
125	1	1
126	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
180	1	1
181	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
193	1	1
203	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
258	1	1
259	1	1
261	1	1

---

Branch Coverage for Module : prim_ram_1r1w_async_adv

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	118	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' or '../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	118	if ((!rst_b_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_ram_1r1w_async_adv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CannotHaveEccAndParity_A	1810	1810	0	0
gen_byte_parity.ParityNeedsByteWriteMask_A	1810	1810	0	0
gen_byte_parity.WidthNeedsToBeByteAligned_A	1810	1810	0	0

CannotHaveEccAndParity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1810	1810	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

gen_byte_parity.ParityNeedsByteWriteMask_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1810	1810	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

gen_byte_parity.WidthNeedsToBeByteAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1810	1810	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem

	Line No.	Total	Covered	Percent
TOTAL		28	28	100.00
ALWAYS	118	3	3	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
ALWAYS	180	8	8	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	261	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' or '../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
118	1	1
119	1	1
121	1	1
125	1	1
126	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
180	1	1
181	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
193	1	1
203	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
258	1	1
259	1	1
261	1	1

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	118	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' or '../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	118	if ((!rst_b_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CannotHaveEccAndParity_A	905	905	0	0
gen_byte_parity.ParityNeedsByteWriteMask_A	905	905	0	0
gen_byte_parity.WidthNeedsToBeByteAligned_A	905	905	0	0

CannotHaveEccAndParity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

gen_byte_parity.ParityNeedsByteWriteMask_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

gen_byte_parity.WidthNeedsToBeByteAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem

	Line No.	Total	Covered	Percent
TOTAL		28	28	100.00
ALWAYS	118	3	3	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
ALWAYS	180	8	8	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	261	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' or '../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
118	1	1
119	1	1
121	1	1
125	1	1
126	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
180	1	1
181	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
193	1	1
203	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
258	1	1
259	1	1
261	1	1

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	118	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' or '../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	118	if ((!rst_b_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CannotHaveEccAndParity_A	905	905	0	0
gen_byte_parity.ParityNeedsByteWriteMask_A	905	905	0	0
gen_byte_parity.WidthNeedsToBeByteAligned_A	905	905	0	0

CannotHaveEccAndParity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

gen_byte_parity.ParityNeedsByteWriteMask_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

gen_byte_parity.WidthNeedsToBeByteAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0