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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 98.38 93.99 98.62 89.36 97.21 95.45 99.20


Total test records in report: 1080
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T1008 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.516273877 Jun 23 05:14:36 PM PDT 24 Jun 23 05:14:37 PM PDT 24 15413713 ps
T84 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1911520960 Jun 23 05:13:49 PM PDT 24 Jun 23 05:13:51 PM PDT 24 74913471 ps
T1009 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1626239370 Jun 23 05:14:15 PM PDT 24 Jun 23 05:14:16 PM PDT 24 51713022 ps
T1010 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2864313931 Jun 23 05:14:22 PM PDT 24 Jun 23 05:14:25 PM PDT 24 502683211 ps
T1011 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4015770229 Jun 23 05:14:01 PM PDT 24 Jun 23 05:14:04 PM PDT 24 92237197 ps
T1012 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.923213104 Jun 23 05:13:46 PM PDT 24 Jun 23 05:13:49 PM PDT 24 57511607 ps
T1013 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3844346438 Jun 23 05:14:30 PM PDT 24 Jun 23 05:14:44 PM PDT 24 710042664 ps
T1014 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2742487104 Jun 23 05:13:46 PM PDT 24 Jun 23 05:13:50 PM PDT 24 337415068 ps
T1015 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2990574137 Jun 23 05:14:13 PM PDT 24 Jun 23 05:14:14 PM PDT 24 43349550 ps
T1016 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.9511134 Jun 23 05:14:32 PM PDT 24 Jun 23 05:14:34 PM PDT 24 25400583 ps
T1017 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.347133857 Jun 23 05:14:04 PM PDT 24 Jun 23 05:14:05 PM PDT 24 14720032 ps
T1018 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1553596518 Jun 23 05:14:03 PM PDT 24 Jun 23 05:14:05 PM PDT 24 77018823 ps
T1019 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3032659209 Jun 23 05:14:07 PM PDT 24 Jun 23 05:14:12 PM PDT 24 53053571 ps
T1020 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3904775212 Jun 23 05:13:48 PM PDT 24 Jun 23 05:13:49 PM PDT 24 37706680 ps
T1021 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2284941162 Jun 23 05:14:31 PM PDT 24 Jun 23 05:14:34 PM PDT 24 38455254 ps
T175 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2608924644 Jun 23 05:14:02 PM PDT 24 Jun 23 05:14:21 PM PDT 24 701812771 ps
T1022 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1889415354 Jun 23 05:13:53 PM PDT 24 Jun 23 05:13:54 PM PDT 24 85023355 ps
T1023 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.423365202 Jun 23 05:14:30 PM PDT 24 Jun 23 05:14:32 PM PDT 24 19498728 ps
T1024 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3231643467 Jun 23 05:14:22 PM PDT 24 Jun 23 05:14:24 PM PDT 24 212747682 ps
T1025 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2489838340 Jun 23 05:14:23 PM PDT 24 Jun 23 05:14:24 PM PDT 24 37393963 ps
T1026 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2513695548 Jun 23 05:14:31 PM PDT 24 Jun 23 05:14:32 PM PDT 24 11791036 ps
T1027 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1434211789 Jun 23 05:13:44 PM PDT 24 Jun 23 05:13:51 PM PDT 24 259028682 ps
T1028 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2988020471 Jun 23 05:13:47 PM PDT 24 Jun 23 05:13:51 PM PDT 24 42671885 ps
T1029 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.337820501 Jun 23 05:14:11 PM PDT 24 Jun 23 05:14:13 PM PDT 24 19941068 ps
T1030 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2166555062 Jun 23 05:14:47 PM PDT 24 Jun 23 05:14:48 PM PDT 24 24465384 ps
T1031 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.926243378 Jun 23 05:13:54 PM PDT 24 Jun 23 05:13:55 PM PDT 24 56704365 ps
T1032 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2434964327 Jun 23 05:13:45 PM PDT 24 Jun 23 05:13:48 PM PDT 24 321196460 ps
T1033 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.712804966 Jun 23 05:14:02 PM PDT 24 Jun 23 05:14:03 PM PDT 24 14772952 ps
T1034 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1956775723 Jun 23 05:14:28 PM PDT 24 Jun 23 05:14:30 PM PDT 24 132707215 ps
T1035 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3838002015 Jun 23 05:14:33 PM PDT 24 Jun 23 05:14:35 PM PDT 24 22641555 ps
T1036 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3596059963 Jun 23 05:13:52 PM PDT 24 Jun 23 05:13:54 PM PDT 24 56734433 ps
T1037 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3057141088 Jun 23 05:14:33 PM PDT 24 Jun 23 05:14:35 PM PDT 24 48955333 ps
T169 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3557694060 Jun 23 05:14:09 PM PDT 24 Jun 23 05:14:11 PM PDT 24 68865326 ps
T1038 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3278231533 Jun 23 05:13:48 PM PDT 24 Jun 23 05:13:51 PM PDT 24 637865685 ps
T1039 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3543198107 Jun 23 05:13:53 PM PDT 24 Jun 23 05:13:55 PM PDT 24 67306542 ps
T1040 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1810527553 Jun 23 05:13:52 PM PDT 24 Jun 23 05:13:55 PM PDT 24 193841276 ps
T1041 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.773217627 Jun 23 05:14:39 PM PDT 24 Jun 23 05:14:40 PM PDT 24 47321215 ps
T1042 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.654254784 Jun 23 05:14:17 PM PDT 24 Jun 23 05:14:20 PM PDT 24 88400256 ps
T1043 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3957058025 Jun 23 05:13:46 PM PDT 24 Jun 23 05:14:15 PM PDT 24 3688955921 ps
T178 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2770978954 Jun 23 05:14:30 PM PDT 24 Jun 23 05:14:50 PM PDT 24 299701727 ps
T1044 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1745862035 Jun 23 05:14:16 PM PDT 24 Jun 23 05:14:17 PM PDT 24 146998632 ps
T1045 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.721093522 Jun 23 05:14:02 PM PDT 24 Jun 23 05:14:04 PM PDT 24 783949691 ps
T1046 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2529898538 Jun 23 05:14:27 PM PDT 24 Jun 23 05:14:28 PM PDT 24 25460492 ps
T1047 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2794977455 Jun 23 05:14:28 PM PDT 24 Jun 23 05:14:31 PM PDT 24 139436194 ps
T176 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2186263732 Jun 23 05:14:09 PM PDT 24 Jun 23 05:14:17 PM PDT 24 114261160 ps
T1048 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.507993018 Jun 23 05:14:32 PM PDT 24 Jun 23 05:14:33 PM PDT 24 43434735 ps
T1049 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2972598075 Jun 23 05:14:05 PM PDT 24 Jun 23 05:14:07 PM PDT 24 355767915 ps
T1050 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3071124022 Jun 23 05:14:06 PM PDT 24 Jun 23 05:14:15 PM PDT 24 344783356 ps
T1051 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4141149626 Jun 23 05:13:41 PM PDT 24 Jun 23 05:13:43 PM PDT 24 117324267 ps
T1052 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.709905323 Jun 23 05:13:53 PM PDT 24 Jun 23 05:13:55 PM PDT 24 63972359 ps
T1053 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1927560325 Jun 23 05:14:36 PM PDT 24 Jun 23 05:14:37 PM PDT 24 56820758 ps
T1054 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.586379601 Jun 23 05:13:46 PM PDT 24 Jun 23 05:14:11 PM PDT 24 905963558 ps
T1055 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.508986788 Jun 23 05:14:29 PM PDT 24 Jun 23 05:14:47 PM PDT 24 6213304656 ps
T1056 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.364446248 Jun 23 05:14:13 PM PDT 24 Jun 23 05:14:21 PM PDT 24 276907197 ps
T1057 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.924329100 Jun 23 05:13:48 PM PDT 24 Jun 23 05:13:49 PM PDT 24 14016735 ps
T108 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2599485117 Jun 23 05:13:52 PM PDT 24 Jun 23 05:14:05 PM PDT 24 199728414 ps
T1058 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2783866168 Jun 23 05:13:59 PM PDT 24 Jun 23 05:14:01 PM PDT 24 132046052 ps
T1059 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2903611928 Jun 23 05:14:22 PM PDT 24 Jun 23 05:14:26 PM PDT 24 441045033 ps
T1060 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.145224125 Jun 23 05:13:50 PM PDT 24 Jun 23 05:13:54 PM PDT 24 595518958 ps
T170 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.875206456 Jun 23 05:14:06 PM PDT 24 Jun 23 05:14:11 PM PDT 24 222799158 ps
T1061 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1045415985 Jun 23 05:14:37 PM PDT 24 Jun 23 05:14:38 PM PDT 24 52590688 ps
T1062 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3948864212 Jun 23 05:14:29 PM PDT 24 Jun 23 05:14:31 PM PDT 24 595711812 ps
T1063 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3388292746 Jun 23 05:14:37 PM PDT 24 Jun 23 05:14:39 PM PDT 24 66704141 ps
T1064 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2133789490 Jun 23 05:13:49 PM PDT 24 Jun 23 05:13:50 PM PDT 24 12572867 ps
T1065 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.86805971 Jun 23 05:14:12 PM PDT 24 Jun 23 05:14:15 PM PDT 24 119073860 ps
T1066 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.50373553 Jun 23 05:14:29 PM PDT 24 Jun 23 05:14:34 PM PDT 24 326645792 ps
T1067 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.4214359773 Jun 23 05:13:42 PM PDT 24 Jun 23 05:13:43 PM PDT 24 80475199 ps
T1068 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2394113206 Jun 23 05:14:16 PM PDT 24 Jun 23 05:14:24 PM PDT 24 593988252 ps
T1069 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2594037809 Jun 23 05:14:16 PM PDT 24 Jun 23 05:14:17 PM PDT 24 17894952 ps
T1070 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1318981326 Jun 23 05:14:32 PM PDT 24 Jun 23 05:14:33 PM PDT 24 12855346 ps
T1071 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1070673713 Jun 23 05:14:14 PM PDT 24 Jun 23 05:14:17 PM PDT 24 211637518 ps
T1072 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3103942151 Jun 23 05:14:02 PM PDT 24 Jun 23 05:14:05 PM PDT 24 87789440 ps
T1073 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3100801645 Jun 23 05:14:08 PM PDT 24 Jun 23 05:14:10 PM PDT 24 152283744 ps
T1074 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.80171937 Jun 23 05:13:48 PM PDT 24 Jun 23 05:13:50 PM PDT 24 54832990 ps
T1075 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.763299641 Jun 23 05:13:59 PM PDT 24 Jun 23 05:14:00 PM PDT 24 12107523 ps
T1076 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.922543786 Jun 23 05:14:34 PM PDT 24 Jun 23 05:14:35 PM PDT 24 13822080 ps
T1077 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2655787115 Jun 23 05:14:26 PM PDT 24 Jun 23 05:14:29 PM PDT 24 350414890 ps
T1078 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.471698853 Jun 23 05:14:34 PM PDT 24 Jun 23 05:14:35 PM PDT 24 14230147 ps
T1079 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3295709136 Jun 23 05:13:55 PM PDT 24 Jun 23 05:14:04 PM PDT 24 1712440385 ps
T1080 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2315474694 Jun 23 05:14:27 PM PDT 24 Jun 23 05:14:28 PM PDT 24 16482132 ps

Test location /workspace/coverage/default/19.spi_device_stress_all.517967473
Short name T3
Test name
Test status
Simulation time 27697545087 ps
CPU time 134.66 seconds
Started Jun 23 05:50:40 PM PDT 24
Finished Jun 23 05:52:56 PM PDT 24
Peak memory 249464 kb
Host smart-a658baa8-e06d-4208-802c-b8ac521f31b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517967473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.517967473
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.4256602278
Short name T31
Test name
Test status
Simulation time 85278189565 ps
CPU time 416.42 seconds
Started Jun 23 05:51:43 PM PDT 24
Finished Jun 23 05:58:40 PM PDT 24
Peak memory 263168 kb
Host smart-47abe538-ea47-453b-bb28-2f750c0f67d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256602278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.4256602278
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3306336903
Short name T2
Test name
Test status
Simulation time 104496079443 ps
CPU time 175.41 seconds
Started Jun 23 05:50:39 PM PDT 24
Finished Jun 23 05:53:35 PM PDT 24
Peak memory 265220 kb
Host smart-199d20a7-74a7-4b47-be06-ffd1830fb650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306336903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3306336903
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3490255161
Short name T97
Test name
Test status
Simulation time 6038020907 ps
CPU time 20.65 seconds
Started Jun 23 05:14:08 PM PDT 24
Finished Jun 23 05:14:29 PM PDT 24
Peak memory 216032 kb
Host smart-02af8548-e27c-499d-8cdc-a9c3ab0c646c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490255161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3490255161
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2153537644
Short name T15
Test name
Test status
Simulation time 227686085083 ps
CPU time 1007.5 seconds
Started Jun 23 05:49:50 PM PDT 24
Finished Jun 23 06:06:40 PM PDT 24
Peak memory 281652 kb
Host smart-3037bb70-13ee-41e4-99ce-eabef835e1a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153537644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2153537644
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2030245769
Short name T30
Test name
Test status
Simulation time 16531582940 ps
CPU time 112.99 seconds
Started Jun 23 05:51:45 PM PDT 24
Finished Jun 23 05:53:38 PM PDT 24
Peak memory 241240 kb
Host smart-a24ce120-4b11-4342-afde-37580da1f2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030245769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2030245769
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2347695816
Short name T151
Test name
Test status
Simulation time 71852978331 ps
CPU time 678.86 seconds
Started Jun 23 05:50:18 PM PDT 24
Finished Jun 23 06:01:37 PM PDT 24
Peak memory 282388 kb
Host smart-fab48bcc-d30d-4ade-8d3c-e16005d2629e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347695816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2347695816
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3352022016
Short name T67
Test name
Test status
Simulation time 15736801 ps
CPU time 0.78 seconds
Started Jun 23 05:49:41 PM PDT 24
Finished Jun 23 05:49:42 PM PDT 24
Peak memory 216200 kb
Host smart-14a4c62c-344c-486c-a9ab-4ac2bf1ba708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352022016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3352022016
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3940289378
Short name T45
Test name
Test status
Simulation time 12989487875 ps
CPU time 203.38 seconds
Started Jun 23 05:50:58 PM PDT 24
Finished Jun 23 05:54:22 PM PDT 24
Peak memory 265828 kb
Host smart-771eb47c-9041-42f5-be22-7d3ab40956d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940289378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3940289378
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2546707972
Short name T127
Test name
Test status
Simulation time 5214543011 ps
CPU time 124.54 seconds
Started Jun 23 05:50:55 PM PDT 24
Finished Jun 23 05:53:00 PM PDT 24
Peak memory 261256 kb
Host smart-a4ffa878-aee2-4432-a10d-25a4b36f6048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546707972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2546707972
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.4248930096
Short name T165
Test name
Test status
Simulation time 17015010487 ps
CPU time 137.56 seconds
Started Jun 23 05:51:24 PM PDT 24
Finished Jun 23 05:53:42 PM PDT 24
Peak memory 251376 kb
Host smart-bc945143-0699-4666-9257-e498d2072bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248930096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.4248930096
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2420854635
Short name T212
Test name
Test status
Simulation time 137266237309 ps
CPU time 1115.86 seconds
Started Jun 23 05:49:55 PM PDT 24
Finished Jun 23 06:08:33 PM PDT 24
Peak memory 297988 kb
Host smart-c847bedc-118b-40b6-90eb-f8129830ade0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420854635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2420854635
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2474385646
Short name T66
Test name
Test status
Simulation time 324701488 ps
CPU time 2.46 seconds
Started Jun 23 05:13:58 PM PDT 24
Finished Jun 23 05:14:01 PM PDT 24
Peak memory 216148 kb
Host smart-968bb62c-ecf4-4897-a293-156402a7c4d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474385646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
474385646
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3458446311
Short name T100
Test name
Test status
Simulation time 16227884575 ps
CPU time 47.93 seconds
Started Jun 23 05:49:47 PM PDT 24
Finished Jun 23 05:50:36 PM PDT 24
Peak memory 241180 kb
Host smart-b56bcfe4-8752-4351-b59b-3f00d588ebc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458446311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3458446311
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2606753430
Short name T317
Test name
Test status
Simulation time 22785025 ps
CPU time 0.73 seconds
Started Jun 23 05:50:46 PM PDT 24
Finished Jun 23 05:50:48 PM PDT 24
Peak memory 204952 kb
Host smart-6b4641c4-08a6-48b6-900b-bdabeac88ff4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606753430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2606753430
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1997729735
Short name T14
Test name
Test status
Simulation time 489790864543 ps
CPU time 336.7 seconds
Started Jun 23 05:50:40 PM PDT 24
Finished Jun 23 05:56:19 PM PDT 24
Peak memory 253328 kb
Host smart-05057a6f-ec5c-471c-8694-fac5bdd50da4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997729735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1997729735
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.663779540
Short name T182
Test name
Test status
Simulation time 302269831085 ps
CPU time 758.11 seconds
Started Jun 23 05:50:20 PM PDT 24
Finished Jun 23 06:02:59 PM PDT 24
Peak memory 282232 kb
Host smart-24c95088-ddd8-477c-b37c-637b79f7561a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663779540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.663779540
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1106503897
Short name T120
Test name
Test status
Simulation time 27889749 ps
CPU time 1.99 seconds
Started Jun 23 05:14:19 PM PDT 24
Finished Jun 23 05:14:22 PM PDT 24
Peak memory 207720 kb
Host smart-367abe1c-8d50-48ff-956a-6b4c264dfeb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106503897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1106503897
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.625207212
Short name T49
Test name
Test status
Simulation time 46347288309 ps
CPU time 403.43 seconds
Started Jun 23 05:50:58 PM PDT 24
Finished Jun 23 05:57:42 PM PDT 24
Peak memory 294896 kb
Host smart-ec81fddc-4651-47a6-820e-a13c5e1ca0b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625207212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.625207212
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1041369686
Short name T71
Test name
Test status
Simulation time 601254807 ps
CPU time 1.21 seconds
Started Jun 23 05:49:41 PM PDT 24
Finished Jun 23 05:49:43 PM PDT 24
Peak memory 235484 kb
Host smart-ebefb300-0755-4eae-9573-5c411e1bb564
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041369686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1041369686
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.136480605
Short name T215
Test name
Test status
Simulation time 34433001873 ps
CPU time 141.63 seconds
Started Jun 23 05:51:26 PM PDT 24
Finished Jun 23 05:53:48 PM PDT 24
Peak memory 273016 kb
Host smart-43987583-7fb7-43bd-a71b-1359dfae3252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136480605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.136480605
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1135394574
Short name T44
Test name
Test status
Simulation time 3716490037 ps
CPU time 50.09 seconds
Started Jun 23 05:50:36 PM PDT 24
Finished Jun 23 05:51:26 PM PDT 24
Peak memory 238784 kb
Host smart-d7c75094-2530-49a2-bbbe-0625886a019c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135394574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1135394574
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1972829307
Short name T221
Test name
Test status
Simulation time 21358746373 ps
CPU time 101.63 seconds
Started Jun 23 05:50:39 PM PDT 24
Finished Jun 23 05:52:23 PM PDT 24
Peak memory 265828 kb
Host smart-1a69cbbd-85d3-4abc-881b-f25891b0c457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972829307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1972829307
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.626490177
Short name T157
Test name
Test status
Simulation time 186416339535 ps
CPU time 346.75 seconds
Started Jun 23 05:51:22 PM PDT 24
Finished Jun 23 05:57:10 PM PDT 24
Peak memory 273440 kb
Host smart-613b6cda-7773-4f68-84b9-f96078774246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626490177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.626490177
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4015770229
Short name T1011
Test name
Test status
Simulation time 92237197 ps
CPU time 2.59 seconds
Started Jun 23 05:14:01 PM PDT 24
Finished Jun 23 05:14:04 PM PDT 24
Peak memory 216128 kb
Host smart-f4be8869-5a1b-497c-9275-607e10d0179b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015770229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.4
015770229
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.665339737
Short name T174
Test name
Test status
Simulation time 786046332 ps
CPU time 12.63 seconds
Started Jun 23 05:13:45 PM PDT 24
Finished Jun 23 05:13:58 PM PDT 24
Peak memory 217832 kb
Host smart-2ef9ec91-f9ab-4d52-a8c4-dfa4b8b62ea7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665339737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.665339737
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3566672455
Short name T200
Test name
Test status
Simulation time 75417727528 ps
CPU time 238.64 seconds
Started Jun 23 05:50:11 PM PDT 24
Finished Jun 23 05:54:11 PM PDT 24
Peak memory 256212 kb
Host smart-d7fd78b7-63f9-46a8-adb7-c0003505837e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566672455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3566672455
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2174699366
Short name T81
Test name
Test status
Simulation time 299739476825 ps
CPU time 540.3 seconds
Started Jun 23 05:50:40 PM PDT 24
Finished Jun 23 05:59:42 PM PDT 24
Peak memory 272688 kb
Host smart-cf255b5a-a267-44d7-9493-05a671e56f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174699366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2174699366
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3733823832
Short name T283
Test name
Test status
Simulation time 7034802114 ps
CPU time 98.67 seconds
Started Jun 23 05:51:20 PM PDT 24
Finished Jun 23 05:52:59 PM PDT 24
Peak memory 265776 kb
Host smart-6827960d-639b-4287-bc94-deaa0cc19dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733823832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3733823832
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.216788364
Short name T185
Test name
Test status
Simulation time 46624197301 ps
CPU time 429.17 seconds
Started Jun 23 05:50:45 PM PDT 24
Finished Jun 23 05:57:55 PM PDT 24
Peak memory 253548 kb
Host smart-8c223ca5-8b64-4acf-8183-63d9626a3055
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216788364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.216788364
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1864326537
Short name T484
Test name
Test status
Simulation time 8549313263 ps
CPU time 20.87 seconds
Started Jun 23 05:50:13 PM PDT 24
Finished Jun 23 05:50:35 PM PDT 24
Peak memory 241128 kb
Host smart-e106cd0e-fd5c-4ef5-a0a8-d43d38cd377a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864326537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1864326537
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.686549540
Short name T274
Test name
Test status
Simulation time 3674604105 ps
CPU time 56.94 seconds
Started Jun 23 05:50:26 PM PDT 24
Finished Jun 23 05:51:24 PM PDT 24
Peak memory 250468 kb
Host smart-0f5c51cb-6c8d-4ee3-b346-5d8f90ac907b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686549540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.686549540
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.18029681
Short name T310
Test name
Test status
Simulation time 2982642018 ps
CPU time 18.83 seconds
Started Jun 23 05:50:24 PM PDT 24
Finished Jun 23 05:50:43 PM PDT 24
Peak memory 236376 kb
Host smart-43fc778a-f5cd-4817-a549-276d06cfff51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18029681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.18029681
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3339883556
Short name T292
Test name
Test status
Simulation time 70931246511 ps
CPU time 602.54 seconds
Started Jun 23 05:50:41 PM PDT 24
Finished Jun 23 06:00:45 PM PDT 24
Peak memory 282192 kb
Host smart-a0f53236-d11e-4729-9932-913eabc5524a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339883556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3339883556
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.33096501
Short name T286
Test name
Test status
Simulation time 203501686244 ps
CPU time 390.51 seconds
Started Jun 23 05:51:23 PM PDT 24
Finished Jun 23 05:57:54 PM PDT 24
Peak memory 257604 kb
Host smart-6cf1a2c4-1cb7-42a0-9f0f-1d2be6dc2894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33096501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.33096501
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2148223955
Short name T300
Test name
Test status
Simulation time 24169014796 ps
CPU time 55.99 seconds
Started Jun 23 05:51:45 PM PDT 24
Finished Jun 23 05:52:42 PM PDT 24
Peak memory 237012 kb
Host smart-a231a81b-ef8c-4b3d-9a8f-f3a17feb5751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148223955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2148223955
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1166240862
Short name T105
Test name
Test status
Simulation time 583077092 ps
CPU time 3.84 seconds
Started Jun 23 05:13:52 PM PDT 24
Finished Jun 23 05:13:57 PM PDT 24
Peak memory 216248 kb
Host smart-5cd805f8-3f2d-491b-ac89-39087b23c4d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166240862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
166240862
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.263804849
Short name T92
Test name
Test status
Simulation time 4313380514 ps
CPU time 11.43 seconds
Started Jun 23 05:51:56 PM PDT 24
Finished Jun 23 05:52:08 PM PDT 24
Peak memory 224684 kb
Host smart-9f21fd92-dacf-4509-865c-1186c632cdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263804849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.263804849
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2599485117
Short name T108
Test name
Test status
Simulation time 199728414 ps
CPU time 12.05 seconds
Started Jun 23 05:13:52 PM PDT 24
Finished Jun 23 05:14:05 PM PDT 24
Peak memory 215972 kb
Host smart-411cc7f8-fd89-4b16-891c-948373460d14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599485117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2599485117
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3400552644
Short name T253
Test name
Test status
Simulation time 163359258643 ps
CPU time 273.54 seconds
Started Jun 23 05:49:38 PM PDT 24
Finished Jun 23 05:54:12 PM PDT 24
Peak memory 268780 kb
Host smart-cfe52ab3-e12a-41b8-901e-52a2d09eb748
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400552644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3400552644
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3787741370
Short name T230
Test name
Test status
Simulation time 3178252936 ps
CPU time 44.81 seconds
Started Jun 23 05:50:25 PM PDT 24
Finished Jun 23 05:51:11 PM PDT 24
Peak memory 237092 kb
Host smart-1a83dc75-b6db-4761-b8ee-5c403fa52208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787741370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3787741370
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.706930636
Short name T278
Test name
Test status
Simulation time 128433290136 ps
CPU time 526.2 seconds
Started Jun 23 05:50:57 PM PDT 24
Finished Jun 23 05:59:44 PM PDT 24
Peak memory 266456 kb
Host smart-a7d6379f-9c38-4344-a319-86859f54279c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706930636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.706930636
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2132140885
Short name T289
Test name
Test status
Simulation time 39332017856 ps
CPU time 96.44 seconds
Started Jun 23 05:50:01 PM PDT 24
Finished Jun 23 05:51:39 PM PDT 24
Peak memory 257568 kb
Host smart-3d6ced9d-b02d-4232-87cd-b2f922b5f975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132140885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2132140885
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.713403620
Short name T8
Test name
Test status
Simulation time 18823389775 ps
CPU time 14.4 seconds
Started Jun 23 05:50:27 PM PDT 24
Finished Jun 23 05:50:42 PM PDT 24
Peak memory 224744 kb
Host smart-ece0bb66-d54b-4369-9c79-d07f6c34c748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713403620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.713403620
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3472806875
Short name T82
Test name
Test status
Simulation time 199595691 ps
CPU time 1.41 seconds
Started Jun 23 05:13:46 PM PDT 24
Finished Jun 23 05:13:48 PM PDT 24
Peak memory 207668 kb
Host smart-4117002f-0856-42e3-912e-a1135edd2e1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472806875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3472806875
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1913592889
Short name T94
Test name
Test status
Simulation time 213171733627 ps
CPU time 497.92 seconds
Started Jun 23 05:51:48 PM PDT 24
Finished Jun 23 06:00:07 PM PDT 24
Peak memory 281532 kb
Host smart-59ffb4ea-aed8-4ec4-8b52-a8dcf8bd5c65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913592889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1913592889
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.923213104
Short name T1012
Test name
Test status
Simulation time 57511607 ps
CPU time 3.42 seconds
Started Jun 23 05:13:46 PM PDT 24
Finished Jun 23 05:13:49 PM PDT 24
Peak memory 216144 kb
Host smart-2ea849b2-bd0b-4a8f-b583-fba0befd5e83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923213104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.923213104
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.586379601
Short name T1054
Test name
Test status
Simulation time 905963558 ps
CPU time 24.77 seconds
Started Jun 23 05:13:46 PM PDT 24
Finished Jun 23 05:14:11 PM PDT 24
Peak memory 215920 kb
Host smart-2ef2905e-be83-4af7-9a56-a79109ec09cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586379601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.586379601
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3957058025
Short name T1043
Test name
Test status
Simulation time 3688955921 ps
CPU time 27.88 seconds
Started Jun 23 05:13:46 PM PDT 24
Finished Jun 23 05:14:15 PM PDT 24
Peak memory 207856 kb
Host smart-356ba388-5dca-4621-b3e1-976e259bee9a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957058025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3957058025
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4227107102
Short name T126
Test name
Test status
Simulation time 39578263 ps
CPU time 0.96 seconds
Started Jun 23 05:13:46 PM PDT 24
Finished Jun 23 05:13:48 PM PDT 24
Peak memory 207464 kb
Host smart-d8984fff-c8a6-4ef9-bb42-5506262bd50c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227107102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.4227107102
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2901038362
Short name T978
Test name
Test status
Simulation time 517604542 ps
CPU time 3.79 seconds
Started Jun 23 05:13:42 PM PDT 24
Finished Jun 23 05:13:46 PM PDT 24
Peak memory 218412 kb
Host smart-4ef2348a-7c81-435b-8ed2-088ada7dbe71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901038362 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2901038362
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2434964327
Short name T1032
Test name
Test status
Simulation time 321196460 ps
CPU time 2.37 seconds
Started Jun 23 05:13:45 PM PDT 24
Finished Jun 23 05:13:48 PM PDT 24
Peak memory 215964 kb
Host smart-ef8d731c-9190-4db1-b5e3-ab3930cff20b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434964327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
434964327
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1326145488
Short name T963
Test name
Test status
Simulation time 52531931 ps
CPU time 0.77 seconds
Started Jun 23 05:13:45 PM PDT 24
Finished Jun 23 05:13:46 PM PDT 24
Peak memory 204372 kb
Host smart-2d4aaa8f-1b8f-4d74-b0e3-6b709d66a26e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326145488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
326145488
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2727068281
Short name T1001
Test name
Test status
Simulation time 17572586 ps
CPU time 1.24 seconds
Started Jun 23 05:13:45 PM PDT 24
Finished Jun 23 05:13:47 PM PDT 24
Peak memory 215952 kb
Host smart-8005bec1-ad3e-42e7-9fd8-a90134575d5b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727068281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2727068281
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2133789490
Short name T1064
Test name
Test status
Simulation time 12572867 ps
CPU time 0.67 seconds
Started Jun 23 05:13:49 PM PDT 24
Finished Jun 23 05:13:50 PM PDT 24
Peak memory 204280 kb
Host smart-4b033116-ff9c-405f-a6b8-659bbdf7ea3a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133789490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2133789490
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2742487104
Short name T1014
Test name
Test status
Simulation time 337415068 ps
CPU time 3 seconds
Started Jun 23 05:13:46 PM PDT 24
Finished Jun 23 05:13:50 PM PDT 24
Peak memory 215948 kb
Host smart-e6122c6e-2cfd-429a-ae17-8b8a5c4bf07f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742487104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2742487104
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.327259402
Short name T65
Test name
Test status
Simulation time 431141745 ps
CPU time 3.33 seconds
Started Jun 23 05:13:42 PM PDT 24
Finished Jun 23 05:13:46 PM PDT 24
Peak memory 216136 kb
Host smart-e0677067-409a-48e6-b547-80bbab49eef5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327259402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.327259402
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1434211789
Short name T1027
Test name
Test status
Simulation time 259028682 ps
CPU time 7.5 seconds
Started Jun 23 05:13:44 PM PDT 24
Finished Jun 23 05:13:51 PM PDT 24
Peak memory 207760 kb
Host smart-0fd9796f-7641-42ad-84a7-31530e58bd4a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434211789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1434211789
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2363920603
Short name T1005
Test name
Test status
Simulation time 2614050134 ps
CPU time 34.31 seconds
Started Jun 23 05:13:46 PM PDT 24
Finished Jun 23 05:14:21 PM PDT 24
Peak memory 207740 kb
Host smart-4738e76d-5516-44d4-8029-d96f66a9e0c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363920603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2363920603
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1911520960
Short name T84
Test name
Test status
Simulation time 74913471 ps
CPU time 1.34 seconds
Started Jun 23 05:13:49 PM PDT 24
Finished Jun 23 05:13:51 PM PDT 24
Peak memory 207696 kb
Host smart-1fdcd175-a320-4ef4-9915-0dac0fc53813
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911520960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1911520960
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.145224125
Short name T1060
Test name
Test status
Simulation time 595518958 ps
CPU time 3.63 seconds
Started Jun 23 05:13:50 PM PDT 24
Finished Jun 23 05:13:54 PM PDT 24
Peak memory 218292 kb
Host smart-f0bf1b81-0f3d-41af-9eb0-f9bba8395cd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145224125 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.145224125
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3576480233
Short name T115
Test name
Test status
Simulation time 36419456 ps
CPU time 2.49 seconds
Started Jun 23 05:13:46 PM PDT 24
Finished Jun 23 05:13:49 PM PDT 24
Peak memory 215940 kb
Host smart-7abc8c71-c6a9-44d5-87b3-ba899ffdf7aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576480233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
576480233
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.4214359773
Short name T1067
Test name
Test status
Simulation time 80475199 ps
CPU time 0.75 seconds
Started Jun 23 05:13:42 PM PDT 24
Finished Jun 23 05:13:43 PM PDT 24
Peak memory 204360 kb
Host smart-6879e5eb-11a0-4e04-b90b-75a81ceb86bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214359773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.4
214359773
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4141149626
Short name T1051
Test name
Test status
Simulation time 117324267 ps
CPU time 2.05 seconds
Started Jun 23 05:13:41 PM PDT 24
Finished Jun 23 05:13:43 PM PDT 24
Peak memory 215956 kb
Host smart-21d59c09-6f93-4bca-b039-871dccf389a3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141149626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.4141149626
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2442087018
Short name T995
Test name
Test status
Simulation time 36100570 ps
CPU time 0.69 seconds
Started Jun 23 05:13:41 PM PDT 24
Finished Jun 23 05:13:42 PM PDT 24
Peak memory 204292 kb
Host smart-55a0ec2b-6d48-4da8-89c5-c4dbc4c42e5b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442087018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2442087018
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1170528875
Short name T149
Test name
Test status
Simulation time 68676134 ps
CPU time 1.76 seconds
Started Jun 23 05:13:47 PM PDT 24
Finished Jun 23 05:13:49 PM PDT 24
Peak memory 215956 kb
Host smart-21cbbb65-2e20-43d1-af1a-04a0ddd73655
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170528875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1170528875
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1736996650
Short name T1003
Test name
Test status
Simulation time 1046755132 ps
CPU time 7.98 seconds
Started Jun 23 05:13:41 PM PDT 24
Finished Jun 23 05:13:50 PM PDT 24
Peak memory 216912 kb
Host smart-c0fa1f38-a84c-4825-bd63-37ef8bf24610
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736996650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1736996650
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2531832834
Short name T985
Test name
Test status
Simulation time 123664243 ps
CPU time 3.55 seconds
Started Jun 23 05:14:14 PM PDT 24
Finished Jun 23 05:14:18 PM PDT 24
Peak memory 218312 kb
Host smart-09cb4bc0-8020-456d-b7aa-1104b9bbf590
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531832834 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2531832834
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3929302351
Short name T141
Test name
Test status
Simulation time 80418252 ps
CPU time 2.43 seconds
Started Jun 23 05:14:11 PM PDT 24
Finished Jun 23 05:14:14 PM PDT 24
Peak memory 215844 kb
Host smart-5a8dc7b7-b27c-4da2-acb6-3219627f4a32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929302351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3929302351
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1626239370
Short name T1009
Test name
Test status
Simulation time 51713022 ps
CPU time 0.72 seconds
Started Jun 23 05:14:15 PM PDT 24
Finished Jun 23 05:14:16 PM PDT 24
Peak memory 204316 kb
Host smart-70baa752-22b2-4036-99de-509370a53b6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626239370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1626239370
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2480647088
Short name T140
Test name
Test status
Simulation time 44077878 ps
CPU time 2.88 seconds
Started Jun 23 05:14:11 PM PDT 24
Finished Jun 23 05:14:14 PM PDT 24
Peak memory 215940 kb
Host smart-02b01be9-a4c1-4b37-b738-f7f2dde95dde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480647088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2480647088
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1063973262
Short name T107
Test name
Test status
Simulation time 45834973 ps
CPU time 2.72 seconds
Started Jun 23 05:14:07 PM PDT 24
Finished Jun 23 05:14:11 PM PDT 24
Peak memory 215916 kb
Host smart-d8c3dfc5-50d3-4194-9b3b-ed5ca0f41697
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063973262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1063973262
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2186263732
Short name T176
Test name
Test status
Simulation time 114261160 ps
CPU time 7.15 seconds
Started Jun 23 05:14:09 PM PDT 24
Finished Jun 23 05:14:17 PM PDT 24
Peak memory 215868 kb
Host smart-8fcc7ad7-e2fb-44c7-86ed-f645c4ae2ca3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186263732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2186263732
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3634848347
Short name T997
Test name
Test status
Simulation time 79625171 ps
CPU time 1.63 seconds
Started Jun 23 05:14:15 PM PDT 24
Finished Jun 23 05:14:17 PM PDT 24
Peak memory 215968 kb
Host smart-872bcc26-e897-4890-87ad-3841da785a46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634848347 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3634848347
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.86805971
Short name T1065
Test name
Test status
Simulation time 119073860 ps
CPU time 2.56 seconds
Started Jun 23 05:14:12 PM PDT 24
Finished Jun 23 05:14:15 PM PDT 24
Peak memory 215940 kb
Host smart-f37fb493-1e72-4279-b699-417a19b640a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86805971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.86805971
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2990574137
Short name T1015
Test name
Test status
Simulation time 43349550 ps
CPU time 0.72 seconds
Started Jun 23 05:14:13 PM PDT 24
Finished Jun 23 05:14:14 PM PDT 24
Peak memory 204676 kb
Host smart-96475734-f6ef-445e-a610-4ad93d330c74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990574137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2990574137
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2933858702
Short name T988
Test name
Test status
Simulation time 589562948 ps
CPU time 4.04 seconds
Started Jun 23 05:14:13 PM PDT 24
Finished Jun 23 05:14:17 PM PDT 24
Peak memory 215920 kb
Host smart-8ab5aaa4-6db0-4fd6-bf88-6658d2fc00c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933858702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2933858702
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1070673713
Short name T1071
Test name
Test status
Simulation time 211637518 ps
CPU time 3.48 seconds
Started Jun 23 05:14:14 PM PDT 24
Finished Jun 23 05:14:17 PM PDT 24
Peak memory 216160 kb
Host smart-305f98c9-c9c4-414d-a9c3-1d2352dd0939
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070673713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1070673713
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.196354655
Short name T171
Test name
Test status
Simulation time 402607771 ps
CPU time 6.47 seconds
Started Jun 23 05:14:13 PM PDT 24
Finished Jun 23 05:14:19 PM PDT 24
Peak memory 216468 kb
Host smart-e9a616be-f64b-471c-ac71-ed9a16457e85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196354655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.196354655
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4094086140
Short name T1007
Test name
Test status
Simulation time 111267221 ps
CPU time 2 seconds
Started Jun 23 05:14:18 PM PDT 24
Finished Jun 23 05:14:20 PM PDT 24
Peak memory 217060 kb
Host smart-51e2ab43-2098-4be7-97c8-e86cc5bc0414
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094086140 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.4094086140
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3580217186
Short name T124
Test name
Test status
Simulation time 36860305 ps
CPU time 2.26 seconds
Started Jun 23 05:14:17 PM PDT 24
Finished Jun 23 05:14:19 PM PDT 24
Peak memory 215892 kb
Host smart-c9c579d7-56bb-4cbc-a23b-8b2157af3976
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580217186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3580217186
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.337820501
Short name T1029
Test name
Test status
Simulation time 19941068 ps
CPU time 0.79 seconds
Started Jun 23 05:14:11 PM PDT 24
Finished Jun 23 05:14:13 PM PDT 24
Peak memory 204352 kb
Host smart-1333b4f1-9ac2-4f7b-8873-9a193f2966ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337820501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.337820501
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.190557444
Short name T972
Test name
Test status
Simulation time 220057959 ps
CPU time 3.51 seconds
Started Jun 23 05:14:17 PM PDT 24
Finished Jun 23 05:14:21 PM PDT 24
Peak memory 215940 kb
Host smart-48fdb76c-740a-4b63-bc47-6bc30549b7c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190557444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.190557444
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1291606499
Short name T103
Test name
Test status
Simulation time 243107356 ps
CPU time 4.22 seconds
Started Jun 23 05:14:12 PM PDT 24
Finished Jun 23 05:14:17 PM PDT 24
Peak memory 216108 kb
Host smart-6bf695d1-8284-4988-bb15-bd22577485b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291606499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1291606499
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.364446248
Short name T1056
Test name
Test status
Simulation time 276907197 ps
CPU time 7.76 seconds
Started Jun 23 05:14:13 PM PDT 24
Finished Jun 23 05:14:21 PM PDT 24
Peak memory 215892 kb
Host smart-360fc4d6-4f42-4fd1-aed0-4645755cf920
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364446248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.364446248
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.485946857
Short name T979
Test name
Test status
Simulation time 56699423 ps
CPU time 3.34 seconds
Started Jun 23 05:14:19 PM PDT 24
Finished Jun 23 05:14:22 PM PDT 24
Peak memory 217800 kb
Host smart-4a039878-706a-4707-a628-8c355b4c7ac3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485946857 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.485946857
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2594037809
Short name T1069
Test name
Test status
Simulation time 17894952 ps
CPU time 0.79 seconds
Started Jun 23 05:14:16 PM PDT 24
Finished Jun 23 05:14:17 PM PDT 24
Peak memory 204644 kb
Host smart-d42d0dcb-cae6-4a6a-ad77-9fcb32f985c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594037809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2594037809
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.896236090
Short name T975
Test name
Test status
Simulation time 69098063 ps
CPU time 4.44 seconds
Started Jun 23 05:14:17 PM PDT 24
Finished Jun 23 05:14:22 PM PDT 24
Peak memory 215900 kb
Host smart-41d9e9e1-b7e2-4dcb-8889-8d173a7d17de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896236090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.896236090
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1684202739
Short name T102
Test name
Test status
Simulation time 115758091 ps
CPU time 3.47 seconds
Started Jun 23 05:14:16 PM PDT 24
Finished Jun 23 05:14:20 PM PDT 24
Peak memory 216132 kb
Host smart-d3beea7f-e3a2-422b-952d-2ec690265e86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684202739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1684202739
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2394113206
Short name T1068
Test name
Test status
Simulation time 593988252 ps
CPU time 8.02 seconds
Started Jun 23 05:14:16 PM PDT 24
Finished Jun 23 05:14:24 PM PDT 24
Peak memory 215832 kb
Host smart-b5e3bfd8-1159-4744-9e9f-48934001b7ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394113206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2394113206
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3948864212
Short name T1062
Test name
Test status
Simulation time 595711812 ps
CPU time 1.66 seconds
Started Jun 23 05:14:29 PM PDT 24
Finished Jun 23 05:14:31 PM PDT 24
Peak memory 215968 kb
Host smart-b1ba731b-ba8f-4dc9-8140-c58e0cdd3804
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948864212 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3948864212
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1217759406
Short name T123
Test name
Test status
Simulation time 79579416 ps
CPU time 2.18 seconds
Started Jun 23 05:14:22 PM PDT 24
Finished Jun 23 05:14:25 PM PDT 24
Peak memory 216000 kb
Host smart-b6ec2208-5337-4391-a79a-a1729a4685b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217759406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1217759406
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1745862035
Short name T1044
Test name
Test status
Simulation time 146998632 ps
CPU time 0.72 seconds
Started Jun 23 05:14:16 PM PDT 24
Finished Jun 23 05:14:17 PM PDT 24
Peak memory 204332 kb
Host smart-e1269b51-92db-4cd7-be16-59c10ec438be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745862035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1745862035
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2903611928
Short name T1059
Test name
Test status
Simulation time 441045033 ps
CPU time 4.24 seconds
Started Jun 23 05:14:22 PM PDT 24
Finished Jun 23 05:14:26 PM PDT 24
Peak memory 215952 kb
Host smart-d803c44f-ef2c-473e-a193-4bc4e8ed391d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903611928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2903611928
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.654254784
Short name T1042
Test name
Test status
Simulation time 88400256 ps
CPU time 2.36 seconds
Started Jun 23 05:14:17 PM PDT 24
Finished Jun 23 05:14:20 PM PDT 24
Peak memory 216152 kb
Host smart-9db964ab-0359-47c5-b439-7351ab71d660
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654254784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.654254784
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.554913030
Short name T998
Test name
Test status
Simulation time 1440604172 ps
CPU time 8.7 seconds
Started Jun 23 05:14:18 PM PDT 24
Finished Jun 23 05:14:27 PM PDT 24
Peak memory 216140 kb
Host smart-7e7a924a-7dad-4b09-b110-7b669c539ffd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554913030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.554913030
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3209947826
Short name T112
Test name
Test status
Simulation time 485529018 ps
CPU time 2.65 seconds
Started Jun 23 05:14:24 PM PDT 24
Finished Jun 23 05:14:27 PM PDT 24
Peak memory 217136 kb
Host smart-12dfcf56-3f40-4a23-8e71-fe72a72c8e5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209947826 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3209947826
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1338538713
Short name T121
Test name
Test status
Simulation time 196117538 ps
CPU time 2.87 seconds
Started Jun 23 05:14:24 PM PDT 24
Finished Jun 23 05:14:27 PM PDT 24
Peak memory 215916 kb
Host smart-5318e35a-0f1a-45a2-af67-d90c7c2087f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338538713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1338538713
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2169490841
Short name T956
Test name
Test status
Simulation time 51309835 ps
CPU time 0.79 seconds
Started Jun 23 05:14:22 PM PDT 24
Finished Jun 23 05:14:23 PM PDT 24
Peak memory 204648 kb
Host smart-11992a92-ad5d-4b8d-9ab9-80f4311bbcee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169490841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2169490841
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2389119727
Short name T986
Test name
Test status
Simulation time 153807751 ps
CPU time 4.06 seconds
Started Jun 23 05:14:21 PM PDT 24
Finished Jun 23 05:14:25 PM PDT 24
Peak memory 215960 kb
Host smart-ed92fc63-4503-40ed-a778-13bb4197b3d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389119727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2389119727
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1018592388
Short name T996
Test name
Test status
Simulation time 569629498 ps
CPU time 4.64 seconds
Started Jun 23 05:14:22 PM PDT 24
Finished Jun 23 05:14:27 PM PDT 24
Peak memory 216116 kb
Host smart-5915af0d-b6d6-4bca-a523-e2e9ce73454c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018592388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1018592388
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2417882216
Short name T173
Test name
Test status
Simulation time 1243672170 ps
CPU time 16.45 seconds
Started Jun 23 05:14:24 PM PDT 24
Finished Jun 23 05:14:41 PM PDT 24
Peak memory 216164 kb
Host smart-a92e3f7f-0d9d-45a4-9b2e-d34d7cffbb68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417882216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2417882216
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2655787115
Short name T1077
Test name
Test status
Simulation time 350414890 ps
CPU time 2.64 seconds
Started Jun 23 05:14:26 PM PDT 24
Finished Jun 23 05:14:29 PM PDT 24
Peak memory 217960 kb
Host smart-43bd5665-7ecd-4391-ae83-e71ce7a3b413
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655787115 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2655787115
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3453379776
Short name T1002
Test name
Test status
Simulation time 21503075 ps
CPU time 1.54 seconds
Started Jun 23 05:14:24 PM PDT 24
Finished Jun 23 05:14:26 PM PDT 24
Peak memory 215988 kb
Host smart-fb8711a3-ac6d-4a65-85fe-eac1118f3912
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453379776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3453379776
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1398941433
Short name T983
Test name
Test status
Simulation time 23297101 ps
CPU time 0.73 seconds
Started Jun 23 05:14:22 PM PDT 24
Finished Jun 23 05:14:23 PM PDT 24
Peak memory 204356 kb
Host smart-2f34d740-1188-4904-b5fa-8dd169d3e1ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398941433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1398941433
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.50373553
Short name T1066
Test name
Test status
Simulation time 326645792 ps
CPU time 4.08 seconds
Started Jun 23 05:14:29 PM PDT 24
Finished Jun 23 05:14:34 PM PDT 24
Peak memory 215952 kb
Host smart-6e3e0894-94c5-4c75-b743-911700961170
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50373553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sp
i_device_same_csr_outstanding.50373553
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1098823779
Short name T96
Test name
Test status
Simulation time 359840673 ps
CPU time 2.83 seconds
Started Jun 23 05:14:21 PM PDT 24
Finished Jun 23 05:14:25 PM PDT 24
Peak memory 216340 kb
Host smart-8071b830-e1e9-4f80-b52a-4b624f8760ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098823779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1098823779
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.508986788
Short name T1055
Test name
Test status
Simulation time 6213304656 ps
CPU time 17.24 seconds
Started Jun 23 05:14:29 PM PDT 24
Finished Jun 23 05:14:47 PM PDT 24
Peak memory 216040 kb
Host smart-3ac33548-1ce0-4a50-befb-699788fa5faf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508986788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.508986788
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2284941162
Short name T1021
Test name
Test status
Simulation time 38455254 ps
CPU time 2.59 seconds
Started Jun 23 05:14:31 PM PDT 24
Finished Jun 23 05:14:34 PM PDT 24
Peak memory 217456 kb
Host smart-7915836a-b984-4b38-83c9-bba2091b8cfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284941162 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2284941162
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2864313931
Short name T1010
Test name
Test status
Simulation time 502683211 ps
CPU time 3.13 seconds
Started Jun 23 05:14:22 PM PDT 24
Finished Jun 23 05:14:25 PM PDT 24
Peak memory 215992 kb
Host smart-5d652b7c-51f4-4605-9b5c-00fed17ba7d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864313931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2864313931
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2489838340
Short name T1025
Test name
Test status
Simulation time 37393963 ps
CPU time 0.73 seconds
Started Jun 23 05:14:23 PM PDT 24
Finished Jun 23 05:14:24 PM PDT 24
Peak memory 204368 kb
Host smart-af79983a-292d-4c85-8169-e71f1ce0cb3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489838340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2489838340
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2492062308
Short name T139
Test name
Test status
Simulation time 162227438 ps
CPU time 4.26 seconds
Started Jun 23 05:14:25 PM PDT 24
Finished Jun 23 05:14:30 PM PDT 24
Peak memory 215904 kb
Host smart-3bfa03cd-9179-4256-9b9f-c83b8c460301
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492062308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2492062308
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3231643467
Short name T1024
Test name
Test status
Simulation time 212747682 ps
CPU time 1.59 seconds
Started Jun 23 05:14:22 PM PDT 24
Finished Jun 23 05:14:24 PM PDT 24
Peak memory 216116 kb
Host smart-db0eb39d-943e-4fe9-86a9-1c37612b6010
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231643467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3231643467
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1333730653
Short name T999
Test name
Test status
Simulation time 1302697316 ps
CPU time 9.48 seconds
Started Jun 23 05:14:29 PM PDT 24
Finished Jun 23 05:14:39 PM PDT 24
Peak memory 215944 kb
Host smart-845cd161-12a2-451d-b573-0de478e53d9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333730653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1333730653
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3058368761
Short name T64
Test name
Test status
Simulation time 27818895 ps
CPU time 1.74 seconds
Started Jun 23 05:14:30 PM PDT 24
Finished Jun 23 05:14:32 PM PDT 24
Peak memory 217184 kb
Host smart-6986aa7f-5376-4013-b63b-39e9c413b934
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058368761 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3058368761
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.110320016
Short name T1000
Test name
Test status
Simulation time 40956867 ps
CPU time 1.32 seconds
Started Jun 23 05:14:28 PM PDT 24
Finished Jun 23 05:14:30 PM PDT 24
Peak memory 215948 kb
Host smart-597efcb2-e2aa-4e07-9c18-664889c43f64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110320016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.110320016
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2270095533
Short name T994
Test name
Test status
Simulation time 108778760 ps
CPU time 0.73 seconds
Started Jun 23 05:14:28 PM PDT 24
Finished Jun 23 05:14:30 PM PDT 24
Peak memory 204352 kb
Host smart-70123d12-a580-4e7c-b4f7-3c0c122fda4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270095533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2270095533
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3279924853
Short name T981
Test name
Test status
Simulation time 207125457 ps
CPU time 4.7 seconds
Started Jun 23 05:14:28 PM PDT 24
Finished Jun 23 05:14:34 PM PDT 24
Peak memory 215984 kb
Host smart-360254f6-cf23-421b-ab18-0cc64c90484d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279924853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3279924853
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3057141088
Short name T1037
Test name
Test status
Simulation time 48955333 ps
CPU time 1.58 seconds
Started Jun 23 05:14:33 PM PDT 24
Finished Jun 23 05:14:35 PM PDT 24
Peak memory 216112 kb
Host smart-4dd1fae0-2dfc-4f75-833c-5f528ad46693
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057141088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3057141088
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3844346438
Short name T1013
Test name
Test status
Simulation time 710042664 ps
CPU time 13.3 seconds
Started Jun 23 05:14:30 PM PDT 24
Finished Jun 23 05:14:44 PM PDT 24
Peak memory 216000 kb
Host smart-6d431f23-93de-40ed-8d25-22e35a79cd7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844346438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3844346438
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.9511134
Short name T1016
Test name
Test status
Simulation time 25400583 ps
CPU time 1.64 seconds
Started Jun 23 05:14:32 PM PDT 24
Finished Jun 23 05:14:34 PM PDT 24
Peak memory 216972 kb
Host smart-1a3b2d03-90c0-4e54-9713-8fda958c4af7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9511134 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.9511134
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.892292528
Short name T968
Test name
Test status
Simulation time 20102497 ps
CPU time 1.3 seconds
Started Jun 23 05:14:28 PM PDT 24
Finished Jun 23 05:14:30 PM PDT 24
Peak memory 207808 kb
Host smart-27afe9dd-92e7-4c15-bd11-1e247d98c105
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892292528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.892292528
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1532970665
Short name T977
Test name
Test status
Simulation time 43962480 ps
CPU time 0.68 seconds
Started Jun 23 05:14:28 PM PDT 24
Finished Jun 23 05:14:30 PM PDT 24
Peak memory 204368 kb
Host smart-2b9dac81-da6b-4be2-85f3-7f86d78879be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532970665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1532970665
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2794977455
Short name T1047
Test name
Test status
Simulation time 139436194 ps
CPU time 2 seconds
Started Jun 23 05:14:28 PM PDT 24
Finished Jun 23 05:14:31 PM PDT 24
Peak memory 207748 kb
Host smart-5d3920f7-a283-4f6e-9572-a7d80336aa39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794977455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2794977455
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.731715327
Short name T109
Test name
Test status
Simulation time 402985473 ps
CPU time 3.85 seconds
Started Jun 23 05:14:28 PM PDT 24
Finished Jun 23 05:14:33 PM PDT 24
Peak memory 216016 kb
Host smart-4caa9e89-8a37-4810-a866-4a2d44baf83e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731715327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.731715327
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2770978954
Short name T178
Test name
Test status
Simulation time 299701727 ps
CPU time 19.89 seconds
Started Jun 23 05:14:30 PM PDT 24
Finished Jun 23 05:14:50 PM PDT 24
Peak memory 216004 kb
Host smart-c952341b-95f4-48f6-8435-827252282c76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770978954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2770978954
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2099294691
Short name T959
Test name
Test status
Simulation time 553193671 ps
CPU time 8.04 seconds
Started Jun 23 05:13:47 PM PDT 24
Finished Jun 23 05:13:55 PM PDT 24
Peak memory 215940 kb
Host smart-95db2015-c64b-4be3-82db-0957fa2960b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099294691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2099294691
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2915890245
Short name T147
Test name
Test status
Simulation time 7209828178 ps
CPU time 25.58 seconds
Started Jun 23 05:13:52 PM PDT 24
Finished Jun 23 05:14:18 PM PDT 24
Peak memory 215988 kb
Host smart-dbd0b07e-b702-4b9b-9de4-a257bf2a08ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915890245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2915890245
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2988020471
Short name T1028
Test name
Test status
Simulation time 42671885 ps
CPU time 2.96 seconds
Started Jun 23 05:13:47 PM PDT 24
Finished Jun 23 05:13:51 PM PDT 24
Peak memory 217572 kb
Host smart-84ff46b1-6b3d-4f3e-89db-a4a344df3f84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988020471 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2988020471
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.658254229
Short name T118
Test name
Test status
Simulation time 38645971 ps
CPU time 1.29 seconds
Started Jun 23 05:13:50 PM PDT 24
Finished Jun 23 05:13:51 PM PDT 24
Peak memory 207668 kb
Host smart-3b7a1d90-e76a-42cf-81f4-e6a077ea32de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658254229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.658254229
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2017739341
Short name T993
Test name
Test status
Simulation time 18765258 ps
CPU time 0.67 seconds
Started Jun 23 05:13:48 PM PDT 24
Finished Jun 23 05:13:49 PM PDT 24
Peak memory 204652 kb
Host smart-0dcb25e3-8980-4bdc-a9fb-eccb1f4d634b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017739341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
017739341
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.80171937
Short name T1074
Test name
Test status
Simulation time 54832990 ps
CPU time 1.68 seconds
Started Jun 23 05:13:48 PM PDT 24
Finished Jun 23 05:13:50 PM PDT 24
Peak memory 215972 kb
Host smart-51db7f15-51f1-46d7-bc7d-398e77798d3c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80171937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi
_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_d
evice_mem_partial_access.80171937
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.924329100
Short name T1057
Test name
Test status
Simulation time 14016735 ps
CPU time 0.7 seconds
Started Jun 23 05:13:48 PM PDT 24
Finished Jun 23 05:13:49 PM PDT 24
Peak memory 204296 kb
Host smart-73f36ed9-cdaf-429b-8d6d-8fd1ead710ad
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924329100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.924329100
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3278231533
Short name T1038
Test name
Test status
Simulation time 637865685 ps
CPU time 1.99 seconds
Started Jun 23 05:13:48 PM PDT 24
Finished Jun 23 05:13:51 PM PDT 24
Peak memory 215952 kb
Host smart-99076f0c-c412-4457-996d-5de808ee7538
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278231533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3278231533
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.414166412
Short name T101
Test name
Test status
Simulation time 311197241 ps
CPU time 2.31 seconds
Started Jun 23 05:13:49 PM PDT 24
Finished Jun 23 05:13:52 PM PDT 24
Peak memory 216100 kb
Host smart-f994ca2f-ba5b-42ee-a8dd-c2e1a781c4e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414166412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.414166412
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2312076707
Short name T98
Test name
Test status
Simulation time 7241289357 ps
CPU time 17.6 seconds
Started Jun 23 05:13:48 PM PDT 24
Finished Jun 23 05:14:06 PM PDT 24
Peak memory 215980 kb
Host smart-a8f94e38-116f-4e37-a006-6da2909bde31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312076707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2312076707
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2885761126
Short name T990
Test name
Test status
Simulation time 31117805 ps
CPU time 0.79 seconds
Started Jun 23 05:14:29 PM PDT 24
Finished Jun 23 05:14:31 PM PDT 24
Peak memory 204372 kb
Host smart-18243cd3-91d2-41ae-b643-5426bfb7f191
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885761126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2885761126
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2529898538
Short name T1046
Test name
Test status
Simulation time 25460492 ps
CPU time 0.73 seconds
Started Jun 23 05:14:27 PM PDT 24
Finished Jun 23 05:14:28 PM PDT 24
Peak memory 204372 kb
Host smart-769813cb-b36d-4703-a542-a656b230b780
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529898538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2529898538
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2315474694
Short name T1080
Test name
Test status
Simulation time 16482132 ps
CPU time 0.71 seconds
Started Jun 23 05:14:27 PM PDT 24
Finished Jun 23 05:14:28 PM PDT 24
Peak memory 204564 kb
Host smart-99db6c3e-6cff-4520-bb4f-b44ce4654a18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315474694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2315474694
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4016865550
Short name T982
Test name
Test status
Simulation time 57598247 ps
CPU time 0.77 seconds
Started Jun 23 05:14:30 PM PDT 24
Finished Jun 23 05:14:31 PM PDT 24
Peak memory 204380 kb
Host smart-092835d2-5149-4cce-acdb-059f951b3466
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016865550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
4016865550
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2513695548
Short name T1026
Test name
Test status
Simulation time 11791036 ps
CPU time 0.75 seconds
Started Jun 23 05:14:31 PM PDT 24
Finished Jun 23 05:14:32 PM PDT 24
Peak memory 204352 kb
Host smart-2f9dec6d-144c-4c8c-8418-080ec28999fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513695548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2513695548
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3094183260
Short name T961
Test name
Test status
Simulation time 11867838 ps
CPU time 0.71 seconds
Started Jun 23 05:14:28 PM PDT 24
Finished Jun 23 05:14:29 PM PDT 24
Peak memory 204348 kb
Host smart-a444e072-4d6d-40e2-af66-0f180441cab8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094183260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3094183260
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1956775723
Short name T1034
Test name
Test status
Simulation time 132707215 ps
CPU time 0.78 seconds
Started Jun 23 05:14:28 PM PDT 24
Finished Jun 23 05:14:30 PM PDT 24
Peak memory 204360 kb
Host smart-21218352-1e52-42b0-9f01-bdfcad68c596
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956775723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1956775723
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.423365202
Short name T1023
Test name
Test status
Simulation time 19498728 ps
CPU time 0.76 seconds
Started Jun 23 05:14:30 PM PDT 24
Finished Jun 23 05:14:32 PM PDT 24
Peak memory 204684 kb
Host smart-5e1a9fa1-8950-45f8-899f-8c618fd75605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423365202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.423365202
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1318981326
Short name T1070
Test name
Test status
Simulation time 12855346 ps
CPU time 0.78 seconds
Started Jun 23 05:14:32 PM PDT 24
Finished Jun 23 05:14:33 PM PDT 24
Peak memory 204672 kb
Host smart-85c6fc0a-6b85-4e9f-bb5d-a638855b15e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318981326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1318981326
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3318233072
Short name T967
Test name
Test status
Simulation time 42903596 ps
CPU time 0.7 seconds
Started Jun 23 05:14:28 PM PDT 24
Finished Jun 23 05:14:30 PM PDT 24
Peak memory 204340 kb
Host smart-77351ab2-88fb-422d-b7c4-e3f493e65e38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318233072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3318233072
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3004874041
Short name T122
Test name
Test status
Simulation time 2473987983 ps
CPU time 9.3 seconds
Started Jun 23 05:13:53 PM PDT 24
Finished Jun 23 05:14:03 PM PDT 24
Peak memory 207720 kb
Host smart-955a9dd7-c559-425e-ac0f-f2f02971c635
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004874041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3004874041
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.977841935
Short name T119
Test name
Test status
Simulation time 1632521987 ps
CPU time 27.27 seconds
Started Jun 23 05:13:52 PM PDT 24
Finished Jun 23 05:14:20 PM PDT 24
Peak memory 207716 kb
Host smart-098f9985-3f18-41cd-a38f-691ea10389bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977841935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.977841935
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.709905323
Short name T1052
Test name
Test status
Simulation time 63972359 ps
CPU time 0.92 seconds
Started Jun 23 05:13:53 PM PDT 24
Finished Jun 23 05:13:55 PM PDT 24
Peak memory 207460 kb
Host smart-f3f79950-cd3d-4a9c-89c0-c9034185a421
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709905323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.709905323
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3743313158
Short name T984
Test name
Test status
Simulation time 78343012 ps
CPU time 2.01 seconds
Started Jun 23 05:13:54 PM PDT 24
Finished Jun 23 05:13:56 PM PDT 24
Peak memory 216048 kb
Host smart-8ae6ba8e-877f-4009-a659-13238dd7142e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743313158 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3743313158
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3543198107
Short name T1039
Test name
Test status
Simulation time 67306542 ps
CPU time 1.87 seconds
Started Jun 23 05:13:53 PM PDT 24
Finished Jun 23 05:13:55 PM PDT 24
Peak memory 207764 kb
Host smart-a8c636a4-5e58-45dc-ae11-9b3591fdc9c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543198107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
543198107
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3293697321
Short name T969
Test name
Test status
Simulation time 13826800 ps
CPU time 0.7 seconds
Started Jun 23 05:13:52 PM PDT 24
Finished Jun 23 05:13:53 PM PDT 24
Peak memory 203948 kb
Host smart-fb51a0c7-fd83-4afd-961c-0c2c73c306dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293697321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
293697321
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1889415354
Short name T1022
Test name
Test status
Simulation time 85023355 ps
CPU time 1.18 seconds
Started Jun 23 05:13:53 PM PDT 24
Finished Jun 23 05:13:54 PM PDT 24
Peak memory 215900 kb
Host smart-6ca0322d-1a8e-402e-a659-3531cebb46d4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889415354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1889415354
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3904775212
Short name T1020
Test name
Test status
Simulation time 37706680 ps
CPU time 0.65 seconds
Started Jun 23 05:13:48 PM PDT 24
Finished Jun 23 05:13:49 PM PDT 24
Peak memory 204288 kb
Host smart-96c61a72-f19b-4cf1-b34b-4a27124f9285
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904775212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3904775212
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3596059963
Short name T1036
Test name
Test status
Simulation time 56734433 ps
CPU time 1.78 seconds
Started Jun 23 05:13:52 PM PDT 24
Finished Jun 23 05:13:54 PM PDT 24
Peak memory 216980 kb
Host smart-916f826f-67ba-4106-8e53-47b7966a1d25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596059963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3596059963
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1810527553
Short name T1040
Test name
Test status
Simulation time 193841276 ps
CPU time 3.09 seconds
Started Jun 23 05:13:52 PM PDT 24
Finished Jun 23 05:13:55 PM PDT 24
Peak memory 215652 kb
Host smart-b3d435f0-ebc3-403a-b546-025731a0e754
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810527553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
810527553
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1045415985
Short name T1061
Test name
Test status
Simulation time 52590688 ps
CPU time 0.73 seconds
Started Jun 23 05:14:37 PM PDT 24
Finished Jun 23 05:14:38 PM PDT 24
Peak memory 204364 kb
Host smart-5168539f-fe52-47b1-bea2-c89bee624e4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045415985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1045415985
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1232949975
Short name T962
Test name
Test status
Simulation time 17527492 ps
CPU time 0.73 seconds
Started Jun 23 05:14:33 PM PDT 24
Finished Jun 23 05:14:34 PM PDT 24
Peak memory 204376 kb
Host smart-b581811d-d3d1-4bf0-88e4-bb3efe6a5d7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232949975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1232949975
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2478157496
Short name T964
Test name
Test status
Simulation time 42758688 ps
CPU time 0.73 seconds
Started Jun 23 05:14:35 PM PDT 24
Finished Jun 23 05:14:36 PM PDT 24
Peak memory 204680 kb
Host smart-b1f7b146-1839-4e43-8d59-8f10bc4de2fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478157496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2478157496
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.441655569
Short name T957
Test name
Test status
Simulation time 56371800 ps
CPU time 0.73 seconds
Started Jun 23 05:14:33 PM PDT 24
Finished Jun 23 05:14:34 PM PDT 24
Peak memory 204668 kb
Host smart-ae36dcac-581f-484a-890d-dec5ba509578
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441655569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.441655569
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3653263021
Short name T960
Test name
Test status
Simulation time 16337424 ps
CPU time 0.69 seconds
Started Jun 23 05:14:33 PM PDT 24
Finished Jun 23 05:14:34 PM PDT 24
Peak memory 204252 kb
Host smart-70b311c1-18d0-479e-afc8-86ced09aba6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653263021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3653263021
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.322724741
Short name T1006
Test name
Test status
Simulation time 50574598 ps
CPU time 0.79 seconds
Started Jun 23 05:14:34 PM PDT 24
Finished Jun 23 05:14:35 PM PDT 24
Peak memory 204316 kb
Host smart-98788cd9-04fd-4117-a3e0-baf58b2d1812
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322724741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.322724741
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.516273877
Short name T1008
Test name
Test status
Simulation time 15413713 ps
CPU time 0.82 seconds
Started Jun 23 05:14:36 PM PDT 24
Finished Jun 23 05:14:37 PM PDT 24
Peak memory 204360 kb
Host smart-70747468-a4b4-4efa-aedd-2e733f22b6c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516273877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.516273877
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3838002015
Short name T1035
Test name
Test status
Simulation time 22641555 ps
CPU time 0.78 seconds
Started Jun 23 05:14:33 PM PDT 24
Finished Jun 23 05:14:35 PM PDT 24
Peak memory 204368 kb
Host smart-ff981551-344d-4efa-90a7-34f24a41b114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838002015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3838002015
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.507993018
Short name T1048
Test name
Test status
Simulation time 43434735 ps
CPU time 0.72 seconds
Started Jun 23 05:14:32 PM PDT 24
Finished Jun 23 05:14:33 PM PDT 24
Peak memory 204360 kb
Host smart-31f39783-1d32-4a1c-ad2c-8aa160ff9fe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507993018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.507993018
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1927560325
Short name T1053
Test name
Test status
Simulation time 56820758 ps
CPU time 0.79 seconds
Started Jun 23 05:14:36 PM PDT 24
Finished Jun 23 05:14:37 PM PDT 24
Peak memory 204336 kb
Host smart-d27b31ed-3338-49f3-9c74-49fbe1c696f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927560325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1927560325
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3295709136
Short name T1079
Test name
Test status
Simulation time 1712440385 ps
CPU time 8.29 seconds
Started Jun 23 05:13:55 PM PDT 24
Finished Jun 23 05:14:04 PM PDT 24
Peak memory 207952 kb
Host smart-f02e9568-41bb-47a4-ad2d-6674212e2d35
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295709136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3295709136
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.30954238
Short name T125
Test name
Test status
Simulation time 1801867809 ps
CPU time 28.76 seconds
Started Jun 23 05:13:59 PM PDT 24
Finished Jun 23 05:14:28 PM PDT 24
Peak memory 215924 kb
Host smart-0c010adb-ab86-4f60-afc4-f684a0b3793f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30954238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_
bit_bash.30954238
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.734811080
Short name T83
Test name
Test status
Simulation time 112017972 ps
CPU time 1.35 seconds
Started Jun 23 05:13:59 PM PDT 24
Finished Jun 23 05:14:01 PM PDT 24
Peak memory 207748 kb
Host smart-81aa2c91-2568-4b86-ae8b-15cfe8d3d1cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734811080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.734811080
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.837100396
Short name T980
Test name
Test status
Simulation time 190705336 ps
CPU time 4.24 seconds
Started Jun 23 05:13:59 PM PDT 24
Finished Jun 23 05:14:03 PM PDT 24
Peak memory 218384 kb
Host smart-15ae832f-1652-4e47-9fe5-2fa8f161c81d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837100396 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.837100396
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4028905637
Short name T117
Test name
Test status
Simulation time 140661431 ps
CPU time 1.42 seconds
Started Jun 23 05:13:59 PM PDT 24
Finished Jun 23 05:14:01 PM PDT 24
Peak memory 207776 kb
Host smart-cf967149-542c-48b4-a8a0-777fffa87166
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028905637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4
028905637
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.926243378
Short name T1031
Test name
Test status
Simulation time 56704365 ps
CPU time 0.78 seconds
Started Jun 23 05:13:54 PM PDT 24
Finished Jun 23 05:13:55 PM PDT 24
Peak memory 204352 kb
Host smart-6ecf2669-9163-4ceb-9ae8-b3bce4f841e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926243378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.926243378
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2783866168
Short name T1058
Test name
Test status
Simulation time 132046052 ps
CPU time 1.68 seconds
Started Jun 23 05:13:59 PM PDT 24
Finished Jun 23 05:14:01 PM PDT 24
Peak memory 215980 kb
Host smart-0ba5caa9-04c0-4b8a-8ca7-86ad79289113
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783866168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2783866168
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2804102696
Short name T958
Test name
Test status
Simulation time 12445801 ps
CPU time 0.67 seconds
Started Jun 23 05:13:58 PM PDT 24
Finished Jun 23 05:13:59 PM PDT 24
Peak memory 204272 kb
Host smart-d2946220-689e-48c4-89bf-63d026f503b1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804102696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2804102696
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2798201141
Short name T991
Test name
Test status
Simulation time 76301839 ps
CPU time 2.46 seconds
Started Jun 23 05:14:01 PM PDT 24
Finished Jun 23 05:14:03 PM PDT 24
Peak memory 215892 kb
Host smart-3919ed45-db8d-4e5b-ad24-bd4bf541a4a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798201141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2798201141
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3236715521
Short name T177
Test name
Test status
Simulation time 2667363739 ps
CPU time 15.97 seconds
Started Jun 23 05:13:53 PM PDT 24
Finished Jun 23 05:14:09 PM PDT 24
Peak memory 216044 kb
Host smart-34f8b6af-e0d3-4b53-b86f-b28973377588
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236715521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3236715521
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3388292746
Short name T1063
Test name
Test status
Simulation time 66704141 ps
CPU time 0.79 seconds
Started Jun 23 05:14:37 PM PDT 24
Finished Jun 23 05:14:39 PM PDT 24
Peak memory 204356 kb
Host smart-7bf58ce5-17b1-416d-a4f6-27c1185df8c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388292746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3388292746
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3708675787
Short name T971
Test name
Test status
Simulation time 16483567 ps
CPU time 0.79 seconds
Started Jun 23 05:14:35 PM PDT 24
Finished Jun 23 05:14:36 PM PDT 24
Peak memory 204280 kb
Host smart-f295eb42-d3f5-49c0-bd56-406d32bc6075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708675787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3708675787
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.471698853
Short name T1078
Test name
Test status
Simulation time 14230147 ps
CPU time 0.69 seconds
Started Jun 23 05:14:34 PM PDT 24
Finished Jun 23 05:14:35 PM PDT 24
Peak memory 204356 kb
Host smart-2bbc94f0-180f-47ea-9cf1-b08740e15450
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471698853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.471698853
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3624788608
Short name T989
Test name
Test status
Simulation time 11212880 ps
CPU time 0.74 seconds
Started Jun 23 05:14:34 PM PDT 24
Finished Jun 23 05:14:35 PM PDT 24
Peak memory 204676 kb
Host smart-820f3b24-83d3-463e-96cc-780486c33fad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624788608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3624788608
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.922543786
Short name T1076
Test name
Test status
Simulation time 13822080 ps
CPU time 0.73 seconds
Started Jun 23 05:14:34 PM PDT 24
Finished Jun 23 05:14:35 PM PDT 24
Peak memory 204368 kb
Host smart-24fa3c03-fe73-4a99-8c60-4c1f65dad76b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922543786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.922543786
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3664146488
Short name T973
Test name
Test status
Simulation time 32289784 ps
CPU time 0.72 seconds
Started Jun 23 05:14:36 PM PDT 24
Finished Jun 23 05:14:37 PM PDT 24
Peak memory 204660 kb
Host smart-9c2cfce1-2c93-468e-856a-47883a643022
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664146488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3664146488
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.297274001
Short name T965
Test name
Test status
Simulation time 52303221 ps
CPU time 0.76 seconds
Started Jun 23 05:14:35 PM PDT 24
Finished Jun 23 05:14:36 PM PDT 24
Peak memory 204592 kb
Host smart-a142b527-099e-4127-9ed1-9fbee56bef68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297274001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.297274001
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3087928203
Short name T987
Test name
Test status
Simulation time 15223556 ps
CPU time 0.68 seconds
Started Jun 23 05:14:39 PM PDT 24
Finished Jun 23 05:14:40 PM PDT 24
Peak memory 204360 kb
Host smart-a9cccde0-27ff-459e-a240-5d999042d4f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087928203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3087928203
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.773217627
Short name T1041
Test name
Test status
Simulation time 47321215 ps
CPU time 0.75 seconds
Started Jun 23 05:14:39 PM PDT 24
Finished Jun 23 05:14:40 PM PDT 24
Peak memory 204684 kb
Host smart-92af05a2-2050-4eff-ab98-7836f537abd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773217627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.773217627
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2166555062
Short name T1030
Test name
Test status
Simulation time 24465384 ps
CPU time 0.69 seconds
Started Jun 23 05:14:47 PM PDT 24
Finished Jun 23 05:14:48 PM PDT 24
Peak memory 204676 kb
Host smart-ba34101d-a458-4af5-9e10-49389f9d4660
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166555062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2166555062
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.875206456
Short name T170
Test name
Test status
Simulation time 222799158 ps
CPU time 4.29 seconds
Started Jun 23 05:14:06 PM PDT 24
Finished Jun 23 05:14:11 PM PDT 24
Peak memory 219348 kb
Host smart-d416c7d8-4d17-4b33-865e-d1154b086471
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875206456 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.875206456
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.721093522
Short name T1045
Test name
Test status
Simulation time 783949691 ps
CPU time 1.9 seconds
Started Jun 23 05:14:02 PM PDT 24
Finished Jun 23 05:14:04 PM PDT 24
Peak memory 215880 kb
Host smart-596f39ba-3535-4913-8eaa-73d145030338
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721093522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.721093522
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.763299641
Short name T1075
Test name
Test status
Simulation time 12107523 ps
CPU time 0.7 seconds
Started Jun 23 05:13:59 PM PDT 24
Finished Jun 23 05:14:00 PM PDT 24
Peak memory 204356 kb
Host smart-85a70d8a-607d-438b-86b4-1c7fa8c8cb12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763299641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.763299641
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1373337633
Short name T992
Test name
Test status
Simulation time 509143320 ps
CPU time 2.21 seconds
Started Jun 23 05:14:03 PM PDT 24
Finished Jun 23 05:14:06 PM PDT 24
Peak memory 207688 kb
Host smart-8aac12df-e5c7-4854-b26b-e42ef2c25bc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373337633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1373337633
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2608924644
Short name T175
Test name
Test status
Simulation time 701812771 ps
CPU time 18.33 seconds
Started Jun 23 05:14:02 PM PDT 24
Finished Jun 23 05:14:21 PM PDT 24
Peak memory 215972 kb
Host smart-b8674e6a-2fb3-4aa7-bdbd-b66ee08e9d47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608924644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2608924644
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3103942151
Short name T1072
Test name
Test status
Simulation time 87789440 ps
CPU time 2.72 seconds
Started Jun 23 05:14:02 PM PDT 24
Finished Jun 23 05:14:05 PM PDT 24
Peak memory 217056 kb
Host smart-15dd8d5d-6aa6-48a3-9890-09fe6797efaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103942151 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3103942151
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1553596518
Short name T1018
Test name
Test status
Simulation time 77018823 ps
CPU time 2.53 seconds
Started Jun 23 05:14:03 PM PDT 24
Finished Jun 23 05:14:05 PM PDT 24
Peak memory 207808 kb
Host smart-3e425e52-9208-412e-bdbe-b5ebdb3b92f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553596518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
553596518
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.712804966
Short name T1033
Test name
Test status
Simulation time 14772952 ps
CPU time 0.71 seconds
Started Jun 23 05:14:02 PM PDT 24
Finished Jun 23 05:14:03 PM PDT 24
Peak memory 204368 kb
Host smart-f485e099-dac5-4d82-8ef7-5ed16cab3eb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712804966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.712804966
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2972598075
Short name T1049
Test name
Test status
Simulation time 355767915 ps
CPU time 2 seconds
Started Jun 23 05:14:05 PM PDT 24
Finished Jun 23 05:14:07 PM PDT 24
Peak memory 215868 kb
Host smart-3b715d2a-75c0-4d06-a4de-8eb2d6104e4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972598075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2972598075
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1935960561
Short name T172
Test name
Test status
Simulation time 607685202 ps
CPU time 13.94 seconds
Started Jun 23 05:14:03 PM PDT 24
Finished Jun 23 05:14:17 PM PDT 24
Peak memory 215944 kb
Host smart-155d8dc5-652c-481d-bc9b-0fa17fc027eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935960561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1935960561
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3032659209
Short name T1019
Test name
Test status
Simulation time 53053571 ps
CPU time 3.85 seconds
Started Jun 23 05:14:07 PM PDT 24
Finished Jun 23 05:14:12 PM PDT 24
Peak memory 218852 kb
Host smart-91617353-0c13-47fd-bea5-72a38d7850f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032659209 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3032659209
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1242644399
Short name T116
Test name
Test status
Simulation time 95158667 ps
CPU time 2.78 seconds
Started Jun 23 05:14:02 PM PDT 24
Finished Jun 23 05:14:05 PM PDT 24
Peak memory 215952 kb
Host smart-89e2cdf2-de7b-4dee-ad6d-edb71e6e751a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242644399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
242644399
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.347133857
Short name T1017
Test name
Test status
Simulation time 14720032 ps
CPU time 0.72 seconds
Started Jun 23 05:14:04 PM PDT 24
Finished Jun 23 05:14:05 PM PDT 24
Peak memory 204328 kb
Host smart-4a62cd7c-9bea-4964-b7eb-6f07a4b8fe2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347133857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.347133857
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2981016475
Short name T974
Test name
Test status
Simulation time 166648595 ps
CPU time 4.69 seconds
Started Jun 23 05:14:05 PM PDT 24
Finished Jun 23 05:14:10 PM PDT 24
Peak memory 215880 kb
Host smart-d8195400-c215-48c5-b31c-60ad90d5b70f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981016475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2981016475
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.4239229164
Short name T106
Test name
Test status
Simulation time 714142286 ps
CPU time 5 seconds
Started Jun 23 05:14:03 PM PDT 24
Finished Jun 23 05:14:09 PM PDT 24
Peak memory 216116 kb
Host smart-dd57e5aa-ffc6-4078-9472-103d56f414a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239229164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.4
239229164
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.730002731
Short name T99
Test name
Test status
Simulation time 679024597 ps
CPU time 14.57 seconds
Started Jun 23 05:14:02 PM PDT 24
Finished Jun 23 05:14:17 PM PDT 24
Peak memory 216568 kb
Host smart-fcb5284a-1e33-4ed8-9c08-0a8793ed7a02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730002731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.730002731
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3580568450
Short name T110
Test name
Test status
Simulation time 509242378 ps
CPU time 4 seconds
Started Jun 23 05:14:07 PM PDT 24
Finished Jun 23 05:14:12 PM PDT 24
Peak memory 218772 kb
Host smart-e129ec2a-250a-4351-9171-83e16ae9ebbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580568450 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3580568450
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3854308127
Short name T970
Test name
Test status
Simulation time 45213054 ps
CPU time 1.48 seconds
Started Jun 23 05:14:10 PM PDT 24
Finished Jun 23 05:14:12 PM PDT 24
Peak memory 207744 kb
Host smart-a2d11417-549b-4903-bf0a-a8795fed2364
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854308127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
854308127
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2856151921
Short name T1004
Test name
Test status
Simulation time 14244228 ps
CPU time 0.7 seconds
Started Jun 23 05:14:08 PM PDT 24
Finished Jun 23 05:14:09 PM PDT 24
Peak memory 204564 kb
Host smart-1b35f663-a4cd-4756-9722-23e815340d14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856151921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
856151921
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1791598320
Short name T148
Test name
Test status
Simulation time 484815910 ps
CPU time 3.03 seconds
Started Jun 23 05:14:08 PM PDT 24
Finished Jun 23 05:14:12 PM PDT 24
Peak memory 215976 kb
Host smart-7378bc59-dabd-45a5-b384-44473ede8d78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791598320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1791598320
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.205058352
Short name T104
Test name
Test status
Simulation time 96477798 ps
CPU time 3.33 seconds
Started Jun 23 05:14:09 PM PDT 24
Finished Jun 23 05:14:13 PM PDT 24
Peak memory 216240 kb
Host smart-d22129a3-a52a-4cde-b13d-cda45d75e88e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205058352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.205058352
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3071124022
Short name T1050
Test name
Test status
Simulation time 344783356 ps
CPU time 8.36 seconds
Started Jun 23 05:14:06 PM PDT 24
Finished Jun 23 05:14:15 PM PDT 24
Peak memory 215932 kb
Host smart-4ea3275f-39ad-47f1-9c32-03677bc13864
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071124022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3071124022
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2440048263
Short name T111
Test name
Test status
Simulation time 273078409 ps
CPU time 3.77 seconds
Started Jun 23 05:14:08 PM PDT 24
Finished Jun 23 05:14:12 PM PDT 24
Peak memory 217792 kb
Host smart-b26065eb-d287-414a-8f4c-46e77097fbbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440048263 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2440048263
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3100801645
Short name T1073
Test name
Test status
Simulation time 152283744 ps
CPU time 1.35 seconds
Started Jun 23 05:14:08 PM PDT 24
Finished Jun 23 05:14:10 PM PDT 24
Peak memory 207716 kb
Host smart-21862f33-1076-4172-80b0-46a215b2a7e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100801645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
100801645
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3149528073
Short name T976
Test name
Test status
Simulation time 54113368 ps
CPU time 0.74 seconds
Started Jun 23 05:14:09 PM PDT 24
Finished Jun 23 05:14:11 PM PDT 24
Peak memory 204296 kb
Host smart-6211db42-e311-4623-9ca4-d0280eb981a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149528073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
149528073
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4133181862
Short name T966
Test name
Test status
Simulation time 127592479 ps
CPU time 1.89 seconds
Started Jun 23 05:14:09 PM PDT 24
Finished Jun 23 05:14:12 PM PDT 24
Peak memory 215956 kb
Host smart-160adb26-319c-4b31-b553-5f6f3783f35f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133181862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.4133181862
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3557694060
Short name T169
Test name
Test status
Simulation time 68865326 ps
CPU time 2.19 seconds
Started Jun 23 05:14:09 PM PDT 24
Finished Jun 23 05:14:11 PM PDT 24
Peak memory 216020 kb
Host smart-ede3e609-74da-4cf8-bd83-f8f68bdc42dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557694060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
557694060
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3143768876
Short name T339
Test name
Test status
Simulation time 62859331 ps
CPU time 0.75 seconds
Started Jun 23 05:49:40 PM PDT 24
Finished Jun 23 05:49:41 PM PDT 24
Peak memory 205500 kb
Host smart-a15fe8b9-a7e2-4480-bbe0-0804e68a081d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143768876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
143768876
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.181450776
Short name T234
Test name
Test status
Simulation time 1062939073 ps
CPU time 8.81 seconds
Started Jun 23 05:49:41 PM PDT 24
Finished Jun 23 05:49:50 PM PDT 24
Peak memory 224688 kb
Host smart-8667e9f9-cf02-4892-885d-8a01e08754d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181450776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.181450776
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2290843491
Short name T390
Test name
Test status
Simulation time 42787703 ps
CPU time 0.77 seconds
Started Jun 23 05:49:41 PM PDT 24
Finished Jun 23 05:49:42 PM PDT 24
Peak memory 206756 kb
Host smart-357b77d9-5964-4669-8eb9-0900ed32544b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290843491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2290843491
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3972420849
Short name T33
Test name
Test status
Simulation time 5151369926 ps
CPU time 50.2 seconds
Started Jun 23 05:49:43 PM PDT 24
Finished Jun 23 05:50:34 PM PDT 24
Peak memory 249316 kb
Host smart-0476c952-98cc-4162-b65c-21cdd124b9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972420849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3972420849
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1692313264
Short name T946
Test name
Test status
Simulation time 50310140624 ps
CPU time 507.5 seconds
Started Jun 23 05:49:43 PM PDT 24
Finished Jun 23 05:58:11 PM PDT 24
Peak memory 270076 kb
Host smart-b621e1db-0feb-4aea-b0ed-12551594965d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692313264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1692313264
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2665370540
Short name T513
Test name
Test status
Simulation time 7891997207 ps
CPU time 102.83 seconds
Started Jun 23 05:49:45 PM PDT 24
Finished Jun 23 05:51:28 PM PDT 24
Peak memory 249448 kb
Host smart-455ac4bd-57c5-4f59-8349-44f9257521b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665370540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2665370540
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.4225155010
Short name T482
Test name
Test status
Simulation time 317603547 ps
CPU time 4.3 seconds
Started Jun 23 05:49:41 PM PDT 24
Finished Jun 23 05:49:46 PM PDT 24
Peak memory 237916 kb
Host smart-302be52d-ba11-4763-9975-6f04e7918c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225155010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.4225155010
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3712656353
Short name T765
Test name
Test status
Simulation time 10326450051 ps
CPU time 11.36 seconds
Started Jun 23 05:49:40 PM PDT 24
Finished Jun 23 05:49:52 PM PDT 24
Peak memory 224772 kb
Host smart-1c7231b5-12e6-4872-ba98-0eac3beb4444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712656353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3712656353
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.573227994
Short name T669
Test name
Test status
Simulation time 1157280365 ps
CPU time 10.76 seconds
Started Jun 23 05:49:40 PM PDT 24
Finished Jun 23 05:49:51 PM PDT 24
Peak memory 241048 kb
Host smart-2eed0f63-7d14-4620-97d1-89e4ff1a1e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573227994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.573227994
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3076626756
Short name T832
Test name
Test status
Simulation time 672996536 ps
CPU time 10.13 seconds
Started Jun 23 05:49:44 PM PDT 24
Finished Jun 23 05:49:55 PM PDT 24
Peak memory 232820 kb
Host smart-da77ab06-7b6a-4a75-8389-f32a23774b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076626756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3076626756
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.4035091019
Short name T56
Test name
Test status
Simulation time 10693776997 ps
CPU time 23.52 seconds
Started Jun 23 05:49:44 PM PDT 24
Finished Jun 23 05:50:08 PM PDT 24
Peak memory 224768 kb
Host smart-f43b2a0a-0037-4fea-83d7-047acc3d4cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035091019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.4035091019
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1466574115
Short name T142
Test name
Test status
Simulation time 1435991878 ps
CPU time 16.34 seconds
Started Jun 23 05:49:39 PM PDT 24
Finished Jun 23 05:49:55 PM PDT 24
Peak memory 219164 kb
Host smart-389c37b2-687b-41f2-a310-fa0e1bd3549f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1466574115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1466574115
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.4218676136
Short name T921
Test name
Test status
Simulation time 4493340011 ps
CPU time 18.02 seconds
Started Jun 23 05:49:37 PM PDT 24
Finished Jun 23 05:49:55 PM PDT 24
Peak memory 220116 kb
Host smart-8f988424-9108-4cdc-8b19-e93dec6611cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218676136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.4218676136
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1514780434
Short name T476
Test name
Test status
Simulation time 665836373 ps
CPU time 1.74 seconds
Started Jun 23 05:49:41 PM PDT 24
Finished Jun 23 05:49:43 PM PDT 24
Peak memory 208096 kb
Host smart-01675e88-4a3f-4155-ac4b-6b5cf3d6a1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514780434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1514780434
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2660547458
Short name T647
Test name
Test status
Simulation time 60818077 ps
CPU time 1.57 seconds
Started Jun 23 05:49:37 PM PDT 24
Finished Jun 23 05:49:39 PM PDT 24
Peak memory 216388 kb
Host smart-c2485773-7270-46fc-b6c1-2b0dd95d558f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660547458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2660547458
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3609255700
Short name T927
Test name
Test status
Simulation time 17350866 ps
CPU time 0.75 seconds
Started Jun 23 05:49:42 PM PDT 24
Finished Jun 23 05:49:44 PM PDT 24
Peak memory 206108 kb
Host smart-92d9acaf-7988-4368-85bd-1490fb52b380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609255700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3609255700
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3049745302
Short name T672
Test name
Test status
Simulation time 105281573640 ps
CPU time 28.89 seconds
Started Jun 23 05:49:42 PM PDT 24
Finished Jun 23 05:50:12 PM PDT 24
Peak memory 249412 kb
Host smart-aac5544c-6e3d-414b-88e9-128a07b08bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049745302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3049745302
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3442829334
Short name T474
Test name
Test status
Simulation time 16488430 ps
CPU time 0.71 seconds
Started Jun 23 05:49:42 PM PDT 24
Finished Jun 23 05:49:43 PM PDT 24
Peak memory 205508 kb
Host smart-dfd43fa9-b41b-4ae2-ae44-35ebc066b28f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442829334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
442829334
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2840706074
Short name T242
Test name
Test status
Simulation time 653009765 ps
CPU time 6.18 seconds
Started Jun 23 05:49:49 PM PDT 24
Finished Jun 23 05:49:56 PM PDT 24
Peak memory 224608 kb
Host smart-cda26126-9ea8-4fe8-90f5-a657a53cb4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840706074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2840706074
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3896946338
Short name T620
Test name
Test status
Simulation time 24130107 ps
CPU time 0.77 seconds
Started Jun 23 05:49:42 PM PDT 24
Finished Jun 23 05:49:43 PM PDT 24
Peak memory 207072 kb
Host smart-6b39a8ff-af94-43bc-aab4-6328744f0b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896946338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3896946338
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1511865782
Short name T855
Test name
Test status
Simulation time 62034760355 ps
CPU time 126.59 seconds
Started Jun 23 05:49:45 PM PDT 24
Finished Jun 23 05:51:52 PM PDT 24
Peak memory 256716 kb
Host smart-0a05b7fd-636d-4441-9703-c9d821d9b313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511865782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1511865782
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2725626044
Short name T48
Test name
Test status
Simulation time 57778074825 ps
CPU time 508.13 seconds
Started Jun 23 05:49:48 PM PDT 24
Finished Jun 23 05:58:17 PM PDT 24
Peak memory 263960 kb
Host smart-bcaeb27a-bf38-4aaa-8cc8-374958d17cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725626044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2725626044
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2383631693
Short name T130
Test name
Test status
Simulation time 7762468195 ps
CPU time 29.4 seconds
Started Jun 23 05:49:43 PM PDT 24
Finished Jun 23 05:50:13 PM PDT 24
Peak memory 233984 kb
Host smart-598382c4-c1e8-4db6-b7f9-cd83e8ec9628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383631693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2383631693
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.4187811223
Short name T604
Test name
Test status
Simulation time 260216129 ps
CPU time 2.42 seconds
Started Jun 23 05:49:47 PM PDT 24
Finished Jun 23 05:49:50 PM PDT 24
Peak memory 224532 kb
Host smart-acf1bccf-d271-4d34-8b8e-9d4217ca2eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187811223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.4187811223
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2842359711
Short name T191
Test name
Test status
Simulation time 401702199 ps
CPU time 5.65 seconds
Started Jun 23 05:49:44 PM PDT 24
Finished Jun 23 05:49:50 PM PDT 24
Peak memory 224620 kb
Host smart-2184afd7-44e2-4668-9543-041c23a910a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842359711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2842359711
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.640046999
Short name T158
Test name
Test status
Simulation time 8118167765 ps
CPU time 60.98 seconds
Started Jun 23 05:49:45 PM PDT 24
Finished Jun 23 05:50:47 PM PDT 24
Peak memory 233924 kb
Host smart-9e5ebb8d-6549-46e6-aa72-5f1f44a280be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640046999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.640046999
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2507719499
Short name T589
Test name
Test status
Simulation time 161322476 ps
CPU time 2.81 seconds
Started Jun 23 05:49:45 PM PDT 24
Finished Jun 23 05:49:49 PM PDT 24
Peak memory 232872 kb
Host smart-54610d74-d74a-48d5-889e-7497df2dc35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507719499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2507719499
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3598105150
Short name T835
Test name
Test status
Simulation time 27119837857 ps
CPU time 18.82 seconds
Started Jun 23 05:49:55 PM PDT 24
Finished Jun 23 05:50:15 PM PDT 24
Peak memory 233000 kb
Host smart-e0b9a094-390b-4617-a109-38afd7f717da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598105150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3598105150
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1307473308
Short name T870
Test name
Test status
Simulation time 2066856375 ps
CPU time 8.83 seconds
Started Jun 23 05:49:45 PM PDT 24
Finished Jun 23 05:49:55 PM PDT 24
Peak memory 221088 kb
Host smart-d9a40e35-018b-4d2b-bb38-453576df12a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1307473308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1307473308
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.4065343459
Short name T72
Test name
Test status
Simulation time 715369854 ps
CPU time 1.03 seconds
Started Jun 23 05:49:44 PM PDT 24
Finished Jun 23 05:49:45 PM PDT 24
Peak memory 235796 kb
Host smart-b0cff486-07d1-4466-ab9a-a074490bc5b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065343459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.4065343459
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3840007611
Short name T281
Test name
Test status
Simulation time 24969255776 ps
CPU time 241.04 seconds
Started Jun 23 05:49:48 PM PDT 24
Finished Jun 23 05:53:50 PM PDT 24
Peak memory 255024 kb
Host smart-c6a9737a-6657-4e6a-ba21-71a645374d89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840007611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3840007611
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1741483436
Short name T542
Test name
Test status
Simulation time 27696069918 ps
CPU time 38.87 seconds
Started Jun 23 05:49:46 PM PDT 24
Finished Jun 23 05:50:25 PM PDT 24
Peak memory 216492 kb
Host smart-e064beb3-e452-4028-a9bc-b3d9f0b5a844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741483436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1741483436
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.595855147
Short name T478
Test name
Test status
Simulation time 1974317169 ps
CPU time 7.71 seconds
Started Jun 23 05:49:39 PM PDT 24
Finished Jun 23 05:49:47 PM PDT 24
Peak memory 216348 kb
Host smart-9cab8b24-a070-4084-9b96-026ef835b651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595855147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.595855147
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.281024149
Short name T630
Test name
Test status
Simulation time 43687194 ps
CPU time 0.75 seconds
Started Jun 23 05:49:46 PM PDT 24
Finished Jun 23 05:49:47 PM PDT 24
Peak memory 206152 kb
Host smart-e7422c65-fab6-4207-a002-c8855090fb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281024149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.281024149
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1830784755
Short name T12
Test name
Test status
Simulation time 78080186 ps
CPU time 0.93 seconds
Started Jun 23 05:49:44 PM PDT 24
Finished Jun 23 05:49:46 PM PDT 24
Peak memory 206300 kb
Host smart-37df32cd-35eb-4b07-acf0-c96193f5cc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830784755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1830784755
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1915680857
Short name T607
Test name
Test status
Simulation time 6720322381 ps
CPU time 16.53 seconds
Started Jun 23 05:49:42 PM PDT 24
Finished Jun 23 05:49:59 PM PDT 24
Peak memory 224824 kb
Host smart-cf3c9d6e-802d-40c4-bbb3-ad1134369b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915680857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1915680857
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1679071987
Short name T893
Test name
Test status
Simulation time 38036056 ps
CPU time 0.74 seconds
Started Jun 23 05:50:09 PM PDT 24
Finished Jun 23 05:50:11 PM PDT 24
Peak memory 205520 kb
Host smart-2c1a7e53-ca92-49fe-b675-c28617b26581
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679071987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1679071987
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1498568211
Short name T375
Test name
Test status
Simulation time 47407633 ps
CPU time 2.51 seconds
Started Jun 23 05:50:00 PM PDT 24
Finished Jun 23 05:50:03 PM PDT 24
Peak memory 232872 kb
Host smart-630d566b-fd6d-4ea4-91f6-e084a5885071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498568211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1498568211
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2253931872
Short name T324
Test name
Test status
Simulation time 14003276 ps
CPU time 0.77 seconds
Started Jun 23 05:50:09 PM PDT 24
Finished Jun 23 05:50:10 PM PDT 24
Peak memory 207068 kb
Host smart-a17b796d-9b7c-45bb-8a39-4fa2a5e68f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253931872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2253931872
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1749543730
Short name T7
Test name
Test status
Simulation time 1751054407 ps
CPU time 44.42 seconds
Started Jun 23 05:50:09 PM PDT 24
Finished Jun 23 05:50:54 PM PDT 24
Peak memory 257436 kb
Host smart-7fd6cd96-0fc2-4584-a920-af0c2d6daa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749543730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1749543730
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2584207178
Short name T737
Test name
Test status
Simulation time 571406690 ps
CPU time 3.38 seconds
Started Jun 23 05:50:07 PM PDT 24
Finished Jun 23 05:50:11 PM PDT 24
Peak memory 217640 kb
Host smart-93889501-90b9-4f00-ad4c-443cea3d8326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584207178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2584207178
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.4204449149
Short name T32
Test name
Test status
Simulation time 9693444802 ps
CPU time 95.69 seconds
Started Jun 23 05:50:07 PM PDT 24
Finished Jun 23 05:51:43 PM PDT 24
Peak memory 251872 kb
Host smart-611fecfe-d0f9-48e6-9e2a-26ff0bee9a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204449149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.4204449149
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1044641999
Short name T227
Test name
Test status
Simulation time 363666068 ps
CPU time 5.84 seconds
Started Jun 23 05:50:09 PM PDT 24
Finished Jun 23 05:50:15 PM PDT 24
Peak memory 232328 kb
Host smart-0b803971-27b4-4a76-95b5-bb2199768977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044641999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1044641999
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1079218
Short name T252
Test name
Test status
Simulation time 582816985 ps
CPU time 4.39 seconds
Started Jun 23 05:50:11 PM PDT 24
Finished Jun 23 05:50:17 PM PDT 24
Peak memory 224636 kb
Host smart-17ae8605-5b4d-46e9-bfbe-dcfe67066209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1079218
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2515664769
Short name T736
Test name
Test status
Simulation time 1398719991 ps
CPU time 8.83 seconds
Started Jun 23 05:50:04 PM PDT 24
Finished Jun 23 05:50:14 PM PDT 24
Peak memory 240136 kb
Host smart-1b142653-c476-4654-a2f9-33258ec98bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515664769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2515664769
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.870267263
Short name T563
Test name
Test status
Simulation time 1370029181 ps
CPU time 3.77 seconds
Started Jun 23 05:50:08 PM PDT 24
Finished Jun 23 05:50:12 PM PDT 24
Peak memory 224640 kb
Host smart-a86299ee-ae2d-47e9-8c5d-9d2e84604630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870267263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.870267263
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.4289993577
Short name T450
Test name
Test status
Simulation time 1841136043 ps
CPU time 8.16 seconds
Started Jun 23 05:50:06 PM PDT 24
Finished Jun 23 05:50:14 PM PDT 24
Peak memory 224696 kb
Host smart-0618e983-4be6-4f35-81a8-487664370215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289993577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.4289993577
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1400015922
Short name T568
Test name
Test status
Simulation time 193842397 ps
CPU time 4.88 seconds
Started Jun 23 05:50:08 PM PDT 24
Finished Jun 23 05:50:13 PM PDT 24
Peak memory 223160 kb
Host smart-dffbd4a1-8c50-4edb-8461-54ceffd7663d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1400015922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1400015922
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1346552890
Short name T590
Test name
Test status
Simulation time 5958289120 ps
CPU time 38.23 seconds
Started Jun 23 05:50:03 PM PDT 24
Finished Jun 23 05:50:42 PM PDT 24
Peak memory 216496 kb
Host smart-61ceaeaa-940c-4c9d-9534-84881142ccfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346552890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1346552890
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2843553450
Short name T879
Test name
Test status
Simulation time 4217200485 ps
CPU time 14.96 seconds
Started Jun 23 05:50:04 PM PDT 24
Finished Jun 23 05:50:20 PM PDT 24
Peak memory 216576 kb
Host smart-ec767103-cab0-4dfa-8eba-0d35a30dd3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843553450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2843553450
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.4168084096
Short name T608
Test name
Test status
Simulation time 790823895 ps
CPU time 4.65 seconds
Started Jun 23 05:50:08 PM PDT 24
Finished Jun 23 05:50:13 PM PDT 24
Peak memory 216404 kb
Host smart-f7966522-c154-43ea-b9a2-2174a4166d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168084096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.4168084096
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2517031162
Short name T678
Test name
Test status
Simulation time 60759877 ps
CPU time 0.97 seconds
Started Jun 23 05:50:11 PM PDT 24
Finished Jun 23 05:50:13 PM PDT 24
Peak memory 206112 kb
Host smart-e7539c4e-5d78-4fcb-9dbe-d2cf72ad6bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517031162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2517031162
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1218354603
Short name T473
Test name
Test status
Simulation time 1366038197 ps
CPU time 8.04 seconds
Started Jun 23 05:50:08 PM PDT 24
Finished Jun 23 05:50:16 PM PDT 24
Peak memory 240684 kb
Host smart-c4172923-d061-4608-9e00-3d9c730bddb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218354603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1218354603
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3508802356
Short name T814
Test name
Test status
Simulation time 42312581 ps
CPU time 0.74 seconds
Started Jun 23 05:50:13 PM PDT 24
Finished Jun 23 05:50:14 PM PDT 24
Peak memory 205876 kb
Host smart-5ac093d9-97d6-4465-a4a3-d2693106db20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508802356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3508802356
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2622218442
Short name T490
Test name
Test status
Simulation time 316097653 ps
CPU time 4.73 seconds
Started Jun 23 05:50:11 PM PDT 24
Finished Jun 23 05:50:17 PM PDT 24
Peak memory 224640 kb
Host smart-2a58d3d1-05ef-4ca6-b88c-5f69e277b2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622218442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2622218442
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.606624800
Short name T776
Test name
Test status
Simulation time 171127324 ps
CPU time 0.78 seconds
Started Jun 23 05:50:09 PM PDT 24
Finished Jun 23 05:50:10 PM PDT 24
Peak memory 206748 kb
Host smart-bcaf13c8-b425-4539-a5d7-5927a2aa87b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606624800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.606624800
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.4103403373
Short name T223
Test name
Test status
Simulation time 7052259789 ps
CPU time 31.36 seconds
Started Jun 23 05:50:09 PM PDT 24
Finished Jun 23 05:50:42 PM PDT 24
Peak memory 251656 kb
Host smart-e7152a96-a630-430d-8995-ee758311a86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103403373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.4103403373
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3320049526
Short name T850
Test name
Test status
Simulation time 17726070933 ps
CPU time 192.49 seconds
Started Jun 23 05:50:11 PM PDT 24
Finished Jun 23 05:53:24 PM PDT 24
Peak memory 249360 kb
Host smart-2fdbb55b-c3b1-49e7-ad17-1007946cb6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320049526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3320049526
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1052572454
Short name T592
Test name
Test status
Simulation time 245541473639 ps
CPU time 250.82 seconds
Started Jun 23 05:50:07 PM PDT 24
Finished Jun 23 05:54:19 PM PDT 24
Peak memory 249452 kb
Host smart-e4f101b0-59c4-4b6d-ac66-449ccf884771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052572454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1052572454
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2752021664
Short name T948
Test name
Test status
Simulation time 122296265 ps
CPU time 4.3 seconds
Started Jun 23 05:50:05 PM PDT 24
Finished Jun 23 05:50:10 PM PDT 24
Peak memory 224684 kb
Host smart-bf095ac9-8d0b-4676-98c3-de13ba7b927a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752021664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2752021664
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3220129885
Short name T423
Test name
Test status
Simulation time 292841371 ps
CPU time 2.99 seconds
Started Jun 23 05:50:09 PM PDT 24
Finished Jun 23 05:50:12 PM PDT 24
Peak memory 218724 kb
Host smart-39e8ef81-0206-44ca-9e3a-e8b121b324fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220129885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3220129885
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.176722643
Short name T928
Test name
Test status
Simulation time 5321378682 ps
CPU time 23.57 seconds
Started Jun 23 05:50:10 PM PDT 24
Finished Jun 23 05:50:35 PM PDT 24
Peak memory 224772 kb
Host smart-7181c4f6-3d3c-4737-bfcf-f2ea3841f1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176722643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.176722643
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.743875103
Short name T262
Test name
Test status
Simulation time 803920300 ps
CPU time 6.3 seconds
Started Jun 23 05:50:06 PM PDT 24
Finished Jun 23 05:50:13 PM PDT 24
Peak memory 232832 kb
Host smart-ef646160-61ed-4adc-8d82-d26872582ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743875103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.743875103
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2682949135
Short name T844
Test name
Test status
Simulation time 3904564603 ps
CPU time 10.16 seconds
Started Jun 23 05:50:05 PM PDT 24
Finished Jun 23 05:50:16 PM PDT 24
Peak memory 249368 kb
Host smart-a89d3048-8b94-4f07-8adc-603379deb920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682949135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2682949135
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.430108212
Short name T701
Test name
Test status
Simulation time 706169978 ps
CPU time 8.74 seconds
Started Jun 23 05:50:05 PM PDT 24
Finished Jun 23 05:50:14 PM PDT 24
Peak memory 220820 kb
Host smart-af7b953b-c858-43c1-bd6a-d807beabd8ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=430108212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.430108212
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3781873880
Short name T571
Test name
Test status
Simulation time 10118109477 ps
CPU time 23.49 seconds
Started Jun 23 05:50:11 PM PDT 24
Finished Jun 23 05:50:35 PM PDT 24
Peak memory 216780 kb
Host smart-1d32ffe4-2f35-4272-a4d8-52fc422bc575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781873880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3781873880
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2193350195
Short name T447
Test name
Test status
Simulation time 6021117455 ps
CPU time 9.79 seconds
Started Jun 23 05:50:07 PM PDT 24
Finished Jun 23 05:50:17 PM PDT 24
Peak memory 216540 kb
Host smart-5b81955a-0630-4725-9567-2434a25bfbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193350195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2193350195
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3378157904
Short name T611
Test name
Test status
Simulation time 21561752 ps
CPU time 1.27 seconds
Started Jun 23 05:50:29 PM PDT 24
Finished Jun 23 05:50:31 PM PDT 24
Peak memory 216388 kb
Host smart-81d91855-7c59-4b43-97e6-593b24ad1abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378157904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3378157904
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.430054524
Short name T851
Test name
Test status
Simulation time 17488861 ps
CPU time 0.69 seconds
Started Jun 23 05:50:07 PM PDT 24
Finished Jun 23 05:50:08 PM PDT 24
Peak memory 205644 kb
Host smart-c4ecaf32-03e5-4427-af08-e0aa8da53e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430054524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.430054524
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1647696620
Short name T949
Test name
Test status
Simulation time 299113742 ps
CPU time 7.54 seconds
Started Jun 23 05:50:11 PM PDT 24
Finished Jun 23 05:50:20 PM PDT 24
Peak memory 224712 kb
Host smart-64a0dda0-cc19-4741-a2a0-f3b81febbf34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647696620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1647696620
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2208224684
Short name T536
Test name
Test status
Simulation time 14131042 ps
CPU time 0.72 seconds
Started Jun 23 05:50:25 PM PDT 24
Finished Jun 23 05:50:26 PM PDT 24
Peak memory 204952 kb
Host smart-8322d0da-4672-4808-884d-61a7de0807ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208224684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2208224684
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3873996854
Short name T131
Test name
Test status
Simulation time 1775708028 ps
CPU time 6.61 seconds
Started Jun 23 05:50:17 PM PDT 24
Finished Jun 23 05:50:24 PM PDT 24
Peak memory 232864 kb
Host smart-2a7b6933-3b20-4d73-a8e5-c4b7c2c0d33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873996854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3873996854
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3608369652
Short name T852
Test name
Test status
Simulation time 16820147 ps
CPU time 0.81 seconds
Started Jun 23 05:50:14 PM PDT 24
Finished Jun 23 05:50:15 PM PDT 24
Peak memory 206708 kb
Host smart-247fc574-ad01-4fcc-8234-0c4e5c16ceac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608369652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3608369652
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3965046094
Short name T898
Test name
Test status
Simulation time 6237079451 ps
CPU time 67.86 seconds
Started Jun 23 05:50:17 PM PDT 24
Finished Jun 23 05:51:25 PM PDT 24
Peak memory 250876 kb
Host smart-8f95c88a-6e2f-4884-8ffd-0fd6efb9cec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965046094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3965046094
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1718193346
Short name T187
Test name
Test status
Simulation time 6728626723 ps
CPU time 49.95 seconds
Started Jun 23 05:50:18 PM PDT 24
Finished Jun 23 05:51:08 PM PDT 24
Peak memory 224804 kb
Host smart-1557ed86-7589-4b46-a8a2-11f37b66b389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718193346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1718193346
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2561138398
Short name T50
Test name
Test status
Simulation time 95052099263 ps
CPU time 293.68 seconds
Started Jun 23 05:50:21 PM PDT 24
Finished Jun 23 05:55:15 PM PDT 24
Peak memory 257616 kb
Host smart-da1f5e61-972b-471d-9e98-c7376cd05dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561138398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2561138398
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1858851514
Short name T769
Test name
Test status
Simulation time 163706032 ps
CPU time 2.28 seconds
Started Jun 23 05:50:11 PM PDT 24
Finished Jun 23 05:50:15 PM PDT 24
Peak memory 224588 kb
Host smart-f2896e1b-37f7-4283-9388-67725778eb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858851514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1858851514
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1077735733
Short name T679
Test name
Test status
Simulation time 11760268714 ps
CPU time 72.04 seconds
Started Jun 23 05:50:12 PM PDT 24
Finished Jun 23 05:51:25 PM PDT 24
Peak memory 239732 kb
Host smart-3ccddaa9-5fcb-4640-90cb-92038b00c100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077735733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1077735733
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2333074615
Short name T265
Test name
Test status
Simulation time 1237431110 ps
CPU time 5.69 seconds
Started Jun 23 05:50:13 PM PDT 24
Finished Jun 23 05:50:20 PM PDT 24
Peak memory 232856 kb
Host smart-54b4c142-8bcc-42f2-9064-c43e290c66e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333074615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2333074615
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3886363175
Short name T60
Test name
Test status
Simulation time 369402166 ps
CPU time 3.56 seconds
Started Jun 23 05:50:12 PM PDT 24
Finished Jun 23 05:50:16 PM PDT 24
Peak memory 224636 kb
Host smart-f0e13a73-8e42-4089-9462-534ea12ae85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886363175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3886363175
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2180674160
Short name T144
Test name
Test status
Simulation time 1387073355 ps
CPU time 8.65 seconds
Started Jun 23 05:50:21 PM PDT 24
Finished Jun 23 05:50:30 PM PDT 24
Peak memory 219320 kb
Host smart-4a67f3dd-d243-417e-8887-fdeafde29ba0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2180674160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2180674160
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1327379539
Short name T729
Test name
Test status
Simulation time 774305108 ps
CPU time 4.73 seconds
Started Jun 23 05:50:14 PM PDT 24
Finished Jun 23 05:50:19 PM PDT 24
Peak memory 216408 kb
Host smart-85378d78-7fa1-489a-bad7-fe297fdb75c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327379539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1327379539
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2280872265
Short name T25
Test name
Test status
Simulation time 3334590982 ps
CPU time 10.17 seconds
Started Jun 23 05:50:11 PM PDT 24
Finished Jun 23 05:50:22 PM PDT 24
Peak memory 216500 kb
Host smart-5a6fd684-ebc7-4b7a-afac-90a313a6dc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280872265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2280872265
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3010017073
Short name T371
Test name
Test status
Simulation time 347985395 ps
CPU time 1.44 seconds
Started Jun 23 05:50:10 PM PDT 24
Finished Jun 23 05:50:13 PM PDT 24
Peak memory 216372 kb
Host smart-a5ce50f2-1597-4a91-9dc1-13375c277c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010017073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3010017073
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3854837134
Short name T498
Test name
Test status
Simulation time 107260836 ps
CPU time 0.78 seconds
Started Jun 23 05:50:13 PM PDT 24
Finished Jun 23 05:50:14 PM PDT 24
Peak memory 206084 kb
Host smart-edccbeb5-a5dd-4831-b47e-bbc5e39cde86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854837134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3854837134
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2851580326
Short name T53
Test name
Test status
Simulation time 12373919337 ps
CPU time 10.53 seconds
Started Jun 23 05:50:13 PM PDT 24
Finished Jun 23 05:50:24 PM PDT 24
Peak memory 224744 kb
Host smart-353f2522-5301-444d-a674-c40b95f9a22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851580326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2851580326
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.432079993
Short name T535
Test name
Test status
Simulation time 13075198 ps
CPU time 0.74 seconds
Started Jun 23 05:50:16 PM PDT 24
Finished Jun 23 05:50:17 PM PDT 24
Peak memory 205452 kb
Host smart-d30269b6-f89d-450f-9b8e-a6de970e3b33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432079993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.432079993
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1894875564
Short name T644
Test name
Test status
Simulation time 486729173 ps
CPU time 5.92 seconds
Started Jun 23 05:50:29 PM PDT 24
Finished Jun 23 05:50:36 PM PDT 24
Peak memory 224628 kb
Host smart-b090434b-08be-4d64-93b6-9afa63c67e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894875564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1894875564
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1147674972
Short name T24
Test name
Test status
Simulation time 15750085 ps
CPU time 0.77 seconds
Started Jun 23 05:50:21 PM PDT 24
Finished Jun 23 05:50:22 PM PDT 24
Peak memory 206760 kb
Host smart-8852d7c0-7477-4e90-8554-643f72f49247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147674972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1147674972
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1885992662
Short name T724
Test name
Test status
Simulation time 8712446475 ps
CPU time 23.74 seconds
Started Jun 23 05:50:26 PM PDT 24
Finished Jun 23 05:50:51 PM PDT 24
Peak memory 233024 kb
Host smart-c733b9c6-187a-4c6e-8397-6a861d45cb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885992662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1885992662
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3552043588
Short name T705
Test name
Test status
Simulation time 13290914349 ps
CPU time 127.56 seconds
Started Jun 23 05:50:19 PM PDT 24
Finished Jun 23 05:52:27 PM PDT 24
Peak memory 266504 kb
Host smart-813a091f-71ee-462d-b447-962bef6b58d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552043588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3552043588
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1107654628
Short name T533
Test name
Test status
Simulation time 870575467 ps
CPU time 15.43 seconds
Started Jun 23 05:50:19 PM PDT 24
Finished Jun 23 05:50:35 PM PDT 24
Peak memory 237296 kb
Host smart-be8b1904-6aee-432a-96cf-cc92563e8453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107654628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1107654628
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.4196012588
Short name T222
Test name
Test status
Simulation time 459646369 ps
CPU time 5.89 seconds
Started Jun 23 05:50:15 PM PDT 24
Finished Jun 23 05:50:22 PM PDT 24
Peak memory 232892 kb
Host smart-74d23f43-f447-41c0-971d-6e86996e2d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196012588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.4196012588
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.399083844
Short name T220
Test name
Test status
Simulation time 369015924 ps
CPU time 6.32 seconds
Started Jun 23 05:50:20 PM PDT 24
Finished Jun 23 05:50:26 PM PDT 24
Peak memory 232872 kb
Host smart-01210d29-0452-4090-95ce-6132f4e45f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399083844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.399083844
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3929601656
Short name T534
Test name
Test status
Simulation time 1204303354 ps
CPU time 4.93 seconds
Started Jun 23 05:50:24 PM PDT 24
Finished Jun 23 05:50:30 PM PDT 24
Peak memory 232880 kb
Host smart-674e45de-c0bc-4f97-9acb-d8119e064b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929601656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3929601656
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.184091649
Short name T146
Test name
Test status
Simulation time 69739384 ps
CPU time 3.54 seconds
Started Jun 23 05:50:22 PM PDT 24
Finished Jun 23 05:50:26 PM PDT 24
Peak memory 223196 kb
Host smart-1baaf763-8c54-46b3-be82-34f43ab8ed85
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=184091649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.184091649
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.91719675
Short name T442
Test name
Test status
Simulation time 6936336954 ps
CPU time 18.67 seconds
Started Jun 23 05:50:18 PM PDT 24
Finished Jun 23 05:50:37 PM PDT 24
Peak memory 216516 kb
Host smart-e552d943-cf44-40b8-a047-b8e7f694a579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91719675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.91719675
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1867335533
Short name T789
Test name
Test status
Simulation time 5209908333 ps
CPU time 5.02 seconds
Started Jun 23 05:50:25 PM PDT 24
Finished Jun 23 05:50:31 PM PDT 24
Peak memory 216472 kb
Host smart-1247b6bd-7b3b-46d9-871b-3e3bed67e382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867335533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1867335533
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.104816850
Short name T554
Test name
Test status
Simulation time 128126688 ps
CPU time 1.02 seconds
Started Jun 23 05:50:22 PM PDT 24
Finished Jun 23 05:50:24 PM PDT 24
Peak memory 207420 kb
Host smart-0f91dc37-6eff-4123-9a4d-3fde7e75047a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104816850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.104816850
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1887584373
Short name T762
Test name
Test status
Simulation time 196507723 ps
CPU time 0.9 seconds
Started Jun 23 05:50:19 PM PDT 24
Finished Jun 23 05:50:20 PM PDT 24
Peak memory 206020 kb
Host smart-355759a2-9721-4591-aed6-7e4689e68188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887584373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1887584373
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.4066728084
Short name T741
Test name
Test status
Simulation time 391535635 ps
CPU time 3.22 seconds
Started Jun 23 05:50:27 PM PDT 24
Finished Jun 23 05:50:31 PM PDT 24
Peak memory 232908 kb
Host smart-d9099ce5-d086-4a03-b1ed-7e7cbafb4056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066728084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.4066728084
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1332801517
Short name T612
Test name
Test status
Simulation time 13611390 ps
CPU time 0.76 seconds
Started Jun 23 05:50:27 PM PDT 24
Finished Jun 23 05:50:28 PM PDT 24
Peak memory 205516 kb
Host smart-5dbcbbb9-0442-45f0-a821-a04b789f627c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332801517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1332801517
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1903710559
Short name T653
Test name
Test status
Simulation time 31296399 ps
CPU time 2.11 seconds
Started Jun 23 05:50:24 PM PDT 24
Finished Jun 23 05:50:27 PM PDT 24
Peak memory 222900 kb
Host smart-a031838a-2c34-4e14-9948-6718bdbf58e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903710559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1903710559
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3966272494
Short name T649
Test name
Test status
Simulation time 39908820 ps
CPU time 0.84 seconds
Started Jun 23 05:50:15 PM PDT 24
Finished Jun 23 05:50:17 PM PDT 24
Peak memory 206708 kb
Host smart-e3fdd3e6-1de5-4c59-b251-980ac7a52292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966272494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3966272494
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.273794009
Short name T779
Test name
Test status
Simulation time 29569624324 ps
CPU time 51.83 seconds
Started Jun 23 05:50:22 PM PDT 24
Finished Jun 23 05:51:15 PM PDT 24
Peak memory 256164 kb
Host smart-43bd815e-9897-401f-9999-80914e1a4ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273794009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.273794009
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.824358314
Short name T868
Test name
Test status
Simulation time 29041121718 ps
CPU time 161.23 seconds
Started Jun 23 05:50:22 PM PDT 24
Finished Jun 23 05:53:04 PM PDT 24
Peak memory 265112 kb
Host smart-5ee3c563-bf53-46d6-9967-c1ece7d2565d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824358314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.824358314
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3956240710
Short name T916
Test name
Test status
Simulation time 157401474188 ps
CPU time 348.58 seconds
Started Jun 23 05:50:22 PM PDT 24
Finished Jun 23 05:56:11 PM PDT 24
Peak memory 253044 kb
Host smart-af8ec04e-ffc1-4e36-b4e0-179a7e0d867c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956240710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3956240710
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2645542063
Short name T509
Test name
Test status
Simulation time 303151981 ps
CPU time 6.1 seconds
Started Jun 23 05:50:22 PM PDT 24
Finished Jun 23 05:50:29 PM PDT 24
Peak memory 224596 kb
Host smart-7e795e5d-df6a-4c1e-a58e-915abad83b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645542063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2645542063
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.492856370
Short name T618
Test name
Test status
Simulation time 301931352 ps
CPU time 2.65 seconds
Started Jun 23 05:50:16 PM PDT 24
Finished Jun 23 05:50:19 PM PDT 24
Peak memory 232884 kb
Host smart-bc98376a-8f90-4f63-9746-01d56859741d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492856370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.492856370
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1088102606
Short name T547
Test name
Test status
Simulation time 1234043188 ps
CPU time 7.98 seconds
Started Jun 23 05:50:25 PM PDT 24
Finished Jun 23 05:50:35 PM PDT 24
Peak memory 224576 kb
Host smart-5663471a-c7c4-452c-8035-5a20371162d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088102606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1088102606
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2630840406
Short name T848
Test name
Test status
Simulation time 22748612538 ps
CPU time 7.87 seconds
Started Jun 23 05:50:18 PM PDT 24
Finished Jun 23 05:50:26 PM PDT 24
Peak memory 233004 kb
Host smart-6facf647-3a03-4a63-842b-311e6604d9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630840406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2630840406
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1040558137
Short name T788
Test name
Test status
Simulation time 4881937992 ps
CPU time 14.26 seconds
Started Jun 23 05:50:21 PM PDT 24
Finished Jun 23 05:50:36 PM PDT 24
Peak memory 233000 kb
Host smart-9549c0e4-b8a1-4ee6-9fe1-fa552a46cdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040558137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1040558137
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1529089094
Short name T646
Test name
Test status
Simulation time 4477484977 ps
CPU time 16.46 seconds
Started Jun 23 05:50:26 PM PDT 24
Finished Jun 23 05:50:43 PM PDT 24
Peak memory 219380 kb
Host smart-f95d5ce0-451e-4aea-9c04-120a44b9621b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1529089094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1529089094
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.227373142
Short name T622
Test name
Test status
Simulation time 157365913 ps
CPU time 0.97 seconds
Started Jun 23 05:50:26 PM PDT 24
Finished Jun 23 05:50:28 PM PDT 24
Peak memory 206972 kb
Host smart-cd607d70-902f-4bcb-862e-deb643bbc6bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227373142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.227373142
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2776398349
Short name T902
Test name
Test status
Simulation time 13366845568 ps
CPU time 21.62 seconds
Started Jun 23 05:50:16 PM PDT 24
Finished Jun 23 05:50:38 PM PDT 24
Peak memory 216548 kb
Host smart-cc303e47-fcf2-4efa-9e4c-a45770190f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776398349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2776398349
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.4284641062
Short name T342
Test name
Test status
Simulation time 2916963858 ps
CPU time 7.8 seconds
Started Jun 23 05:50:30 PM PDT 24
Finished Jun 23 05:50:39 PM PDT 24
Peak memory 216472 kb
Host smart-25f8d63b-0e52-4811-b936-2590f5f07c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284641062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.4284641062
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2309182565
Short name T865
Test name
Test status
Simulation time 239542773 ps
CPU time 3 seconds
Started Jun 23 05:50:18 PM PDT 24
Finished Jun 23 05:50:21 PM PDT 24
Peak memory 208260 kb
Host smart-ad619786-6c6c-4b3f-a9e6-6e1ab9e1e289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309182565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2309182565
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.269446775
Short name T614
Test name
Test status
Simulation time 81719338 ps
CPU time 0.96 seconds
Started Jun 23 05:50:22 PM PDT 24
Finished Jun 23 05:50:24 PM PDT 24
Peak memory 206104 kb
Host smart-ce781b74-3718-4916-8d1e-545b7828d02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269446775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.269446775
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2802916843
Short name T677
Test name
Test status
Simulation time 129391696 ps
CPU time 2.8 seconds
Started Jun 23 05:50:26 PM PDT 24
Finished Jun 23 05:50:29 PM PDT 24
Peak memory 232772 kb
Host smart-1f88e85f-fd25-4a13-a746-c00433b86017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802916843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2802916843
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2250574010
Short name T708
Test name
Test status
Simulation time 34174119 ps
CPU time 0.75 seconds
Started Jun 23 05:50:23 PM PDT 24
Finished Jun 23 05:50:24 PM PDT 24
Peak memory 204904 kb
Host smart-ebb62779-c32f-49ab-a08c-90105d7fe92c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250574010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2250574010
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1811025165
Short name T246
Test name
Test status
Simulation time 438745194 ps
CPU time 2.54 seconds
Started Jun 23 05:50:24 PM PDT 24
Finished Jun 23 05:50:27 PM PDT 24
Peak memory 224604 kb
Host smart-d577535e-383f-4882-9d67-d5e22bddd2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811025165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1811025165
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2882273216
Short name T61
Test name
Test status
Simulation time 31481783 ps
CPU time 0.74 seconds
Started Jun 23 05:50:23 PM PDT 24
Finished Jun 23 05:50:24 PM PDT 24
Peak memory 205640 kb
Host smart-71e9187c-295d-4f1a-8bd0-be0ac5554c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882273216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2882273216
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.4097793937
Short name T40
Test name
Test status
Simulation time 15813563945 ps
CPU time 77.87 seconds
Started Jun 23 05:50:29 PM PDT 24
Finished Jun 23 05:51:47 PM PDT 24
Peak memory 238120 kb
Host smart-4a7557cf-0ed3-489e-ac0d-99d790e83d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097793937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.4097793937
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3812186566
Short name T486
Test name
Test status
Simulation time 18659298495 ps
CPU time 83.9 seconds
Started Jun 23 05:50:25 PM PDT 24
Finished Jun 23 05:51:50 PM PDT 24
Peak memory 253656 kb
Host smart-3d5da656-8a4e-4dc4-ae0e-e286e8e7e55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812186566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3812186566
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3260879488
Short name T52
Test name
Test status
Simulation time 24479337346 ps
CPU time 93.42 seconds
Started Jun 23 05:50:24 PM PDT 24
Finished Jun 23 05:51:58 PM PDT 24
Peak memory 249444 kb
Host smart-e3822d1b-7457-4810-b321-9385c370abf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260879488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3260879488
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2546558569
Short name T437
Test name
Test status
Simulation time 597202081 ps
CPU time 7.7 seconds
Started Jun 23 05:50:24 PM PDT 24
Finished Jun 23 05:50:32 PM PDT 24
Peak memory 224636 kb
Host smart-a22c3563-05d2-47c1-a022-88650a80636e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546558569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2546558569
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2493138390
Short name T791
Test name
Test status
Simulation time 910155993 ps
CPU time 6.5 seconds
Started Jun 23 05:50:23 PM PDT 24
Finished Jun 23 05:50:30 PM PDT 24
Peak memory 232892 kb
Host smart-ff7a2f72-b5b6-468b-a844-8e12a76ca5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493138390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2493138390
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2786668578
Short name T917
Test name
Test status
Simulation time 918518236 ps
CPU time 3.11 seconds
Started Jun 23 05:50:23 PM PDT 24
Finished Jun 23 05:50:26 PM PDT 24
Peak memory 224616 kb
Host smart-8f4584dc-7d9d-4b15-849c-a2841644494d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786668578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2786668578
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1294112184
Short name T384
Test name
Test status
Simulation time 12493883488 ps
CPU time 10.21 seconds
Started Jun 23 05:50:28 PM PDT 24
Finished Jun 23 05:50:39 PM PDT 24
Peak memory 224716 kb
Host smart-c97fafdc-921b-4bb7-9b42-e42f4d7d9c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294112184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1294112184
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.4231629285
Short name T205
Test name
Test status
Simulation time 1617565479 ps
CPU time 4.89 seconds
Started Jun 23 05:50:26 PM PDT 24
Finished Jun 23 05:50:32 PM PDT 24
Peak memory 232844 kb
Host smart-7db498cc-e81d-46eb-8e2b-9be2d8138e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231629285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.4231629285
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.811818102
Short name T435
Test name
Test status
Simulation time 8044170325 ps
CPU time 4.57 seconds
Started Jun 23 05:50:20 PM PDT 24
Finished Jun 23 05:50:25 PM PDT 24
Peak memory 219296 kb
Host smart-45e97af7-dd4d-43c9-93d5-6fdd441f3426
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=811818102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.811818102
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3569549973
Short name T430
Test name
Test status
Simulation time 397353378 ps
CPU time 0.97 seconds
Started Jun 23 05:50:27 PM PDT 24
Finished Jun 23 05:50:29 PM PDT 24
Peak memory 207832 kb
Host smart-3af5aed5-8ee9-45b4-9fbd-c92146dd61bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569549973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3569549973
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1729557050
Short name T923
Test name
Test status
Simulation time 4458588688 ps
CPU time 21.05 seconds
Started Jun 23 05:50:25 PM PDT 24
Finished Jun 23 05:50:46 PM PDT 24
Peak memory 216888 kb
Host smart-a1c60731-9302-4819-98b1-41ac421b4734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729557050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1729557050
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.45422125
Short name T704
Test name
Test status
Simulation time 793973575 ps
CPU time 5.56 seconds
Started Jun 23 05:50:29 PM PDT 24
Finished Jun 23 05:50:35 PM PDT 24
Peak memory 216372 kb
Host smart-20b4933a-2311-462a-8044-858cc552a774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45422125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.45422125
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2010780875
Short name T761
Test name
Test status
Simulation time 77702578 ps
CPU time 1.17 seconds
Started Jun 23 05:50:35 PM PDT 24
Finished Jun 23 05:50:36 PM PDT 24
Peak memory 208104 kb
Host smart-eeb72ce5-60fd-4507-afd3-250f9be70aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010780875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2010780875
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3931450768
Short name T540
Test name
Test status
Simulation time 168814673 ps
CPU time 0.92 seconds
Started Jun 23 05:50:21 PM PDT 24
Finished Jun 23 05:50:23 PM PDT 24
Peak memory 206132 kb
Host smart-f654c084-b026-46b7-b005-f5335d3b22ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931450768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3931450768
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3428838422
Short name T453
Test name
Test status
Simulation time 1752885382 ps
CPU time 7.55 seconds
Started Jun 23 05:50:25 PM PDT 24
Finished Jun 23 05:50:34 PM PDT 24
Peak memory 232908 kb
Host smart-619dddb4-5b50-4849-81e9-4b48c535e22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428838422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3428838422
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2986473463
Short name T480
Test name
Test status
Simulation time 46428844 ps
CPU time 0.74 seconds
Started Jun 23 05:50:28 PM PDT 24
Finished Jun 23 05:50:30 PM PDT 24
Peak memory 204952 kb
Host smart-37ff5ed4-c9c8-4b8c-81fe-858d8dc75f69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986473463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2986473463
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2908472206
Short name T937
Test name
Test status
Simulation time 2889617143 ps
CPU time 9.56 seconds
Started Jun 23 05:50:29 PM PDT 24
Finished Jun 23 05:50:39 PM PDT 24
Peak memory 233008 kb
Host smart-be4e8eaa-f4c3-45c7-a684-04ff52e92509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908472206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2908472206
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.98504167
Short name T863
Test name
Test status
Simulation time 58044951 ps
CPU time 0.78 seconds
Started Jun 23 05:50:21 PM PDT 24
Finished Jun 23 05:50:22 PM PDT 24
Peak memory 206776 kb
Host smart-f7e9d834-f6ef-4cde-8291-7a11572c2b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98504167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.98504167
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1197586405
Short name T434
Test name
Test status
Simulation time 12753753827 ps
CPU time 56.11 seconds
Started Jun 23 05:50:21 PM PDT 24
Finished Jun 23 05:51:18 PM PDT 24
Peak memory 254884 kb
Host smart-4303ec4d-443e-4061-959c-4bdd503adb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197586405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1197586405
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.4026705935
Short name T364
Test name
Test status
Simulation time 670305322 ps
CPU time 9.43 seconds
Started Jun 23 05:50:24 PM PDT 24
Finished Jun 23 05:50:34 PM PDT 24
Peak memory 217764 kb
Host smart-32516434-8f6f-4f98-a174-4043bfa584a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026705935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.4026705935
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2498989939
Short name T594
Test name
Test status
Simulation time 1409640692 ps
CPU time 14.71 seconds
Started Jun 23 05:50:22 PM PDT 24
Finished Jun 23 05:50:37 PM PDT 24
Peak memory 241048 kb
Host smart-9ae57b2a-3707-4826-a5f0-b70cc9c568fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498989939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2498989939
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1262881362
Short name T418
Test name
Test status
Simulation time 12700167696 ps
CPU time 19.9 seconds
Started Jun 23 05:50:24 PM PDT 24
Finished Jun 23 05:50:44 PM PDT 24
Peak memory 232920 kb
Host smart-433c4098-693b-42ac-abc3-728add937147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262881362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1262881362
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.878352994
Short name T208
Test name
Test status
Simulation time 256066689 ps
CPU time 3.97 seconds
Started Jun 23 05:50:21 PM PDT 24
Finished Jun 23 05:50:26 PM PDT 24
Peak memory 224656 kb
Host smart-e1f6ae49-cead-4944-b6c5-657635cfec6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878352994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.878352994
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.510723510
Short name T1
Test name
Test status
Simulation time 6943068807 ps
CPU time 8.67 seconds
Started Jun 23 05:50:29 PM PDT 24
Finished Jun 23 05:50:38 PM PDT 24
Peak memory 228288 kb
Host smart-e6cc9bbb-0d42-48d0-afbb-6b7d9c1f3644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510723510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.510723510
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.284380670
Short name T924
Test name
Test status
Simulation time 1707997620 ps
CPU time 9.72 seconds
Started Jun 23 05:50:29 PM PDT 24
Finished Jun 23 05:50:39 PM PDT 24
Peak memory 249284 kb
Host smart-4de12a3a-2d47-4181-a754-18e4072429b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284380670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.284380670
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3085717101
Short name T834
Test name
Test status
Simulation time 644189492 ps
CPU time 6.73 seconds
Started Jun 23 05:50:21 PM PDT 24
Finished Jun 23 05:50:28 PM PDT 24
Peak memory 222652 kb
Host smart-45c6d377-0f00-450e-9171-a3d00ec10f2c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3085717101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3085717101
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.4012482971
Short name T150
Test name
Test status
Simulation time 208307966 ps
CPU time 1.06 seconds
Started Jun 23 05:50:38 PM PDT 24
Finished Jun 23 05:50:40 PM PDT 24
Peak memory 207068 kb
Host smart-486b48a9-13e9-4766-ad16-e35032d7c06a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012482971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.4012482971
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.753056026
Short name T922
Test name
Test status
Simulation time 2900773537 ps
CPU time 31.49 seconds
Started Jun 23 05:50:23 PM PDT 24
Finished Jun 23 05:50:55 PM PDT 24
Peak memory 216492 kb
Host smart-fd81722e-fbff-4f6f-94ac-bbd8a37811b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753056026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.753056026
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1130313694
Short name T366
Test name
Test status
Simulation time 3288222630 ps
CPU time 7.5 seconds
Started Jun 23 05:50:21 PM PDT 24
Finished Jun 23 05:50:29 PM PDT 24
Peak memory 216524 kb
Host smart-03c7df29-6f20-4f30-87a7-2444bad259af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130313694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1130313694
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2228279857
Short name T655
Test name
Test status
Simulation time 24056960 ps
CPU time 0.93 seconds
Started Jun 23 05:50:18 PM PDT 24
Finished Jun 23 05:50:20 PM PDT 24
Peak memory 207404 kb
Host smart-9fda60e6-c654-48cc-aac9-22550d82c026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228279857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2228279857
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1148537473
Short name T755
Test name
Test status
Simulation time 31561373 ps
CPU time 0.89 seconds
Started Jun 23 05:50:26 PM PDT 24
Finished Jun 23 05:50:28 PM PDT 24
Peak memory 206112 kb
Host smart-f49125cc-2903-44d3-994c-093f98007b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148537473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1148537473
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1073057460
Short name T617
Test name
Test status
Simulation time 599920924 ps
CPU time 3.91 seconds
Started Jun 23 05:50:28 PM PDT 24
Finished Jun 23 05:50:32 PM PDT 24
Peak memory 232696 kb
Host smart-8a08ab4f-b4a8-4518-9de7-1880f20aba65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073057460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1073057460
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.801892917
Short name T925
Test name
Test status
Simulation time 26088050 ps
CPU time 0.72 seconds
Started Jun 23 05:50:35 PM PDT 24
Finished Jun 23 05:50:36 PM PDT 24
Peak memory 205492 kb
Host smart-7116667e-17f4-4fb5-b7dc-97bf9604feca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801892917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.801892917
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2468314968
Short name T79
Test name
Test status
Simulation time 7521159495 ps
CPU time 19.16 seconds
Started Jun 23 05:50:29 PM PDT 24
Finished Jun 23 05:50:49 PM PDT 24
Peak memory 232988 kb
Host smart-6105f0e6-a71d-4365-bb6b-0b17ae5b5dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468314968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2468314968
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.166301149
Short name T501
Test name
Test status
Simulation time 32523004 ps
CPU time 0.75 seconds
Started Jun 23 05:50:31 PM PDT 24
Finished Jun 23 05:50:32 PM PDT 24
Peak memory 207076 kb
Host smart-194d0136-a9b6-40c9-a6a5-99a3c8648443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166301149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.166301149
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3962473637
Short name T54
Test name
Test status
Simulation time 3389358525 ps
CPU time 64.41 seconds
Started Jun 23 05:50:32 PM PDT 24
Finished Jun 23 05:51:37 PM PDT 24
Peak memory 252856 kb
Host smart-2ba3282e-38ad-4a38-82f9-da536e92e8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962473637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3962473637
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2104510469
Short name T550
Test name
Test status
Simulation time 33529767480 ps
CPU time 317.65 seconds
Started Jun 23 05:50:28 PM PDT 24
Finished Jun 23 05:55:47 PM PDT 24
Peak memory 253956 kb
Host smart-69946fe8-dbe6-4b40-935e-3c179ba121b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104510469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2104510469
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.4042805270
Short name T209
Test name
Test status
Simulation time 28966930075 ps
CPU time 178.73 seconds
Started Jun 23 05:50:27 PM PDT 24
Finished Jun 23 05:53:27 PM PDT 24
Peak memory 257288 kb
Host smart-fd51cbdc-181e-4b9e-ac91-8b031168b6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042805270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.4042805270
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1069059281
Short name T643
Test name
Test status
Simulation time 7223280519 ps
CPU time 18.66 seconds
Started Jun 23 05:50:28 PM PDT 24
Finished Jun 23 05:50:47 PM PDT 24
Peak memory 224768 kb
Host smart-8e24a5ab-93d6-42ec-86f2-a15fe92d5a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069059281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1069059281
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.4065824835
Short name T59
Test name
Test status
Simulation time 1002442023 ps
CPU time 13.13 seconds
Started Jun 23 05:50:26 PM PDT 24
Finished Jun 23 05:50:40 PM PDT 24
Peak memory 224784 kb
Host smart-1cf9ec88-d44b-463c-bfb7-b839c2ae807f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065824835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.4065824835
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.239063646
Short name T714
Test name
Test status
Simulation time 1694888586 ps
CPU time 10.19 seconds
Started Jun 23 05:50:26 PM PDT 24
Finished Jun 23 05:50:37 PM PDT 24
Peak memory 232860 kb
Host smart-b458cdfa-4328-444d-946d-11bf54c5775a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239063646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.239063646
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.400684679
Short name T160
Test name
Test status
Simulation time 1528059555 ps
CPU time 6.84 seconds
Started Jun 23 05:50:26 PM PDT 24
Finished Jun 23 05:50:34 PM PDT 24
Peak memory 232852 kb
Host smart-d4cd0c05-788b-4429-b614-8fa4843d6e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400684679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.400684679
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2188931319
Short name T660
Test name
Test status
Simulation time 2038669752 ps
CPU time 4.4 seconds
Started Jun 23 05:50:27 PM PDT 24
Finished Jun 23 05:50:32 PM PDT 24
Peak memory 219196 kb
Host smart-fa65ceb2-906d-41ee-a50a-61cdb95bc42d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2188931319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2188931319
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.390449689
Short name T156
Test name
Test status
Simulation time 39506084084 ps
CPU time 92.69 seconds
Started Jun 23 05:50:29 PM PDT 24
Finished Jun 23 05:52:03 PM PDT 24
Peak memory 241244 kb
Host smart-f8083ea0-e2ab-4ee7-9caa-ced00614eb67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390449689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.390449689
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3902029740
Short name T874
Test name
Test status
Simulation time 10414000401 ps
CPU time 53.48 seconds
Started Jun 23 05:50:27 PM PDT 24
Finished Jun 23 05:51:21 PM PDT 24
Peak memory 216588 kb
Host smart-eb89a002-ecaa-40cb-aa83-c23f287c8ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902029740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3902029740
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3231276167
Short name T628
Test name
Test status
Simulation time 5902883139 ps
CPU time 10.17 seconds
Started Jun 23 05:50:37 PM PDT 24
Finished Jun 23 05:50:48 PM PDT 24
Peak memory 216576 kb
Host smart-9bf0903d-88e8-46b1-9210-75945742d2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231276167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3231276167
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2962936890
Short name T652
Test name
Test status
Simulation time 53233139 ps
CPU time 1.12 seconds
Started Jun 23 05:50:28 PM PDT 24
Finished Jun 23 05:50:30 PM PDT 24
Peak memory 207916 kb
Host smart-e7f22e86-4e1b-4667-a1b1-a13ac0048aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962936890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2962936890
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.348631014
Short name T512
Test name
Test status
Simulation time 75655789 ps
CPU time 0.89 seconds
Started Jun 23 05:50:27 PM PDT 24
Finished Jun 23 05:50:29 PM PDT 24
Peak memory 206088 kb
Host smart-bd78038b-9784-4130-aec1-f32aab224c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348631014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.348631014
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2602178344
Short name T609
Test name
Test status
Simulation time 4919609722 ps
CPU time 12.67 seconds
Started Jun 23 05:50:28 PM PDT 24
Finished Jun 23 05:50:41 PM PDT 24
Peak memory 232956 kb
Host smart-b61a219f-96bb-451b-9b25-526bacf4c03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602178344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2602178344
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.4145210505
Short name T458
Test name
Test status
Simulation time 19364655 ps
CPU time 0.69 seconds
Started Jun 23 05:50:38 PM PDT 24
Finished Jun 23 05:50:40 PM PDT 24
Peak memory 205404 kb
Host smart-7057e0f7-eba0-4e94-a3b3-adaab2a25104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145210505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
4145210505
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2643943385
Short name T750
Test name
Test status
Simulation time 1594498630 ps
CPU time 3.9 seconds
Started Jun 23 05:50:31 PM PDT 24
Finished Jun 23 05:50:35 PM PDT 24
Peak memory 232864 kb
Host smart-f51e05a8-e496-4a5c-9af5-b1e4778f9646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643943385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2643943385
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.70892280
Short name T394
Test name
Test status
Simulation time 174788039 ps
CPU time 0.78 seconds
Started Jun 23 05:50:25 PM PDT 24
Finished Jun 23 05:50:27 PM PDT 24
Peak memory 205692 kb
Host smart-638340fc-1122-4104-beb1-9113214287c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70892280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.70892280
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.577541256
Short name T41
Test name
Test status
Simulation time 151162203598 ps
CPU time 270.32 seconds
Started Jun 23 05:50:40 PM PDT 24
Finished Jun 23 05:55:12 PM PDT 24
Peak memory 250328 kb
Host smart-10e33634-ab6e-4f9f-a1ac-70bda8be06b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577541256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.577541256
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1231898736
Short name T763
Test name
Test status
Simulation time 8408634972 ps
CPU time 139.56 seconds
Started Jun 23 05:50:40 PM PDT 24
Finished Jun 23 05:53:01 PM PDT 24
Peak memory 273276 kb
Host smart-d49a6757-6426-4964-b16a-2d9ff1c8db45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231898736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1231898736
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3470990985
Short name T305
Test name
Test status
Simulation time 10161982309 ps
CPU time 23.24 seconds
Started Jun 23 05:50:44 PM PDT 24
Finished Jun 23 05:51:08 PM PDT 24
Peak memory 224744 kb
Host smart-0d933e70-bcd8-4659-a4cf-742f457ed29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470990985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3470990985
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1488422979
Short name T635
Test name
Test status
Simulation time 194380544 ps
CPU time 3.56 seconds
Started Jun 23 05:50:43 PM PDT 24
Finished Jun 23 05:50:47 PM PDT 24
Peak memory 224648 kb
Host smart-93b2828c-3f83-4559-9fc2-9f50d115e8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488422979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1488422979
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2112847268
Short name T943
Test name
Test status
Simulation time 10295250141 ps
CPU time 79.84 seconds
Started Jun 23 05:50:39 PM PDT 24
Finished Jun 23 05:52:01 PM PDT 24
Peak memory 240784 kb
Host smart-b6eb9091-59bb-467e-b898-5ec9703e7281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112847268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2112847268
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2507108766
Short name T664
Test name
Test status
Simulation time 317234596 ps
CPU time 3.62 seconds
Started Jun 23 05:50:38 PM PDT 24
Finished Jun 23 05:50:42 PM PDT 24
Peak memory 224572 kb
Host smart-7ddb302f-fee5-46dc-a083-7f11b20e6bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507108766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2507108766
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.6091319
Short name T386
Test name
Test status
Simulation time 2632827423 ps
CPU time 6.96 seconds
Started Jun 23 05:50:28 PM PDT 24
Finished Jun 23 05:50:35 PM PDT 24
Peak memory 241032 kb
Host smart-8c5a5355-4303-4cf5-8124-1ca7ad2e01e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6091319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.6091319
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2717105641
Short name T715
Test name
Test status
Simulation time 1480973605 ps
CPU time 6.05 seconds
Started Jun 23 05:50:38 PM PDT 24
Finished Jun 23 05:50:45 PM PDT 24
Peak memory 223276 kb
Host smart-09344812-bbf8-44ff-a887-71a21c427ea5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2717105641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2717105641
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1304934873
Short name T295
Test name
Test status
Simulation time 10181155281 ps
CPU time 42.97 seconds
Started Jun 23 05:50:47 PM PDT 24
Finished Jun 23 05:51:31 PM PDT 24
Peak memory 249480 kb
Host smart-b82fc624-87fa-441d-803d-31efdb799318
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304934873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1304934873
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3350101495
Short name T626
Test name
Test status
Simulation time 5287894595 ps
CPU time 32.11 seconds
Started Jun 23 05:50:27 PM PDT 24
Finished Jun 23 05:51:00 PM PDT 24
Peak memory 220072 kb
Host smart-fb1b4a13-43c1-400c-a6db-d4243d03673e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350101495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3350101495
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2506870208
Short name T358
Test name
Test status
Simulation time 4866823423 ps
CPU time 16.75 seconds
Started Jun 23 05:50:25 PM PDT 24
Finished Jun 23 05:50:42 PM PDT 24
Peak memory 216480 kb
Host smart-77016e91-6c17-4855-9028-dc634b9a7e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506870208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2506870208
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2563600229
Short name T13
Test name
Test status
Simulation time 168244182 ps
CPU time 2.96 seconds
Started Jun 23 05:50:28 PM PDT 24
Finished Jun 23 05:50:32 PM PDT 24
Peak memory 216404 kb
Host smart-98d1254e-d779-4e1a-a307-fb67960cda52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563600229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2563600229
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2652369352
Short name T363
Test name
Test status
Simulation time 305071711 ps
CPU time 0.89 seconds
Started Jun 23 05:50:29 PM PDT 24
Finished Jun 23 05:50:31 PM PDT 24
Peak memory 206120 kb
Host smart-320124cb-a5b9-4b50-ae2e-985dc885f3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652369352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2652369352
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3581314984
Short name T352
Test name
Test status
Simulation time 2763910923 ps
CPU time 6.11 seconds
Started Jun 23 05:50:33 PM PDT 24
Finished Jun 23 05:50:40 PM PDT 24
Peak memory 233028 kb
Host smart-ae91c046-7099-43a3-9ad3-b4c06c4622ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581314984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3581314984
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.509105886
Short name T634
Test name
Test status
Simulation time 937520496 ps
CPU time 4.06 seconds
Started Jun 23 05:50:40 PM PDT 24
Finished Jun 23 05:50:46 PM PDT 24
Peak memory 224640 kb
Host smart-be84eec3-3975-45f8-a80b-6d0bbf859e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509105886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.509105886
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2491502548
Short name T952
Test name
Test status
Simulation time 22035420 ps
CPU time 0.84 seconds
Started Jun 23 05:50:40 PM PDT 24
Finished Jun 23 05:50:42 PM PDT 24
Peak memory 206720 kb
Host smart-65ce866c-7630-4cc1-81ab-6282c440841f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491502548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2491502548
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3483574503
Short name T134
Test name
Test status
Simulation time 33104302810 ps
CPU time 37.78 seconds
Started Jun 23 05:50:32 PM PDT 24
Finished Jun 23 05:51:10 PM PDT 24
Peak memory 217880 kb
Host smart-b2ed764e-176e-4f19-81a4-8da82d63456b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483574503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3483574503
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.566363468
Short name T847
Test name
Test status
Simulation time 2469450868 ps
CPU time 53.68 seconds
Started Jun 23 05:50:30 PM PDT 24
Finished Jun 23 05:51:24 PM PDT 24
Peak memory 249424 kb
Host smart-4f990cb8-3018-470b-bf88-e1c8ed943df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566363468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.566363468
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1811006383
Short name T306
Test name
Test status
Simulation time 1781093343 ps
CPU time 11.91 seconds
Started Jun 23 05:50:39 PM PDT 24
Finished Jun 23 05:50:52 PM PDT 24
Peak memory 248364 kb
Host smart-1da240f7-194c-40ef-9dc1-0d16ceab1f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811006383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1811006383
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.765805698
Short name T665
Test name
Test status
Simulation time 697908624 ps
CPU time 6.11 seconds
Started Jun 23 05:50:30 PM PDT 24
Finished Jun 23 05:50:36 PM PDT 24
Peak memory 224624 kb
Host smart-d4e21eec-3964-4e92-b6fb-71c885f5ea30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765805698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.765805698
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3419449334
Short name T4
Test name
Test status
Simulation time 188311630 ps
CPU time 2.52 seconds
Started Jun 23 05:50:39 PM PDT 24
Finished Jun 23 05:50:43 PM PDT 24
Peak memory 224560 kb
Host smart-ab4e0631-e0ec-4ff8-a9fe-bf8728e7dcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419449334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3419449334
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1497967244
Short name T201
Test name
Test status
Simulation time 8033924143 ps
CPU time 25 seconds
Started Jun 23 05:50:34 PM PDT 24
Finished Jun 23 05:51:00 PM PDT 24
Peak memory 232868 kb
Host smart-275dc44d-7ed6-4a98-82d9-340faf9571ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497967244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1497967244
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2998228111
Short name T662
Test name
Test status
Simulation time 13573818633 ps
CPU time 33.82 seconds
Started Jun 23 05:50:32 PM PDT 24
Finished Jun 23 05:51:06 PM PDT 24
Peak memory 224804 kb
Host smart-7c4517a4-01af-4e65-9e09-f30bd4c640b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998228111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2998228111
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1149420140
Short name T145
Test name
Test status
Simulation time 963651469 ps
CPU time 5.74 seconds
Started Jun 23 05:50:32 PM PDT 24
Finished Jun 23 05:50:38 PM PDT 24
Peak memory 220596 kb
Host smart-83506d0f-b53a-4e01-8961-000cfe837dda
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1149420140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1149420140
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.4249507384
Short name T519
Test name
Test status
Simulation time 4013956465 ps
CPU time 17.35 seconds
Started Jun 23 05:50:39 PM PDT 24
Finished Jun 23 05:50:58 PM PDT 24
Peak memory 216536 kb
Host smart-3235cd74-d7f2-4a60-b8fc-e53fa1c5c522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249507384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.4249507384
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1439351729
Short name T333
Test name
Test status
Simulation time 1346060105 ps
CPU time 4.14 seconds
Started Jun 23 05:50:39 PM PDT 24
Finished Jun 23 05:50:45 PM PDT 24
Peak memory 216412 kb
Host smart-8cf088c7-f694-4be3-9a8f-6a85732f279d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439351729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1439351729
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2421591444
Short name T792
Test name
Test status
Simulation time 2660134222 ps
CPU time 3.82 seconds
Started Jun 23 05:50:36 PM PDT 24
Finished Jun 23 05:50:40 PM PDT 24
Peak memory 216552 kb
Host smart-186bf00a-8965-4465-befa-12c1955cd0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421591444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2421591444
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2449591832
Short name T393
Test name
Test status
Simulation time 336684284 ps
CPU time 1 seconds
Started Jun 23 05:50:38 PM PDT 24
Finished Jun 23 05:50:40 PM PDT 24
Peak memory 206016 kb
Host smart-6775ae41-74d4-4e56-a37c-99116fccdbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449591832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2449591832
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.39746591
Short name T233
Test name
Test status
Simulation time 17460280358 ps
CPU time 18.9 seconds
Started Jun 23 05:50:39 PM PDT 24
Finished Jun 23 05:51:00 PM PDT 24
Peak memory 240904 kb
Host smart-8c4dc21a-758a-4dd7-97af-8a4c48c67092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39746591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.39746591
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3433021334
Short name T347
Test name
Test status
Simulation time 39795433 ps
CPU time 0.7 seconds
Started Jun 23 05:49:46 PM PDT 24
Finished Jun 23 05:49:47 PM PDT 24
Peak memory 205472 kb
Host smart-705b048e-4a95-4f67-b955-1ce142314a1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433021334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
433021334
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.856677610
Short name T651
Test name
Test status
Simulation time 218320424 ps
CPU time 3.83 seconds
Started Jun 23 05:49:46 PM PDT 24
Finished Jun 23 05:49:51 PM PDT 24
Peak memory 232864 kb
Host smart-6a91ba85-a7df-4a54-aded-8083a47428af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856677610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.856677610
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1853311952
Short name T885
Test name
Test status
Simulation time 138618775 ps
CPU time 0.85 seconds
Started Jun 23 05:49:45 PM PDT 24
Finished Jun 23 05:49:46 PM PDT 24
Peak memory 206724 kb
Host smart-d6bc8f97-bb87-4f8c-89da-7e4ad061024b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853311952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1853311952
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1367147672
Short name T168
Test name
Test status
Simulation time 11878147692 ps
CPU time 86.57 seconds
Started Jun 23 05:49:48 PM PDT 24
Finished Jun 23 05:51:15 PM PDT 24
Peak memory 273900 kb
Host smart-7496365e-71ba-487f-bc17-448c048df796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367147672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1367147672
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2789441443
Short name T585
Test name
Test status
Simulation time 27254867794 ps
CPU time 115.29 seconds
Started Jun 23 05:49:54 PM PDT 24
Finished Jun 23 05:51:50 PM PDT 24
Peak memory 251484 kb
Host smart-e6cf319b-435a-474e-bc4e-a877e261b5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789441443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2789441443
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.725196304
Short name T28
Test name
Test status
Simulation time 6155197950 ps
CPU time 57.77 seconds
Started Jun 23 05:49:45 PM PDT 24
Finished Jun 23 05:50:43 PM PDT 24
Peak memory 255252 kb
Host smart-9d5820b2-773b-437b-8a12-43d118b13219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725196304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
725196304
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3911089071
Short name T239
Test name
Test status
Simulation time 848151557 ps
CPU time 10.61 seconds
Started Jun 23 05:49:45 PM PDT 24
Finished Jun 23 05:49:57 PM PDT 24
Peak memory 232868 kb
Host smart-de5a5810-2dee-4cf3-b900-dbc49af10b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911089071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3911089071
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3169968213
Short name T10
Test name
Test status
Simulation time 6737018225 ps
CPU time 17.55 seconds
Started Jun 23 05:49:42 PM PDT 24
Finished Jun 23 05:50:00 PM PDT 24
Peak memory 233020 kb
Host smart-0df54195-6eb2-419f-a7f3-1ae171fc7dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169968213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3169968213
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3931583728
Short name T287
Test name
Test status
Simulation time 165919132 ps
CPU time 4.14 seconds
Started Jun 23 05:49:55 PM PDT 24
Finished Jun 23 05:50:00 PM PDT 24
Peak memory 232856 kb
Host smart-39dcb6a7-29bb-4f6f-8cdf-45a6554a6794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931583728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3931583728
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1523196498
Short name T846
Test name
Test status
Simulation time 60466373756 ps
CPU time 17.36 seconds
Started Jun 23 05:49:46 PM PDT 24
Finished Jun 23 05:50:05 PM PDT 24
Peak memory 233028 kb
Host smart-7da1ff9b-a4b6-4df5-ba7d-879e14209910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523196498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1523196498
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2888345547
Short name T820
Test name
Test status
Simulation time 4217203359 ps
CPU time 7.58 seconds
Started Jun 23 05:49:45 PM PDT 24
Finished Jun 23 05:49:53 PM PDT 24
Peak memory 219704 kb
Host smart-02cc6607-d602-482f-a8ac-3168a6a39110
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2888345547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2888345547
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3991764229
Short name T69
Test name
Test status
Simulation time 133010521 ps
CPU time 1.06 seconds
Started Jun 23 05:49:41 PM PDT 24
Finished Jun 23 05:49:43 PM PDT 24
Peak memory 235524 kb
Host smart-46d33af4-c8cd-43fc-a8f6-df11ef7a9a01
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991764229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3991764229
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1655877544
Short name T886
Test name
Test status
Simulation time 11686222153 ps
CPU time 53.33 seconds
Started Jun 23 05:49:54 PM PDT 24
Finished Jun 23 05:50:48 PM PDT 24
Peak memory 249484 kb
Host smart-5dd613af-da2b-4ea2-8207-ebc0c05a804f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655877544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1655877544
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3502641182
Short name T935
Test name
Test status
Simulation time 12788658527 ps
CPU time 36.09 seconds
Started Jun 23 05:49:45 PM PDT 24
Finished Jun 23 05:50:21 PM PDT 24
Peak memory 216516 kb
Host smart-f22b68b9-45d8-491a-98e2-81f7d9283d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502641182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3502641182
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1057399449
Short name T470
Test name
Test status
Simulation time 59591276 ps
CPU time 0.7 seconds
Started Jun 23 05:49:43 PM PDT 24
Finished Jun 23 05:49:45 PM PDT 24
Peak memory 205804 kb
Host smart-4f5f85fc-5d55-4daa-b767-004b9c9aba6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057399449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1057399449
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2814809333
Short name T817
Test name
Test status
Simulation time 125255298 ps
CPU time 1.4 seconds
Started Jun 23 05:49:46 PM PDT 24
Finished Jun 23 05:49:49 PM PDT 24
Peak memory 216364 kb
Host smart-9da90ec2-5447-45e7-bf21-c2ccccb065ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814809333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2814809333
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3530491507
Short name T340
Test name
Test status
Simulation time 24414054 ps
CPU time 0.68 seconds
Started Jun 23 05:49:44 PM PDT 24
Finished Jun 23 05:49:45 PM PDT 24
Peak memory 205700 kb
Host smart-2fb3b3f6-fb54-4e22-a185-226b1a4a8ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530491507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3530491507
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1650156115
Short name T456
Test name
Test status
Simulation time 710289590 ps
CPU time 6.77 seconds
Started Jun 23 05:49:46 PM PDT 24
Finished Jun 23 05:49:53 PM PDT 24
Peak memory 224632 kb
Host smart-fbe00a96-60e1-476d-8c02-66ed9b850286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650156115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1650156115
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.862059439
Short name T819
Test name
Test status
Simulation time 33597368 ps
CPU time 0.72 seconds
Started Jun 23 05:50:40 PM PDT 24
Finished Jun 23 05:50:42 PM PDT 24
Peak memory 204944 kb
Host smart-dbad5546-cfac-47f9-8139-173fbc233bf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862059439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.862059439
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1998652357
Short name T460
Test name
Test status
Simulation time 160247811 ps
CPU time 4.39 seconds
Started Jun 23 05:50:45 PM PDT 24
Finished Jun 23 05:50:50 PM PDT 24
Peak memory 224708 kb
Host smart-c8174ee5-e2fb-443d-8563-8a70ba693e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998652357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1998652357
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1173726164
Short name T485
Test name
Test status
Simulation time 19666365 ps
CPU time 0.82 seconds
Started Jun 23 05:50:40 PM PDT 24
Finished Jun 23 05:50:43 PM PDT 24
Peak memory 206020 kb
Host smart-b7d944e3-17b7-4add-95be-7479ed096a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173726164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1173726164
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2015269645
Short name T51
Test name
Test status
Simulation time 10702687157 ps
CPU time 87.6 seconds
Started Jun 23 05:50:40 PM PDT 24
Finished Jun 23 05:52:09 PM PDT 24
Peak memory 249568 kb
Host smart-fec7f1bf-3df5-4222-8cd7-8242d42e2b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015269645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2015269645
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3621764094
Short name T80
Test name
Test status
Simulation time 190319986 ps
CPU time 6.42 seconds
Started Jun 23 05:50:39 PM PDT 24
Finished Jun 23 05:50:46 PM PDT 24
Peak memory 238428 kb
Host smart-731b7add-66d7-4047-b449-b443676d9d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621764094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3621764094
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1094244914
Short name T424
Test name
Test status
Simulation time 744318131 ps
CPU time 8.46 seconds
Started Jun 23 05:50:46 PM PDT 24
Finished Jun 23 05:50:56 PM PDT 24
Peak memory 232376 kb
Host smart-4ef2083a-2fc8-48a2-9cd8-31fdc831aeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094244914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1094244914
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2043414930
Short name T881
Test name
Test status
Simulation time 74281072 ps
CPU time 2.3 seconds
Started Jun 23 05:50:41 PM PDT 24
Finished Jun 23 05:50:45 PM PDT 24
Peak memory 223288 kb
Host smart-1f468b3d-c7df-4e80-ba4c-7253f6001b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043414930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2043414930
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2988371886
Short name T467
Test name
Test status
Simulation time 4058172894 ps
CPU time 7.91 seconds
Started Jun 23 05:50:45 PM PDT 24
Finished Jun 23 05:50:53 PM PDT 24
Peak memory 232940 kb
Host smart-c74c9af1-3b81-498b-9a23-c6d53229779c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988371886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2988371886
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2856313912
Short name T593
Test name
Test status
Simulation time 3175828967 ps
CPU time 4.45 seconds
Started Jun 23 05:50:38 PM PDT 24
Finished Jun 23 05:50:44 PM PDT 24
Peak memory 233016 kb
Host smart-87af2652-2b87-4609-a314-c40268b0906e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856313912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2856313912
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2543806987
Short name T420
Test name
Test status
Simulation time 4704724545 ps
CPU time 15.26 seconds
Started Jun 23 05:50:39 PM PDT 24
Finished Jun 23 05:50:56 PM PDT 24
Peak memory 223388 kb
Host smart-30c14398-c94f-4164-98a1-850bee4e8ded
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2543806987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2543806987
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2978884383
Short name T280
Test name
Test status
Simulation time 523867036041 ps
CPU time 848.9 seconds
Started Jun 23 05:50:39 PM PDT 24
Finished Jun 23 06:04:50 PM PDT 24
Peak memory 270824 kb
Host smart-758cdf03-dfec-44c3-a57b-22c1b567d717
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978884383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2978884383
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3133922370
Short name T392
Test name
Test status
Simulation time 4388593584 ps
CPU time 16.47 seconds
Started Jun 23 05:50:38 PM PDT 24
Finished Jun 23 05:50:54 PM PDT 24
Peak memory 216776 kb
Host smart-67e85103-22e2-442c-98eb-511d1bc85ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133922370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3133922370
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.957119620
Short name T506
Test name
Test status
Simulation time 40165224 ps
CPU time 0.69 seconds
Started Jun 23 05:50:39 PM PDT 24
Finished Jun 23 05:50:42 PM PDT 24
Peak memory 205788 kb
Host smart-166670bb-0b77-4401-957e-7200b851ab17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957119620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.957119620
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3627410712
Short name T892
Test name
Test status
Simulation time 17961157 ps
CPU time 0.92 seconds
Started Jun 23 05:50:46 PM PDT 24
Finished Jun 23 05:50:49 PM PDT 24
Peak memory 206744 kb
Host smart-efcdae3e-80bb-41aa-982a-7f8f341db137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627410712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3627410712
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1852697978
Short name T415
Test name
Test status
Simulation time 78007104 ps
CPU time 0.78 seconds
Started Jun 23 05:50:39 PM PDT 24
Finished Jun 23 05:50:41 PM PDT 24
Peak memory 206092 kb
Host smart-39ed6641-df47-4fcc-8755-6f4b5c7c4fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852697978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1852697978
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.344908164
Short name T656
Test name
Test status
Simulation time 702534685 ps
CPU time 4.03 seconds
Started Jun 23 05:50:39 PM PDT 24
Finished Jun 23 05:50:45 PM PDT 24
Peak memory 232904 kb
Host smart-984cd73b-5c96-450f-b7aa-6b8c9006f78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344908164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.344908164
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1092712439
Short name T369
Test name
Test status
Simulation time 10495786 ps
CPU time 0.71 seconds
Started Jun 23 05:50:46 PM PDT 24
Finished Jun 23 05:50:48 PM PDT 24
Peak memory 204904 kb
Host smart-ebfc6800-3cde-43a9-ae3b-e30fe5c78d5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092712439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1092712439
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1852258787
Short name T559
Test name
Test status
Simulation time 363687567 ps
CPU time 3.82 seconds
Started Jun 23 05:50:35 PM PDT 24
Finished Jun 23 05:50:40 PM PDT 24
Peak memory 232824 kb
Host smart-4eb3db00-8bc8-4e51-b6fd-06ca2661eddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852258787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1852258787
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.4158976338
Short name T659
Test name
Test status
Simulation time 36484750 ps
CPU time 0.87 seconds
Started Jun 23 05:50:46 PM PDT 24
Finished Jun 23 05:50:49 PM PDT 24
Peak memory 206220 kb
Host smart-dfab701c-14a5-4a1b-ad56-15b63f372067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158976338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.4158976338
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1128577583
Short name T301
Test name
Test status
Simulation time 67804481203 ps
CPU time 296.41 seconds
Started Jun 23 05:50:40 PM PDT 24
Finished Jun 23 05:55:38 PM PDT 24
Peak memory 271208 kb
Host smart-9eb64218-039c-47fc-a274-914403dbe3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128577583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1128577583
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2378715352
Short name T217
Test name
Test status
Simulation time 6236319493 ps
CPU time 79.31 seconds
Started Jun 23 05:50:45 PM PDT 24
Finished Jun 23 05:52:06 PM PDT 24
Peak memory 271604 kb
Host smart-37551075-706c-4af7-ae13-95227b8c5ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378715352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2378715352
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3522010368
Short name T226
Test name
Test status
Simulation time 16545094491 ps
CPU time 196.52 seconds
Started Jun 23 05:50:40 PM PDT 24
Finished Jun 23 05:53:58 PM PDT 24
Peak memory 257420 kb
Host smart-ddcd740b-5563-4270-a00d-03b30a455eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522010368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3522010368
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1152246570
Short name T903
Test name
Test status
Simulation time 2026822907 ps
CPU time 5.81 seconds
Started Jun 23 05:50:39 PM PDT 24
Finished Jun 23 05:50:47 PM PDT 24
Peak memory 234108 kb
Host smart-34672b31-a10d-462a-96ab-df687b866f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152246570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1152246570
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1855095546
Short name T471
Test name
Test status
Simulation time 1563690411 ps
CPU time 13.94 seconds
Started Jun 23 05:50:39 PM PDT 24
Finished Jun 23 05:50:54 PM PDT 24
Peak memory 219768 kb
Host smart-2a2772c3-1f88-451e-8116-0e04ce3c64fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855095546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1855095546
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2318440711
Short name T511
Test name
Test status
Simulation time 1201256146 ps
CPU time 19.42 seconds
Started Jun 23 05:50:45 PM PDT 24
Finished Jun 23 05:51:05 PM PDT 24
Peak memory 232812 kb
Host smart-8f98d6df-d025-4dda-b1cc-7a249536623d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318440711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2318440711
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.999954971
Short name T37
Test name
Test status
Simulation time 3348637203 ps
CPU time 13.4 seconds
Started Jun 23 05:50:40 PM PDT 24
Finished Jun 23 05:50:55 PM PDT 24
Peak memory 240968 kb
Host smart-8bd9de6a-5f3c-4275-9fe9-1db9038618cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999954971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.999954971
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3102069894
Short name T391
Test name
Test status
Simulation time 346532768 ps
CPU time 2.31 seconds
Started Jun 23 05:50:38 PM PDT 24
Finished Jun 23 05:50:41 PM PDT 24
Peak memory 224616 kb
Host smart-8d751dd4-9341-496d-b188-733ec83406cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102069894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3102069894
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3554107928
Short name T443
Test name
Test status
Simulation time 6527423954 ps
CPU time 10.56 seconds
Started Jun 23 05:50:40 PM PDT 24
Finished Jun 23 05:50:53 PM PDT 24
Peak memory 223320 kb
Host smart-4c732578-acfa-48a8-abb5-dd2af52167bd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3554107928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3554107928
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.4250788594
Short name T703
Test name
Test status
Simulation time 13994789591 ps
CPU time 125.46 seconds
Started Jun 23 05:50:41 PM PDT 24
Finished Jun 23 05:52:48 PM PDT 24
Peak memory 265880 kb
Host smart-f35ccb19-9031-4617-8c64-34fd65895e72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250788594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.4250788594
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.466181993
Short name T757
Test name
Test status
Simulation time 3492731815 ps
CPU time 10.14 seconds
Started Jun 23 05:50:39 PM PDT 24
Finished Jun 23 05:50:50 PM PDT 24
Peak memory 216596 kb
Host smart-445b8428-475e-4618-8d44-985c0957b882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466181993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.466181993
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.4286373841
Short name T399
Test name
Test status
Simulation time 60384253252 ps
CPU time 12.43 seconds
Started Jun 23 05:50:37 PM PDT 24
Finished Jun 23 05:50:49 PM PDT 24
Peak memory 216520 kb
Host smart-14e08409-7894-4229-ad1f-8d15a8d3a933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286373841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.4286373841
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3302876370
Short name T326
Test name
Test status
Simulation time 1470004955 ps
CPU time 2.92 seconds
Started Jun 23 05:50:40 PM PDT 24
Finished Jun 23 05:50:44 PM PDT 24
Peak memory 216376 kb
Host smart-4a665d92-6405-44ac-b80e-9d52fe8deb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302876370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3302876370
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3383429109
Short name T587
Test name
Test status
Simulation time 92228862 ps
CPU time 0.73 seconds
Started Jun 23 05:50:36 PM PDT 24
Finished Jun 23 05:50:38 PM PDT 24
Peak memory 206120 kb
Host smart-ef475a15-a022-465e-a692-e5dbbbbcdd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383429109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3383429109
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.495616582
Short name T826
Test name
Test status
Simulation time 7061491584 ps
CPU time 8.14 seconds
Started Jun 23 05:50:38 PM PDT 24
Finished Jun 23 05:50:47 PM PDT 24
Peak memory 233004 kb
Host smart-37611a21-9213-4508-b7e3-7975c10873a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495616582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.495616582
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.676788083
Short name T320
Test name
Test status
Simulation time 49886654 ps
CPU time 0.74 seconds
Started Jun 23 05:50:43 PM PDT 24
Finished Jun 23 05:50:44 PM PDT 24
Peak memory 205520 kb
Host smart-b9b2ec3c-ff7e-4cb2-ad1c-1b40c9aca92e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676788083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.676788083
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.826227767
Short name T93
Test name
Test status
Simulation time 110949688 ps
CPU time 3.69 seconds
Started Jun 23 05:50:44 PM PDT 24
Finished Jun 23 05:50:48 PM PDT 24
Peak memory 232840 kb
Host smart-35c7e998-6e59-4ffd-b196-766fdd37079d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826227767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.826227767
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3048910422
Short name T499
Test name
Test status
Simulation time 39349333 ps
CPU time 0.78 seconds
Started Jun 23 05:50:44 PM PDT 24
Finished Jun 23 05:50:45 PM PDT 24
Peak memory 206692 kb
Host smart-eaf92c06-b796-4cf8-bfff-1a45e10d97f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048910422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3048910422
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.510666640
Short name T190
Test name
Test status
Simulation time 18305968073 ps
CPU time 99.87 seconds
Started Jun 23 05:50:46 PM PDT 24
Finished Jun 23 05:52:28 PM PDT 24
Peak memory 255488 kb
Host smart-3afd5d62-df26-4b82-bd42-92e94234955e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510666640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.510666640
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.616720489
Short name T905
Test name
Test status
Simulation time 27102471804 ps
CPU time 114.42 seconds
Started Jun 23 05:50:39 PM PDT 24
Finished Jun 23 05:52:34 PM PDT 24
Peak memory 255540 kb
Host smart-0f434e36-ff69-4a80-ad47-59d4a98cf0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616720489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.616720489
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.62823045
Short name T379
Test name
Test status
Simulation time 2245814037 ps
CPU time 35.98 seconds
Started Jun 23 05:50:45 PM PDT 24
Finished Jun 23 05:51:23 PM PDT 24
Peak memory 232856 kb
Host smart-807eddea-e0ea-401a-a4d7-2586093bc612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62823045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.62823045
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.295392242
Short name T595
Test name
Test status
Simulation time 237631746 ps
CPU time 3.31 seconds
Started Jun 23 05:50:43 PM PDT 24
Finished Jun 23 05:50:47 PM PDT 24
Peak memory 232884 kb
Host smart-bd7236f2-6111-4eb8-a159-699c9e42b135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295392242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.295392242
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3788041252
Short name T532
Test name
Test status
Simulation time 306496241 ps
CPU time 4.07 seconds
Started Jun 23 05:50:44 PM PDT 24
Finished Jun 23 05:50:48 PM PDT 24
Peak memory 224568 kb
Host smart-ae79c109-5334-481c-a990-f2ddab2b0578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788041252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3788041252
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3373234410
Short name T930
Test name
Test status
Simulation time 813160217 ps
CPU time 5.43 seconds
Started Jun 23 05:50:44 PM PDT 24
Finished Jun 23 05:50:51 PM PDT 24
Peak memory 224552 kb
Host smart-f7ea7fd1-7cda-4f1f-a661-95bbfbbf220c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373234410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3373234410
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3728904331
Short name T526
Test name
Test status
Simulation time 178745510 ps
CPU time 3.97 seconds
Started Jun 23 05:50:43 PM PDT 24
Finished Jun 23 05:50:47 PM PDT 24
Peak memory 232828 kb
Host smart-ec421ae2-696c-4b55-8fb3-d0255f1cd148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728904331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3728904331
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.961403845
Short name T780
Test name
Test status
Simulation time 743646314 ps
CPU time 7.91 seconds
Started Jun 23 05:50:39 PM PDT 24
Finished Jun 23 05:50:49 PM PDT 24
Peak memory 223280 kb
Host smart-45fe262a-f09f-4534-9638-6b7e9e589c27
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=961403845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.961403845
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2485428370
Short name T758
Test name
Test status
Simulation time 26003459856 ps
CPU time 42.95 seconds
Started Jun 23 05:50:40 PM PDT 24
Finished Jun 23 05:51:25 PM PDT 24
Peak memory 216548 kb
Host smart-c1ec0101-fafa-42e5-8ce4-5b3d4983cdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485428370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2485428370
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1593116527
Short name T548
Test name
Test status
Simulation time 7255661742 ps
CPU time 3.89 seconds
Started Jun 23 05:50:44 PM PDT 24
Finished Jun 23 05:50:49 PM PDT 24
Peak memory 217492 kb
Host smart-69f557ae-3479-43a0-a30b-6e44c8026571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593116527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1593116527
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.721281365
Short name T367
Test name
Test status
Simulation time 661187747 ps
CPU time 2.55 seconds
Started Jun 23 05:50:46 PM PDT 24
Finished Jun 23 05:50:49 PM PDT 24
Peak memory 216384 kb
Host smart-47652343-80c8-4ac2-8e02-4fd1d03bfd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721281365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.721281365
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.878605413
Short name T520
Test name
Test status
Simulation time 92205533 ps
CPU time 0.83 seconds
Started Jun 23 05:50:40 PM PDT 24
Finished Jun 23 05:50:43 PM PDT 24
Peak memory 206112 kb
Host smart-eb4ffe39-14f5-41c9-adc7-c218d1649492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878605413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.878605413
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3078801500
Short name T461
Test name
Test status
Simulation time 50376842558 ps
CPU time 29.22 seconds
Started Jun 23 05:50:41 PM PDT 24
Finished Jun 23 05:51:12 PM PDT 24
Peak memory 240676 kb
Host smart-9aaaeef3-4c3d-441d-b744-563f6b51a8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078801500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3078801500
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1110089018
Short name T417
Test name
Test status
Simulation time 12918782 ps
CPU time 0.71 seconds
Started Jun 23 05:50:46 PM PDT 24
Finished Jun 23 05:50:48 PM PDT 24
Peak memory 205452 kb
Host smart-fb17ea7b-86fd-40fd-9252-93eb46a4aa7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110089018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1110089018
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3275772601
Short name T745
Test name
Test status
Simulation time 1716088624 ps
CPU time 2.37 seconds
Started Jun 23 05:50:46 PM PDT 24
Finished Jun 23 05:50:50 PM PDT 24
Peak memory 224336 kb
Host smart-a13317be-d6a8-4662-a7f1-a7eec21f0cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275772601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3275772601
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1893552265
Short name T561
Test name
Test status
Simulation time 20914016 ps
CPU time 0.77 seconds
Started Jun 23 05:50:46 PM PDT 24
Finished Jun 23 05:50:48 PM PDT 24
Peak memory 205992 kb
Host smart-b414ab23-dc2a-4b1d-b983-8332921afe70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893552265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1893552265
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2424609509
Short name T183
Test name
Test status
Simulation time 17979540818 ps
CPU time 62.89 seconds
Started Jun 23 05:50:46 PM PDT 24
Finished Jun 23 05:51:50 PM PDT 24
Peak memory 254632 kb
Host smart-61b428ff-ea99-4f59-9336-e07f49cbec20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424609509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2424609509
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1498573083
Short name T316
Test name
Test status
Simulation time 7724885160 ps
CPU time 81.74 seconds
Started Jun 23 05:50:46 PM PDT 24
Finished Jun 23 05:52:09 PM PDT 24
Peak memory 254292 kb
Host smart-d25c3d84-64b6-4b88-b0dc-37e611d3c117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498573083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1498573083
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.904665114
Short name T527
Test name
Test status
Simulation time 7583026283 ps
CPU time 92.05 seconds
Started Jun 23 05:50:51 PM PDT 24
Finished Jun 23 05:52:23 PM PDT 24
Peak memory 257656 kb
Host smart-2c456987-8c8d-49e3-b364-6a4915cb9ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904665114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.904665114
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.687060817
Short name T783
Test name
Test status
Simulation time 145694703 ps
CPU time 3.74 seconds
Started Jun 23 05:50:46 PM PDT 24
Finished Jun 23 05:50:51 PM PDT 24
Peak memory 232736 kb
Host smart-bbe3e785-8555-4439-ac5e-99da282cbcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687060817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.687060817
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2259347921
Short name T821
Test name
Test status
Simulation time 31935197 ps
CPU time 2.2 seconds
Started Jun 23 05:50:45 PM PDT 24
Finished Jun 23 05:50:48 PM PDT 24
Peak memory 224620 kb
Host smart-790cb800-ed5e-499a-9dae-0b65c082e34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259347921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2259347921
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3761116761
Short name T610
Test name
Test status
Simulation time 28723524979 ps
CPU time 72.19 seconds
Started Jun 23 05:50:47 PM PDT 24
Finished Jun 23 05:52:01 PM PDT 24
Peak memory 233016 kb
Host smart-c58468fa-a714-44a7-b2a0-0dbf5ed9279c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761116761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3761116761
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3880121064
Short name T334
Test name
Test status
Simulation time 479246209 ps
CPU time 2.4 seconds
Started Jun 23 05:50:45 PM PDT 24
Finished Jun 23 05:50:49 PM PDT 24
Peak memory 232488 kb
Host smart-698f3db2-d104-43fa-b52e-74942ebf545d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880121064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3880121064
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.4207970038
Short name T931
Test name
Test status
Simulation time 4839554068 ps
CPU time 12.39 seconds
Started Jun 23 05:50:45 PM PDT 24
Finished Jun 23 05:50:58 PM PDT 24
Peak memory 224832 kb
Host smart-3c833b7a-a66f-40f4-88ef-27e83a73adfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207970038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4207970038
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2410936364
Short name T697
Test name
Test status
Simulation time 191912817 ps
CPU time 3.77 seconds
Started Jun 23 05:50:47 PM PDT 24
Finished Jun 23 05:50:52 PM PDT 24
Peak memory 222808 kb
Host smart-da7a6738-3e27-44bb-aae8-03e9ce05d74d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2410936364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2410936364
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1713510121
Short name T285
Test name
Test status
Simulation time 87688258236 ps
CPU time 272.7 seconds
Started Jun 23 05:50:46 PM PDT 24
Finished Jun 23 05:55:20 PM PDT 24
Peak memory 267848 kb
Host smart-e0441b6c-bbf5-41eb-b685-db850f97837c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713510121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1713510121
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2128802249
Short name T349
Test name
Test status
Simulation time 22014250688 ps
CPU time 31.31 seconds
Started Jun 23 05:50:45 PM PDT 24
Finished Jun 23 05:51:18 PM PDT 24
Peak memory 216464 kb
Host smart-4538785d-3edd-41d0-9f4d-0e54b8b850cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128802249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2128802249
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.897436696
Short name T86
Test name
Test status
Simulation time 1958221612 ps
CPU time 1.6 seconds
Started Jun 23 05:50:45 PM PDT 24
Finished Jun 23 05:50:48 PM PDT 24
Peak memory 208024 kb
Host smart-b27e54f7-7cc2-48ce-91aa-c4bf91c010ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897436696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.897436696
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3805604079
Short name T336
Test name
Test status
Simulation time 203863219 ps
CPU time 7.04 seconds
Started Jun 23 05:50:42 PM PDT 24
Finished Jun 23 05:50:50 PM PDT 24
Peak memory 216408 kb
Host smart-0f0cedfa-c6eb-4413-aa26-85da05281bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805604079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3805604079
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3047809980
Short name T402
Test name
Test status
Simulation time 59415875 ps
CPU time 0.85 seconds
Started Jun 23 05:50:45 PM PDT 24
Finished Jun 23 05:50:47 PM PDT 24
Peak memory 206132 kb
Host smart-5a1e086f-46f6-40d8-b90c-3f46bcc1dffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047809980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3047809980
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1464112859
Short name T803
Test name
Test status
Simulation time 881935383 ps
CPU time 6.23 seconds
Started Jun 23 05:50:45 PM PDT 24
Finished Jun 23 05:50:51 PM PDT 24
Peak memory 241028 kb
Host smart-a2a132d0-fcac-4fd2-b8aa-fb21580da079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464112859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1464112859
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.111583886
Short name T493
Test name
Test status
Simulation time 42593321 ps
CPU time 0.75 seconds
Started Jun 23 05:50:45 PM PDT 24
Finished Jun 23 05:50:46 PM PDT 24
Peak memory 205816 kb
Host smart-43c6cfa0-b566-4567-9ef7-03b8991b026f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111583886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.111583886
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3888444794
Short name T244
Test name
Test status
Simulation time 915991078 ps
CPU time 9.57 seconds
Started Jun 23 05:50:43 PM PDT 24
Finished Jun 23 05:50:53 PM PDT 24
Peak memory 224712 kb
Host smart-f0a5739d-5e2e-444c-9a33-a5b2207cbe49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888444794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3888444794
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.253749331
Short name T795
Test name
Test status
Simulation time 67184045 ps
CPU time 0.8 seconds
Started Jun 23 05:50:47 PM PDT 24
Finished Jun 23 05:50:49 PM PDT 24
Peak memory 205724 kb
Host smart-382089af-56e1-4920-9113-e67f8993e732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253749331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.253749331
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3263374863
Short name T294
Test name
Test status
Simulation time 5763683606 ps
CPU time 52.82 seconds
Started Jun 23 05:50:45 PM PDT 24
Finished Jun 23 05:51:39 PM PDT 24
Peak memory 249408 kb
Host smart-9db0fefd-871e-4999-9cd3-cd7d19a7e53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263374863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3263374863
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1992140641
Short name T312
Test name
Test status
Simulation time 32094604044 ps
CPU time 52.33 seconds
Started Jun 23 05:50:47 PM PDT 24
Finished Jun 23 05:51:41 PM PDT 24
Peak memory 241244 kb
Host smart-40f38ce1-0932-4888-994a-5ff58e620ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992140641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1992140641
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2045773748
Short name T529
Test name
Test status
Simulation time 110525680744 ps
CPU time 315.55 seconds
Started Jun 23 05:50:48 PM PDT 24
Finished Jun 23 05:56:05 PM PDT 24
Peak memory 256180 kb
Host smart-e3dc5a12-32c5-497f-a96c-92ee226e0099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045773748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2045773748
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2434832459
Short name T307
Test name
Test status
Simulation time 398520830 ps
CPU time 4.76 seconds
Started Jun 23 05:50:47 PM PDT 24
Finished Jun 23 05:50:53 PM PDT 24
Peak memory 232884 kb
Host smart-e5cc0159-137a-486a-b2c3-6152e67b48fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434832459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2434832459
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1847671796
Short name T401
Test name
Test status
Simulation time 5861968953 ps
CPU time 16.85 seconds
Started Jun 23 05:50:46 PM PDT 24
Finished Jun 23 05:51:04 PM PDT 24
Peak memory 232988 kb
Host smart-4b5853f4-c19b-48e0-873f-3a4cb5a0092c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847671796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1847671796
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1074104086
Short name T403
Test name
Test status
Simulation time 1180787505 ps
CPU time 17.63 seconds
Started Jun 23 05:50:43 PM PDT 24
Finished Jun 23 05:51:01 PM PDT 24
Peak memory 224684 kb
Host smart-6a321c79-d394-428e-b798-4868e1382b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074104086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1074104086
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.835269862
Short name T876
Test name
Test status
Simulation time 2291763465 ps
CPU time 8.24 seconds
Started Jun 23 05:50:48 PM PDT 24
Finished Jun 23 05:50:57 PM PDT 24
Peak memory 236040 kb
Host smart-dabbcae1-91ad-4df4-adfa-de473debd35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835269862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.835269862
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2420376767
Short name T487
Test name
Test status
Simulation time 12529407501 ps
CPU time 21.58 seconds
Started Jun 23 05:50:44 PM PDT 24
Finished Jun 23 05:51:07 PM PDT 24
Peak memory 240448 kb
Host smart-5ddf3bf3-fa46-41f5-9bef-87f6bf98fe53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420376767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2420376767
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1281253170
Short name T382
Test name
Test status
Simulation time 3402768078 ps
CPU time 8.91 seconds
Started Jun 23 05:50:47 PM PDT 24
Finished Jun 23 05:50:57 PM PDT 24
Peak memory 221044 kb
Host smart-31ed89eb-1897-4104-b62f-277e2e3f2344
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1281253170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1281253170
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1094108493
Short name T20
Test name
Test status
Simulation time 54192253698 ps
CPU time 126.47 seconds
Started Jun 23 05:50:45 PM PDT 24
Finished Jun 23 05:52:52 PM PDT 24
Peak memory 254348 kb
Host smart-7065234a-c0fb-4725-861c-627e0ec934c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094108493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1094108493
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.902868018
Short name T425
Test name
Test status
Simulation time 1388852984 ps
CPU time 13.64 seconds
Started Jun 23 05:50:47 PM PDT 24
Finished Jun 23 05:51:02 PM PDT 24
Peak memory 216456 kb
Host smart-d7a24fcb-f4f0-4a47-b433-abc4f17738d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902868018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.902868018
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1940850354
Short name T503
Test name
Test status
Simulation time 56856038159 ps
CPU time 16.27 seconds
Started Jun 23 05:50:48 PM PDT 24
Finished Jun 23 05:51:05 PM PDT 24
Peak memory 216644 kb
Host smart-daf8181f-be39-459f-a1a0-5d8191d77c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940850354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1940850354
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2929161124
Short name T543
Test name
Test status
Simulation time 124947320 ps
CPU time 2.95 seconds
Started Jun 23 05:50:47 PM PDT 24
Finished Jun 23 05:50:51 PM PDT 24
Peak memory 216408 kb
Host smart-48f9d545-345f-4640-8b82-c26526925b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929161124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2929161124
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3271770453
Short name T73
Test name
Test status
Simulation time 859583723 ps
CPU time 0.87 seconds
Started Jun 23 05:50:47 PM PDT 24
Finished Jun 23 05:50:49 PM PDT 24
Peak memory 206112 kb
Host smart-ad2019cf-248d-4cd5-bfe8-ec02fc465c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271770453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3271770453
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2700261351
Short name T553
Test name
Test status
Simulation time 3880470588 ps
CPU time 7.44 seconds
Started Jun 23 05:50:45 PM PDT 24
Finished Jun 23 05:50:54 PM PDT 24
Peak memory 239952 kb
Host smart-898d05bd-c9f7-4cfa-b6d5-f77c3006ec0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700261351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2700261351
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2060321814
Short name T523
Test name
Test status
Simulation time 52065355 ps
CPU time 0.7 seconds
Started Jun 23 05:50:59 PM PDT 24
Finished Jun 23 05:51:01 PM PDT 24
Peak memory 205540 kb
Host smart-dbaea9b9-9967-4515-abe3-f34a971cf702
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060321814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2060321814
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.626307951
Short name T428
Test name
Test status
Simulation time 116978251 ps
CPU time 2.72 seconds
Started Jun 23 05:50:49 PM PDT 24
Finished Jun 23 05:50:53 PM PDT 24
Peak memory 232832 kb
Host smart-c244fc78-6590-4243-9380-0668fae047dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626307951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.626307951
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.644799454
Short name T410
Test name
Test status
Simulation time 13406324 ps
CPU time 0.79 seconds
Started Jun 23 05:50:47 PM PDT 24
Finished Jun 23 05:50:49 PM PDT 24
Peak memory 206984 kb
Host smart-45f66caa-f8c6-4420-a890-3aee0f132826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644799454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.644799454
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3271825221
Short name T261
Test name
Test status
Simulation time 111603647011 ps
CPU time 149.42 seconds
Started Jun 23 05:50:51 PM PDT 24
Finished Jun 23 05:53:21 PM PDT 24
Peak memory 249388 kb
Host smart-87c41c80-cebf-4dfa-b819-2a0c4dd758c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271825221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3271825221
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1374110017
Short name T774
Test name
Test status
Simulation time 133722796426 ps
CPU time 81.37 seconds
Started Jun 23 05:50:59 PM PDT 24
Finished Jun 23 05:52:20 PM PDT 24
Peak memory 239108 kb
Host smart-7de4ce78-475c-485c-9c93-2b8f4ccabac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374110017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1374110017
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3049496125
Short name T202
Test name
Test status
Simulation time 11137571043 ps
CPU time 164.78 seconds
Started Jun 23 05:50:49 PM PDT 24
Finished Jun 23 05:53:35 PM PDT 24
Peak memory 265500 kb
Host smart-a23e9d6e-f1ab-404a-add6-011a875740ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049496125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3049496125
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2004207799
Short name T11
Test name
Test status
Simulation time 20863847174 ps
CPU time 28.1 seconds
Started Jun 23 05:50:49 PM PDT 24
Finished Jun 23 05:51:18 PM PDT 24
Peak memory 233012 kb
Host smart-0fe14ebf-ad77-435e-acba-a2ae31bc5dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004207799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2004207799
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2645220373
Short name T206
Test name
Test status
Simulation time 6278507329 ps
CPU time 11.3 seconds
Started Jun 23 05:50:50 PM PDT 24
Finished Jun 23 05:51:02 PM PDT 24
Peak memory 224844 kb
Host smart-0d3b36e4-d8c4-4adf-ba7e-66f7c84ae1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645220373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2645220373
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1995674470
Short name T794
Test name
Test status
Simulation time 1606272065 ps
CPU time 10.95 seconds
Started Jun 23 05:50:49 PM PDT 24
Finished Jun 23 05:51:01 PM PDT 24
Peak memory 224620 kb
Host smart-1dc06cd6-afef-4285-93ca-6da0e56c4c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995674470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1995674470
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.4655949
Short name T260
Test name
Test status
Simulation time 2808047019 ps
CPU time 9.3 seconds
Started Jun 23 05:50:50 PM PDT 24
Finished Jun 23 05:51:00 PM PDT 24
Peak memory 232940 kb
Host smart-f200078c-a304-47b5-bf88-c499a1c1eae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4655949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.4655949
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.466675496
Short name T804
Test name
Test status
Simulation time 1635627399 ps
CPU time 6.47 seconds
Started Jun 23 05:50:59 PM PDT 24
Finished Jun 23 05:51:06 PM PDT 24
Peak memory 240716 kb
Host smart-fd0518ff-b8e9-4116-b0d6-4e4c09441fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466675496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.466675496
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2088408656
Short name T825
Test name
Test status
Simulation time 169125433 ps
CPU time 4.5 seconds
Started Jun 23 05:50:51 PM PDT 24
Finished Jun 23 05:50:56 PM PDT 24
Peak memory 223300 kb
Host smart-279a6130-7a24-4eb0-b233-404219d902c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2088408656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2088408656
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.784073425
Short name T521
Test name
Test status
Simulation time 4975318344 ps
CPU time 56.51 seconds
Started Jun 23 05:50:54 PM PDT 24
Finished Jun 23 05:51:51 PM PDT 24
Peak memory 255864 kb
Host smart-c6b986ba-bf43-4fb0-98ae-6efb4cfd689e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784073425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.784073425
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3545767421
Short name T315
Test name
Test status
Simulation time 7028879605 ps
CPU time 32.07 seconds
Started Jun 23 05:50:46 PM PDT 24
Finished Jun 23 05:51:20 PM PDT 24
Peak memory 216480 kb
Host smart-dc8f47b9-0061-41b7-82ce-3fd4204aebc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545767421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3545767421
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2386195321
Short name T790
Test name
Test status
Simulation time 6524425272 ps
CPU time 4.72 seconds
Started Jun 23 05:50:48 PM PDT 24
Finished Jun 23 05:50:54 PM PDT 24
Peak memory 216544 kb
Host smart-ee02d7e6-2e52-4129-bef3-b5d9c447956f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386195321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2386195321
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2069238169
Short name T329
Test name
Test status
Simulation time 126957319 ps
CPU time 0.89 seconds
Started Jun 23 05:50:59 PM PDT 24
Finished Jun 23 05:51:01 PM PDT 24
Peak memory 208100 kb
Host smart-ceb42459-ae9a-4485-bb16-6a750a02d746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069238169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2069238169
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3060006142
Short name T805
Test name
Test status
Simulation time 124944726 ps
CPU time 0.81 seconds
Started Jun 23 05:50:59 PM PDT 24
Finished Jun 23 05:51:01 PM PDT 24
Peak memory 206112 kb
Host smart-a3a5bb96-fd68-4c06-b8c0-30ccbb6ebe13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060006142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3060006142
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1923584601
Short name T829
Test name
Test status
Simulation time 3459099051 ps
CPU time 9.99 seconds
Started Jun 23 05:50:50 PM PDT 24
Finished Jun 23 05:51:01 PM PDT 24
Peak memory 241104 kb
Host smart-6b26637e-a25a-4f20-b6c3-3456adedadd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923584601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1923584601
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3264626843
Short name T436
Test name
Test status
Simulation time 16285181 ps
CPU time 0.74 seconds
Started Jun 23 05:50:56 PM PDT 24
Finished Jun 23 05:50:57 PM PDT 24
Peak memory 204948 kb
Host smart-665332be-3ac2-4ce3-8802-7d977d713210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264626843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3264626843
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1986328369
Short name T673
Test name
Test status
Simulation time 112086590 ps
CPU time 2.12 seconds
Started Jun 23 05:50:50 PM PDT 24
Finished Jun 23 05:50:53 PM PDT 24
Peak memory 232552 kb
Host smart-df8a970b-8bcf-4df3-a080-37fb60a721a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986328369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1986328369
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2095663114
Short name T739
Test name
Test status
Simulation time 19468127 ps
CPU time 0.76 seconds
Started Jun 23 05:50:48 PM PDT 24
Finished Jun 23 05:50:50 PM PDT 24
Peak memory 205696 kb
Host smart-aa6ad630-3d3f-4346-869f-4b2a19a11e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095663114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2095663114
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3317078780
Short name T841
Test name
Test status
Simulation time 76058549 ps
CPU time 0.74 seconds
Started Jun 23 05:50:51 PM PDT 24
Finished Jun 23 05:50:52 PM PDT 24
Peak memory 215968 kb
Host smart-efd51f52-610f-4f9f-a20c-b1ab3bf16b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317078780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3317078780
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.465085046
Short name T207
Test name
Test status
Simulation time 4485660369 ps
CPU time 32.81 seconds
Started Jun 23 05:50:59 PM PDT 24
Finished Jun 23 05:51:32 PM PDT 24
Peak memory 236656 kb
Host smart-7bfd624f-1dda-44a8-9dfa-af326c2ebf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465085046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.465085046
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3047623600
Short name T210
Test name
Test status
Simulation time 12550563758 ps
CPU time 67.56 seconds
Started Jun 23 05:50:57 PM PDT 24
Finished Jun 23 05:52:05 PM PDT 24
Peak memory 252388 kb
Host smart-9054fcf2-4166-4ec8-9745-3c09dd07623e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047623600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3047623600
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3523398491
Short name T768
Test name
Test status
Simulation time 2428619014 ps
CPU time 11.36 seconds
Started Jun 23 05:50:49 PM PDT 24
Finished Jun 23 05:51:01 PM PDT 24
Peak memory 234708 kb
Host smart-5c4dec51-f0c4-44f3-ae32-663b041f2d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523398491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3523398491
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1217921815
Short name T224
Test name
Test status
Simulation time 1806577403 ps
CPU time 8.72 seconds
Started Jun 23 05:50:48 PM PDT 24
Finished Jun 23 05:50:58 PM PDT 24
Peak memory 232880 kb
Host smart-3cfe1bd6-7335-40b4-a889-0b60894b3e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217921815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1217921815
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.449015281
Short name T718
Test name
Test status
Simulation time 1788086832 ps
CPU time 15.58 seconds
Started Jun 23 05:50:50 PM PDT 24
Finished Jun 23 05:51:07 PM PDT 24
Peak memory 232856 kb
Host smart-d1678f8b-2f97-4762-81fb-c0f3e08fe359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449015281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.449015281
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.130458117
Short name T229
Test name
Test status
Simulation time 4665616120 ps
CPU time 14.73 seconds
Started Jun 23 05:50:52 PM PDT 24
Finished Jun 23 05:51:07 PM PDT 24
Peak memory 232932 kb
Host smart-ef8b0324-d450-4f15-9f23-b0b4892923c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130458117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.130458117
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2824479327
Short name T381
Test name
Test status
Simulation time 30481709 ps
CPU time 1.97 seconds
Started Jun 23 05:50:51 PM PDT 24
Finished Jun 23 05:50:53 PM PDT 24
Peak memory 223004 kb
Host smart-4b1d61b5-0403-4fe4-aaaf-0ce0f1b778e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824479327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2824479327
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2914595376
Short name T361
Test name
Test status
Simulation time 1643031769 ps
CPU time 15.9 seconds
Started Jun 23 05:50:50 PM PDT 24
Finished Jun 23 05:51:07 PM PDT 24
Peak memory 222832 kb
Host smart-1513d59e-b56f-4425-8f7f-6d7da2a14a57
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2914595376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2914595376
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.893095921
Short name T839
Test name
Test status
Simulation time 9537248664 ps
CPU time 49.54 seconds
Started Jun 23 05:50:52 PM PDT 24
Finished Jun 23 05:51:42 PM PDT 24
Peak memory 216552 kb
Host smart-5de4c867-8dd7-46e5-9111-271ea6f1f746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893095921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.893095921
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3233944032
Short name T932
Test name
Test status
Simulation time 2308299214 ps
CPU time 5.38 seconds
Started Jun 23 05:50:51 PM PDT 24
Finished Jun 23 05:50:57 PM PDT 24
Peak memory 216480 kb
Host smart-790a2e4f-0f8a-4ec2-bc23-d6cefdc8de2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233944032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3233944032
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3252000516
Short name T955
Test name
Test status
Simulation time 64637174 ps
CPU time 0.99 seconds
Started Jun 23 05:50:49 PM PDT 24
Finished Jun 23 05:50:51 PM PDT 24
Peak memory 207776 kb
Host smart-a652df81-9830-4ace-b9c5-58552a4d5c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252000516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3252000516
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2329932683
Short name T332
Test name
Test status
Simulation time 61904046 ps
CPU time 0.84 seconds
Started Jun 23 05:50:49 PM PDT 24
Finished Jun 23 05:50:50 PM PDT 24
Peak memory 206096 kb
Host smart-75c647de-a558-4ed3-91f8-a2b12651e60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329932683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2329932683
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2604649975
Short name T895
Test name
Test status
Simulation time 14492970964 ps
CPU time 10.14 seconds
Started Jun 23 05:50:51 PM PDT 24
Finished Jun 23 05:51:02 PM PDT 24
Peak memory 232980 kb
Host smart-bf4979bf-2fcc-4c85-89f3-5b40d3494828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604649975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2604649975
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3568806966
Short name T934
Test name
Test status
Simulation time 17264620 ps
CPU time 0.75 seconds
Started Jun 23 05:50:56 PM PDT 24
Finished Jun 23 05:50:57 PM PDT 24
Peak memory 205484 kb
Host smart-45c51800-1c61-4896-b08c-49692d5b7062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568806966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3568806966
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.676204139
Short name T717
Test name
Test status
Simulation time 362135997 ps
CPU time 2.74 seconds
Started Jun 23 05:50:54 PM PDT 24
Finished Jun 23 05:50:57 PM PDT 24
Peak memory 224644 kb
Host smart-3f8d24ce-91ef-42b1-8ade-6665b9ceba86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676204139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.676204139
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1064632501
Short name T663
Test name
Test status
Simulation time 23302139 ps
CPU time 0.77 seconds
Started Jun 23 05:50:56 PM PDT 24
Finished Jun 23 05:50:57 PM PDT 24
Peak memory 207068 kb
Host smart-411e740e-2bd9-41f0-9d85-c860ba999c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064632501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1064632501
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2503765434
Short name T831
Test name
Test status
Simulation time 63197031437 ps
CPU time 250.88 seconds
Started Jun 23 05:50:52 PM PDT 24
Finished Jun 23 05:55:03 PM PDT 24
Peak memory 251968 kb
Host smart-e0b12817-c3fb-4495-b181-b0ac8214ca9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503765434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2503765434
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1873770430
Short name T34
Test name
Test status
Simulation time 95465262 ps
CPU time 3.11 seconds
Started Jun 23 05:50:55 PM PDT 24
Finished Jun 23 05:50:58 PM PDT 24
Peak memory 224684 kb
Host smart-900e69d0-c790-40c9-ab19-486726066bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873770430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1873770430
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1473689555
Short name T378
Test name
Test status
Simulation time 107681108 ps
CPU time 2.14 seconds
Started Jun 23 05:50:55 PM PDT 24
Finished Jun 23 05:50:58 PM PDT 24
Peak memory 223196 kb
Host smart-13b9f57b-de92-4de2-b2f7-04aad16baf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473689555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1473689555
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2766163606
Short name T514
Test name
Test status
Simulation time 436449461 ps
CPU time 4.16 seconds
Started Jun 23 05:50:59 PM PDT 24
Finished Jun 23 05:51:03 PM PDT 24
Peak memory 224588 kb
Host smart-ff06e55c-293f-4da6-b062-18e9f06d6a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766163606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2766163606
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.598004178
Short name T42
Test name
Test status
Simulation time 1692255209 ps
CPU time 6.82 seconds
Started Jun 23 05:50:56 PM PDT 24
Finished Jun 23 05:51:03 PM PDT 24
Peak memory 224628 kb
Host smart-02332a82-bfad-448e-a73c-dbe969113db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598004178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.598004178
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1133078098
Short name T6
Test name
Test status
Simulation time 2758833827 ps
CPU time 12.99 seconds
Started Jun 23 05:50:56 PM PDT 24
Finished Jun 23 05:51:09 PM PDT 24
Peak memory 240876 kb
Host smart-6acf4bbd-3394-47fc-8f7c-3b4eb628f2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133078098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1133078098
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1943115527
Short name T427
Test name
Test status
Simulation time 6310405135 ps
CPU time 13.7 seconds
Started Jun 23 05:50:54 PM PDT 24
Finished Jun 23 05:51:08 PM PDT 24
Peak memory 223356 kb
Host smart-99fa813c-554e-498b-8d3a-2369d81aef68
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1943115527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1943115527
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.470438491
Short name T787
Test name
Test status
Simulation time 129938881368 ps
CPU time 244.21 seconds
Started Jun 23 05:50:57 PM PDT 24
Finished Jun 23 05:55:01 PM PDT 24
Peak memory 254824 kb
Host smart-33197ee6-a36b-4ea8-a169-2facc3f43bec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470438491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.470438491
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3816203427
Short name T597
Test name
Test status
Simulation time 561304406 ps
CPU time 6.39 seconds
Started Jun 23 05:50:57 PM PDT 24
Finished Jun 23 05:51:03 PM PDT 24
Peak memory 216652 kb
Host smart-d91b04e0-4bc1-49a1-8b54-2c4f8d7cb547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816203427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3816203427
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1039152759
Short name T338
Test name
Test status
Simulation time 14675393658 ps
CPU time 9.47 seconds
Started Jun 23 05:51:00 PM PDT 24
Finished Jun 23 05:51:10 PM PDT 24
Peak memory 216552 kb
Host smart-25b82273-1efc-4b02-982c-6ea009b57fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039152759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1039152759
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.4264115379
Short name T26
Test name
Test status
Simulation time 43064554 ps
CPU time 0.9 seconds
Started Jun 23 05:50:56 PM PDT 24
Finished Jun 23 05:50:57 PM PDT 24
Peak memory 206756 kb
Host smart-7a64c02e-c178-47ec-9e05-58271bd28b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264115379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.4264115379
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.869987547
Short name T362
Test name
Test status
Simulation time 48355448 ps
CPU time 0.81 seconds
Started Jun 23 05:50:57 PM PDT 24
Finished Jun 23 05:50:58 PM PDT 24
Peak memory 206024 kb
Host smart-60cf7786-9471-4ef7-a253-4389c7fdf716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869987547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.869987547
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.4158287356
Short name T802
Test name
Test status
Simulation time 2172525018 ps
CPU time 4.57 seconds
Started Jun 23 05:50:58 PM PDT 24
Finished Jun 23 05:51:03 PM PDT 24
Peak memory 224740 kb
Host smart-7ae2227d-84d9-48a3-b9ae-4574416078e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158287356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.4158287356
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.918081462
Short name T5
Test name
Test status
Simulation time 15076483 ps
CPU time 0.72 seconds
Started Jun 23 05:51:00 PM PDT 24
Finished Jun 23 05:51:02 PM PDT 24
Peak memory 205512 kb
Host smart-e2b956aa-6af7-4a14-ba10-0d52c2084142
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918081462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.918081462
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3465795433
Short name T345
Test name
Test status
Simulation time 517141350 ps
CPU time 3.77 seconds
Started Jun 23 05:51:02 PM PDT 24
Finished Jun 23 05:51:07 PM PDT 24
Peak memory 232864 kb
Host smart-d4ace48a-4816-4783-b7a1-2a93e08d9deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465795433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3465795433
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3270254918
Short name T573
Test name
Test status
Simulation time 58326243 ps
CPU time 0.81 seconds
Started Jun 23 05:50:57 PM PDT 24
Finished Jun 23 05:50:58 PM PDT 24
Peak memory 206752 kb
Host smart-4c4cce13-c348-4623-8df0-9cac5324668b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270254918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3270254918
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2961162162
Short name T452
Test name
Test status
Simulation time 1589283441 ps
CPU time 12.32 seconds
Started Jun 23 05:51:01 PM PDT 24
Finished Jun 23 05:51:14 PM PDT 24
Peak memory 232920 kb
Host smart-1b5df027-0450-4de9-8202-6191d284abec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961162162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2961162162
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3613212617
Short name T711
Test name
Test status
Simulation time 25088715701 ps
CPU time 46.07 seconds
Started Jun 23 05:50:58 PM PDT 24
Finished Jun 23 05:51:45 PM PDT 24
Peak memory 223728 kb
Host smart-2d469c4d-9f97-4435-a886-2dcd5b47e78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613212617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3613212617
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.4178131411
Short name T598
Test name
Test status
Simulation time 733228286 ps
CPU time 9.17 seconds
Started Jun 23 05:51:00 PM PDT 24
Finished Jun 23 05:51:09 PM PDT 24
Peak memory 239800 kb
Host smart-11927b17-0cb4-4978-9432-3778c6ebfad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178131411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4178131411
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.378702212
Short name T195
Test name
Test status
Simulation time 1545573668 ps
CPU time 19.18 seconds
Started Jun 23 05:50:58 PM PDT 24
Finished Jun 23 05:51:18 PM PDT 24
Peak memory 232880 kb
Host smart-63525352-7aba-4fcf-be3d-7631ef409077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378702212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.378702212
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3199142952
Short name T255
Test name
Test status
Simulation time 13736120641 ps
CPU time 52.86 seconds
Started Jun 23 05:50:58 PM PDT 24
Finished Jun 23 05:51:51 PM PDT 24
Peak memory 232936 kb
Host smart-3c2801e2-79c1-4562-a4d2-e7589d6b1c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199142952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3199142952
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2322546785
Short name T259
Test name
Test status
Simulation time 172213001 ps
CPU time 3.14 seconds
Started Jun 23 05:51:00 PM PDT 24
Finished Jun 23 05:51:03 PM PDT 24
Peak memory 232880 kb
Host smart-82c3c6c2-c682-4186-bc28-4209a92d98cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322546785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2322546785
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1364035100
Short name T907
Test name
Test status
Simulation time 3576565691 ps
CPU time 9.92 seconds
Started Jun 23 05:51:05 PM PDT 24
Finished Jun 23 05:51:15 PM PDT 24
Peak memory 241004 kb
Host smart-2072946f-999e-4ae6-87a2-8a7893543a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364035100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1364035100
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2019893940
Short name T719
Test name
Test status
Simulation time 1207647520 ps
CPU time 6.63 seconds
Started Jun 23 05:51:01 PM PDT 24
Finished Jun 23 05:51:08 PM PDT 24
Peak memory 220592 kb
Host smart-97ad82ca-00f6-4ae9-ae87-b2d62eb9638e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2019893940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2019893940
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1363067878
Short name T155
Test name
Test status
Simulation time 19359078690 ps
CPU time 67.42 seconds
Started Jun 23 05:51:01 PM PDT 24
Finished Jun 23 05:52:09 PM PDT 24
Peak memory 251276 kb
Host smart-c0c1cc6e-83f9-4f39-93a8-ab913c0353e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363067878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1363067878
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3681999331
Short name T357
Test name
Test status
Simulation time 2043759648 ps
CPU time 15.06 seconds
Started Jun 23 05:50:57 PM PDT 24
Finished Jun 23 05:51:12 PM PDT 24
Peak memory 216408 kb
Host smart-b2ce1501-6de2-41f0-b311-e7dbbc7d90be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681999331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3681999331
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3828000151
Short name T676
Test name
Test status
Simulation time 5901345685 ps
CPU time 4.73 seconds
Started Jun 23 05:51:00 PM PDT 24
Finished Jun 23 05:51:05 PM PDT 24
Peak memory 216580 kb
Host smart-17860809-40f9-4713-a5d6-6be0f9ebc4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828000151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3828000151
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.764173585
Short name T926
Test name
Test status
Simulation time 83579232 ps
CPU time 2.62 seconds
Started Jun 23 05:51:00 PM PDT 24
Finished Jun 23 05:51:03 PM PDT 24
Peak memory 216424 kb
Host smart-6cf8c87f-4985-4e97-a8f0-7a821726ebda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764173585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.764173585
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2703671919
Short name T875
Test name
Test status
Simulation time 46318704 ps
CPU time 0.9 seconds
Started Jun 23 05:50:59 PM PDT 24
Finished Jun 23 05:51:01 PM PDT 24
Peak memory 206056 kb
Host smart-ea0a1f8d-f185-4a54-92ee-5a627881b169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703671919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2703671919
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.4096995168
Short name T806
Test name
Test status
Simulation time 55468596 ps
CPU time 2.26 seconds
Started Jun 23 05:51:01 PM PDT 24
Finished Jun 23 05:51:04 PM PDT 24
Peak memory 232872 kb
Host smart-6cc264a0-e43a-4f83-899b-83ee4c1dae02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096995168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.4096995168
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1421743944
Short name T857
Test name
Test status
Simulation time 188486682 ps
CPU time 0.72 seconds
Started Jun 23 05:51:04 PM PDT 24
Finished Jun 23 05:51:05 PM PDT 24
Peak memory 205524 kb
Host smart-4f6ae417-f888-477b-adf2-0ce6333bdeb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421743944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1421743944
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1655258397
Short name T671
Test name
Test status
Simulation time 152362143 ps
CPU time 4.78 seconds
Started Jun 23 05:51:08 PM PDT 24
Finished Jun 23 05:51:13 PM PDT 24
Peak memory 232812 kb
Host smart-956a13d9-e979-499b-b503-43ba977ee7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655258397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1655258397
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3835229760
Short name T915
Test name
Test status
Simulation time 40521208 ps
CPU time 0.83 seconds
Started Jun 23 05:51:01 PM PDT 24
Finished Jun 23 05:51:03 PM PDT 24
Peak memory 206752 kb
Host smart-3650c5c3-a872-4dc6-a564-5fa6e8d4f81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835229760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3835229760
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2411601047
Short name T270
Test name
Test status
Simulation time 73703291869 ps
CPU time 507.21 seconds
Started Jun 23 05:51:08 PM PDT 24
Finished Jun 23 05:59:35 PM PDT 24
Peak memory 257596 kb
Host smart-49008a55-c2d0-4f74-9e7a-36ebcace80f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411601047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2411601047
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.733353826
Short name T908
Test name
Test status
Simulation time 42753839747 ps
CPU time 335.12 seconds
Started Jun 23 05:51:05 PM PDT 24
Finished Jun 23 05:56:40 PM PDT 24
Peak memory 268868 kb
Host smart-7a3bcad5-f468-4bf4-9c71-b2adbd33a88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733353826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.733353826
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.411773838
Short name T397
Test name
Test status
Simulation time 465704510 ps
CPU time 2.03 seconds
Started Jun 23 05:51:06 PM PDT 24
Finished Jun 23 05:51:08 PM PDT 24
Peak memory 217676 kb
Host smart-45954a59-4e5c-4d92-9201-83aa06504a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411773838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.411773838
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3550665690
Short name T309
Test name
Test status
Simulation time 3273029439 ps
CPU time 14.75 seconds
Started Jun 23 05:51:07 PM PDT 24
Finished Jun 23 05:51:22 PM PDT 24
Peak memory 249388 kb
Host smart-4fe89044-adc3-44d5-8edc-d12e061addbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550665690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3550665690
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2652302189
Short name T264
Test name
Test status
Simulation time 191690891 ps
CPU time 3.26 seconds
Started Jun 23 05:51:06 PM PDT 24
Finished Jun 23 05:51:09 PM PDT 24
Peak memory 224676 kb
Host smart-88bc7f1d-a93f-47fc-a28d-b3917dba8c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652302189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2652302189
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3411070625
Short name T197
Test name
Test status
Simulation time 6434498151 ps
CPU time 34.2 seconds
Started Jun 23 05:51:03 PM PDT 24
Finished Jun 23 05:51:37 PM PDT 24
Peak memory 249576 kb
Host smart-71fdfaaa-710c-4bf0-b4ca-c1fd0bb4940c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411070625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3411070625
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.238028438
Short name T740
Test name
Test status
Simulation time 1002926518 ps
CPU time 3.28 seconds
Started Jun 23 05:51:01 PM PDT 24
Finished Jun 23 05:51:04 PM PDT 24
Peak memory 232884 kb
Host smart-97670536-5a66-4bb3-bb74-6505968cdab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238028438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.238028438
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1032737258
Short name T247
Test name
Test status
Simulation time 1232803201 ps
CPU time 2.9 seconds
Started Jun 23 05:51:00 PM PDT 24
Finished Jun 23 05:51:03 PM PDT 24
Peak memory 224608 kb
Host smart-8d8d21d8-98dd-42e1-8d8c-f5ad2414fc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032737258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1032737258
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1855080853
Short name T746
Test name
Test status
Simulation time 2264266522 ps
CPU time 4.76 seconds
Started Jun 23 05:51:07 PM PDT 24
Finished Jun 23 05:51:12 PM PDT 24
Peak memory 220632 kb
Host smart-bbe22ede-ea02-4f05-9a41-38705a4cbf22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1855080853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1855080853
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1975773525
Short name T153
Test name
Test status
Simulation time 5769868867 ps
CPU time 86.27 seconds
Started Jun 23 05:51:07 PM PDT 24
Finished Jun 23 05:52:33 PM PDT 24
Peak memory 251672 kb
Host smart-578e04d8-1005-40ee-a2d5-2b39d222e92d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975773525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1975773525
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3458220909
Short name T674
Test name
Test status
Simulation time 1321626312 ps
CPU time 15.13 seconds
Started Jun 23 05:51:05 PM PDT 24
Finished Jun 23 05:51:20 PM PDT 24
Peak memory 216460 kb
Host smart-8ed76629-46ed-4381-a380-45c367257261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458220909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3458220909
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2487485355
Short name T574
Test name
Test status
Simulation time 1307654848 ps
CPU time 2.91 seconds
Started Jun 23 05:51:00 PM PDT 24
Finished Jun 23 05:51:03 PM PDT 24
Peak memory 216452 kb
Host smart-ab853f9b-27d8-427b-8c64-9e370d2b618d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487485355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2487485355
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.4097308025
Short name T360
Test name
Test status
Simulation time 63423354 ps
CPU time 1.22 seconds
Started Jun 23 05:50:59 PM PDT 24
Finished Jun 23 05:51:01 PM PDT 24
Peak memory 216300 kb
Host smart-1ffc2506-a1c2-4840-a015-21b76eb6d410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097308025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.4097308025
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2018144497
Short name T528
Test name
Test status
Simulation time 48326192 ps
CPU time 0.81 seconds
Started Jun 23 05:51:05 PM PDT 24
Finished Jun 23 05:51:06 PM PDT 24
Peak memory 206116 kb
Host smart-d6176556-420f-4d50-bbeb-54004cfc72ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018144497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2018144497
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3541431025
Short name T444
Test name
Test status
Simulation time 564334925 ps
CPU time 4.42 seconds
Started Jun 23 05:51:06 PM PDT 24
Finished Jun 23 05:51:11 PM PDT 24
Peak memory 232860 kb
Host smart-f9161d88-1930-423f-9a17-7a1052c874ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541431025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3541431025
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2368118201
Short name T433
Test name
Test status
Simulation time 18201594 ps
CPU time 0.69 seconds
Started Jun 23 05:49:48 PM PDT 24
Finished Jun 23 05:49:49 PM PDT 24
Peak memory 204952 kb
Host smart-dee79c42-88ea-4188-b872-8a72c4eb11d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368118201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
368118201
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1772513519
Short name T913
Test name
Test status
Simulation time 2609779153 ps
CPU time 13.06 seconds
Started Jun 23 05:49:50 PM PDT 24
Finished Jun 23 05:50:05 PM PDT 24
Peak memory 224824 kb
Host smart-8139ede3-93ee-45b4-b5f3-4772589c94c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772513519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1772513519
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3895359091
Short name T57
Test name
Test status
Simulation time 19098311 ps
CPU time 0.78 seconds
Started Jun 23 05:49:46 PM PDT 24
Finished Jun 23 05:49:48 PM PDT 24
Peak memory 205728 kb
Host smart-afce0cc9-3e7b-4711-9045-4ed0dadcb5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895359091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3895359091
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3274725348
Short name T232
Test name
Test status
Simulation time 4119717341 ps
CPU time 37.4 seconds
Started Jun 23 05:49:48 PM PDT 24
Finished Jun 23 05:50:27 PM PDT 24
Peak memory 249376 kb
Host smart-7ab8d844-c83f-4ca7-af8e-88d0c2442c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274725348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3274725348
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2168792283
Short name T356
Test name
Test status
Simulation time 129208057711 ps
CPU time 295.02 seconds
Started Jun 23 05:49:50 PM PDT 24
Finished Jun 23 05:54:47 PM PDT 24
Peak memory 256136 kb
Host smart-fba86619-bbd9-4262-9f83-20d2e8db1af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168792283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2168792283
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3014776565
Short name T159
Test name
Test status
Simulation time 20153794707 ps
CPU time 206.38 seconds
Started Jun 23 05:49:47 PM PDT 24
Finished Jun 23 05:53:14 PM PDT 24
Peak memory 260940 kb
Host smart-681485f0-3cc5-4130-9160-677d577abb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014776565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3014776565
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3674114634
Short name T579
Test name
Test status
Simulation time 200338203 ps
CPU time 4.48 seconds
Started Jun 23 05:49:48 PM PDT 24
Finished Jun 23 05:49:54 PM PDT 24
Peak memory 233000 kb
Host smart-ab2aabea-4bdc-4b35-bb28-7a076ee523d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674114634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3674114634
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2872701062
Short name T909
Test name
Test status
Simulation time 1033249229 ps
CPU time 11.59 seconds
Started Jun 23 05:49:45 PM PDT 24
Finished Jun 23 05:49:57 PM PDT 24
Peak memory 232868 kb
Host smart-58eb4030-a1c8-4a2c-a36e-c8d3c863396a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872701062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2872701062
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2045946542
Short name T910
Test name
Test status
Simulation time 392413202 ps
CPU time 2.35 seconds
Started Jun 23 05:49:50 PM PDT 24
Finished Jun 23 05:49:53 PM PDT 24
Peak memory 223112 kb
Host smart-a72b1947-b39c-420c-b0ae-bf606b3ba466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045946542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2045946542
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3847982160
Short name T275
Test name
Test status
Simulation time 1551707005 ps
CPU time 3.14 seconds
Started Jun 23 05:49:47 PM PDT 24
Finished Jun 23 05:49:51 PM PDT 24
Peak memory 232848 kb
Host smart-32a5893c-f48c-4be5-8f6a-83f9916b499b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847982160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3847982160
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.4294577785
Short name T625
Test name
Test status
Simulation time 29002960 ps
CPU time 2.05 seconds
Started Jun 23 05:49:47 PM PDT 24
Finished Jun 23 05:49:50 PM PDT 24
Peak memory 223092 kb
Host smart-bdb8d66b-d6f9-48e7-8b72-41de6702c49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294577785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.4294577785
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2120922531
Short name T616
Test name
Test status
Simulation time 365869538 ps
CPU time 4 seconds
Started Jun 23 05:49:51 PM PDT 24
Finished Jun 23 05:49:56 PM PDT 24
Peak memory 222516 kb
Host smart-958708ea-340b-43bf-a7f4-c38f42a35b0b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2120922531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2120922531
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.58675852
Short name T70
Test name
Test status
Simulation time 106186711 ps
CPU time 1.19 seconds
Started Jun 23 05:49:53 PM PDT 24
Finished Jun 23 05:49:55 PM PDT 24
Peak memory 236568 kb
Host smart-a9f9c213-b62f-4f43-abc9-cc047f1d7ca5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58675852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.58675852
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1792471397
Short name T258
Test name
Test status
Simulation time 17426447260 ps
CPU time 125.61 seconds
Started Jun 23 05:49:49 PM PDT 24
Finished Jun 23 05:51:57 PM PDT 24
Peak memory 224888 kb
Host smart-49586558-f1b5-4522-ab46-fd5fafd953e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792471397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1792471397
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.269647966
Short name T773
Test name
Test status
Simulation time 6605400295 ps
CPU time 11.82 seconds
Started Jun 23 05:49:54 PM PDT 24
Finished Jun 23 05:50:07 PM PDT 24
Peak memory 216564 kb
Host smart-a5ea0e01-1322-4b51-ab67-8289dbb224bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269647966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.269647966
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.4110016951
Short name T797
Test name
Test status
Simulation time 911157514 ps
CPU time 6.38 seconds
Started Jun 23 05:49:55 PM PDT 24
Finished Jun 23 05:50:02 PM PDT 24
Peak memory 216448 kb
Host smart-155139d5-e063-4331-ae0b-b0d1be596695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110016951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.4110016951
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3033125175
Short name T682
Test name
Test status
Simulation time 54606586 ps
CPU time 0.81 seconds
Started Jun 23 05:49:46 PM PDT 24
Finished Jun 23 05:49:48 PM PDT 24
Peak memory 206124 kb
Host smart-d7fef148-aaa1-467d-9fcc-c15da9e405d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033125175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3033125175
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.436070598
Short name T691
Test name
Test status
Simulation time 23061215 ps
CPU time 0.7 seconds
Started Jun 23 05:49:54 PM PDT 24
Finished Jun 23 05:49:57 PM PDT 24
Peak memory 206116 kb
Host smart-6a38540e-89ca-4847-aa1c-35cc46118079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436070598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.436070598
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1387437020
Short name T744
Test name
Test status
Simulation time 2747402530 ps
CPU time 13.73 seconds
Started Jun 23 05:49:49 PM PDT 24
Finished Jun 23 05:50:05 PM PDT 24
Peak memory 240964 kb
Host smart-7633164f-5d3c-41cd-bde1-5fb6693199f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387437020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1387437020
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.895297048
Short name T843
Test name
Test status
Simulation time 42410110 ps
CPU time 0.7 seconds
Started Jun 23 05:51:08 PM PDT 24
Finished Jun 23 05:51:09 PM PDT 24
Peak memory 204896 kb
Host smart-7bed043d-d762-4200-abbd-c82e78a94868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895297048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.895297048
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2611744750
Short name T91
Test name
Test status
Simulation time 582998303 ps
CPU time 3.48 seconds
Started Jun 23 05:51:05 PM PDT 24
Finished Jun 23 05:51:09 PM PDT 24
Peak memory 224632 kb
Host smart-5863aa87-fc5c-42a0-8a75-b078feb84409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611744750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2611744750
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.687337810
Short name T409
Test name
Test status
Simulation time 36899509 ps
CPU time 0.86 seconds
Started Jun 23 05:51:06 PM PDT 24
Finished Jun 23 05:51:07 PM PDT 24
Peak memory 206240 kb
Host smart-13ee3faf-c3a1-4bd8-97e0-cc18f870501c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687337810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.687337810
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3878380787
Short name T666
Test name
Test status
Simulation time 22399541682 ps
CPU time 47.59 seconds
Started Jun 23 05:51:07 PM PDT 24
Finished Jun 23 05:51:55 PM PDT 24
Peak memory 224820 kb
Host smart-56cfa600-c41a-4aa2-ac59-f6258a91f900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878380787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3878380787
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3923823253
Short name T276
Test name
Test status
Simulation time 15162457873 ps
CPU time 65.29 seconds
Started Jun 23 05:51:04 PM PDT 24
Finished Jun 23 05:52:09 PM PDT 24
Peak memory 251992 kb
Host smart-b3541994-9cc7-4ff7-a229-602da9c7ae4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923823253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3923823253
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1485865402
Short name T288
Test name
Test status
Simulation time 105710326122 ps
CPU time 436.08 seconds
Started Jun 23 05:51:07 PM PDT 24
Finished Jun 23 05:58:24 PM PDT 24
Peak memory 253964 kb
Host smart-f3e06fb2-c106-4d76-b9d2-463bc0d451ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485865402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1485865402
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3759636611
Short name T713
Test name
Test status
Simulation time 148715976 ps
CPU time 2.9 seconds
Started Jun 23 05:51:06 PM PDT 24
Finished Jun 23 05:51:10 PM PDT 24
Peak memory 232860 kb
Host smart-668a6a8d-2dbe-4f3e-964b-79d4ae61ef30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759636611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3759636611
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1613667079
Short name T639
Test name
Test status
Simulation time 9054847873 ps
CPU time 43.87 seconds
Started Jun 23 05:51:12 PM PDT 24
Finished Jun 23 05:51:57 PM PDT 24
Peak memory 224676 kb
Host smart-be6a2851-c472-49cb-a5a0-09fcbc53b262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613667079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1613667079
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1176835159
Short name T734
Test name
Test status
Simulation time 722720289 ps
CPU time 11.39 seconds
Started Jun 23 05:51:08 PM PDT 24
Finished Jun 23 05:51:19 PM PDT 24
Peak memory 232812 kb
Host smart-776fc0b8-bd70-46e9-86d5-556f806364e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176835159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1176835159
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.475012841
Short name T640
Test name
Test status
Simulation time 3547136534 ps
CPU time 6.76 seconds
Started Jun 23 05:51:06 PM PDT 24
Finished Jun 23 05:51:13 PM PDT 24
Peak memory 224172 kb
Host smart-ac02ac76-807d-4ed1-98a3-275ed91cfe3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475012841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.475012841
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1597970699
Short name T764
Test name
Test status
Simulation time 32328257 ps
CPU time 2.46 seconds
Started Jun 23 05:51:12 PM PDT 24
Finished Jun 23 05:51:15 PM PDT 24
Peak memory 232452 kb
Host smart-2a4b332e-9bdf-43d8-9584-8738f169d610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597970699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1597970699
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2468861617
Short name T801
Test name
Test status
Simulation time 85932612 ps
CPU time 3.84 seconds
Started Jun 23 05:51:05 PM PDT 24
Finished Jun 23 05:51:09 PM PDT 24
Peak memory 223272 kb
Host smart-136cdf56-1e9c-4c51-8d72-538b447057ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2468861617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2468861617
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3222009386
Short name T395
Test name
Test status
Simulation time 40723608 ps
CPU time 0.98 seconds
Started Jun 23 05:51:02 PM PDT 24
Finished Jun 23 05:51:03 PM PDT 24
Peak memory 207084 kb
Host smart-67580e94-bfbf-40bc-9362-70ed979a5012
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222009386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3222009386
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2559492890
Short name T816
Test name
Test status
Simulation time 16754232657 ps
CPU time 19.56 seconds
Started Jun 23 05:51:02 PM PDT 24
Finished Jun 23 05:51:22 PM PDT 24
Peak memory 216516 kb
Host smart-ac5c7120-c7ca-479c-89ac-3722d743b898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559492890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2559492890
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1724921752
Short name T728
Test name
Test status
Simulation time 40623069675 ps
CPU time 16.19 seconds
Started Jun 23 05:51:07 PM PDT 24
Finished Jun 23 05:51:23 PM PDT 24
Peak memory 216560 kb
Host smart-7b2d25f1-f4cd-4896-b884-ece2d565f8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724921752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1724921752
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2959335685
Short name T808
Test name
Test status
Simulation time 13191202 ps
CPU time 0.78 seconds
Started Jun 23 05:51:10 PM PDT 24
Finished Jun 23 05:51:11 PM PDT 24
Peak memory 206132 kb
Host smart-f81a2b32-a5b7-45d7-b99c-594ea3e7cd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959335685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2959335685
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.4273881831
Short name T738
Test name
Test status
Simulation time 77640616 ps
CPU time 0.93 seconds
Started Jun 23 05:51:08 PM PDT 24
Finished Jun 23 05:51:09 PM PDT 24
Peak memory 206124 kb
Host smart-55b350b2-ec85-43df-b041-d3d7bb697a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273881831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.4273881831
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.931612657
Short name T566
Test name
Test status
Simulation time 11495989742 ps
CPU time 14.55 seconds
Started Jun 23 05:51:07 PM PDT 24
Finished Jun 23 05:51:22 PM PDT 24
Peak memory 232992 kb
Host smart-574999e9-20d6-480e-9c1e-d952037b7b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931612657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.931612657
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.208840652
Short name T462
Test name
Test status
Simulation time 59852609 ps
CPU time 0.7 seconds
Started Jun 23 05:51:12 PM PDT 24
Finished Jun 23 05:51:13 PM PDT 24
Peak memory 205428 kb
Host smart-aec64272-c542-48fd-9b1c-71e1a786e776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208840652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.208840652
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2711451879
Short name T722
Test name
Test status
Simulation time 7803329971 ps
CPU time 17.01 seconds
Started Jun 23 05:51:12 PM PDT 24
Finished Jun 23 05:51:30 PM PDT 24
Peak memory 232960 kb
Host smart-586ee250-d0da-4ef7-ba1c-0e9d8fd9349d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711451879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2711451879
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3012734501
Short name T815
Test name
Test status
Simulation time 18995824 ps
CPU time 0.8 seconds
Started Jun 23 05:51:05 PM PDT 24
Finished Jun 23 05:51:06 PM PDT 24
Peak memory 207072 kb
Host smart-7a794a28-ee92-43de-905c-89cbec9976b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012734501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3012734501
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2964355070
Short name T271
Test name
Test status
Simulation time 23060418933 ps
CPU time 156 seconds
Started Jun 23 05:51:09 PM PDT 24
Finished Jun 23 05:53:46 PM PDT 24
Peak memory 254956 kb
Host smart-fe5d769a-034b-40e3-9dd2-a91684e20994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964355070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2964355070
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.940045811
Short name T196
Test name
Test status
Simulation time 36128780522 ps
CPU time 347.97 seconds
Started Jun 23 05:51:11 PM PDT 24
Finished Jun 23 05:56:59 PM PDT 24
Peak memory 255228 kb
Host smart-a89bb762-1dfd-4ffd-9720-0d19c440fa9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940045811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.940045811
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1324724879
Short name T282
Test name
Test status
Simulation time 1841604529 ps
CPU time 24.28 seconds
Started Jun 23 05:51:12 PM PDT 24
Finished Jun 23 05:51:36 PM PDT 24
Peak memory 249568 kb
Host smart-5896504d-5aed-4328-ba7d-5b6d75f9d6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324724879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1324724879
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3116480089
Short name T911
Test name
Test status
Simulation time 5418422005 ps
CPU time 80.54 seconds
Started Jun 23 05:51:12 PM PDT 24
Finished Jun 23 05:52:33 PM PDT 24
Peak memory 249328 kb
Host smart-f93c68d2-0887-4c48-8312-0ce2c009a3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116480089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3116480089
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1223480111
Short name T689
Test name
Test status
Simulation time 61068874 ps
CPU time 3.43 seconds
Started Jun 23 05:51:09 PM PDT 24
Finished Jun 23 05:51:12 PM PDT 24
Peak memory 232844 kb
Host smart-734f8a9b-6a9b-478e-9e1d-8ebe8864fb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223480111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1223480111
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.861264482
Short name T753
Test name
Test status
Simulation time 6100114672 ps
CPU time 40.34 seconds
Started Jun 23 05:51:10 PM PDT 24
Finished Jun 23 05:51:51 PM PDT 24
Peak memory 239204 kb
Host smart-5bc4215e-6486-46b1-afb2-ef8e97c3bd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861264482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.861264482
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1533379909
Short name T39
Test name
Test status
Simulation time 18870558644 ps
CPU time 34.75 seconds
Started Jun 23 05:51:12 PM PDT 24
Finished Jun 23 05:51:48 PM PDT 24
Peak memory 232956 kb
Host smart-1cf003b1-72b8-4074-88eb-d5f6d606a3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533379909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1533379909
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.925151915
Short name T864
Test name
Test status
Simulation time 5031420970 ps
CPU time 10.95 seconds
Started Jun 23 05:51:10 PM PDT 24
Finished Jun 23 05:51:21 PM PDT 24
Peak memory 228356 kb
Host smart-95fd37bc-f4e9-49e1-a223-61cec9b5b4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925151915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.925151915
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.930684464
Short name T422
Test name
Test status
Simulation time 412714096 ps
CPU time 4.26 seconds
Started Jun 23 05:51:11 PM PDT 24
Finished Jun 23 05:51:15 PM PDT 24
Peak memory 222612 kb
Host smart-26ae4856-34ff-4cc1-9663-4f2ac0a9c076
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=930684464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.930684464
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.955871894
Short name T161
Test name
Test status
Simulation time 7802169916 ps
CPU time 14.79 seconds
Started Jun 23 05:51:12 PM PDT 24
Finished Jun 23 05:51:28 PM PDT 24
Peak memory 216452 kb
Host smart-f2752b3e-9687-47d9-a148-e176e09b684c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955871894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.955871894
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.488430513
Short name T862
Test name
Test status
Simulation time 754996696 ps
CPU time 4.06 seconds
Started Jun 23 05:51:16 PM PDT 24
Finished Jun 23 05:51:20 PM PDT 24
Peak memory 216340 kb
Host smart-ca978d7b-3fc3-4035-8ad0-5ec01aaf03b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488430513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.488430513
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2998559544
Short name T368
Test name
Test status
Simulation time 143921492 ps
CPU time 1.55 seconds
Started Jun 23 05:51:07 PM PDT 24
Finished Jun 23 05:51:09 PM PDT 24
Peak memory 216248 kb
Host smart-b644a6d9-43d0-4b10-b945-692e462979e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998559544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2998559544
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.4208483461
Short name T454
Test name
Test status
Simulation time 42529910 ps
CPU time 0.83 seconds
Started Jun 23 05:51:12 PM PDT 24
Finished Jun 23 05:51:14 PM PDT 24
Peak memory 206120 kb
Host smart-903ee885-4bc0-47ab-861b-163d36f88bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208483461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.4208483461
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1199881038
Short name T623
Test name
Test status
Simulation time 56479203251 ps
CPU time 16.28 seconds
Started Jun 23 05:51:11 PM PDT 24
Finished Jun 23 05:51:28 PM PDT 24
Peak memory 240764 kb
Host smart-7d8b87ec-5624-4a20-b952-ea87364eae6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199881038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1199881038
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3481086046
Short name T556
Test name
Test status
Simulation time 39766884 ps
CPU time 0.71 seconds
Started Jun 23 05:51:23 PM PDT 24
Finished Jun 23 05:51:24 PM PDT 24
Peak memory 205864 kb
Host smart-8857dd1e-54bb-4b27-82a1-6e1d2cbe3673
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481086046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3481086046
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2646044243
Short name T268
Test name
Test status
Simulation time 138294471 ps
CPU time 3.04 seconds
Started Jun 23 05:51:12 PM PDT 24
Finished Jun 23 05:51:15 PM PDT 24
Peak memory 224600 kb
Host smart-d21f60cd-5490-4b6f-8680-7fbff9234ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646044243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2646044243
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3405664044
Short name T752
Test name
Test status
Simulation time 43073427 ps
CPU time 0.78 seconds
Started Jun 23 05:51:08 PM PDT 24
Finished Jun 23 05:51:09 PM PDT 24
Peak memory 207024 kb
Host smart-9391d8ff-0683-4d99-9975-895b38f4b184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405664044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3405664044
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.614490150
Short name T799
Test name
Test status
Simulation time 1667775900 ps
CPU time 28.23 seconds
Started Jun 23 05:51:21 PM PDT 24
Finished Jun 23 05:51:50 PM PDT 24
Peak memory 249316 kb
Host smart-0e503bdc-236f-4fab-8e5a-c9b0809e7951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614490150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.614490150
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1783531290
Short name T951
Test name
Test status
Simulation time 2383164331 ps
CPU time 40.33 seconds
Started Jun 23 05:51:15 PM PDT 24
Finished Jun 23 05:51:56 PM PDT 24
Peak memory 239308 kb
Host smart-fa7086f9-27ef-4e29-a2a1-a716ff45e960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783531290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1783531290
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.5605687
Short name T137
Test name
Test status
Simulation time 29837561519 ps
CPU time 165.97 seconds
Started Jun 23 05:51:13 PM PDT 24
Finished Jun 23 05:53:59 PM PDT 24
Peak memory 255948 kb
Host smart-b6a9f985-b36d-412b-917c-8b608857f6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5605687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.5605687
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2715782451
Short name T302
Test name
Test status
Simulation time 2500582013 ps
CPU time 7.22 seconds
Started Jun 23 05:51:11 PM PDT 24
Finished Jun 23 05:51:19 PM PDT 24
Peak memory 241188 kb
Host smart-7fc4558d-e196-4281-a6a3-dd2ebf86061a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715782451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2715782451
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2874882964
Short name T491
Test name
Test status
Simulation time 1160381484 ps
CPU time 13.27 seconds
Started Jun 23 05:51:08 PM PDT 24
Finished Jun 23 05:51:21 PM PDT 24
Peak memory 224608 kb
Host smart-90113e26-d94e-482e-a117-64ea4b01fd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874882964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2874882964
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1499216282
Short name T213
Test name
Test status
Simulation time 5657763736 ps
CPU time 75.98 seconds
Started Jun 23 05:51:11 PM PDT 24
Finished Jun 23 05:52:27 PM PDT 24
Peak memory 232964 kb
Host smart-0b8e591d-7bc2-485a-8556-e154bfc450f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499216282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1499216282
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2761757096
Short name T211
Test name
Test status
Simulation time 22382039460 ps
CPU time 20.84 seconds
Started Jun 23 05:51:07 PM PDT 24
Finished Jun 23 05:51:29 PM PDT 24
Peak memory 241152 kb
Host smart-30575dd5-0a32-4e93-b121-21c90048b4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761757096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2761757096
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3407362824
Short name T627
Test name
Test status
Simulation time 101764270 ps
CPU time 2.17 seconds
Started Jun 23 05:51:15 PM PDT 24
Finished Jun 23 05:51:18 PM PDT 24
Peak memory 232572 kb
Host smart-ac1393f4-1c19-4584-995c-140493fc8e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407362824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3407362824
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4104693342
Short name T475
Test name
Test status
Simulation time 2100891480 ps
CPU time 7.87 seconds
Started Jun 23 05:51:12 PM PDT 24
Finished Jun 23 05:51:21 PM PDT 24
Peak memory 223216 kb
Host smart-32779cef-0beb-491b-b6eb-25fb06e6c070
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4104693342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4104693342
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.4260534153
Short name T17
Test name
Test status
Simulation time 58756169975 ps
CPU time 181.27 seconds
Started Jun 23 05:51:17 PM PDT 24
Finished Jun 23 05:54:24 PM PDT 24
Peak memory 266824 kb
Host smart-1e915c09-9784-4ab0-9943-702504da64c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260534153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.4260534153
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1426589537
Short name T602
Test name
Test status
Simulation time 16300815321 ps
CPU time 20.83 seconds
Started Jun 23 05:51:09 PM PDT 24
Finished Jun 23 05:51:31 PM PDT 24
Peak memory 216500 kb
Host smart-15c43374-564d-465c-ad75-65c452c6090c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426589537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1426589537
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1939231391
Short name T504
Test name
Test status
Simulation time 11654904 ps
CPU time 0.71 seconds
Started Jun 23 05:51:11 PM PDT 24
Finished Jun 23 05:51:12 PM PDT 24
Peak memory 205764 kb
Host smart-dcfffe62-00e4-42d6-8eeb-1977cfd0d247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939231391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1939231391
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1127498998
Short name T918
Test name
Test status
Simulation time 18579749 ps
CPU time 0.91 seconds
Started Jun 23 05:51:12 PM PDT 24
Finished Jun 23 05:51:14 PM PDT 24
Peak memory 207496 kb
Host smart-460a967d-2f8d-4cad-9cff-9a44db0bce30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127498998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1127498998
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.492009156
Short name T838
Test name
Test status
Simulation time 375492117 ps
CPU time 1.01 seconds
Started Jun 23 05:51:08 PM PDT 24
Finished Jun 23 05:51:10 PM PDT 24
Peak memory 206368 kb
Host smart-e450b37e-d1c1-4369-9d2b-a9d0aa86d977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492009156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.492009156
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3393987530
Short name T570
Test name
Test status
Simulation time 4773681912 ps
CPU time 5.59 seconds
Started Jun 23 05:51:11 PM PDT 24
Finished Jun 23 05:51:17 PM PDT 24
Peak memory 218316 kb
Host smart-66a50305-d114-45b3-a290-283645cbe95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393987530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3393987530
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.4090248631
Short name T537
Test name
Test status
Simulation time 20854058 ps
CPU time 0.73 seconds
Started Jun 23 05:51:15 PM PDT 24
Finished Jun 23 05:51:16 PM PDT 24
Peak memory 205524 kb
Host smart-32947c58-c521-4c12-a30b-14d966cc5835
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090248631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
4090248631
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2159313379
Short name T235
Test name
Test status
Simulation time 1763642598 ps
CPU time 13.4 seconds
Started Jun 23 05:51:17 PM PDT 24
Finished Jun 23 05:51:31 PM PDT 24
Peak memory 224640 kb
Host smart-a2bdb178-f143-4f45-8c4e-b4a6d26262bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159313379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2159313379
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1150381897
Short name T62
Test name
Test status
Simulation time 21190283 ps
CPU time 0.77 seconds
Started Jun 23 05:51:17 PM PDT 24
Finished Jun 23 05:51:18 PM PDT 24
Peak memory 206752 kb
Host smart-413ee37f-e953-4137-bc8f-fd32bc7e2462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150381897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1150381897
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.937129946
Short name T55
Test name
Test status
Simulation time 27526520223 ps
CPU time 203.09 seconds
Started Jun 23 05:51:21 PM PDT 24
Finished Jun 23 05:54:45 PM PDT 24
Peak memory 254000 kb
Host smart-b522c20f-f14a-4c14-82b6-05b1e1c207c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937129946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.937129946
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3312210738
Short name T166
Test name
Test status
Simulation time 54493539864 ps
CPU time 175.17 seconds
Started Jun 23 05:51:18 PM PDT 24
Finished Jun 23 05:54:14 PM PDT 24
Peak memory 262924 kb
Host smart-b446044d-3686-4629-8e72-aac94e694eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312210738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3312210738
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2278911536
Short name T459
Test name
Test status
Simulation time 509669453 ps
CPU time 3.15 seconds
Started Jun 23 05:51:21 PM PDT 24
Finished Jun 23 05:51:25 PM PDT 24
Peak memory 224616 kb
Host smart-cd8d79df-5f61-400d-8cc7-f0485cd3df4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278911536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2278911536
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.9923315
Short name T193
Test name
Test status
Simulation time 19203001251 ps
CPU time 17.23 seconds
Started Jun 23 05:51:13 PM PDT 24
Finished Jun 23 05:51:31 PM PDT 24
Peak memory 224760 kb
Host smart-aa658040-9baf-466f-b95f-dc69fc5c2e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9923315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.9923315
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3945213957
Short name T325
Test name
Test status
Simulation time 491715138 ps
CPU time 5.92 seconds
Started Jun 23 05:51:17 PM PDT 24
Finished Jun 23 05:51:23 PM PDT 24
Peak memory 232852 kb
Host smart-3e4f282a-a876-4c8a-8bb7-1dbfc60489dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945213957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3945213957
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.20953257
Short name T890
Test name
Test status
Simulation time 91740462 ps
CPU time 2.5 seconds
Started Jun 23 05:51:17 PM PDT 24
Finished Jun 23 05:51:20 PM PDT 24
Peak memory 224592 kb
Host smart-c4284505-4327-49a3-bd9e-ba0e5d6bf5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20953257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.20953257
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.4256172084
Short name T818
Test name
Test status
Simulation time 4371689398 ps
CPU time 4.17 seconds
Started Jun 23 05:51:20 PM PDT 24
Finished Jun 23 05:51:24 PM PDT 24
Peak memory 232964 kb
Host smart-8ea9ef44-92ce-42c7-89c1-4791b672d41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256172084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.4256172084
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3923671103
Short name T670
Test name
Test status
Simulation time 3479699109 ps
CPU time 12.07 seconds
Started Jun 23 05:51:14 PM PDT 24
Finished Jun 23 05:51:26 PM PDT 24
Peak memory 223264 kb
Host smart-0a36fdfc-28ac-457d-af92-8d6a803eaec0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3923671103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3923671103
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1403803129
Short name T945
Test name
Test status
Simulation time 14577979548 ps
CPU time 202.16 seconds
Started Jun 23 05:51:15 PM PDT 24
Finished Jun 23 05:54:38 PM PDT 24
Peak memory 266872 kb
Host smart-3ae600a2-d32f-4636-8fc6-b0aee032c7f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403803129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1403803129
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.344482617
Short name T545
Test name
Test status
Simulation time 1531751171 ps
CPU time 9.35 seconds
Started Jun 23 05:51:22 PM PDT 24
Finished Jun 23 05:51:32 PM PDT 24
Peak memory 216404 kb
Host smart-9d09cf6a-6e59-4b93-ac3c-6a5150949c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344482617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.344482617
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2974441834
Short name T867
Test name
Test status
Simulation time 40241858421 ps
CPU time 12.17 seconds
Started Jun 23 05:51:22 PM PDT 24
Finished Jun 23 05:51:34 PM PDT 24
Peak memory 216472 kb
Host smart-405c901c-0278-4725-98d9-9403047375cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974441834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2974441834
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.4272254604
Short name T128
Test name
Test status
Simulation time 80210722 ps
CPU time 0.93 seconds
Started Jun 23 05:51:17 PM PDT 24
Finished Jun 23 05:51:19 PM PDT 24
Peak memory 206948 kb
Host smart-7b81d3a6-2611-4864-831a-585b3f7596ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272254604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.4272254604
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.852819447
Short name T85
Test name
Test status
Simulation time 121157145 ps
CPU time 1.04 seconds
Started Jun 23 05:51:16 PM PDT 24
Finished Jun 23 05:51:17 PM PDT 24
Peak memory 206580 kb
Host smart-ce23ff23-c652-470f-983f-938d6c8c0610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852819447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.852819447
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1357806258
Short name T800
Test name
Test status
Simulation time 47108766905 ps
CPU time 31.69 seconds
Started Jun 23 05:51:15 PM PDT 24
Finished Jun 23 05:51:47 PM PDT 24
Peak memory 249412 kb
Host smart-f544cbdf-9ed2-4e36-96f4-d338361bf497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357806258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1357806258
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3833170935
Short name T365
Test name
Test status
Simulation time 11464189 ps
CPU time 0.69 seconds
Started Jun 23 05:51:25 PM PDT 24
Finished Jun 23 05:51:26 PM PDT 24
Peak memory 205444 kb
Host smart-ba14a9a9-d9fb-46d8-b009-5cabb298f709
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833170935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3833170935
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1936586009
Short name T181
Test name
Test status
Simulation time 6455265561 ps
CPU time 21.26 seconds
Started Jun 23 05:51:23 PM PDT 24
Finished Jun 23 05:51:45 PM PDT 24
Peak memory 224364 kb
Host smart-101f2136-e689-4426-9abe-c3dbc6207d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936586009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1936586009
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2467339465
Short name T575
Test name
Test status
Simulation time 70431829 ps
CPU time 0.77 seconds
Started Jun 23 05:51:17 PM PDT 24
Finished Jun 23 05:51:18 PM PDT 24
Peak memory 207072 kb
Host smart-651b103c-d158-476e-949a-0da1db93f8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467339465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2467339465
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1622280098
Short name T603
Test name
Test status
Simulation time 7269740234 ps
CPU time 28.17 seconds
Started Jun 23 05:51:21 PM PDT 24
Finished Jun 23 05:51:50 PM PDT 24
Peak memory 218148 kb
Host smart-94d9f378-c270-48a3-9079-bf041d995874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622280098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1622280098
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1634481676
Short name T683
Test name
Test status
Simulation time 91833842 ps
CPU time 2.55 seconds
Started Jun 23 05:51:20 PM PDT 24
Finished Jun 23 05:51:23 PM PDT 24
Peak memory 232888 kb
Host smart-b8f6f5f9-f377-45ed-a389-58d0451343ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634481676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1634481676
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.485069082
Short name T830
Test name
Test status
Simulation time 2553090949 ps
CPU time 23.66 seconds
Started Jun 23 05:51:19 PM PDT 24
Finished Jun 23 05:51:43 PM PDT 24
Peak memory 233004 kb
Host smart-f0af5c6f-cdd6-4334-b8d6-70e22e7ea7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485069082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.485069082
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3770311799
Short name T887
Test name
Test status
Simulation time 3509702690 ps
CPU time 27.71 seconds
Started Jun 23 05:51:24 PM PDT 24
Finished Jun 23 05:51:53 PM PDT 24
Peak memory 224660 kb
Host smart-99862dfe-9faa-4267-a0f1-a493a234f9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770311799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3770311799
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2195696270
Short name T828
Test name
Test status
Simulation time 11188766497 ps
CPU time 10.22 seconds
Started Jun 23 05:51:26 PM PDT 24
Finished Jun 23 05:51:37 PM PDT 24
Peak memory 232856 kb
Host smart-b4cd340d-372f-492b-b65c-8444329eb672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195696270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2195696270
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.4160807981
Short name T411
Test name
Test status
Simulation time 148578393 ps
CPU time 2.45 seconds
Started Jun 23 05:51:16 PM PDT 24
Finished Jun 23 05:51:19 PM PDT 24
Peak memory 223040 kb
Host smart-20872859-ab1d-42e1-b856-2978411ae7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160807981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.4160807981
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.233991204
Short name T849
Test name
Test status
Simulation time 1015133973 ps
CPU time 12.39 seconds
Started Jun 23 05:51:20 PM PDT 24
Finished Jun 23 05:51:33 PM PDT 24
Peak memory 222836 kb
Host smart-986062ec-6f45-4344-bcf8-791e447dd5ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=233991204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.233991204
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1815577709
Short name T219
Test name
Test status
Simulation time 62944183268 ps
CPU time 280.9 seconds
Started Jun 23 05:51:24 PM PDT 24
Finished Jun 23 05:56:06 PM PDT 24
Peak memory 256320 kb
Host smart-49b82e83-d5fe-4a39-a787-f503cc134b46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815577709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1815577709
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2860228546
Short name T947
Test name
Test status
Simulation time 1978950498 ps
CPU time 30.62 seconds
Started Jun 23 05:51:17 PM PDT 24
Finished Jun 23 05:51:48 PM PDT 24
Peak memory 216296 kb
Host smart-6f3babb9-38fb-4fe1-99e4-c84530dbbd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860228546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2860228546
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2604853458
Short name T583
Test name
Test status
Simulation time 1518028484 ps
CPU time 5.31 seconds
Started Jun 23 05:51:21 PM PDT 24
Finished Jun 23 05:51:27 PM PDT 24
Peak memory 216424 kb
Host smart-b8eb06db-5bc7-4720-b14f-8d4ce1ba6af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604853458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2604853458
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.36195940
Short name T827
Test name
Test status
Simulation time 20294681 ps
CPU time 1.22 seconds
Started Jun 23 05:51:14 PM PDT 24
Finished Jun 23 05:51:15 PM PDT 24
Peak memory 208156 kb
Host smart-76db3de9-9670-4573-a5ad-6af6cafa94b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36195940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.36195940
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.597546313
Short name T560
Test name
Test status
Simulation time 377002247 ps
CPU time 1.02 seconds
Started Jun 23 05:51:21 PM PDT 24
Finished Jun 23 05:51:22 PM PDT 24
Peak memory 206600 kb
Host smart-8c7ea17c-b355-4d5e-8176-d86645297667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597546313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.597546313
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.855596779
Short name T426
Test name
Test status
Simulation time 1842205533 ps
CPU time 7.27 seconds
Started Jun 23 05:51:21 PM PDT 24
Finished Jun 23 05:51:29 PM PDT 24
Peak memory 232900 kb
Host smart-78eb9764-b265-475b-80bf-5c25e34e8c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855596779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.855596779
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1611747541
Short name T798
Test name
Test status
Simulation time 23911362 ps
CPU time 0.7 seconds
Started Jun 23 05:51:21 PM PDT 24
Finished Jun 23 05:51:22 PM PDT 24
Peak memory 205504 kb
Host smart-2b31fd04-b6d8-47dd-8f8e-8100fe9ff152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611747541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1611747541
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1283297158
Short name T250
Test name
Test status
Simulation time 761095547 ps
CPU time 4.57 seconds
Started Jun 23 05:51:23 PM PDT 24
Finished Jun 23 05:51:28 PM PDT 24
Peak memory 224672 kb
Host smart-784d2db3-8d3a-4bbb-9961-01f4ccdabd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283297158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1283297158
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3693636283
Short name T858
Test name
Test status
Simulation time 19207485 ps
CPU time 0.77 seconds
Started Jun 23 05:51:18 PM PDT 24
Finished Jun 23 05:51:19 PM PDT 24
Peak memory 205712 kb
Host smart-929162f0-7a67-4301-85b6-979034938a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693636283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3693636283
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2582984483
Short name T624
Test name
Test status
Simulation time 6987364882 ps
CPU time 13.66 seconds
Started Jun 23 05:51:19 PM PDT 24
Finished Jun 23 05:51:33 PM PDT 24
Peak memory 236500 kb
Host smart-60ea2364-6b4f-4b37-90e1-fbbc4272f03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582984483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2582984483
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2701336135
Short name T43
Test name
Test status
Simulation time 16036976297 ps
CPU time 105.81 seconds
Started Jun 23 05:51:26 PM PDT 24
Finished Jun 23 05:53:12 PM PDT 24
Peak memory 264996 kb
Host smart-ebc5c261-c4ce-4b43-9c27-c306b451474a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701336135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2701336135
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.4213208108
Short name T194
Test name
Test status
Simulation time 298066121747 ps
CPU time 490.41 seconds
Started Jun 23 05:51:23 PM PDT 24
Finished Jun 23 05:59:34 PM PDT 24
Peak memory 268444 kb
Host smart-2c1475c1-d482-4434-b296-947bf106df78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213208108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.4213208108
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2023481668
Short name T318
Test name
Test status
Simulation time 140072497 ps
CPU time 2.83 seconds
Started Jun 23 05:51:21 PM PDT 24
Finished Jun 23 05:51:24 PM PDT 24
Peak memory 224596 kb
Host smart-82572400-aa7f-4931-b873-062a86bc0619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023481668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2023481668
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2907675897
Short name T706
Test name
Test status
Simulation time 138506730 ps
CPU time 5.13 seconds
Started Jun 23 05:51:21 PM PDT 24
Finished Jun 23 05:51:27 PM PDT 24
Peak memory 232900 kb
Host smart-5c9e7d2a-c4d9-400c-bb40-7de77b3ecbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907675897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2907675897
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3120357566
Short name T388
Test name
Test status
Simulation time 2850032624 ps
CPU time 16.83 seconds
Started Jun 23 05:51:20 PM PDT 24
Finished Jun 23 05:51:38 PM PDT 24
Peak memory 232980 kb
Host smart-a711193b-6f2c-4185-bc8b-6c249333f747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120357566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3120357566
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.491877892
Short name T293
Test name
Test status
Simulation time 20757219339 ps
CPU time 12.46 seconds
Started Jun 23 05:51:22 PM PDT 24
Finished Jun 23 05:51:35 PM PDT 24
Peak memory 224752 kb
Host smart-f196a5b8-95b2-409f-8ca4-f411c5a84a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491877892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.491877892
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.220439750
Short name T416
Test name
Test status
Simulation time 2197157920 ps
CPU time 3.87 seconds
Started Jun 23 05:51:23 PM PDT 24
Finished Jun 23 05:51:28 PM PDT 24
Peak memory 232364 kb
Host smart-36de37af-1245-4081-b9e9-cf8c2a6ba248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220439750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.220439750
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2395646817
Short name T900
Test name
Test status
Simulation time 1154160439 ps
CPU time 14.37 seconds
Started Jun 23 05:51:24 PM PDT 24
Finished Jun 23 05:51:39 PM PDT 24
Peak memory 218984 kb
Host smart-5a108d7b-1ea6-458d-ae0e-fe621db925f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2395646817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2395646817
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1431648772
Short name T373
Test name
Test status
Simulation time 14956472960 ps
CPU time 37.12 seconds
Started Jun 23 05:51:25 PM PDT 24
Finished Jun 23 05:52:03 PM PDT 24
Peak memory 216472 kb
Host smart-6b1c94ea-2939-4809-803e-7b49bd29844c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431648772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1431648772
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.196185938
Short name T136
Test name
Test status
Simulation time 12337922977 ps
CPU time 9.03 seconds
Started Jun 23 05:51:23 PM PDT 24
Finished Jun 23 05:51:32 PM PDT 24
Peak memory 216604 kb
Host smart-03ddd728-718d-4a2b-b2eb-df3113190f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196185938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.196185938
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2537997437
Short name T327
Test name
Test status
Simulation time 19254041 ps
CPU time 1.12 seconds
Started Jun 23 05:51:22 PM PDT 24
Finished Jun 23 05:51:24 PM PDT 24
Peak memory 208112 kb
Host smart-7b55dc27-390e-4c97-834d-37a87238de41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537997437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2537997437
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2121559250
Short name T510
Test name
Test status
Simulation time 62581752 ps
CPU time 0.84 seconds
Started Jun 23 05:51:19 PM PDT 24
Finished Jun 23 05:51:20 PM PDT 24
Peak memory 207320 kb
Host smart-83f64e92-bbe0-40d4-b83a-a085a18abd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121559250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2121559250
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2781041264
Short name T58
Test name
Test status
Simulation time 1027993599 ps
CPU time 5.91 seconds
Started Jun 23 05:51:26 PM PDT 24
Finished Jun 23 05:51:32 PM PDT 24
Peak memory 239932 kb
Host smart-42c1b42f-8647-4b18-a03d-f775bffcbf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781041264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2781041264
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2211930957
Short name T950
Test name
Test status
Simulation time 41037588 ps
CPU time 0.7 seconds
Started Jun 23 05:51:26 PM PDT 24
Finished Jun 23 05:51:28 PM PDT 24
Peak memory 204884 kb
Host smart-3f1afaae-9dbf-4fd1-94ee-1e301d203917
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211930957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2211930957
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3009188711
Short name T477
Test name
Test status
Simulation time 51234807 ps
CPU time 2.16 seconds
Started Jun 23 05:51:27 PM PDT 24
Finished Jun 23 05:51:30 PM PDT 24
Peak memory 223840 kb
Host smart-6e335414-c516-4d62-b1cf-0b5bbd7b836b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009188711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3009188711
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3205514164
Short name T322
Test name
Test status
Simulation time 18012786 ps
CPU time 0.87 seconds
Started Jun 23 05:51:22 PM PDT 24
Finished Jun 23 05:51:24 PM PDT 24
Peak memory 206656 kb
Host smart-e1c50424-e20c-4a3e-b4fb-72f9f5d66a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205514164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3205514164
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.935754365
Short name T760
Test name
Test status
Simulation time 6348101193 ps
CPU time 83.62 seconds
Started Jun 23 05:51:26 PM PDT 24
Finished Jun 23 05:52:51 PM PDT 24
Peak memory 249344 kb
Host smart-de3f5b5d-7aff-4f5f-b274-c5aa3d08a3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935754365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.935754365
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.424275603
Short name T238
Test name
Test status
Simulation time 15003588979 ps
CPU time 156.12 seconds
Started Jun 23 05:51:31 PM PDT 24
Finished Jun 23 05:54:07 PM PDT 24
Peak memory 249412 kb
Host smart-c34e746e-303d-4ec0-8672-fe35d84e3f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424275603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.424275603
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2402232412
Short name T419
Test name
Test status
Simulation time 58796722499 ps
CPU time 252.04 seconds
Started Jun 23 05:51:26 PM PDT 24
Finished Jun 23 05:55:39 PM PDT 24
Peak memory 253796 kb
Host smart-1f7f0870-22c5-40f0-9b3e-7a7a2080fb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402232412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2402232412
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1710612631
Short name T877
Test name
Test status
Simulation time 960722117 ps
CPU time 13.4 seconds
Started Jun 23 05:51:25 PM PDT 24
Finished Jun 23 05:51:39 PM PDT 24
Peak memory 233880 kb
Host smart-b5725cdd-b0bd-4736-970a-a23d8501529c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710612631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1710612631
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3260765700
Short name T87
Test name
Test status
Simulation time 572050885 ps
CPU time 3.15 seconds
Started Jun 23 05:51:26 PM PDT 24
Finished Jun 23 05:51:30 PM PDT 24
Peak memory 224648 kb
Host smart-a15522ed-4c62-40e5-bb05-15bed87d332c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260765700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3260765700
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1970603069
Short name T786
Test name
Test status
Simulation time 4886476067 ps
CPU time 41.35 seconds
Started Jun 23 05:51:26 PM PDT 24
Finished Jun 23 05:52:08 PM PDT 24
Peak memory 241160 kb
Host smart-3b65572b-aa8c-44e0-a5d7-2d9737f13cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970603069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1970603069
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2792197920
Short name T809
Test name
Test status
Simulation time 4774749495 ps
CPU time 17.31 seconds
Started Jun 23 05:51:35 PM PDT 24
Finished Jun 23 05:51:53 PM PDT 24
Peak memory 249392 kb
Host smart-f71cda41-7b4c-4b3f-8f7c-f2b76ed19a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792197920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2792197920
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3826719570
Short name T500
Test name
Test status
Simulation time 58350900 ps
CPU time 2.7 seconds
Started Jun 23 05:51:26 PM PDT 24
Finished Jun 23 05:51:30 PM PDT 24
Peak memory 232552 kb
Host smart-4fc71f02-9761-48f3-a2fe-dbdf544ee824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826719570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3826719570
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.4191837386
Short name T341
Test name
Test status
Simulation time 1644588372 ps
CPU time 6.2 seconds
Started Jun 23 05:51:26 PM PDT 24
Finished Jun 23 05:51:32 PM PDT 24
Peak memory 219464 kb
Host smart-6567d898-7068-4b7a-9bcc-ad74e285a5d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4191837386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.4191837386
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3021494974
Short name T448
Test name
Test status
Simulation time 196994491 ps
CPU time 1.25 seconds
Started Jun 23 05:51:27 PM PDT 24
Finished Jun 23 05:51:29 PM PDT 24
Peak memory 207024 kb
Host smart-356bf41e-92fa-439e-b8ed-f2913bf59003
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021494974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3021494974
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2359492920
Short name T772
Test name
Test status
Simulation time 37198120 ps
CPU time 0.71 seconds
Started Jun 23 05:51:23 PM PDT 24
Finished Jun 23 05:51:25 PM PDT 24
Peak memory 205804 kb
Host smart-d7d9921b-647b-4353-bfbf-3be9b6b137b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359492920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2359492920
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2104811861
Short name T546
Test name
Test status
Simulation time 1263060395 ps
CPU time 4.08 seconds
Started Jun 23 05:51:24 PM PDT 24
Finished Jun 23 05:51:29 PM PDT 24
Peak memory 216364 kb
Host smart-d34f5402-1949-4d63-8f33-6a98005dac7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104811861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2104811861
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1965832664
Short name T888
Test name
Test status
Simulation time 102306725 ps
CPU time 1.72 seconds
Started Jun 23 05:51:25 PM PDT 24
Finished Jun 23 05:51:27 PM PDT 24
Peak memory 216400 kb
Host smart-26bec847-de54-43a3-8339-f0cd46d93fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965832664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1965832664
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1636910561
Short name T376
Test name
Test status
Simulation time 419955067 ps
CPU time 1 seconds
Started Jun 23 05:51:22 PM PDT 24
Finished Jun 23 05:51:24 PM PDT 24
Peak memory 206360 kb
Host smart-e2b84626-ea27-4410-a43f-3c5c60283811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636910561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1636910561
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2475103942
Short name T446
Test name
Test status
Simulation time 4792511686 ps
CPU time 8.06 seconds
Started Jun 23 05:51:25 PM PDT 24
Finished Jun 23 05:51:34 PM PDT 24
Peak memory 224800 kb
Host smart-5a5eb5cf-3dfe-4e05-a4bd-b9cf6576db52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475103942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2475103942
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.899014885
Short name T343
Test name
Test status
Simulation time 14718961 ps
CPU time 0.71 seconds
Started Jun 23 05:51:22 PM PDT 24
Finished Jun 23 05:51:23 PM PDT 24
Peak memory 204904 kb
Host smart-5323c398-eada-4446-bc57-c70e7657d9ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899014885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.899014885
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1033741791
Short name T404
Test name
Test status
Simulation time 608913884 ps
CPU time 6.94 seconds
Started Jun 23 05:51:29 PM PDT 24
Finished Jun 23 05:51:36 PM PDT 24
Peak memory 224612 kb
Host smart-6a850dcc-ff33-484b-8c53-ea43c07d0261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033741791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1033741791
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.4219339524
Short name T522
Test name
Test status
Simulation time 71150555 ps
CPU time 0.79 seconds
Started Jun 23 05:51:31 PM PDT 24
Finished Jun 23 05:51:32 PM PDT 24
Peak memory 206724 kb
Host smart-7a81ff8b-cb13-467c-9eae-a2b221615697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219339524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.4219339524
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.328277845
Short name T680
Test name
Test status
Simulation time 7864562990 ps
CPU time 80.13 seconds
Started Jun 23 05:51:25 PM PDT 24
Finished Jun 23 05:52:46 PM PDT 24
Peak memory 249520 kb
Host smart-79f2407e-f01b-4398-a194-8d7ad5c37332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328277845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.328277845
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1481044069
Short name T941
Test name
Test status
Simulation time 46977916810 ps
CPU time 121.37 seconds
Started Jun 23 05:51:24 PM PDT 24
Finished Jun 23 05:53:26 PM PDT 24
Peak memory 250448 kb
Host smart-13ce24ec-8e8a-45d9-8952-b5f9ea5cb320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481044069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1481044069
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3194178933
Short name T89
Test name
Test status
Simulation time 2651888765 ps
CPU time 45.28 seconds
Started Jun 23 05:51:30 PM PDT 24
Finished Jun 23 05:52:16 PM PDT 24
Peak memory 232976 kb
Host smart-a334ebdd-97f6-4975-9f97-adacbc1aa3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194178933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3194178933
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1868396456
Short name T929
Test name
Test status
Simulation time 582360276 ps
CPU time 3.39 seconds
Started Jun 23 05:51:23 PM PDT 24
Finished Jun 23 05:51:27 PM PDT 24
Peak memory 224680 kb
Host smart-5555dc53-8ef6-4f1d-bbd6-e93ef2abf7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868396456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1868396456
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3449514499
Short name T778
Test name
Test status
Simulation time 40344519468 ps
CPU time 23.82 seconds
Started Jun 23 05:51:26 PM PDT 24
Finished Jun 23 05:51:51 PM PDT 24
Peak memory 234968 kb
Host smart-e45dc6fe-7dff-4e90-a41c-bad63ec33fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449514499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3449514499
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.420887240
Short name T296
Test name
Test status
Simulation time 1617795167 ps
CPU time 9.86 seconds
Started Jun 23 05:51:28 PM PDT 24
Finished Jun 23 05:51:39 PM PDT 24
Peak memory 232876 kb
Host smart-073b81da-356e-4b35-96cb-17cfd3492acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420887240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.420887240
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2670557296
Short name T619
Test name
Test status
Simulation time 792702182 ps
CPU time 7.66 seconds
Started Jun 23 05:51:28 PM PDT 24
Finished Jun 23 05:51:36 PM PDT 24
Peak memory 240884 kb
Host smart-ccde78f4-4774-4d52-81a9-c3d40c399a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670557296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2670557296
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1285230765
Short name T953
Test name
Test status
Simulation time 199608252 ps
CPU time 4.04 seconds
Started Jun 23 05:51:27 PM PDT 24
Finished Jun 23 05:51:32 PM PDT 24
Peak memory 223216 kb
Host smart-a288e4d6-2e4d-4099-8dd2-aa5d17ee936a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1285230765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1285230765
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1630821034
Short name T19
Test name
Test status
Simulation time 2820472952 ps
CPU time 38.36 seconds
Started Jun 23 05:51:23 PM PDT 24
Finished Jun 23 05:52:02 PM PDT 24
Peak memory 239332 kb
Host smart-82bb1aec-a821-4737-b648-e2867403ee13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630821034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1630821034
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1594976004
Short name T27
Test name
Test status
Simulation time 2577140437 ps
CPU time 21.94 seconds
Started Jun 23 05:51:25 PM PDT 24
Finished Jun 23 05:51:48 PM PDT 24
Peak memory 219628 kb
Host smart-5e55afb3-43a7-45d1-9116-13a68082368a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594976004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1594976004
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1447393439
Short name T707
Test name
Test status
Simulation time 1784232147 ps
CPU time 6.69 seconds
Started Jun 23 05:51:26 PM PDT 24
Finished Jun 23 05:51:34 PM PDT 24
Peak memory 216320 kb
Host smart-556f2048-fd3d-4fba-926c-e2a66e2ca04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447393439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1447393439
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.272976206
Short name T353
Test name
Test status
Simulation time 1384717317 ps
CPU time 16.5 seconds
Started Jun 23 05:51:27 PM PDT 24
Finished Jun 23 05:51:44 PM PDT 24
Peak memory 216400 kb
Host smart-adcaeb0d-84d5-4285-831a-bab36281e322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272976206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.272976206
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3998579885
Short name T129
Test name
Test status
Simulation time 42540834 ps
CPU time 0.83 seconds
Started Jun 23 05:51:28 PM PDT 24
Finished Jun 23 05:51:29 PM PDT 24
Peak memory 206112 kb
Host smart-bdbd712d-1023-4949-9310-50b335cd4664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998579885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3998579885
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2571129925
Short name T396
Test name
Test status
Simulation time 78488432881 ps
CPU time 18.31 seconds
Started Jun 23 05:51:28 PM PDT 24
Finished Jun 23 05:51:46 PM PDT 24
Peak memory 233024 kb
Host smart-bbc8ed66-4207-4d7e-aea4-b0a6069ab1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571129925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2571129925
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2947760294
Short name T749
Test name
Test status
Simulation time 11620073 ps
CPU time 0.71 seconds
Started Jun 23 05:51:37 PM PDT 24
Finished Jun 23 05:51:38 PM PDT 24
Peak memory 204952 kb
Host smart-432d6436-0b69-4bd4-a24b-a30e5beb681f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947760294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2947760294
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1212221045
Short name T872
Test name
Test status
Simulation time 7942892342 ps
CPU time 18.62 seconds
Started Jun 23 05:51:26 PM PDT 24
Finished Jun 23 05:51:45 PM PDT 24
Peak memory 233016 kb
Host smart-e9d2c79e-49d6-46ae-8cda-297585223988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212221045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1212221045
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.974742072
Short name T726
Test name
Test status
Simulation time 39039898 ps
CPU time 0.79 seconds
Started Jun 23 05:51:25 PM PDT 24
Finished Jun 23 05:51:26 PM PDT 24
Peak memory 206772 kb
Host smart-74b3277b-c7c1-4a23-a192-e96461f533aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974742072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.974742072
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2305638022
Short name T637
Test name
Test status
Simulation time 16545622 ps
CPU time 0.76 seconds
Started Jun 23 05:51:32 PM PDT 24
Finished Jun 23 05:51:33 PM PDT 24
Peak memory 215996 kb
Host smart-787fe793-b08f-4b7b-8a98-c537ea1412c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305638022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2305638022
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3927567236
Short name T47
Test name
Test status
Simulation time 3553257456 ps
CPU time 84.25 seconds
Started Jun 23 05:51:30 PM PDT 24
Finished Jun 23 05:52:55 PM PDT 24
Peak memory 255304 kb
Host smart-c58d658d-0df6-4a58-8784-eedee0300935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927567236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3927567236
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2121172057
Short name T882
Test name
Test status
Simulation time 75233207834 ps
CPU time 235.33 seconds
Started Jun 23 05:51:32 PM PDT 24
Finished Jun 23 05:55:28 PM PDT 24
Peak memory 272332 kb
Host smart-ac6835e2-6997-4c7f-b01f-b02267239475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121172057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2121172057
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1190183957
Short name T742
Test name
Test status
Simulation time 10315430846 ps
CPU time 92.93 seconds
Started Jun 23 05:51:30 PM PDT 24
Finished Jun 23 05:53:03 PM PDT 24
Peak memory 241188 kb
Host smart-6ca95852-33f4-465f-8431-de358349d4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190183957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1190183957
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1891809678
Short name T531
Test name
Test status
Simulation time 1169516083 ps
CPU time 4.29 seconds
Started Jun 23 05:51:29 PM PDT 24
Finished Jun 23 05:51:34 PM PDT 24
Peak memory 224644 kb
Host smart-5a52d217-589f-40d9-8dd4-a91c8ef9263b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891809678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1891809678
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1841915983
Short name T747
Test name
Test status
Simulation time 1505138952 ps
CPU time 20.63 seconds
Started Jun 23 05:51:27 PM PDT 24
Finished Jun 23 05:51:48 PM PDT 24
Peak memory 232892 kb
Host smart-30c7a6cc-815c-45c2-9106-ba7460d8b4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841915983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1841915983
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1201332767
Short name T297
Test name
Test status
Simulation time 11663968438 ps
CPU time 11.29 seconds
Started Jun 23 05:51:28 PM PDT 24
Finished Jun 23 05:51:40 PM PDT 24
Peak memory 224728 kb
Host smart-2b56265b-f08e-4cfc-9d0c-11def73083b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201332767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1201332767
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3245855693
Short name T251
Test name
Test status
Simulation time 12514566593 ps
CPU time 14.79 seconds
Started Jun 23 05:51:28 PM PDT 24
Finished Jun 23 05:51:43 PM PDT 24
Peak memory 233020 kb
Host smart-32676471-821a-4c62-9f52-591768578e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245855693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3245855693
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.4111878175
Short name T878
Test name
Test status
Simulation time 3629297947 ps
CPU time 11.13 seconds
Started Jun 23 05:51:36 PM PDT 24
Finished Jun 23 05:51:48 PM PDT 24
Peak memory 221136 kb
Host smart-752a9384-c4c7-4350-9a25-a77314ca75cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4111878175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.4111878175
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.284996434
Short name T22
Test name
Test status
Simulation time 42661738 ps
CPU time 1.03 seconds
Started Jun 23 05:51:34 PM PDT 24
Finished Jun 23 05:51:36 PM PDT 24
Peak memory 207268 kb
Host smart-e620e379-042c-43e4-900f-a154d8a22cff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284996434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.284996434
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3922465075
Short name T684
Test name
Test status
Simulation time 9210483447 ps
CPU time 21.17 seconds
Started Jun 23 05:51:27 PM PDT 24
Finished Jun 23 05:51:49 PM PDT 24
Peak memory 220424 kb
Host smart-c8352815-788d-4921-84ea-b3efb8efef29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922465075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3922465075
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2611126894
Short name T605
Test name
Test status
Simulation time 26789828 ps
CPU time 0.74 seconds
Started Jun 23 05:51:24 PM PDT 24
Finished Jun 23 05:51:25 PM PDT 24
Peak memory 205780 kb
Host smart-8dfc1f86-077b-4c46-b323-60f1ced6dc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611126894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2611126894
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.503385115
Short name T871
Test name
Test status
Simulation time 65034280 ps
CPU time 1.7 seconds
Started Jun 23 05:51:24 PM PDT 24
Finished Jun 23 05:51:26 PM PDT 24
Peak memory 216476 kb
Host smart-2c15245f-da87-4f7c-99ee-29115f044fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503385115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.503385115
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3260128251
Short name T668
Test name
Test status
Simulation time 332838702 ps
CPU time 0.83 seconds
Started Jun 23 05:51:27 PM PDT 24
Finished Jun 23 05:51:28 PM PDT 24
Peak memory 206072 kb
Host smart-505cad4a-c320-4a75-95e2-6fdd31f38947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260128251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3260128251
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3093614312
Short name T642
Test name
Test status
Simulation time 899590044 ps
CPU time 5.18 seconds
Started Jun 23 05:51:27 PM PDT 24
Finished Jun 23 05:51:33 PM PDT 24
Peak memory 224704 kb
Host smart-5d3ab188-dc05-4372-a0de-57974393fec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093614312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3093614312
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2851386758
Short name T337
Test name
Test status
Simulation time 13710290 ps
CPU time 0.7 seconds
Started Jun 23 05:51:32 PM PDT 24
Finished Jun 23 05:51:34 PM PDT 24
Peak memory 205552 kb
Host smart-0ff66892-936e-485a-92c6-b6d5482e453b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851386758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2851386758
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2327299095
Short name T555
Test name
Test status
Simulation time 79354478 ps
CPU time 2.21 seconds
Started Jun 23 05:51:38 PM PDT 24
Finished Jun 23 05:51:41 PM PDT 24
Peak memory 224632 kb
Host smart-69b918d7-4643-4fcc-a979-cb28d758e7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327299095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2327299095
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.407268796
Short name T648
Test name
Test status
Simulation time 14515005 ps
CPU time 0.78 seconds
Started Jun 23 05:51:37 PM PDT 24
Finished Jun 23 05:51:38 PM PDT 24
Peak memory 206756 kb
Host smart-64a84070-d098-44bd-9ec4-32b1a5b10e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407268796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.407268796
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2101543914
Short name T933
Test name
Test status
Simulation time 251593284 ps
CPU time 0.8 seconds
Started Jun 23 05:51:36 PM PDT 24
Finished Jun 23 05:51:37 PM PDT 24
Peak memory 215936 kb
Host smart-f63c57c6-6c5d-4fea-a91a-815cd1a90413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101543914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2101543914
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1609007898
Short name T46
Test name
Test status
Simulation time 5397547493 ps
CPU time 71.33 seconds
Started Jun 23 05:51:33 PM PDT 24
Finished Jun 23 05:52:44 PM PDT 24
Peak memory 249392 kb
Host smart-a17ad24a-9f2f-4190-984c-7d5c5474d3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609007898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1609007898
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1271790408
Short name T330
Test name
Test status
Simulation time 5992962994 ps
CPU time 31.08 seconds
Started Jun 23 05:51:39 PM PDT 24
Finished Jun 23 05:52:10 PM PDT 24
Peak memory 239936 kb
Host smart-afc76cea-dc42-42b3-b8fc-229151dc3fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271790408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1271790408
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1029877466
Short name T304
Test name
Test status
Simulation time 4660407027 ps
CPU time 51.51 seconds
Started Jun 23 05:51:44 PM PDT 24
Finished Jun 23 05:52:36 PM PDT 24
Peak memory 237480 kb
Host smart-5e2ec0f4-4795-4c42-a777-c1c2215d2c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029877466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1029877466
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3916384132
Short name T186
Test name
Test status
Simulation time 571014467 ps
CPU time 8.27 seconds
Started Jun 23 05:51:33 PM PDT 24
Finished Jun 23 05:51:41 PM PDT 24
Peak memory 219748 kb
Host smart-ac0d2d05-abe8-44b3-8d0b-9cf184dfd8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916384132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3916384132
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3446495066
Short name T775
Test name
Test status
Simulation time 287670297 ps
CPU time 2.68 seconds
Started Jun 23 05:51:45 PM PDT 24
Finished Jun 23 05:51:48 PM PDT 24
Peak memory 232564 kb
Host smart-df6db517-061b-4536-b3a0-f8ce9f104d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446495066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3446495066
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.361902495
Short name T751
Test name
Test status
Simulation time 25595584084 ps
CPU time 18.21 seconds
Started Jun 23 05:51:29 PM PDT 24
Finished Jun 23 05:51:48 PM PDT 24
Peak memory 232892 kb
Host smart-354613ec-56a2-4508-8326-2c1b4f82f785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361902495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.361902495
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2337812722
Short name T785
Test name
Test status
Simulation time 527473000 ps
CPU time 6.97 seconds
Started Jun 23 05:51:33 PM PDT 24
Finished Jun 23 05:51:40 PM PDT 24
Peak memory 232896 kb
Host smart-d05d842d-1e9d-4c4f-932a-b4054d8805cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337812722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2337812722
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.359270264
Short name T455
Test name
Test status
Simulation time 812431244 ps
CPU time 7.82 seconds
Started Jun 23 05:51:50 PM PDT 24
Finished Jun 23 05:51:58 PM PDT 24
Peak memory 222360 kb
Host smart-8cf52820-50f1-4184-9c14-285a3aaa0ca9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=359270264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.359270264
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3553649831
Short name T154
Test name
Test status
Simulation time 44232102573 ps
CPU time 27.15 seconds
Started Jun 23 05:51:34 PM PDT 24
Finished Jun 23 05:52:01 PM PDT 24
Peak memory 217948 kb
Host smart-827a0ca4-9b0b-49d8-9cc0-9e934e73b724
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553649831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3553649831
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.213649374
Short name T901
Test name
Test status
Simulation time 1720742978 ps
CPU time 17.33 seconds
Started Jun 23 05:51:43 PM PDT 24
Finished Jun 23 05:52:00 PM PDT 24
Peak memory 216476 kb
Host smart-4c6f510d-5f19-4d3e-9c89-47f8186cb513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213649374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.213649374
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.435260640
Short name T335
Test name
Test status
Simulation time 3023497623 ps
CPU time 4.57 seconds
Started Jun 23 05:51:31 PM PDT 24
Finished Jun 23 05:51:36 PM PDT 24
Peak memory 216548 kb
Host smart-7a60fbd2-d795-48b3-a113-0b152a5cddfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435260640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.435260640
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2562219612
Short name T591
Test name
Test status
Simulation time 187689052 ps
CPU time 1.25 seconds
Started Jun 23 05:51:31 PM PDT 24
Finished Jun 23 05:51:32 PM PDT 24
Peak memory 208100 kb
Host smart-7eb2f6e2-8267-4c8d-b2b0-fb1468f01ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562219612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2562219612
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.4163675659
Short name T351
Test name
Test status
Simulation time 92829849 ps
CPU time 0.8 seconds
Started Jun 23 05:51:30 PM PDT 24
Finished Jun 23 05:51:31 PM PDT 24
Peak memory 206004 kb
Host smart-803e2c4c-717a-46b1-b5bb-9c4337d520b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163675659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.4163675659
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1889616765
Short name T254
Test name
Test status
Simulation time 244424454 ps
CPU time 4.28 seconds
Started Jun 23 05:51:34 PM PDT 24
Finished Jun 23 05:51:39 PM PDT 24
Peak memory 224652 kb
Host smart-d5e3c44e-736b-48ff-a0f4-3c08a63a4f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889616765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1889616765
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1437390293
Short name T23
Test name
Test status
Simulation time 51465776 ps
CPU time 0.73 seconds
Started Jun 23 05:49:48 PM PDT 24
Finished Jun 23 05:49:50 PM PDT 24
Peak memory 206088 kb
Host smart-df41c4fc-b64b-4f62-b5aa-d44ec5a89903
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437390293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
437390293
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3904583405
Short name T457
Test name
Test status
Simulation time 150835465 ps
CPU time 2.68 seconds
Started Jun 23 05:49:51 PM PDT 24
Finished Jun 23 05:49:55 PM PDT 24
Peak memory 232796 kb
Host smart-4757fd44-109c-475b-9b0d-563cd5523f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904583405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3904583405
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.737705990
Short name T720
Test name
Test status
Simulation time 31322910 ps
CPU time 0.75 seconds
Started Jun 23 05:49:54 PM PDT 24
Finished Jun 23 05:49:56 PM PDT 24
Peak memory 205716 kb
Host smart-14f62114-762b-475d-9bef-4da836f52851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737705990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.737705990
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2047681829
Short name T712
Test name
Test status
Simulation time 7065575065 ps
CPU time 46.91 seconds
Started Jun 23 05:49:51 PM PDT 24
Finished Jun 23 05:50:39 PM PDT 24
Peak memory 235620 kb
Host smart-8f14120d-d0f4-4d04-878e-37fc7abd4039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047681829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2047681829
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1707558820
Short name T214
Test name
Test status
Simulation time 36911631103 ps
CPU time 131.06 seconds
Started Jun 23 05:49:53 PM PDT 24
Finished Jun 23 05:52:05 PM PDT 24
Peak memory 241252 kb
Host smart-82b13f05-c9e1-4d4f-9f3e-26c2a1edbaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707558820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1707558820
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.611097734
Short name T279
Test name
Test status
Simulation time 119883101835 ps
CPU time 306.27 seconds
Started Jun 23 05:49:52 PM PDT 24
Finished Jun 23 05:54:59 PM PDT 24
Peak memory 290156 kb
Host smart-52c68385-7850-4ea4-98d8-f24606d755c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611097734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
611097734
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3100112877
Short name T577
Test name
Test status
Simulation time 226634987 ps
CPU time 4.4 seconds
Started Jun 23 05:49:51 PM PDT 24
Finished Jun 23 05:49:56 PM PDT 24
Peak memory 224700 kb
Host smart-a3d8b23c-d4d0-4c8f-910c-9bdbfc4d2b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100112877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3100112877
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.935989025
Short name T518
Test name
Test status
Simulation time 124150561 ps
CPU time 4.54 seconds
Started Jun 23 05:49:50 PM PDT 24
Finished Jun 23 05:49:57 PM PDT 24
Peak memory 232820 kb
Host smart-12ace603-4691-41c6-a31d-c5e7d3f98047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935989025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.935989025
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3213398124
Short name T199
Test name
Test status
Simulation time 79815088 ps
CPU time 2.09 seconds
Started Jun 23 05:49:50 PM PDT 24
Finished Jun 23 05:49:54 PM PDT 24
Peak memory 224644 kb
Host smart-916087cd-ef01-41eb-8a78-1f99b9c5e85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213398124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3213398124
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.407125208
Short name T198
Test name
Test status
Simulation time 1140263692 ps
CPU time 3.27 seconds
Started Jun 23 05:49:50 PM PDT 24
Finished Jun 23 05:49:55 PM PDT 24
Peak memory 232816 kb
Host smart-593b5fc5-8828-4be9-b757-b8b4bfcdea2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407125208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
407125208
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2128148396
Short name T380
Test name
Test status
Simulation time 1979711057 ps
CPU time 6.22 seconds
Started Jun 23 05:49:52 PM PDT 24
Finished Jun 23 05:49:59 PM PDT 24
Peak memory 232892 kb
Host smart-f3a4820c-0480-42c9-b738-c3cdbce33e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128148396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2128148396
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3509685927
Short name T525
Test name
Test status
Simulation time 1401244993 ps
CPU time 17.97 seconds
Started Jun 23 05:49:49 PM PDT 24
Finished Jun 23 05:50:08 PM PDT 24
Peak memory 220132 kb
Host smart-e20d1b51-fd3d-4bb5-9c00-a837106a9406
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3509685927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3509685927
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1755980809
Short name T68
Test name
Test status
Simulation time 115156096 ps
CPU time 0.95 seconds
Started Jun 23 05:49:48 PM PDT 24
Finished Jun 23 05:49:50 PM PDT 24
Peak memory 235828 kb
Host smart-1d7783d4-44fa-473f-8461-ac34d9c61b59
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755980809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1755980809
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3190157666
Short name T687
Test name
Test status
Simulation time 32025336044 ps
CPU time 41.04 seconds
Started Jun 23 05:49:51 PM PDT 24
Finished Jun 23 05:50:33 PM PDT 24
Peak memory 215896 kb
Host smart-13717ea9-896a-4d4c-ac46-3c0bc7ec53a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190157666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3190157666
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3209411801
Short name T407
Test name
Test status
Simulation time 13051008320 ps
CPU time 9.98 seconds
Started Jun 23 05:49:50 PM PDT 24
Finished Jun 23 05:50:01 PM PDT 24
Peak memory 216548 kb
Host smart-dfefae25-8f6d-44dd-903e-27da5621e2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209411801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3209411801
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.411396355
Short name T164
Test name
Test status
Simulation time 38440759 ps
CPU time 1.41 seconds
Started Jun 23 05:49:47 PM PDT 24
Finished Jun 23 05:49:49 PM PDT 24
Peak memory 216372 kb
Host smart-cb6b23b7-1b26-4d7d-8375-2feeea1f5dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411396355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.411396355
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.4121470915
Short name T135
Test name
Test status
Simulation time 32591345 ps
CPU time 0.7 seconds
Started Jun 23 05:49:48 PM PDT 24
Finished Jun 23 05:49:50 PM PDT 24
Peak memory 205736 kb
Host smart-618a9b90-ca25-4d7f-b7bc-bd1c4ee5a3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121470915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.4121470915
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2194851029
Short name T581
Test name
Test status
Simulation time 4551333712 ps
CPU time 10.27 seconds
Started Jun 23 05:49:48 PM PDT 24
Finished Jun 23 05:50:00 PM PDT 24
Peak memory 224788 kb
Host smart-c03d8e3e-2807-4481-ae04-13154c047a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194851029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2194851029
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.681300750
Short name T63
Test name
Test status
Simulation time 40081095 ps
CPU time 0.74 seconds
Started Jun 23 05:51:38 PM PDT 24
Finished Jun 23 05:51:40 PM PDT 24
Peak memory 205536 kb
Host smart-452d6214-d554-4e91-a63e-37b8e569c77f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681300750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.681300750
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2626016574
Short name T180
Test name
Test status
Simulation time 206354532 ps
CPU time 2.43 seconds
Started Jun 23 05:51:49 PM PDT 24
Finished Jun 23 05:51:52 PM PDT 24
Peak memory 224604 kb
Host smart-89fb3c3d-be81-447f-b209-74d687648aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626016574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2626016574
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2707088232
Short name T431
Test name
Test status
Simulation time 94549993 ps
CPU time 0.74 seconds
Started Jun 23 05:51:33 PM PDT 24
Finished Jun 23 05:51:34 PM PDT 24
Peak memory 206048 kb
Host smart-0b7830a6-5514-4d7e-9264-961a4a0522a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707088232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2707088232
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2279874922
Short name T766
Test name
Test status
Simulation time 3443537415 ps
CPU time 15.09 seconds
Started Jun 23 05:51:34 PM PDT 24
Finished Jun 23 05:51:49 PM PDT 24
Peak memory 249412 kb
Host smart-d3c11791-0c37-4569-add9-a7ae314e3fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279874922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2279874922
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1256393440
Short name T781
Test name
Test status
Simulation time 17588239234 ps
CPU time 165.22 seconds
Started Jun 23 05:51:40 PM PDT 24
Finished Jun 23 05:54:26 PM PDT 24
Peak memory 249476 kb
Host smart-d5417286-a618-44a0-a209-82aa88542200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256393440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1256393440
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2287941020
Short name T421
Test name
Test status
Simulation time 1114339724 ps
CPU time 16.66 seconds
Started Jun 23 05:51:35 PM PDT 24
Finished Jun 23 05:51:52 PM PDT 24
Peak memory 224688 kb
Host smart-a8a91ae1-cbb7-4b66-b4a1-c0731f15d326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287941020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2287941020
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3011296285
Short name T699
Test name
Test status
Simulation time 1669365754 ps
CPU time 5.74 seconds
Started Jun 23 05:51:37 PM PDT 24
Finished Jun 23 05:51:44 PM PDT 24
Peak memory 224592 kb
Host smart-a3652e7c-68f8-4c82-8bd7-5de9dca7d6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011296285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3011296285
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2821115553
Short name T240
Test name
Test status
Simulation time 1861069517 ps
CPU time 15.18 seconds
Started Jun 23 05:51:34 PM PDT 24
Finished Jun 23 05:51:50 PM PDT 24
Peak memory 224576 kb
Host smart-a9ba2c78-3b7a-46d6-84ee-bd97374dd13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821115553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2821115553
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2426785831
Short name T551
Test name
Test status
Simulation time 7399997154 ps
CPU time 13.58 seconds
Started Jun 23 05:51:38 PM PDT 24
Finished Jun 23 05:51:52 PM PDT 24
Peak memory 240920 kb
Host smart-6bc5d77b-82f5-4aee-a680-010c4f82a61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426785831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2426785831
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.4169474196
Short name T567
Test name
Test status
Simulation time 1931937393 ps
CPU time 7.92 seconds
Started Jun 23 05:51:48 PM PDT 24
Finished Jun 23 05:51:57 PM PDT 24
Peak memory 232900 kb
Host smart-5a54a774-fa2e-48ab-862b-2b9091e4414b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169474196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4169474196
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2619352570
Short name T914
Test name
Test status
Simulation time 1985211724 ps
CPU time 8.41 seconds
Started Jun 23 05:51:38 PM PDT 24
Finished Jun 23 05:51:47 PM PDT 24
Peak memory 222732 kb
Host smart-4d6abc88-913e-48e1-a5e7-ed6ce4ac9af5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2619352570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2619352570
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1080578832
Short name T492
Test name
Test status
Simulation time 16951108506 ps
CPU time 213.59 seconds
Started Jun 23 05:51:46 PM PDT 24
Finished Jun 23 05:55:20 PM PDT 24
Peak memory 254960 kb
Host smart-0a678ecc-5576-4de0-a4e4-7bb6c2a1dac6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080578832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1080578832
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.861097391
Short name T700
Test name
Test status
Simulation time 7139058091 ps
CPU time 31.33 seconds
Started Jun 23 05:51:39 PM PDT 24
Finished Jun 23 05:52:11 PM PDT 24
Peak memory 216528 kb
Host smart-1d5921a8-cbe2-4ddc-b134-d2f78cd5ad08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861097391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.861097391
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3298068750
Short name T331
Test name
Test status
Simulation time 34329484 ps
CPU time 0.68 seconds
Started Jun 23 05:51:30 PM PDT 24
Finished Jun 23 05:51:31 PM PDT 24
Peak memory 205800 kb
Host smart-e4e3b433-4639-4acd-bda8-9d19801323aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298068750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3298068750
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1091319232
Short name T883
Test name
Test status
Simulation time 80384238 ps
CPU time 1.27 seconds
Started Jun 23 05:51:48 PM PDT 24
Finished Jun 23 05:51:50 PM PDT 24
Peak memory 216472 kb
Host smart-69ec72cf-1261-4235-8be4-af5714799a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091319232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1091319232
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3306528431
Short name T767
Test name
Test status
Simulation time 36751235 ps
CPU time 0.91 seconds
Started Jun 23 05:51:41 PM PDT 24
Finished Jun 23 05:51:42 PM PDT 24
Peak memory 207128 kb
Host smart-424e20df-6194-40d8-9c60-b5b1d515c686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306528431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3306528431
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1769071268
Short name T408
Test name
Test status
Simulation time 212784808 ps
CPU time 2.86 seconds
Started Jun 23 05:51:41 PM PDT 24
Finished Jun 23 05:51:44 PM PDT 24
Peak memory 232796 kb
Host smart-e99ebdaf-6a54-41f0-8f86-08d709147ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769071268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1769071268
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.840492416
Short name T541
Test name
Test status
Simulation time 114400300 ps
CPU time 0.74 seconds
Started Jun 23 05:51:46 PM PDT 24
Finished Jun 23 05:51:47 PM PDT 24
Peak memory 205504 kb
Host smart-e01c56c6-9414-4e3a-881d-c0d9bd7ceb1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840492416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.840492416
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2195058947
Short name T248
Test name
Test status
Simulation time 648114739 ps
CPU time 4.2 seconds
Started Jun 23 05:51:39 PM PDT 24
Finished Jun 23 05:51:44 PM PDT 24
Peak memory 232888 kb
Host smart-9e738c71-6e6a-4a54-b7bc-d27071306a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195058947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2195058947
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.4197324325
Short name T508
Test name
Test status
Simulation time 19739613 ps
CPU time 0.79 seconds
Started Jun 23 05:51:40 PM PDT 24
Finished Jun 23 05:51:42 PM PDT 24
Peak memory 205724 kb
Host smart-59d5dd96-23ed-4162-8ea4-0de0660cc015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197324325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.4197324325
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2643014566
Short name T845
Test name
Test status
Simulation time 7138509033 ps
CPU time 25.15 seconds
Started Jun 23 05:51:40 PM PDT 24
Finished Jun 23 05:52:05 PM PDT 24
Peak memory 249404 kb
Host smart-991e259a-0202-4fbc-8729-51ecb64781ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643014566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2643014566
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1441625793
Short name T311
Test name
Test status
Simulation time 12356757467 ps
CPU time 36.75 seconds
Started Jun 23 05:51:42 PM PDT 24
Finished Jun 23 05:52:19 PM PDT 24
Peak memory 240872 kb
Host smart-8f2fc48c-7a02-4e8e-95a8-9abe14b25ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441625793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1441625793
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1511450576
Short name T580
Test name
Test status
Simulation time 3946894661 ps
CPU time 17.55 seconds
Started Jun 23 05:51:36 PM PDT 24
Finished Jun 23 05:51:54 PM PDT 24
Peak memory 241164 kb
Host smart-dcb201b2-38b1-47b2-bf31-ab3dd37f7b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511450576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1511450576
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2690557703
Short name T695
Test name
Test status
Simulation time 329061887 ps
CPU time 2.15 seconds
Started Jun 23 05:51:38 PM PDT 24
Finished Jun 23 05:51:40 PM PDT 24
Peak memory 223204 kb
Host smart-ccc0fa6e-f104-4abe-ae81-5875e3735c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690557703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2690557703
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1405775096
Short name T95
Test name
Test status
Simulation time 1392460113 ps
CPU time 9.44 seconds
Started Jun 23 05:51:40 PM PDT 24
Finished Jun 23 05:51:50 PM PDT 24
Peak memory 239412 kb
Host smart-712a96cc-2e50-4b85-bb04-8bf822200353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405775096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1405775096
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.4142326067
Short name T203
Test name
Test status
Simulation time 8432779438 ps
CPU time 8.03 seconds
Started Jun 23 05:51:37 PM PDT 24
Finished Jun 23 05:51:46 PM PDT 24
Peak memory 224748 kb
Host smart-1b2cbd4f-0f0b-44f7-8047-d2392f2cf79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142326067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.4142326067
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1686181696
Short name T216
Test name
Test status
Simulation time 1930654316 ps
CPU time 10.99 seconds
Started Jun 23 05:51:37 PM PDT 24
Finished Jun 23 05:51:49 PM PDT 24
Peak memory 241064 kb
Host smart-55d89e27-19b4-4ea4-8f8b-2564d6983132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686181696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1686181696
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3450330366
Short name T36
Test name
Test status
Simulation time 257716225 ps
CPU time 5.72 seconds
Started Jun 23 05:51:38 PM PDT 24
Finished Jun 23 05:51:44 PM PDT 24
Peak memory 223308 kb
Host smart-7300b67b-388f-4154-96fb-716c6cd3ecb5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3450330366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3450330366
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.270376036
Short name T152
Test name
Test status
Simulation time 155882755 ps
CPU time 0.89 seconds
Started Jun 23 05:51:40 PM PDT 24
Finished Jun 23 05:51:41 PM PDT 24
Peak memory 205672 kb
Host smart-f27ce6a1-012e-49fc-aa49-a31bd85ebb23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270376036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.270376036
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2981896676
Short name T464
Test name
Test status
Simulation time 4218516552 ps
CPU time 5.47 seconds
Started Jun 23 05:51:49 PM PDT 24
Finished Jun 23 05:51:55 PM PDT 24
Peak memory 216544 kb
Host smart-665a83e8-c89d-4a83-a362-a6af9bd13cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981896676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2981896676
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.920485047
Short name T344
Test name
Test status
Simulation time 4597853332 ps
CPU time 13.55 seconds
Started Jun 23 05:51:43 PM PDT 24
Finished Jun 23 05:51:57 PM PDT 24
Peak memory 216524 kb
Host smart-9cd95845-ad83-434f-b70f-80a58f32d805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920485047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.920485047
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3781133079
Short name T372
Test name
Test status
Simulation time 308731699 ps
CPU time 1.72 seconds
Started Jun 23 05:51:41 PM PDT 24
Finished Jun 23 05:51:43 PM PDT 24
Peak memory 216424 kb
Host smart-c5548855-eea2-4040-a959-5b6a041e9fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781133079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3781133079
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.846677321
Short name T584
Test name
Test status
Simulation time 84591795 ps
CPU time 0.85 seconds
Started Jun 23 05:51:47 PM PDT 24
Finished Jun 23 05:51:49 PM PDT 24
Peak memory 206116 kb
Host smart-db3088a6-230d-4fe7-97eb-da062697038b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846677321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.846677321
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2934338514
Short name T389
Test name
Test status
Simulation time 2029417354 ps
CPU time 3.64 seconds
Started Jun 23 05:51:39 PM PDT 24
Finished Jun 23 05:51:43 PM PDT 24
Peak memory 224556 kb
Host smart-63241cd6-4c9b-4ba4-a271-575b06526273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934338514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2934338514
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2759144227
Short name T412
Test name
Test status
Simulation time 34617990 ps
CPU time 0.72 seconds
Started Jun 23 05:51:43 PM PDT 24
Finished Jun 23 05:51:45 PM PDT 24
Peak memory 204900 kb
Host smart-66ebe773-65d7-4006-85de-53f49ebb8548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759144227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2759144227
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1631925263
Short name T88
Test name
Test status
Simulation time 51209370 ps
CPU time 2.96 seconds
Started Jun 23 05:51:40 PM PDT 24
Finished Jun 23 05:51:44 PM PDT 24
Peak memory 232848 kb
Host smart-6af18c06-54bb-4adc-9261-4a9c953026ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631925263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1631925263
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1084674378
Short name T374
Test name
Test status
Simulation time 66756548 ps
CPU time 0.8 seconds
Started Jun 23 05:51:41 PM PDT 24
Finished Jun 23 05:51:42 PM PDT 24
Peak memory 206736 kb
Host smart-d44ed700-70cf-4adb-9fac-8e447c3d9d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084674378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1084674378
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2140912892
Short name T784
Test name
Test status
Simulation time 41231138422 ps
CPU time 146.24 seconds
Started Jun 23 05:51:39 PM PDT 24
Finished Jun 23 05:54:06 PM PDT 24
Peak memory 249412 kb
Host smart-5691e688-35c8-4481-a1f4-89a5e4f6629f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140912892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2140912892
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.49710371
Short name T793
Test name
Test status
Simulation time 213774550563 ps
CPU time 387.49 seconds
Started Jun 23 05:51:40 PM PDT 24
Finished Jun 23 05:58:08 PM PDT 24
Peak memory 265836 kb
Host smart-d913acac-ce46-408a-8beb-154cd2b8eab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49710371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.49710371
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.338535118
Short name T429
Test name
Test status
Simulation time 52783640893 ps
CPU time 140.49 seconds
Started Jun 23 05:51:46 PM PDT 24
Finished Jun 23 05:54:07 PM PDT 24
Peak memory 249460 kb
Host smart-edadb504-e324-4b5e-bc5a-346b234d609f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338535118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.338535118
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2321363403
Short name T938
Test name
Test status
Simulation time 556954248 ps
CPU time 5.03 seconds
Started Jun 23 05:51:41 PM PDT 24
Finished Jun 23 05:51:47 PM PDT 24
Peak memory 235152 kb
Host smart-e6ee5fec-5fb9-412d-bcc5-c78bbea590ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321363403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2321363403
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.37204134
Short name T189
Test name
Test status
Simulation time 420366358 ps
CPU time 7.02 seconds
Started Jun 23 05:51:43 PM PDT 24
Finished Jun 23 05:51:51 PM PDT 24
Peak memory 232876 kb
Host smart-33fcbc15-c94a-4aef-97f1-e9da735b3494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37204134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.37204134
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.4213373677
Short name T721
Test name
Test status
Simulation time 3372096002 ps
CPU time 9.77 seconds
Started Jun 23 05:51:43 PM PDT 24
Finished Jun 23 05:51:54 PM PDT 24
Peak memory 232852 kb
Host smart-a2d4022a-d007-4c62-8db6-9eb2b3167423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213373677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.4213373677
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3391638558
Short name T601
Test name
Test status
Simulation time 444256546 ps
CPU time 3.21 seconds
Started Jun 23 05:51:47 PM PDT 24
Finished Jun 23 05:51:50 PM PDT 24
Peak memory 232848 kb
Host smart-048bee04-12a4-4237-8ff2-bab05df71476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391638558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3391638558
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2473836121
Short name T578
Test name
Test status
Simulation time 120560410 ps
CPU time 2.44 seconds
Started Jun 23 05:51:46 PM PDT 24
Finished Jun 23 05:51:49 PM PDT 24
Peak memory 232876 kb
Host smart-be26f58a-fc1b-4276-8210-3388323610f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473836121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2473836121
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.898959720
Short name T693
Test name
Test status
Simulation time 873977916 ps
CPU time 13.05 seconds
Started Jun 23 05:51:45 PM PDT 24
Finished Jun 23 05:51:59 PM PDT 24
Peak memory 220316 kb
Host smart-9a88c05e-fc13-4ec7-b679-8f842b6b9f89
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=898959720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.898959720
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.696810062
Short name T75
Test name
Test status
Simulation time 32969326 ps
CPU time 0.72 seconds
Started Jun 23 05:51:40 PM PDT 24
Finished Jun 23 05:51:41 PM PDT 24
Peak memory 205812 kb
Host smart-feb54db8-b389-4e73-8e8f-3e8ab0506f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696810062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.696810062
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2687939180
Short name T133
Test name
Test status
Simulation time 1621168855 ps
CPU time 5.6 seconds
Started Jun 23 05:51:43 PM PDT 24
Finished Jun 23 05:51:49 PM PDT 24
Peak memory 216352 kb
Host smart-391819e8-855b-4033-983c-fc49184b3e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687939180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2687939180
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3534761698
Short name T621
Test name
Test status
Simulation time 268302396 ps
CPU time 1.31 seconds
Started Jun 23 05:51:43 PM PDT 24
Finished Jun 23 05:51:45 PM PDT 24
Peak memory 207988 kb
Host smart-80accc29-25dc-4432-af71-14cb4f11b70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534761698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3534761698
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1892368718
Short name T557
Test name
Test status
Simulation time 268555672 ps
CPU time 0.87 seconds
Started Jun 23 05:51:49 PM PDT 24
Finished Jun 23 05:51:50 PM PDT 24
Peak memory 206112 kb
Host smart-9b5a13fc-6e9b-4607-818a-ad3584c1fb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892368718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1892368718
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3313642613
Short name T114
Test name
Test status
Simulation time 79279411488 ps
CPU time 17.33 seconds
Started Jun 23 05:51:41 PM PDT 24
Finished Jun 23 05:51:59 PM PDT 24
Peak memory 240924 kb
Host smart-0b3e974e-dd23-4aab-9ca5-8f6de8d1e2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313642613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3313642613
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1844311023
Short name T748
Test name
Test status
Simulation time 14998091 ps
CPU time 0.75 seconds
Started Jun 23 05:51:47 PM PDT 24
Finished Jun 23 05:51:48 PM PDT 24
Peak memory 205824 kb
Host smart-e75e67ad-10c1-40ac-88bf-e94a53c8c422
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844311023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1844311023
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2145653777
Short name T465
Test name
Test status
Simulation time 160504692 ps
CPU time 2.54 seconds
Started Jun 23 05:51:47 PM PDT 24
Finished Jun 23 05:51:51 PM PDT 24
Peak memory 232544 kb
Host smart-e421d509-322b-4445-bbab-831f05b98b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145653777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2145653777
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.622781001
Short name T387
Test name
Test status
Simulation time 57348577 ps
CPU time 0.75 seconds
Started Jun 23 05:51:41 PM PDT 24
Finished Jun 23 05:51:42 PM PDT 24
Peak memory 205644 kb
Host smart-c48b0f48-cd76-4860-b2c8-4f3ce902a482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622781001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.622781001
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2232065797
Short name T549
Test name
Test status
Simulation time 29878252496 ps
CPU time 124.89 seconds
Started Jun 23 05:51:47 PM PDT 24
Finished Jun 23 05:53:52 PM PDT 24
Peak memory 249464 kb
Host smart-20035dc7-7cf3-4b5a-8b35-ee4896d58330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232065797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2232065797
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.754552668
Short name T899
Test name
Test status
Simulation time 30572623661 ps
CPU time 234.19 seconds
Started Jun 23 05:51:53 PM PDT 24
Finished Jun 23 05:55:47 PM PDT 24
Peak memory 250732 kb
Host smart-a7485a4c-01af-4630-9cd5-f71ee445d2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754552668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.754552668
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2887487141
Short name T685
Test name
Test status
Simulation time 30773454307 ps
CPU time 35.36 seconds
Started Jun 23 05:51:46 PM PDT 24
Finished Jun 23 05:52:22 PM PDT 24
Peak memory 249420 kb
Host smart-d8ce0e07-13c5-43cc-8389-cd02169470a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887487141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2887487141
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1073035274
Short name T723
Test name
Test status
Simulation time 191560418 ps
CPU time 2.6 seconds
Started Jun 23 05:51:53 PM PDT 24
Finished Jun 23 05:51:56 PM PDT 24
Peak memory 224244 kb
Host smart-4a5825a8-edf9-4db8-a7c5-1cce3e2c67c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073035274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1073035274
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.4051841931
Short name T472
Test name
Test status
Simulation time 4260228305 ps
CPU time 13.92 seconds
Started Jun 23 05:51:48 PM PDT 24
Finished Jun 23 05:52:03 PM PDT 24
Peak memory 232996 kb
Host smart-a82c7a5d-29fa-4fe5-919c-1962fe1edf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051841931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.4051841931
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.454669003
Short name T319
Test name
Test status
Simulation time 10234802058 ps
CPU time 35.97 seconds
Started Jun 23 05:51:53 PM PDT 24
Finished Jun 23 05:52:30 PM PDT 24
Peak memory 237796 kb
Host smart-c02bb223-c6fd-4b3e-8fbd-e5ff2c6f37a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454669003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.454669003
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2846279794
Short name T267
Test name
Test status
Simulation time 10100462766 ps
CPU time 12.5 seconds
Started Jun 23 05:51:41 PM PDT 24
Finished Jun 23 05:51:54 PM PDT 24
Peak memory 232992 kb
Host smart-fe839015-ebeb-48d2-86cd-cc3bfcacdad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846279794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2846279794
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3093767465
Short name T856
Test name
Test status
Simulation time 4172283404 ps
CPU time 8.38 seconds
Started Jun 23 05:51:43 PM PDT 24
Finished Jun 23 05:51:52 PM PDT 24
Peak memory 232880 kb
Host smart-131caca8-0780-43c5-97da-9804e3f4e584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093767465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3093767465
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1631349967
Short name T735
Test name
Test status
Simulation time 2697598386 ps
CPU time 9.27 seconds
Started Jun 23 05:51:45 PM PDT 24
Finished Jun 23 05:51:55 PM PDT 24
Peak memory 219044 kb
Host smart-67419faa-7470-451b-8f55-d583e8f4f360
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1631349967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1631349967
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3660040578
Short name T807
Test name
Test status
Simulation time 7873671551 ps
CPU time 41.27 seconds
Started Jun 23 05:51:42 PM PDT 24
Finished Jun 23 05:52:24 PM PDT 24
Peak memory 216424 kb
Host smart-6a85bbc1-8f91-4290-9f7e-c4eb1152e91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660040578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3660040578
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2641285457
Short name T576
Test name
Test status
Simulation time 980487270 ps
CPU time 4.95 seconds
Started Jun 23 05:51:46 PM PDT 24
Finished Jun 23 05:51:51 PM PDT 24
Peak memory 216364 kb
Host smart-788c6e69-ede2-41d8-88f1-11c23a6f3401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641285457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2641285457
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2346184009
Short name T414
Test name
Test status
Simulation time 55254976 ps
CPU time 0.78 seconds
Started Jun 23 05:51:44 PM PDT 24
Finished Jun 23 05:51:45 PM PDT 24
Peak memory 206140 kb
Host smart-0084d839-2691-4888-b6a0-d9143c8e0e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346184009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2346184009
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3034540119
Short name T348
Test name
Test status
Simulation time 23181428 ps
CPU time 0.82 seconds
Started Jun 23 05:51:43 PM PDT 24
Finished Jun 23 05:51:44 PM PDT 24
Peak memory 206020 kb
Host smart-599779d2-7445-4f56-96be-f457dbb65e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034540119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3034540119
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.750086433
Short name T439
Test name
Test status
Simulation time 930823802 ps
CPU time 5.19 seconds
Started Jun 23 05:51:47 PM PDT 24
Finished Jun 23 05:51:53 PM PDT 24
Peak memory 232904 kb
Host smart-349fbb60-9934-4976-9b0e-92e6954a3293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750086433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.750086433
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3093708542
Short name T497
Test name
Test status
Simulation time 15196330 ps
CPU time 0.71 seconds
Started Jun 23 05:51:47 PM PDT 24
Finished Jun 23 05:51:48 PM PDT 24
Peak memory 204952 kb
Host smart-7cc4ed2a-5fdf-4996-bc78-098a8a877d62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093708542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3093708542
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2929770634
Short name T438
Test name
Test status
Simulation time 196055932 ps
CPU time 2.69 seconds
Started Jun 23 05:51:49 PM PDT 24
Finished Jun 23 05:51:52 PM PDT 24
Peak memory 224660 kb
Host smart-55c417f4-7aa3-4a72-b0e6-fc8b4ca4320b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929770634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2929770634
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3299706666
Short name T502
Test name
Test status
Simulation time 54745478 ps
CPU time 0.74 seconds
Started Jun 23 05:51:46 PM PDT 24
Finished Jun 23 05:51:48 PM PDT 24
Peak memory 205708 kb
Host smart-3f270afe-2c28-4838-8f75-16b0d25888d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299706666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3299706666
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3091087081
Short name T188
Test name
Test status
Simulation time 30937006647 ps
CPU time 54.63 seconds
Started Jun 23 05:51:48 PM PDT 24
Finished Jun 23 05:52:44 PM PDT 24
Peak memory 251540 kb
Host smart-f355fd91-7294-48e2-9189-55da33a1c31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091087081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3091087081
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1630159840
Short name T842
Test name
Test status
Simulation time 171378855 ps
CPU time 2.39 seconds
Started Jun 23 05:51:46 PM PDT 24
Finished Jun 23 05:51:49 PM PDT 24
Peak memory 217748 kb
Host smart-756f4d21-074e-4db9-9440-59ba534c9ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630159840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1630159840
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2983200473
Short name T298
Test name
Test status
Simulation time 5814392580 ps
CPU time 61.55 seconds
Started Jun 23 05:51:46 PM PDT 24
Finished Jun 23 05:52:48 PM PDT 24
Peak memory 233068 kb
Host smart-9eca84ed-45ae-4b8e-ba1b-29c60817da45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983200473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2983200473
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1385380795
Short name T303
Test name
Test status
Simulation time 4489124967 ps
CPU time 39.42 seconds
Started Jun 23 05:51:46 PM PDT 24
Finished Jun 23 05:52:26 PM PDT 24
Peak memory 232960 kb
Host smart-46ecb683-eca7-4991-8936-7e349a9bc420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385380795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1385380795
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.313398170
Short name T770
Test name
Test status
Simulation time 2649226450 ps
CPU time 17.74 seconds
Started Jun 23 05:51:47 PM PDT 24
Finished Jun 23 05:52:06 PM PDT 24
Peak memory 232960 kb
Host smart-d082975c-0c87-4e2f-ba56-fd1650ec8303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313398170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.313398170
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.4170463265
Short name T517
Test name
Test status
Simulation time 332354025 ps
CPU time 11.19 seconds
Started Jun 23 05:51:50 PM PDT 24
Finished Jun 23 05:52:02 PM PDT 24
Peak memory 240956 kb
Host smart-2bd7562c-661c-48b1-b3d5-b835c625fd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170463265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.4170463265
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.4047936991
Short name T290
Test name
Test status
Simulation time 2608714192 ps
CPU time 11.23 seconds
Started Jun 23 05:51:57 PM PDT 24
Finished Jun 23 05:52:09 PM PDT 24
Peak memory 241104 kb
Host smart-a982225e-e83e-4eb3-8a0e-761cdf2e2607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047936991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.4047936991
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1508012473
Short name T237
Test name
Test status
Simulation time 4561326354 ps
CPU time 7.8 seconds
Started Jun 23 05:51:53 PM PDT 24
Finished Jun 23 05:52:02 PM PDT 24
Peak memory 232708 kb
Host smart-38ed2884-00f9-4ab6-8fc7-c548676a8e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508012473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1508012473
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3339400037
Short name T377
Test name
Test status
Simulation time 2631054728 ps
CPU time 11.49 seconds
Started Jun 23 05:51:45 PM PDT 24
Finished Jun 23 05:51:57 PM PDT 24
Peak memory 220520 kb
Host smart-11b8fa07-8d29-4312-a515-66d24947e2f5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3339400037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3339400037
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3716155048
Short name T179
Test name
Test status
Simulation time 20926969350 ps
CPU time 91.64 seconds
Started Jun 23 05:51:48 PM PDT 24
Finished Jun 23 05:53:20 PM PDT 24
Peak memory 237812 kb
Host smart-163a9d3d-49bf-4b14-b290-136a0e49a615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716155048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3716155048
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.990922493
Short name T754
Test name
Test status
Simulation time 8107707332 ps
CPU time 16.72 seconds
Started Jun 23 05:51:48 PM PDT 24
Finished Jun 23 05:52:06 PM PDT 24
Peak memory 215736 kb
Host smart-536ac065-104a-4b71-82e3-9c2ef3b253a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990922493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.990922493
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3055227178
Short name T897
Test name
Test status
Simulation time 3128505909 ps
CPU time 9.11 seconds
Started Jun 23 05:51:46 PM PDT 24
Finished Jun 23 05:51:55 PM PDT 24
Peak memory 216524 kb
Host smart-35ac6ce7-697e-4af7-b4c9-8d55373152a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055227178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3055227178
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3598566163
Short name T355
Test name
Test status
Simulation time 123292420 ps
CPU time 4.95 seconds
Started Jun 23 05:51:48 PM PDT 24
Finished Jun 23 05:51:54 PM PDT 24
Peak memory 216452 kb
Host smart-22dc5daf-7466-41e7-9025-b263aa5e9063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598566163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3598566163
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2690815401
Short name T954
Test name
Test status
Simulation time 260813614 ps
CPU time 0.9 seconds
Started Jun 23 05:51:46 PM PDT 24
Finished Jun 23 05:51:47 PM PDT 24
Peak memory 206072 kb
Host smart-f51920a5-1cc0-4a82-974e-75de83505217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690815401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2690815401
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.4242110076
Short name T606
Test name
Test status
Simulation time 81211223 ps
CPU time 2.65 seconds
Started Jun 23 05:51:53 PM PDT 24
Finished Jun 23 05:51:55 PM PDT 24
Peak memory 224384 kb
Host smart-a4dec45f-2e33-4d80-bd64-43f15c7aa58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242110076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.4242110076
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3191986922
Short name T163
Test name
Test status
Simulation time 37111533 ps
CPU time 0.69 seconds
Started Jun 23 05:51:48 PM PDT 24
Finished Jun 23 05:51:50 PM PDT 24
Peak memory 204944 kb
Host smart-46a94804-a242-406e-a6c5-d365b1466133
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191986922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3191986922
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1862943860
Short name T241
Test name
Test status
Simulation time 420337098 ps
CPU time 4.98 seconds
Started Jun 23 05:51:49 PM PDT 24
Finished Jun 23 05:51:55 PM PDT 24
Peak memory 232888 kb
Host smart-53f0db33-c43f-422b-90a3-8529893e2b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862943860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1862943860
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3367561089
Short name T600
Test name
Test status
Simulation time 27122740 ps
CPU time 0.76 seconds
Started Jun 23 05:51:47 PM PDT 24
Finished Jun 23 05:51:49 PM PDT 24
Peak memory 206756 kb
Host smart-0d22d5de-e360-41cd-9071-f5a907e6a2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367561089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3367561089
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.840168170
Short name T936
Test name
Test status
Simulation time 9175562363 ps
CPU time 34.17 seconds
Started Jun 23 05:51:57 PM PDT 24
Finished Jun 23 05:52:31 PM PDT 24
Peak memory 251608 kb
Host smart-aead9954-b66b-4a7a-a470-b1996ca54ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840168170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.840168170
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3145532585
Short name T277
Test name
Test status
Simulation time 37566105699 ps
CPU time 346.02 seconds
Started Jun 23 05:51:51 PM PDT 24
Finished Jun 23 05:57:38 PM PDT 24
Peak memory 253836 kb
Host smart-ffda6f4f-7ade-4024-b772-d2f715300b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145532585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3145532585
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.4224829983
Short name T313
Test name
Test status
Simulation time 5024978107 ps
CPU time 18.85 seconds
Started Jun 23 05:51:48 PM PDT 24
Finished Jun 23 05:52:08 PM PDT 24
Peak memory 217856 kb
Host smart-e333e42b-0661-497f-8577-8f9b629073ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224829983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.4224829983
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1323631167
Short name T836
Test name
Test status
Simulation time 169394316 ps
CPU time 6.17 seconds
Started Jun 23 05:51:48 PM PDT 24
Finished Jun 23 05:51:55 PM PDT 24
Peak memory 237924 kb
Host smart-fc45ec3b-006b-40c5-ad42-cc972fe7c6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323631167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1323631167
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3400189312
Short name T853
Test name
Test status
Simulation time 8428740422 ps
CPU time 15.92 seconds
Started Jun 23 05:51:55 PM PDT 24
Finished Jun 23 05:52:11 PM PDT 24
Peak memory 224716 kb
Host smart-0cb36c10-af7f-4eb5-ab5b-7b68a5836c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400189312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3400189312
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.4210305434
Short name T245
Test name
Test status
Simulation time 13862640812 ps
CPU time 24.2 seconds
Started Jun 23 05:51:46 PM PDT 24
Finished Jun 23 05:52:11 PM PDT 24
Peak memory 232884 kb
Host smart-e5030e4a-8134-4749-bf07-b0ea561f3c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210305434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.4210305434
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3064307526
Short name T463
Test name
Test status
Simulation time 74517327523 ps
CPU time 22.15 seconds
Started Jun 23 05:51:50 PM PDT 24
Finished Jun 23 05:52:13 PM PDT 24
Peak memory 224800 kb
Host smart-71c1eaf3-d2fe-4225-b271-54b2a8717140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064307526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3064307526
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1408614368
Short name T204
Test name
Test status
Simulation time 7178402614 ps
CPU time 25.68 seconds
Started Jun 23 05:51:51 PM PDT 24
Finished Jun 23 05:52:17 PM PDT 24
Peak memory 238560 kb
Host smart-755ed90c-6af4-4759-b9a1-ddc826f6b3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408614368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1408614368
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1030287898
Short name T731
Test name
Test status
Simulation time 329014168 ps
CPU time 3.98 seconds
Started Jun 23 05:51:53 PM PDT 24
Finished Jun 23 05:51:57 PM PDT 24
Peak memory 219536 kb
Host smart-c7034b1f-0057-48b8-b0fd-0624852477ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1030287898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1030287898
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.672943405
Short name T18
Test name
Test status
Simulation time 24009025769 ps
CPU time 104 seconds
Started Jun 23 05:51:51 PM PDT 24
Finished Jun 23 05:53:36 PM PDT 24
Peak memory 255764 kb
Host smart-4aafcdc7-680e-4a3e-85da-ae5765ee0d07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672943405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.672943405
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3623019546
Short name T866
Test name
Test status
Simulation time 528177524 ps
CPU time 6.27 seconds
Started Jun 23 05:51:44 PM PDT 24
Finished Jun 23 05:51:51 PM PDT 24
Peak memory 216592 kb
Host smart-03384d06-0e0a-43d4-844d-bddd2aff146a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623019546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3623019546
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.153837723
Short name T596
Test name
Test status
Simulation time 3906789045 ps
CPU time 3.18 seconds
Started Jun 23 05:51:47 PM PDT 24
Finished Jun 23 05:51:51 PM PDT 24
Peak memory 216524 kb
Host smart-58c2df90-2c80-4b4c-b545-862f11d375dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153837723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.153837723
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2492308001
Short name T694
Test name
Test status
Simulation time 129489778 ps
CPU time 3.34 seconds
Started Jun 23 05:51:58 PM PDT 24
Finished Jun 23 05:52:02 PM PDT 24
Peak memory 216424 kb
Host smart-143f2d48-05e0-4b5f-8123-a3c4300d5da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492308001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2492308001
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2251347533
Short name T833
Test name
Test status
Simulation time 239676393 ps
CPU time 0.85 seconds
Started Jun 23 05:51:50 PM PDT 24
Finished Jun 23 05:51:52 PM PDT 24
Peak memory 206080 kb
Host smart-7ed2a679-1b09-4f7f-8d2d-1c10fc1d8f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251347533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2251347533
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1574559836
Short name T539
Test name
Test status
Simulation time 8327132484 ps
CPU time 8.59 seconds
Started Jun 23 05:51:52 PM PDT 24
Finished Jun 23 05:52:01 PM PDT 24
Peak memory 224780 kb
Host smart-d8e09e28-aa75-4332-97bd-ddd48a9cd002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574559836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1574559836
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2278583867
Short name T441
Test name
Test status
Simulation time 156556084 ps
CPU time 0.81 seconds
Started Jun 23 05:52:09 PM PDT 24
Finished Jun 23 05:52:11 PM PDT 24
Peak memory 206060 kb
Host smart-b0ba1432-a490-4ae2-ae86-4eee9f1a7385
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278583867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2278583867
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1171641113
Short name T406
Test name
Test status
Simulation time 13565714 ps
CPU time 0.75 seconds
Started Jun 23 05:51:55 PM PDT 24
Finished Jun 23 05:51:56 PM PDT 24
Peak memory 206752 kb
Host smart-1c04f972-b406-4b30-a23a-f7e242e31c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171641113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1171641113
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3408328219
Short name T641
Test name
Test status
Simulation time 1748129110 ps
CPU time 29.57 seconds
Started Jun 23 05:51:58 PM PDT 24
Finished Jun 23 05:52:28 PM PDT 24
Peak memory 255972 kb
Host smart-e3615693-77f8-4595-8e12-4e09de1fb2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408328219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3408328219
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1446292130
Short name T631
Test name
Test status
Simulation time 43792693942 ps
CPU time 83.78 seconds
Started Jun 23 05:52:10 PM PDT 24
Finished Jun 23 05:53:35 PM PDT 24
Peak memory 251416 kb
Host smart-0cf1e389-458d-402c-903c-c8e352c6fd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446292130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1446292130
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2712530252
Short name T132
Test name
Test status
Simulation time 82629303935 ps
CPU time 432.55 seconds
Started Jun 23 05:52:09 PM PDT 24
Finished Jun 23 05:59:23 PM PDT 24
Peak memory 271976 kb
Host smart-18889bf8-85ba-40ae-9944-31a6ce446c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712530252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2712530252
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2050786474
Short name T692
Test name
Test status
Simulation time 95666376 ps
CPU time 4.44 seconds
Started Jun 23 05:51:57 PM PDT 24
Finished Jun 23 05:52:02 PM PDT 24
Peak memory 236980 kb
Host smart-46b70bef-7f97-4819-86de-bd3122075054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050786474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2050786474
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2955521522
Short name T812
Test name
Test status
Simulation time 907804813 ps
CPU time 3.82 seconds
Started Jun 23 05:51:53 PM PDT 24
Finished Jun 23 05:51:58 PM PDT 24
Peak memory 224648 kb
Host smart-bb84948e-dce8-47bb-aad1-a25715d8c767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955521522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2955521522
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.4136708570
Short name T588
Test name
Test status
Simulation time 6308316396 ps
CPU time 40.38 seconds
Started Jun 23 05:51:59 PM PDT 24
Finished Jun 23 05:52:40 PM PDT 24
Peak memory 241044 kb
Host smart-163eb577-37b1-42f9-8820-b108e303f41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136708570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.4136708570
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2344962379
Short name T284
Test name
Test status
Simulation time 247953756 ps
CPU time 5.02 seconds
Started Jun 23 05:51:52 PM PDT 24
Finished Jun 23 05:51:57 PM PDT 24
Peak memory 232808 kb
Host smart-83b017ff-94d7-4125-8c94-48b58823a69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344962379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2344962379
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.178403048
Short name T489
Test name
Test status
Simulation time 153940653145 ps
CPU time 29.68 seconds
Started Jun 23 05:51:48 PM PDT 24
Finished Jun 23 05:52:19 PM PDT 24
Peak memory 232976 kb
Host smart-0891d1e6-d159-4666-80bb-140f8d65d61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178403048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.178403048
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3061923540
Short name T77
Test name
Test status
Simulation time 85728100 ps
CPU time 3.71 seconds
Started Jun 23 05:51:56 PM PDT 24
Finished Jun 23 05:52:00 PM PDT 24
Peak memory 222908 kb
Host smart-426c86fa-b86e-4f4a-84cf-cec1b951cf27
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3061923540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3061923540
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3892783735
Short name T299
Test name
Test status
Simulation time 9040902878 ps
CPU time 102.4 seconds
Started Jun 23 05:52:09 PM PDT 24
Finished Jun 23 05:53:53 PM PDT 24
Peak memory 255300 kb
Host smart-4a542409-2829-48e7-b473-80f755fd0b2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892783735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3892783735
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3526999087
Short name T615
Test name
Test status
Simulation time 3140999039 ps
CPU time 23.47 seconds
Started Jun 23 05:51:52 PM PDT 24
Finished Jun 23 05:52:16 PM PDT 24
Peak memory 218208 kb
Host smart-6b8bdd95-47df-452a-a9cc-9fa1b094c0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526999087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3526999087
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1761818129
Short name T771
Test name
Test status
Simulation time 5344616876 ps
CPU time 18.43 seconds
Started Jun 23 05:51:55 PM PDT 24
Finished Jun 23 05:52:14 PM PDT 24
Peak memory 216424 kb
Host smart-5500a6d6-2024-42bf-853c-f86ee20c57d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761818129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1761818129
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.798605815
Short name T645
Test name
Test status
Simulation time 35194529 ps
CPU time 1.05 seconds
Started Jun 23 05:51:53 PM PDT 24
Finished Jun 23 05:51:55 PM PDT 24
Peak memory 208100 kb
Host smart-26eb1ead-4eb6-4369-ad7e-71975427d1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798605815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.798605815
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1662588208
Short name T869
Test name
Test status
Simulation time 63594136 ps
CPU time 0.89 seconds
Started Jun 23 05:51:56 PM PDT 24
Finished Jun 23 05:51:57 PM PDT 24
Peak memory 206304 kb
Host smart-af8476ba-f4b6-4ea3-ab46-2b3af737bafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662588208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1662588208
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.909808191
Short name T162
Test name
Test status
Simulation time 243507730 ps
CPU time 3.95 seconds
Started Jun 23 05:51:56 PM PDT 24
Finished Jun 23 05:52:01 PM PDT 24
Peak memory 232848 kb
Host smart-93d487c2-7dae-49c9-8df7-3dbbd972f7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909808191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.909808191
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1799266207
Short name T323
Test name
Test status
Simulation time 23335041 ps
CPU time 0.71 seconds
Started Jun 23 05:52:02 PM PDT 24
Finished Jun 23 05:52:03 PM PDT 24
Peak memory 205552 kb
Host smart-d6e114ac-ade1-446e-aa2e-f0c36563e7bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799266207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1799266207
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2374161181
Short name T599
Test name
Test status
Simulation time 4868173419 ps
CPU time 12.69 seconds
Started Jun 23 05:51:55 PM PDT 24
Finished Jun 23 05:52:08 PM PDT 24
Peak memory 224808 kb
Host smart-cf71ca5c-42ef-4551-811a-2ae7fea2f9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374161181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2374161181
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2439038285
Short name T837
Test name
Test status
Simulation time 29845515 ps
CPU time 0.75 seconds
Started Jun 23 05:51:57 PM PDT 24
Finished Jun 23 05:51:58 PM PDT 24
Peak memory 205728 kb
Host smart-29a03100-926a-441f-a44c-20d28d50cfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439038285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2439038285
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.544279350
Short name T257
Test name
Test status
Simulation time 46882406747 ps
CPU time 353.3 seconds
Started Jun 23 05:51:59 PM PDT 24
Finished Jun 23 05:57:52 PM PDT 24
Peak memory 263300 kb
Host smart-7388c3d8-1b5d-497e-a4ad-30c894d61a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544279350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.544279350
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2568617114
Short name T569
Test name
Test status
Simulation time 24324273671 ps
CPU time 33.2 seconds
Started Jun 23 05:51:57 PM PDT 24
Finished Jun 23 05:52:31 PM PDT 24
Peak memory 240560 kb
Host smart-154ad0b4-8153-45f3-9da6-e6b2300aa7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568617114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2568617114
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1605705569
Short name T228
Test name
Test status
Simulation time 107167629118 ps
CPU time 477.17 seconds
Started Jun 23 05:51:56 PM PDT 24
Finished Jun 23 05:59:53 PM PDT 24
Peak memory 252276 kb
Host smart-d934da4f-7e25-40e4-a9af-6d99d2aa6e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605705569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1605705569
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.439695007
Short name T558
Test name
Test status
Simulation time 11226248271 ps
CPU time 45.52 seconds
Started Jun 23 05:51:59 PM PDT 24
Finished Jun 23 05:52:45 PM PDT 24
Peak memory 241204 kb
Host smart-31ac64d6-375d-4289-875c-2385855cf427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439695007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.439695007
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.68348775
Short name T483
Test name
Test status
Simulation time 2495319356 ps
CPU time 22.15 seconds
Started Jun 23 05:52:01 PM PDT 24
Finished Jun 23 05:52:23 PM PDT 24
Peak memory 224760 kb
Host smart-62b893a2-7d5e-4698-b930-4437d19bccc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68348775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.68348775
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2097012185
Short name T650
Test name
Test status
Simulation time 562498553 ps
CPU time 10.97 seconds
Started Jun 23 05:51:54 PM PDT 24
Finished Jun 23 05:52:05 PM PDT 24
Peak memory 233072 kb
Host smart-af43bdd1-d40e-472e-b906-dbf2306ca54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097012185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2097012185
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.367500033
Short name T269
Test name
Test status
Simulation time 1329622870 ps
CPU time 7.47 seconds
Started Jun 23 05:52:01 PM PDT 24
Finished Jun 23 05:52:09 PM PDT 24
Peak memory 232824 kb
Host smart-533c8d73-1c89-44d9-b142-b5d1c1b63709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367500033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.367500033
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.987225944
Short name T688
Test name
Test status
Simulation time 117047194 ps
CPU time 2.51 seconds
Started Jun 23 05:52:09 PM PDT 24
Finished Jun 23 05:52:12 PM PDT 24
Peak memory 232736 kb
Host smart-fae30e41-d328-42d8-bf42-530e591450b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987225944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.987225944
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1356605597
Short name T939
Test name
Test status
Simulation time 821555313 ps
CPU time 4.28 seconds
Started Jun 23 05:51:57 PM PDT 24
Finished Jun 23 05:52:02 PM PDT 24
Peak memory 223240 kb
Host smart-8eaf1961-4828-4bbe-9f8f-b02fd04a46aa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1356605597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1356605597
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2226922947
Short name T291
Test name
Test status
Simulation time 3844911387 ps
CPU time 77.89 seconds
Started Jun 23 05:52:12 PM PDT 24
Finished Jun 23 05:53:30 PM PDT 24
Peak memory 255800 kb
Host smart-77ffa085-2c3d-4c1f-af42-9dbc1709751d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226922947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2226922947
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1170522258
Short name T667
Test name
Test status
Simulation time 800608657 ps
CPU time 11.15 seconds
Started Jun 23 05:52:01 PM PDT 24
Finished Jun 23 05:52:13 PM PDT 24
Peak memory 216596 kb
Host smart-8ed27072-d1b7-4c40-96ab-c5eadf30a352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170522258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1170522258
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2623418824
Short name T942
Test name
Test status
Simulation time 12303662209 ps
CPU time 12.45 seconds
Started Jun 23 05:51:58 PM PDT 24
Finished Jun 23 05:52:11 PM PDT 24
Peak memory 216484 kb
Host smart-fdeafe7f-738c-461c-bb1c-7fd1ff7560ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623418824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2623418824
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1968890881
Short name T880
Test name
Test status
Simulation time 414702628 ps
CPU time 3.25 seconds
Started Jun 23 05:51:58 PM PDT 24
Finished Jun 23 05:52:01 PM PDT 24
Peak memory 216460 kb
Host smart-0ca9bcdd-bbd0-4719-b04a-8ee4ad6bb1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968890881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1968890881
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.474778661
Short name T469
Test name
Test status
Simulation time 87559091 ps
CPU time 0.94 seconds
Started Jun 23 05:52:09 PM PDT 24
Finished Jun 23 05:52:10 PM PDT 24
Peak memory 206776 kb
Host smart-f851ae2c-4ad7-4bbc-b416-b52e45d6310b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474778661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.474778661
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3743857668
Short name T565
Test name
Test status
Simulation time 2949362481 ps
CPU time 6.54 seconds
Started Jun 23 05:51:55 PM PDT 24
Finished Jun 23 05:52:02 PM PDT 24
Peak memory 233028 kb
Host smart-3148e3a5-ce32-4eaf-bf9d-746e74448fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743857668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3743857668
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3246220686
Short name T495
Test name
Test status
Simulation time 13414582 ps
CPU time 0.75 seconds
Started Jun 23 05:52:03 PM PDT 24
Finished Jun 23 05:52:04 PM PDT 24
Peak memory 205512 kb
Host smart-b3e7ab05-36d9-4a15-88ff-a3e38917d971
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246220686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3246220686
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3541685347
Short name T236
Test name
Test status
Simulation time 406585874 ps
CPU time 2.52 seconds
Started Jun 23 05:52:01 PM PDT 24
Finished Jun 23 05:52:05 PM PDT 24
Peak memory 232868 kb
Host smart-23118c22-3bf5-4fd9-89d6-9894756c2f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541685347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3541685347
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.335154653
Short name T686
Test name
Test status
Simulation time 16975343 ps
CPU time 0.76 seconds
Started Jun 23 05:52:04 PM PDT 24
Finished Jun 23 05:52:05 PM PDT 24
Peak memory 207072 kb
Host smart-50ca189b-d50c-46b0-8fa3-0898fbe52d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335154653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.335154653
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.893877898
Short name T733
Test name
Test status
Simulation time 102953192514 ps
CPU time 99.36 seconds
Started Jun 23 05:52:10 PM PDT 24
Finished Jun 23 05:53:50 PM PDT 24
Peak memory 250584 kb
Host smart-2ce2c90b-ee5e-465d-be75-5d3fdc221818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893877898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.893877898
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3514907712
Short name T586
Test name
Test status
Simulation time 1278495512 ps
CPU time 20.01 seconds
Started Jun 23 05:52:00 PM PDT 24
Finished Jun 23 05:52:21 PM PDT 24
Peak memory 217692 kb
Host smart-cd1d550e-0f06-4811-ab7a-d95a82ab5992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514907712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3514907712
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3170858745
Short name T488
Test name
Test status
Simulation time 13847152931 ps
CPU time 86.26 seconds
Started Jun 23 05:52:04 PM PDT 24
Finished Jun 23 05:53:31 PM PDT 24
Peak memory 254256 kb
Host smart-cde01b89-5bff-48d0-b8af-c776c4f4c6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170858745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3170858745
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.124234709
Short name T564
Test name
Test status
Simulation time 375616319 ps
CPU time 8.24 seconds
Started Jun 23 05:52:03 PM PDT 24
Finished Jun 23 05:52:12 PM PDT 24
Peak memory 224700 kb
Host smart-7c903ba7-4a51-4936-970d-fc94fd252fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124234709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.124234709
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2566922242
Short name T709
Test name
Test status
Simulation time 392977024 ps
CPU time 6.2 seconds
Started Jun 23 05:52:00 PM PDT 24
Finished Jun 23 05:52:06 PM PDT 24
Peak memory 224644 kb
Host smart-2be8ca88-b8be-47cd-8c46-8c84e3985640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566922242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2566922242
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.809924144
Short name T218
Test name
Test status
Simulation time 37273763603 ps
CPU time 74.99 seconds
Started Jun 23 05:52:07 PM PDT 24
Finished Jun 23 05:53:22 PM PDT 24
Peak memory 249416 kb
Host smart-e28fa6f6-59ac-4552-9074-d3d4bc67590c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809924144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.809924144
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.56260493
Short name T743
Test name
Test status
Simulation time 5973557439 ps
CPU time 20.6 seconds
Started Jun 23 05:52:03 PM PDT 24
Finished Jun 23 05:52:24 PM PDT 24
Peak memory 241028 kb
Host smart-73e255a1-3dcf-4386-8a3c-347c21521d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56260493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.56260493
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3340250462
Short name T920
Test name
Test status
Simulation time 525595830 ps
CPU time 2.12 seconds
Started Jun 23 05:51:59 PM PDT 24
Finished Jun 23 05:52:01 PM PDT 24
Peak memory 223956 kb
Host smart-50a94d9e-f68b-4f31-b327-ec5fa5e2eff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340250462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3340250462
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1236272906
Short name T840
Test name
Test status
Simulation time 1023115828 ps
CPU time 6.19 seconds
Started Jun 23 05:51:59 PM PDT 24
Finished Jun 23 05:52:05 PM PDT 24
Peak memory 218988 kb
Host smart-f42e6624-ab4e-440b-b611-26864674a3d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1236272906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1236272906
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3525189407
Short name T507
Test name
Test status
Simulation time 5413334543 ps
CPU time 68.24 seconds
Started Jun 23 05:52:10 PM PDT 24
Finished Jun 23 05:53:19 PM PDT 24
Peak memory 255504 kb
Host smart-9e213be8-bbdf-4ecc-bd7b-01bb9d023c7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525189407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3525189407
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3178055949
Short name T912
Test name
Test status
Simulation time 2562839161 ps
CPU time 9.4 seconds
Started Jun 23 05:52:01 PM PDT 24
Finished Jun 23 05:52:11 PM PDT 24
Peak memory 216952 kb
Host smart-00fd703a-db92-4846-bad0-3aea5633d65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178055949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3178055949
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2093932469
Short name T505
Test name
Test status
Simulation time 1726822128 ps
CPU time 6.42 seconds
Started Jun 23 05:52:04 PM PDT 24
Finished Jun 23 05:52:11 PM PDT 24
Peak memory 216368 kb
Host smart-07e9a8c2-05fc-49b5-b31a-8148e50039cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093932469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2093932469
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1961499032
Short name T638
Test name
Test status
Simulation time 132681871 ps
CPU time 0.9 seconds
Started Jun 23 05:52:03 PM PDT 24
Finished Jun 23 05:52:04 PM PDT 24
Peak memory 206956 kb
Host smart-a04fcf8f-5d85-4cbc-9331-e5642b26a202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961499032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1961499032
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.951918868
Short name T78
Test name
Test status
Simulation time 204158400 ps
CPU time 0.76 seconds
Started Jun 23 05:52:03 PM PDT 24
Finished Jun 23 05:52:04 PM PDT 24
Peak memory 206108 kb
Host smart-1d62a5f0-a004-4ded-817d-1a0d97898c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951918868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.951918868
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1081126631
Short name T822
Test name
Test status
Simulation time 1510327139 ps
CPU time 7.69 seconds
Started Jun 23 05:51:58 PM PDT 24
Finished Jun 23 05:52:06 PM PDT 24
Peak memory 224656 kb
Host smart-c310d616-624a-425e-b4a7-3b6a9613929a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081126631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1081126631
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.873713048
Short name T582
Test name
Test status
Simulation time 27267198 ps
CPU time 0.71 seconds
Started Jun 23 05:52:06 PM PDT 24
Finished Jun 23 05:52:07 PM PDT 24
Peak memory 204948 kb
Host smart-7f55d983-fcfe-4553-902b-13f81ba64d80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873713048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.873713048
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1529401528
Short name T658
Test name
Test status
Simulation time 6744828843 ps
CPU time 13.86 seconds
Started Jun 23 05:52:06 PM PDT 24
Finished Jun 23 05:52:20 PM PDT 24
Peak memory 224812 kb
Host smart-86c71ecf-e39e-4f2b-9cb3-29024d1e177a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529401528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1529401528
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1890121508
Short name T861
Test name
Test status
Simulation time 15861322 ps
CPU time 0.73 seconds
Started Jun 23 05:52:01 PM PDT 24
Finished Jun 23 05:52:02 PM PDT 24
Peak memory 206048 kb
Host smart-4e451e10-b9dc-4205-a7f6-2ab43eb8b789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890121508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1890121508
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3744223516
Short name T940
Test name
Test status
Simulation time 1843767207 ps
CPU time 24.92 seconds
Started Jun 23 05:52:02 PM PDT 24
Finished Jun 23 05:52:27 PM PDT 24
Peak memory 249220 kb
Host smart-722af95d-24c6-415c-88ea-45fa9619b133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744223516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3744223516
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1305535730
Short name T730
Test name
Test status
Simulation time 9990353817 ps
CPU time 97.61 seconds
Started Jun 23 05:52:06 PM PDT 24
Finished Jun 23 05:53:44 PM PDT 24
Peak memory 234088 kb
Host smart-9dbdba8d-7f53-444a-9320-950d8604f15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305535730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1305535730
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.4242461972
Short name T796
Test name
Test status
Simulation time 3484287273 ps
CPU time 19.71 seconds
Started Jun 23 05:52:03 PM PDT 24
Finished Jun 23 05:52:23 PM PDT 24
Peak memory 234620 kb
Host smart-20fdbd60-53fa-493e-be30-f83063480b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242461972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.4242461972
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1493599871
Short name T385
Test name
Test status
Simulation time 855108857 ps
CPU time 16.21 seconds
Started Jun 23 05:52:02 PM PDT 24
Finished Jun 23 05:52:18 PM PDT 24
Peak memory 232836 kb
Host smart-a81e6176-7b6c-4030-b31d-6b0adf1505f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493599871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1493599871
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1790588961
Short name T777
Test name
Test status
Simulation time 3090622362 ps
CPU time 6.89 seconds
Started Jun 23 05:52:11 PM PDT 24
Finished Jun 23 05:52:19 PM PDT 24
Peak memory 224744 kb
Host smart-26cd92d0-686e-43ba-bd30-d6ee8ce4b197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790588961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1790588961
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.510395271
Short name T884
Test name
Test status
Simulation time 91688741 ps
CPU time 2.18 seconds
Started Jun 23 05:52:04 PM PDT 24
Finished Jun 23 05:52:06 PM PDT 24
Peak memory 223168 kb
Host smart-e39cd65d-6a22-4b78-a6f4-0aecfc607d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510395271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.510395271
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.68029313
Short name T698
Test name
Test status
Simulation time 563700783 ps
CPU time 5.51 seconds
Started Jun 23 05:52:06 PM PDT 24
Finished Jun 23 05:52:12 PM PDT 24
Peak memory 224628 kb
Host smart-054c7cfc-ef0a-4b49-b67a-9ca17c893490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68029313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.68029313
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.4085966391
Short name T398
Test name
Test status
Simulation time 4650594576 ps
CPU time 17.02 seconds
Started Jun 23 05:52:03 PM PDT 24
Finished Jun 23 05:52:20 PM PDT 24
Peak memory 233016 kb
Host smart-215c998c-65c6-4e8e-8894-59e9ca6b79a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085966391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.4085966391
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3873629024
Short name T143
Test name
Test status
Simulation time 1654784980 ps
CPU time 18.73 seconds
Started Jun 23 05:52:10 PM PDT 24
Finished Jun 23 05:52:29 PM PDT 24
Peak memory 220708 kb
Host smart-3d80918c-d5b0-4d63-aed1-ac5853ad1c31
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3873629024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3873629024
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.4292001754
Short name T350
Test name
Test status
Simulation time 675600827 ps
CPU time 1.11 seconds
Started Jun 23 05:52:00 PM PDT 24
Finished Jun 23 05:52:02 PM PDT 24
Peak memory 206964 kb
Host smart-2c21461d-f36e-44f9-9953-82645539aa77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292001754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.4292001754
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.156767986
Short name T919
Test name
Test status
Simulation time 1798914854 ps
CPU time 7.02 seconds
Started Jun 23 05:52:03 PM PDT 24
Finished Jun 23 05:52:10 PM PDT 24
Peak memory 216584 kb
Host smart-84bdbe55-647d-47c2-856d-38e3bff08d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156767986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.156767986
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2132649720
Short name T449
Test name
Test status
Simulation time 5030224194 ps
CPU time 17.46 seconds
Started Jun 23 05:52:02 PM PDT 24
Finished Jun 23 05:52:20 PM PDT 24
Peak memory 216524 kb
Host smart-4cb7a688-e51a-42fb-9b12-e67be144cd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132649720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2132649720
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3022289318
Short name T354
Test name
Test status
Simulation time 110304282 ps
CPU time 4.16 seconds
Started Jun 23 05:52:00 PM PDT 24
Finished Jun 23 05:52:05 PM PDT 24
Peak memory 216404 kb
Host smart-a6f04e88-f147-452b-8d7e-126471a4d651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022289318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3022289318
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.204418821
Short name T468
Test name
Test status
Simulation time 24765526 ps
CPU time 0.8 seconds
Started Jun 23 05:52:10 PM PDT 24
Finished Jun 23 05:52:11 PM PDT 24
Peak memory 206304 kb
Host smart-27d3074b-72f0-4e6f-935a-43683c3180eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204418821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.204418821
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1868942113
Short name T405
Test name
Test status
Simulation time 170510432 ps
CPU time 2.5 seconds
Started Jun 23 05:52:05 PM PDT 24
Finished Jun 23 05:52:09 PM PDT 24
Peak memory 224592 kb
Host smart-cdcc1e95-d2ca-4a2f-ac86-586c3b5d49a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868942113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1868942113
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3706847626
Short name T894
Test name
Test status
Simulation time 33313470 ps
CPU time 0.72 seconds
Started Jun 23 05:49:59 PM PDT 24
Finished Jun 23 05:50:00 PM PDT 24
Peak memory 204948 kb
Host smart-6eb4a81e-697a-451d-bfa1-7fa39cf344dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706847626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
706847626
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.744741381
Short name T263
Test name
Test status
Simulation time 7487272295 ps
CPU time 15.81 seconds
Started Jun 23 05:49:48 PM PDT 24
Finished Jun 23 05:50:05 PM PDT 24
Peak memory 233148 kb
Host smart-bfed60f2-5970-4945-bc7c-c9c5b7a7f915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744741381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.744741381
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.465976315
Short name T370
Test name
Test status
Simulation time 32938085 ps
CPU time 0.76 seconds
Started Jun 23 05:49:51 PM PDT 24
Finished Jun 23 05:49:53 PM PDT 24
Peak memory 206044 kb
Host smart-d2181d5a-d6e8-4403-ae4e-077c8034df00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465976315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.465976315
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.571120093
Short name T759
Test name
Test status
Simulation time 12570532291 ps
CPU time 48.9 seconds
Started Jun 23 05:49:51 PM PDT 24
Finished Jun 23 05:50:41 PM PDT 24
Peak memory 237096 kb
Host smart-20ec4b45-e930-44b3-91f6-ac3ce151f388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571120093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.571120093
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1005737562
Short name T29
Test name
Test status
Simulation time 9299051714 ps
CPU time 72.73 seconds
Started Jun 23 05:49:54 PM PDT 24
Finished Jun 23 05:51:08 PM PDT 24
Peak memory 254004 kb
Host smart-7d8f6c93-3f32-402f-948b-e4d49db88cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005737562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1005737562
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3163868614
Short name T544
Test name
Test status
Simulation time 4523735773 ps
CPU time 94.56 seconds
Started Jun 23 05:49:57 PM PDT 24
Finished Jun 23 05:51:33 PM PDT 24
Peak memory 265408 kb
Host smart-02f366b3-5be6-462a-8a58-4b514a68b06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163868614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3163868614
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3690688336
Short name T654
Test name
Test status
Simulation time 831721861 ps
CPU time 6.86 seconds
Started Jun 23 05:49:52 PM PDT 24
Finished Jun 23 05:50:00 PM PDT 24
Peak memory 232900 kb
Host smart-6ee79cd1-da43-4b36-8e42-7a716a9e1f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690688336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3690688336
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.378607633
Short name T889
Test name
Test status
Simulation time 360715251 ps
CPU time 5.73 seconds
Started Jun 23 05:49:50 PM PDT 24
Finished Jun 23 05:49:57 PM PDT 24
Peak memory 224592 kb
Host smart-eb6fc874-3abe-4261-bb34-cdaf9ecfe611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378607633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.378607633
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3508259902
Short name T636
Test name
Test status
Simulation time 3723830689 ps
CPU time 30.4 seconds
Started Jun 23 05:49:52 PM PDT 24
Finished Jun 23 05:50:23 PM PDT 24
Peak memory 233000 kb
Host smart-1f2701f7-0f37-41ce-8e2c-df1cb373b6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508259902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3508259902
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1178061586
Short name T657
Test name
Test status
Simulation time 2728970500 ps
CPU time 9.19 seconds
Started Jun 23 05:49:51 PM PDT 24
Finished Jun 23 05:50:02 PM PDT 24
Peak memory 232900 kb
Host smart-75638bb4-8c3d-4577-9d7c-070609f8b85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178061586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1178061586
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1836072327
Short name T860
Test name
Test status
Simulation time 1256198216 ps
CPU time 2.93 seconds
Started Jun 23 05:49:50 PM PDT 24
Finished Jun 23 05:49:54 PM PDT 24
Peak memory 224612 kb
Host smart-42e13dbc-348f-4f64-9128-91ae0460bf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836072327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1836072327
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1359049158
Short name T413
Test name
Test status
Simulation time 1546750212 ps
CPU time 10.21 seconds
Started Jun 23 05:49:56 PM PDT 24
Finished Jun 23 05:50:07 PM PDT 24
Peak memory 223112 kb
Host smart-ccbc1996-38b2-4356-aaa8-ab112002e88a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1359049158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1359049158
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3784354820
Short name T854
Test name
Test status
Simulation time 28685250942 ps
CPU time 24.41 seconds
Started Jun 23 05:49:50 PM PDT 24
Finished Jun 23 05:50:16 PM PDT 24
Peak memory 216404 kb
Host smart-b2ef479a-752a-4ec1-9ec3-9e4a585fd04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784354820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3784354820
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1453130334
Short name T690
Test name
Test status
Simulation time 1997117841 ps
CPU time 9.54 seconds
Started Jun 23 05:49:51 PM PDT 24
Finished Jun 23 05:50:02 PM PDT 24
Peak memory 216376 kb
Host smart-e63c12af-4e0e-4fd6-af21-3ab80a0f0c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453130334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1453130334
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2869718837
Short name T613
Test name
Test status
Simulation time 25730868 ps
CPU time 0.95 seconds
Started Jun 23 05:49:50 PM PDT 24
Finished Jun 23 05:49:53 PM PDT 24
Peak memory 207208 kb
Host smart-56795bce-56eb-4402-a76c-1a7f0ea5952e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869718837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2869718837
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2310589412
Short name T515
Test name
Test status
Simulation time 56078808 ps
CPU time 0.87 seconds
Started Jun 23 05:49:53 PM PDT 24
Finished Jun 23 05:49:55 PM PDT 24
Peak memory 206348 kb
Host smart-4084ef61-f999-4ebe-965d-6d947090ee26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310589412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2310589412
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.296583691
Short name T466
Test name
Test status
Simulation time 6339899225 ps
CPU time 18.72 seconds
Started Jun 23 05:49:50 PM PDT 24
Finished Jun 23 05:50:10 PM PDT 24
Peak memory 232656 kb
Host smart-a3fb9366-1895-446d-8f6d-e192bb0aeb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296583691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.296583691
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.885547176
Short name T891
Test name
Test status
Simulation time 48715637 ps
CPU time 0.72 seconds
Started Jun 23 05:49:54 PM PDT 24
Finished Jun 23 05:49:56 PM PDT 24
Peak memory 205520 kb
Host smart-ac12f065-a369-4aeb-805d-4fa3dfd235ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885547176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.885547176
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3085791522
Short name T243
Test name
Test status
Simulation time 12340388907 ps
CPU time 20.27 seconds
Started Jun 23 05:49:54 PM PDT 24
Finished Jun 23 05:50:16 PM PDT 24
Peak memory 233020 kb
Host smart-e041d3ad-45c0-4275-a733-baa710cd84b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085791522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3085791522
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2474819369
Short name T562
Test name
Test status
Simulation time 54888035 ps
CPU time 0.78 seconds
Started Jun 23 05:49:54 PM PDT 24
Finished Jun 23 05:49:56 PM PDT 24
Peak memory 206764 kb
Host smart-836480a6-fc26-40bc-85f4-4aa9a5f41dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474819369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2474819369
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2797035161
Short name T192
Test name
Test status
Simulation time 4962038485 ps
CPU time 11.84 seconds
Started Jun 23 05:49:53 PM PDT 24
Finished Jun 23 05:50:06 PM PDT 24
Peak memory 224808 kb
Host smart-ad681065-92c3-4e71-9c68-64a8d157589b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797035161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2797035161
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2161559622
Short name T572
Test name
Test status
Simulation time 20586274549 ps
CPU time 83.66 seconds
Started Jun 23 05:49:55 PM PDT 24
Finished Jun 23 05:51:20 PM PDT 24
Peak memory 255788 kb
Host smart-1bcc0a75-bd6c-496b-b3f1-73f8e9170e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161559622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2161559622
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.158151265
Short name T496
Test name
Test status
Simulation time 5907416464 ps
CPU time 54.48 seconds
Started Jun 23 05:49:54 PM PDT 24
Finished Jun 23 05:50:50 PM PDT 24
Peak memory 251020 kb
Host smart-981f5112-2385-4333-84f7-67b0897eac15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158151265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
158151265
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.759303363
Short name T308
Test name
Test status
Simulation time 4676503080 ps
CPU time 11.27 seconds
Started Jun 23 05:49:58 PM PDT 24
Finished Jun 23 05:50:10 PM PDT 24
Peak memory 224804 kb
Host smart-7362745e-46c2-4e36-90fa-21faa6316d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759303363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.759303363
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3388218537
Short name T90
Test name
Test status
Simulation time 1504805020 ps
CPU time 3.2 seconds
Started Jun 23 05:49:53 PM PDT 24
Finished Jun 23 05:49:58 PM PDT 24
Peak memory 224600 kb
Host smart-d89aaa36-6af2-4735-b80a-896e279cf89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388218537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3388218537
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1314880211
Short name T896
Test name
Test status
Simulation time 101772958565 ps
CPU time 90.86 seconds
Started Jun 23 05:49:57 PM PDT 24
Finished Jun 23 05:51:29 PM PDT 24
Peak memory 241064 kb
Host smart-edd6a6ee-578a-4640-8d1f-9ae72efa0e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314880211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1314880211
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.819497974
Short name T400
Test name
Test status
Simulation time 3007161942 ps
CPU time 7.12 seconds
Started Jun 23 05:49:54 PM PDT 24
Finished Jun 23 05:50:03 PM PDT 24
Peak memory 239828 kb
Host smart-8b67ae87-03ac-45bf-84b8-e796b269fa64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819497974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
819497974
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1383366424
Short name T716
Test name
Test status
Simulation time 5689879695 ps
CPU time 9.36 seconds
Started Jun 23 05:49:58 PM PDT 24
Finished Jun 23 05:50:08 PM PDT 24
Peak memory 233000 kb
Host smart-fcb888eb-a72b-4376-80eb-b58936ad0b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383366424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1383366424
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.419485603
Short name T35
Test name
Test status
Simulation time 548582612 ps
CPU time 6.4 seconds
Started Jun 23 05:49:53 PM PDT 24
Finished Jun 23 05:50:00 PM PDT 24
Peak memory 220740 kb
Host smart-9933c3e6-bb8c-4118-b5ce-759af8f015fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=419485603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.419485603
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1244286783
Short name T21
Test name
Test status
Simulation time 56002405 ps
CPU time 1.11 seconds
Started Jun 23 05:50:00 PM PDT 24
Finished Jun 23 05:50:02 PM PDT 24
Peak memory 207188 kb
Host smart-30464f69-4ced-4910-880f-3a0d31220156
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244286783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1244286783
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2370318009
Short name T732
Test name
Test status
Simulation time 15463638134 ps
CPU time 21.08 seconds
Started Jun 23 05:49:52 PM PDT 24
Finished Jun 23 05:50:14 PM PDT 24
Peak memory 216428 kb
Host smart-0f420622-8209-48d7-8013-7c795ad25817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370318009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2370318009
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3995436907
Short name T873
Test name
Test status
Simulation time 156132528 ps
CPU time 1.25 seconds
Started Jun 23 05:49:52 PM PDT 24
Finished Jun 23 05:49:55 PM PDT 24
Peak memory 207344 kb
Host smart-2a5120b6-c1a5-4801-b8b5-16d8b0245b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995436907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3995436907
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.750952562
Short name T727
Test name
Test status
Simulation time 17882040 ps
CPU time 0.77 seconds
Started Jun 23 05:49:57 PM PDT 24
Finished Jun 23 05:49:59 PM PDT 24
Peak memory 206076 kb
Host smart-dc2f31f2-b12d-4b70-bf8e-35e352ade6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750952562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.750952562
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2228555363
Short name T702
Test name
Test status
Simulation time 192970605 ps
CPU time 0.81 seconds
Started Jun 23 05:49:54 PM PDT 24
Finished Jun 23 05:49:56 PM PDT 24
Peak memory 206112 kb
Host smart-67b94290-62e1-45ea-9266-d1a35fa89ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228555363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2228555363
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2220117502
Short name T9
Test name
Test status
Simulation time 21766444453 ps
CPU time 20.3 seconds
Started Jun 23 05:49:53 PM PDT 24
Finished Jun 23 05:50:14 PM PDT 24
Peak memory 224772 kb
Host smart-12e160c4-d0e9-44e5-bf2b-282f04035cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220117502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2220117502
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3893238011
Short name T813
Test name
Test status
Simulation time 44407526 ps
CPU time 0.72 seconds
Started Jun 23 05:49:57 PM PDT 24
Finished Jun 23 05:49:59 PM PDT 24
Peak memory 205868 kb
Host smart-c653384f-91ca-4176-bb09-0c61f8bb0307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893238011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
893238011
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3822229515
Short name T824
Test name
Test status
Simulation time 154011047 ps
CPU time 3.41 seconds
Started Jun 23 05:49:58 PM PDT 24
Finished Jun 23 05:50:02 PM PDT 24
Peak memory 232876 kb
Host smart-7c5126a6-5bb8-4d7b-a725-d6de3cffef53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822229515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3822229515
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.30314148
Short name T328
Test name
Test status
Simulation time 18997233 ps
CPU time 0.77 seconds
Started Jun 23 05:49:58 PM PDT 24
Finished Jun 23 05:50:00 PM PDT 24
Peak memory 206720 kb
Host smart-56e55115-a18c-4108-ad1a-a7f16d34d51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30314148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.30314148
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1996143981
Short name T231
Test name
Test status
Simulation time 64593321718 ps
CPU time 104.06 seconds
Started Jun 23 05:49:56 PM PDT 24
Finished Jun 23 05:51:41 PM PDT 24
Peak memory 241176 kb
Host smart-6af7fdd5-1445-439e-bd39-232dee48740a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996143981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1996143981
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.202131409
Short name T273
Test name
Test status
Simulation time 44064210845 ps
CPU time 395.38 seconds
Started Jun 23 05:49:57 PM PDT 24
Finished Jun 23 05:56:33 PM PDT 24
Peak memory 265056 kb
Host smart-48ddf745-4659-45b2-81ec-40fc929012e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202131409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.202131409
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1729363415
Short name T661
Test name
Test status
Simulation time 10828341770 ps
CPU time 132.61 seconds
Started Jun 23 05:49:59 PM PDT 24
Finished Jun 23 05:52:13 PM PDT 24
Peak memory 249448 kb
Host smart-f00d8d43-3b69-4730-888c-074a9b6559a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729363415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1729363415
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2194936669
Short name T516
Test name
Test status
Simulation time 3647684556 ps
CPU time 27.39 seconds
Started Jun 23 05:50:02 PM PDT 24
Finished Jun 23 05:50:30 PM PDT 24
Peak memory 241004 kb
Host smart-0c9b97db-8516-4671-a502-1c40fc6ff3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194936669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2194936669
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2716619182
Short name T74
Test name
Test status
Simulation time 475650301 ps
CPU time 3.64 seconds
Started Jun 23 05:50:00 PM PDT 24
Finished Jun 23 05:50:04 PM PDT 24
Peak memory 224724 kb
Host smart-0d88ce9a-7994-411b-947e-9545bfa4d29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716619182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2716619182
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3446457641
Short name T113
Test name
Test status
Simulation time 606388842 ps
CPU time 7.88 seconds
Started Jun 23 05:50:00 PM PDT 24
Finished Jun 23 05:50:10 PM PDT 24
Peak memory 240704 kb
Host smart-5271b917-240e-4788-a8b4-f35513a90f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446457641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3446457641
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.182672827
Short name T256
Test name
Test status
Simulation time 3496729054 ps
CPU time 6.95 seconds
Started Jun 23 05:49:58 PM PDT 24
Finished Jun 23 05:50:06 PM PDT 24
Peak memory 224692 kb
Host smart-3ae50589-c3a3-461a-8f61-2ce3472e1a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182672827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
182672827
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3664414076
Short name T440
Test name
Test status
Simulation time 1250799877 ps
CPU time 8.19 seconds
Started Jun 23 05:49:56 PM PDT 24
Finished Jun 23 05:50:05 PM PDT 24
Peak memory 232872 kb
Host smart-2bb7670f-17f3-4dc8-9b7f-3fc344f9be5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664414076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3664414076
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.992607745
Short name T451
Test name
Test status
Simulation time 279616776 ps
CPU time 5.16 seconds
Started Jun 23 05:50:02 PM PDT 24
Finished Jun 23 05:50:08 PM PDT 24
Peak memory 222104 kb
Host smart-8fe41314-126e-4295-9159-5c9ae8ec090e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=992607745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.992607745
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1733543944
Short name T944
Test name
Test status
Simulation time 31114091225 ps
CPU time 165.77 seconds
Started Jun 23 05:49:57 PM PDT 24
Finished Jun 23 05:52:43 PM PDT 24
Peak memory 274052 kb
Host smart-4da63564-41a3-4666-968f-83e68bc7ebf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733543944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1733543944
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2672859774
Short name T906
Test name
Test status
Simulation time 2497692611 ps
CPU time 21.94 seconds
Started Jun 23 05:49:54 PM PDT 24
Finished Jun 23 05:50:17 PM PDT 24
Peak memory 216808 kb
Host smart-553db6ec-00fe-4f01-aeac-9ac26195c4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672859774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2672859774
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.422552849
Short name T479
Test name
Test status
Simulation time 3507893439 ps
CPU time 9.48 seconds
Started Jun 23 05:49:53 PM PDT 24
Finished Jun 23 05:50:04 PM PDT 24
Peak memory 216468 kb
Host smart-526241fe-c8ad-4d43-8070-214b39bcbe84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422552849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.422552849
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1343658566
Short name T538
Test name
Test status
Simulation time 40368736 ps
CPU time 1.29 seconds
Started Jun 23 05:49:58 PM PDT 24
Finished Jun 23 05:50:00 PM PDT 24
Peak memory 216324 kb
Host smart-135af8dc-3f47-4c41-b556-2a3e8080eb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343658566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1343658566
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3126887395
Short name T481
Test name
Test status
Simulation time 70440718 ps
CPU time 0.81 seconds
Started Jun 23 05:49:53 PM PDT 24
Finished Jun 23 05:49:55 PM PDT 24
Peak memory 206120 kb
Host smart-0338fb76-d4d6-41e5-95d9-7a2511d4dbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126887395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3126887395
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1441193676
Short name T266
Test name
Test status
Simulation time 3941130516 ps
CPU time 13.31 seconds
Started Jun 23 05:49:55 PM PDT 24
Finished Jun 23 05:50:09 PM PDT 24
Peak memory 232964 kb
Host smart-92055481-7a70-489f-ad75-f35b9c5935bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441193676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1441193676
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1583259715
Short name T524
Test name
Test status
Simulation time 11338363 ps
CPU time 0.72 seconds
Started Jun 23 05:49:54 PM PDT 24
Finished Jun 23 05:49:56 PM PDT 24
Peak memory 204948 kb
Host smart-5157d0ae-4be8-4618-a19a-cc7dd63ca2f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583259715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
583259715
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2302569710
Short name T675
Test name
Test status
Simulation time 216554834 ps
CPU time 3.69 seconds
Started Jun 23 05:50:03 PM PDT 24
Finished Jun 23 05:50:07 PM PDT 24
Peak memory 224724 kb
Host smart-db014fe1-8378-4900-bcce-43d14ccbb723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302569710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2302569710
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1698966281
Short name T432
Test name
Test status
Simulation time 97560222 ps
CPU time 0.81 seconds
Started Jun 23 05:50:00 PM PDT 24
Finished Jun 23 05:50:01 PM PDT 24
Peak memory 206748 kb
Host smart-e5a6b3b4-c52b-41d6-b35a-b3c7622e3150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698966281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1698966281
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3728575757
Short name T272
Test name
Test status
Simulation time 4959901028 ps
CPU time 51.01 seconds
Started Jun 23 05:50:02 PM PDT 24
Finished Jun 23 05:50:54 PM PDT 24
Peak memory 252864 kb
Host smart-655ac2ff-873c-47b6-bb3a-4e95c8945b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728575757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3728575757
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1290271595
Short name T810
Test name
Test status
Simulation time 13462318161 ps
CPU time 47.42 seconds
Started Jun 23 05:50:00 PM PDT 24
Finished Jun 23 05:50:49 PM PDT 24
Peak memory 240636 kb
Host smart-4778200e-682f-4483-877d-2361f9d5dcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290271595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1290271595
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1660368650
Short name T445
Test name
Test status
Simulation time 7482294024 ps
CPU time 28.64 seconds
Started Jun 23 05:50:02 PM PDT 24
Finished Jun 23 05:50:31 PM PDT 24
Peak memory 241080 kb
Host smart-2d33839a-67d7-44f3-85c5-a08baa590eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660368650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1660368650
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.4035220273
Short name T859
Test name
Test status
Simulation time 1241776795 ps
CPU time 7.71 seconds
Started Jun 23 05:49:58 PM PDT 24
Finished Jun 23 05:50:06 PM PDT 24
Peak memory 232888 kb
Host smart-4eaf944a-ad1f-4f72-a7f5-121a7c3896e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035220273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.4035220273
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.221536182
Short name T725
Test name
Test status
Simulation time 6837263531 ps
CPU time 46.48 seconds
Started Jun 23 05:50:02 PM PDT 24
Finished Jun 23 05:50:49 PM PDT 24
Peak memory 240884 kb
Host smart-5780e3a7-50fd-4782-b730-60057442bfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221536182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.221536182
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.406741077
Short name T629
Test name
Test status
Simulation time 1724873415 ps
CPU time 6.31 seconds
Started Jun 23 05:49:56 PM PDT 24
Finished Jun 23 05:50:03 PM PDT 24
Peak memory 224616 kb
Host smart-3913e096-f5a0-4933-ad94-8b5f3188623c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406741077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
406741077
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1764427270
Short name T710
Test name
Test status
Simulation time 66093523348 ps
CPU time 17.95 seconds
Started Jun 23 05:49:57 PM PDT 24
Finished Jun 23 05:50:15 PM PDT 24
Peak memory 256992 kb
Host smart-8a044d46-59de-41d6-83e5-489c1506e55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764427270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1764427270
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1694421206
Short name T346
Test name
Test status
Simulation time 587115621 ps
CPU time 7.87 seconds
Started Jun 23 05:50:02 PM PDT 24
Finished Jun 23 05:50:10 PM PDT 24
Peak memory 219492 kb
Host smart-01310e37-4ff0-4204-b3f5-d496f22109a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1694421206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1694421206
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.115444219
Short name T632
Test name
Test status
Simulation time 83108247352 ps
CPU time 774.06 seconds
Started Jun 23 05:50:00 PM PDT 24
Finished Jun 23 06:02:56 PM PDT 24
Peak memory 284048 kb
Host smart-03aaadfb-d04a-41f7-82bb-eaba9daff9b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115444219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.115444219
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3698897166
Short name T696
Test name
Test status
Simulation time 18750199 ps
CPU time 0.75 seconds
Started Jun 23 05:49:58 PM PDT 24
Finished Jun 23 05:49:59 PM PDT 24
Peak memory 206140 kb
Host smart-217db71f-b7f2-4794-a2f7-b46ac7f657d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698897166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3698897166
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.91022916
Short name T494
Test name
Test status
Simulation time 281023010 ps
CPU time 1.92 seconds
Started Jun 23 05:50:00 PM PDT 24
Finished Jun 23 05:50:04 PM PDT 24
Peak memory 216284 kb
Host smart-beecb6c2-9c57-4a5b-8879-e730e29060c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91022916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.91022916
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1203492163
Short name T756
Test name
Test status
Simulation time 110277775 ps
CPU time 2.07 seconds
Started Jun 23 05:50:02 PM PDT 24
Finished Jun 23 05:50:05 PM PDT 24
Peak memory 216404 kb
Host smart-20fc612b-0ffc-4cea-815a-c2dbaae41fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203492163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1203492163
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3253781466
Short name T76
Test name
Test status
Simulation time 374834413 ps
CPU time 0.78 seconds
Started Jun 23 05:50:00 PM PDT 24
Finished Jun 23 05:50:01 PM PDT 24
Peak memory 206112 kb
Host smart-290b5476-484a-4653-bcde-cfb6d59b2095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253781466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3253781466
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1308174099
Short name T38
Test name
Test status
Simulation time 100406722 ps
CPU time 2.24 seconds
Started Jun 23 05:50:00 PM PDT 24
Finished Jun 23 05:50:04 PM PDT 24
Peak memory 224624 kb
Host smart-b26e478e-a18c-4ae7-b8ec-b28de45ba9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308174099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1308174099
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.36999839
Short name T904
Test name
Test status
Simulation time 14427439 ps
CPU time 0.83 seconds
Started Jun 23 05:50:03 PM PDT 24
Finished Jun 23 05:50:05 PM PDT 24
Peak memory 205872 kb
Host smart-60d689d4-26a7-4326-9ff4-8a32b351425b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36999839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.36999839
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3933942852
Short name T681
Test name
Test status
Simulation time 37726144 ps
CPU time 2.66 seconds
Started Jun 23 05:50:04 PM PDT 24
Finished Jun 23 05:50:08 PM PDT 24
Peak memory 232828 kb
Host smart-088efd54-e89c-4836-a774-25ad30116fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933942852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3933942852
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2733732595
Short name T321
Test name
Test status
Simulation time 123371137 ps
CPU time 0.72 seconds
Started Jun 23 05:50:00 PM PDT 24
Finished Jun 23 05:50:01 PM PDT 24
Peak memory 205704 kb
Host smart-06c1a1c1-87d6-4d96-8480-94452e240468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733732595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2733732595
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.4103936891
Short name T167
Test name
Test status
Simulation time 1837547644 ps
CPU time 39.87 seconds
Started Jun 23 05:50:03 PM PDT 24
Finished Jun 23 05:50:43 PM PDT 24
Peak memory 257352 kb
Host smart-ea5d7054-4534-400e-a9a6-7aaf5ddf19c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103936891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.4103936891
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2141834508
Short name T138
Test name
Test status
Simulation time 10637268593 ps
CPU time 157.8 seconds
Started Jun 23 05:50:04 PM PDT 24
Finished Jun 23 05:52:43 PM PDT 24
Peak memory 270252 kb
Host smart-eb35c74e-af21-4308-8cfa-535b2d08a443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141834508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2141834508
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3316534757
Short name T225
Test name
Test status
Simulation time 289512657144 ps
CPU time 591.21 seconds
Started Jun 23 05:50:04 PM PDT 24
Finished Jun 23 05:59:56 PM PDT 24
Peak memory 266804 kb
Host smart-98a5dc51-de3e-4f9a-8064-5b374cc1a0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316534757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3316534757
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1225970599
Short name T359
Test name
Test status
Simulation time 1350178679 ps
CPU time 6.88 seconds
Started Jun 23 05:50:11 PM PDT 24
Finished Jun 23 05:50:19 PM PDT 24
Peak memory 224640 kb
Host smart-06663c1a-5bd2-43aa-8fba-3bf7772e8752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225970599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1225970599
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3128502714
Short name T552
Test name
Test status
Simulation time 2048907961 ps
CPU time 7.74 seconds
Started Jun 23 05:50:11 PM PDT 24
Finished Jun 23 05:50:20 PM PDT 24
Peak memory 232900 kb
Host smart-d8e3680d-bd19-486f-a34f-34e77011ca74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128502714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3128502714
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3436548093
Short name T530
Test name
Test status
Simulation time 609714518 ps
CPU time 10.21 seconds
Started Jun 23 05:50:03 PM PDT 24
Finished Jun 23 05:50:14 PM PDT 24
Peak memory 233104 kb
Host smart-d0c32adf-8914-41c2-8c22-1ea1ad7ddfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436548093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3436548093
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.369106209
Short name T184
Test name
Test status
Simulation time 3388131711 ps
CPU time 7.16 seconds
Started Jun 23 05:50:04 PM PDT 24
Finished Jun 23 05:50:12 PM PDT 24
Peak memory 224748 kb
Host smart-d0e0c4e4-fb09-4ab9-84cf-e040cb2ce4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369106209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
369106209
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3067978570
Short name T383
Test name
Test status
Simulation time 1998639904 ps
CPU time 2.25 seconds
Started Jun 23 05:50:05 PM PDT 24
Finished Jun 23 05:50:07 PM PDT 24
Peak memory 223176 kb
Host smart-80995548-5631-48ba-aaa4-0ea00fd3f76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067978570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3067978570
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3362631247
Short name T633
Test name
Test status
Simulation time 1102062208 ps
CPU time 4.45 seconds
Started Jun 23 05:50:01 PM PDT 24
Finished Jun 23 05:50:07 PM PDT 24
Peak memory 219368 kb
Host smart-9c997c6e-bb1d-4c01-af62-27e3b1926cb0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3362631247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3362631247
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1365312526
Short name T16
Test name
Test status
Simulation time 22988971743 ps
CPU time 315.43 seconds
Started Jun 23 05:50:09 PM PDT 24
Finished Jun 23 05:55:25 PM PDT 24
Peak memory 274056 kb
Host smart-a3710a2a-f1cb-4dba-934a-a6bc2c6253ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365312526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1365312526
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2441712920
Short name T314
Test name
Test status
Simulation time 5099645913 ps
CPU time 13.64 seconds
Started Jun 23 05:50:04 PM PDT 24
Finished Jun 23 05:50:18 PM PDT 24
Peak memory 220364 kb
Host smart-99a4ec7a-21b2-427c-8266-e5ebf4e765b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441712920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2441712920
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3767511182
Short name T823
Test name
Test status
Simulation time 4062383406 ps
CPU time 14.26 seconds
Started Jun 23 05:49:58 PM PDT 24
Finished Jun 23 05:50:13 PM PDT 24
Peak memory 216536 kb
Host smart-24374672-bb3b-40e0-a6e5-0b171123f838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767511182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3767511182
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1249080993
Short name T811
Test name
Test status
Simulation time 300115035 ps
CPU time 3.33 seconds
Started Jun 23 05:50:02 PM PDT 24
Finished Jun 23 05:50:06 PM PDT 24
Peak memory 216280 kb
Host smart-714c8743-240e-4ddd-87cd-184da69b02c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249080993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1249080993
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.744254669
Short name T782
Test name
Test status
Simulation time 30317720 ps
CPU time 0.84 seconds
Started Jun 23 05:50:03 PM PDT 24
Finished Jun 23 05:50:04 PM PDT 24
Peak memory 206028 kb
Host smart-f835079e-5bda-4de2-bda2-a3082e8b325b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744254669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.744254669
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3451272945
Short name T249
Test name
Test status
Simulation time 495507075 ps
CPU time 4.74 seconds
Started Jun 23 05:50:07 PM PDT 24
Finished Jun 23 05:50:12 PM PDT 24
Peak memory 232884 kb
Host smart-dff0dc40-2ee2-49f1-8c4e-10e942d06abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451272945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3451272945
Directory /workspace/9.spi_device_upload/latest
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