Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3784874	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4035380

1

T1

5441

T2

166

T3

1156

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4496856	1			T1	4773		T2	1		T3	500
values[0x0]	1661182	1			T1	2573		T2	92		T3	458
values[0x1]	1662216	1			T1	2682		T2	102		T3	457

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2680275	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5139979

1

T1

6751

T2

173

T3

1209

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	34326	1			T1	6		T5	18		T6	69
valid_sources[0x01]	31233	1			T1	47		T2	1		T4	7
valid_sources[0x02]	28545	1			T1	32		T4	8		T6	66
valid_sources[0x03]	41944	1			T1	81		T5	196		T6	56
valid_sources[0x04]	28839	1			T1	54		T4	16		T5	64
valid_sources[0x05]	29834	1			T1	2		T2	2		T6	66
valid_sources[0x06]	26924	1			T1	11		T4	7		T5	153
valid_sources[0x07]	28735	1			T4	1		T5	5		T6	54
valid_sources[0x08]	29393	1			T1	7		T3	421		T4	1
valid_sources[0x09]	31492	1			T1	17		T4	1		T5	98
valid_sources[0x0a]	29907	1			T1	168		T2	4		T4	1
valid_sources[0x0b]	29928	1			T1	46		T2	1		T4	5
valid_sources[0x0c]	27565	1			T1	58		T5	64		T6	83
valid_sources[0x0d]	33837	1			T1	34		T4	3		T5	51
valid_sources[0x0e]	33131	1			T1	17		T2	3		T5	44
valid_sources[0x0f]	33129	1			T1	26		T4	6		T5	42
valid_sources[0x10]	30457	1			T1	16		T2	1		T4	6
valid_sources[0x11]	29623	1			T1	13		T5	35		T6	69
valid_sources[0x12]	36242	1			T1	23		T2	1		T5	51
valid_sources[0x13]	29688	1			T1	40		T4	3		T5	8
valid_sources[0x14]	30396	1			T2	2		T4	3		T5	826
valid_sources[0x15]	27921	1			T1	32		T5	33		T6	65
valid_sources[0x16]	36191	1			T1	15		T4	6		T5	3
valid_sources[0x17]	30352	1			T1	40		T5	90		T6	66
valid_sources[0x18]	34162	1			T1	1		T2	3		T5	1
valid_sources[0x19]	32201	1			T1	54		T4	15		T5	295
valid_sources[0x1a]	29523	1			T5	208		T6	58		T7	76
valid_sources[0x1b]	28302	1			T1	44		T4	5		T5	28
valid_sources[0x1c]	29549	1			T1	1		T2	2		T4	5
valid_sources[0x1d]	30385	1			T1	3		T2	1		T4	6
valid_sources[0x1e]	32212	1			T1	131		T4	7		T5	2
valid_sources[0x1f]	28618	1			T1	1		T2	4		T4	9
valid_sources[0x20]	27306	1			T2	2		T4	25		T5	154
valid_sources[0x21]	30722	1			T1	110		T2	1		T4	6
valid_sources[0x22]	27809	1			T1	33		T5	79		T6	52
valid_sources[0x23]	28368	1			T1	12		T4	3		T5	1
valid_sources[0x24]	28994	1			T1	102		T4	2		T5	15
valid_sources[0x25]	28886	1			T1	3		T2	1		T5	35
valid_sources[0x26]	30490	1			T4	7		T5	8		T6	65
valid_sources[0x27]	27495	1			T1	74		T2	1		T5	163
valid_sources[0x28]	30787	1			T1	67		T2	1		T4	3
valid_sources[0x29]	33137	1			T1	12		T3	59		T4	20
valid_sources[0x2a]	29916	1			T1	86		T2	1		T4	9
valid_sources[0x2b]	29432	1			T1	79		T4	6		T5	23
valid_sources[0x2c]	30373	1			T1	49		T2	2		T4	4
valid_sources[0x2d]	32633	1			T2	1		T4	12		T5	50
valid_sources[0x2e]	29564	1			T1	7		T4	5		T5	493
valid_sources[0x2f]	29765	1			T1	9		T4	6		T5	49
valid_sources[0x30]	27740	1			T1	11		T2	1		T4	4
valid_sources[0x31]	32204	1			T1	95		T4	1		T5	150
valid_sources[0x32]	28145	1			T4	10		T5	8		T6	72
valid_sources[0x33]	27745	1			T1	51		T4	4		T5	125
valid_sources[0x34]	31432	1			T1	19		T2	1		T5	123
valid_sources[0x35]	28970	1			T1	56		T4	13		T5	157
valid_sources[0x36]	29788	1			T1	74		T4	4		T6	52
valid_sources[0x37]	28787	1			T1	8		T4	16		T5	34
valid_sources[0x38]	31156	1			T1	2		T2	2		T4	5
valid_sources[0x39]	30010	1			T1	6		T4	9		T5	54
valid_sources[0x3a]	28609	1			T1	9		T4	6		T5	9
valid_sources[0x3b]	29499	1			T1	33		T2	2		T3	37
valid_sources[0x3c]	28698	1			T1	6		T5	48		T6	69
valid_sources[0x3d]	29861	1			T1	37		T5	1		T6	73
valid_sources[0x3e]	34005	1			T1	82		T5	172		T6	76
valid_sources[0x3f]	28657	1			T1	2		T4	7		T5	67
valid_sources[0x40]	30475	1			T1	32		T4	7		T5	3
valid_sources[0x41]	29612	1			T4	11		T5	91		T6	62
valid_sources[0x42]	28898	1			T1	60		T5	54		T6	50
valid_sources[0x43]	28428	1			T1	26		T2	1		T4	2
valid_sources[0x44]	35285	1			T1	37		T2	1		T4	10
valid_sources[0x45]	28998	1			T2	4		T4	2		T5	1
valid_sources[0x46]	26629	1			T1	9		T4	6		T6	53
valid_sources[0x47]	29534	1			T1	40		T4	12		T5	3
valid_sources[0x48]	27105	1			T1	22		T4	15		T5	86
valid_sources[0x49]	29162	1			T1	25		T4	3		T5	26
valid_sources[0x4a]	29407	1			T1	47		T2	2		T4	3
valid_sources[0x4b]	28835	1			T1	64		T2	1		T5	43
valid_sources[0x4c]	28367	1			T1	10		T4	5		T6	71
valid_sources[0x4d]	30577	1			T1	5		T2	1		T4	7
valid_sources[0x4e]	27248	1			T1	6		T4	1		T5	43
valid_sources[0x4f]	28877	1			T1	138		T5	47		T6	56
valid_sources[0x50]	29299	1			T1	61		T5	23		T6	78
valid_sources[0x51]	30500	1			T1	36		T2	2		T4	16
valid_sources[0x52]	38243	1			T2	3		T4	1		T5	82
valid_sources[0x53]	29010	1			T1	80		T4	4		T5	1
valid_sources[0x54]	30941	1			T1	51		T6	61		T7	32
valid_sources[0x55]	45744	1			T1	48		T4	3		T5	65
valid_sources[0x56]	34666	1			T1	10		T2	1		T4	4
valid_sources[0x57]	27859	1			T1	1		T4	4		T5	2
valid_sources[0x58]	39583	1			T1	48		T4	3		T5	38
valid_sources[0x59]	26685	1			T1	27		T4	4		T6	70
valid_sources[0x5a]	29587	1			T1	3		T4	3		T5	23
valid_sources[0x5b]	31281	1			T1	14		T2	5		T5	283
valid_sources[0x5c]	31222	1			T1	55		T2	4		T4	7
valid_sources[0x5d]	28853	1			T1	50		T4	18		T5	27
valid_sources[0x5e]	28394	1			T1	56		T2	7		T4	3
valid_sources[0x5f]	31901	1			T1	6		T2	1		T4	11
valid_sources[0x60]	32070	1			T1	78		T4	2		T5	593
valid_sources[0x61]	27978	1			T1	146		T4	4		T5	189
valid_sources[0x62]	31205	1			T1	46		T2	2		T4	2
valid_sources[0x63]	33659	1			T1	5		T2	3		T4	2
valid_sources[0x64]	29047	1			T1	130		T2	4		T5	75
valid_sources[0x65]	32929	1			T1	4		T4	2		T5	221
valid_sources[0x66]	28827	1			T1	52		T4	4		T5	1
valid_sources[0x67]	28047	1			T2	1		T4	8		T5	4
valid_sources[0x68]	32363	1			T1	32		T2	1		T4	1
valid_sources[0x69]	30747	1			T1	30		T2	1		T4	5
valid_sources[0x6a]	28393	1			T1	22		T2	1		T4	1
valid_sources[0x6b]	28710	1			T1	84		T4	4		T5	3
valid_sources[0x6c]	61227	1			T2	1		T4	1		T6	53
valid_sources[0x6d]	29342	1			T1	42		T2	1		T4	9
valid_sources[0x6e]	33466	1			T4	1		T5	97		T6	55
valid_sources[0x6f]	28756	1			T1	40		T6	62		T7	46
valid_sources[0x70]	36791	1			T1	38		T5	6		T6	59
valid_sources[0x71]	26947	1			T2	2		T4	1		T5	226
valid_sources[0x72]	27853	1			T1	55		T5	1		T6	68
valid_sources[0x73]	33610	1			T1	116		T4	3		T5	1
valid_sources[0x74]	30629	1			T1	5		T5	21		T6	71
valid_sources[0x75]	35612	1			T1	110		T4	9		T5	11
valid_sources[0x76]	30678	1			T1	33		T4	3		T5	8
valid_sources[0x77]	28062	1			T3	454		T5	173		T6	71
valid_sources[0x78]	29106	1			T1	86		T2	1		T4	7
valid_sources[0x79]	30155	1			T1	22		T2	1		T4	6
valid_sources[0x7a]	27360	1			T1	125		T4	6		T5	14
valid_sources[0x7b]	33009	1			T2	2		T4	3		T5	24
valid_sources[0x7c]	28380	1			T1	2		T5	3		T6	46
valid_sources[0x7d]	38898	1			T1	35		T4	4		T6	60
valid_sources[0x7e]	27657	1			T1	17		T2	5		T4	6
valid_sources[0x7f]	33139	1			T1	60		T2	2		T4	6
valid_sources[0x80]	28063	1			T2	1		T4	2		T5	57

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1054147

1

T1

1114

T2

1

T3

247

values[0x0]

all_enables

biggest_size

1502605

1

T1

2141

T2

81

T3

458

values[0x1]

all_enables

biggest_size

1478628

1

T1

2186

T2

84

T3

451