Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3806107

1

T1

4587

T2

29

T3

259

full_word

4036628

1

T1

5441

T2

166

T3

1156

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7842325	1			T1	10028		T2	195		T3	1415
auto[TlIntgErrCmd]	140	1			T67	9		T94	13		T95	3
auto[TlIntgErrData]	141	1			T67	13		T94	10		T95	5
auto[TlIntgErrBoth]	129	1			T67	8		T94	7		T95	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4500591

1

T1

4773

T2

1

T3

500

auto[1]

3342144

1

T1

5255

T2

194

T3

915

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3445973	1			T1	3659		T3	253		T4	195
auto[TlIntgErrNone]	partial	auto[1]	359759	1			T1	928		T2	29		T3	6
auto[TlIntgErrNone]	full_word	auto[0]	1054443	1			T1	1114		T2	1		T3	247
auto[TlIntgErrNone]	full_word	auto[1]	2982150	1			T1	4327		T2	165		T3	909
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T67	4		T94	5		T95	1
auto[TlIntgErrCmd]	partial	auto[1]	83	1			T67	5		T94	8		T95	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T112	1		T187	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T111	1		T163	2		T164	1
auto[TlIntgErrData]	partial	auto[0]	67	1			T67	8		T94	6		T95	1
auto[TlIntgErrData]	partial	auto[1]	59	1			T67	5		T94	1		T95	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T94	1		T161	1		T188	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T94	2		T95	1		T111	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T94	4		T95	2		T111	2
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T67	8		T94	2		T111	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T111	1		T186	1		T189	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T94	1		T164	1		T187	1