Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	541629489	2912447	0	0
gen_wmask[1].MaskCheckPortA_A	541629489	2912447	0	0
gen_wmask[2].MaskCheckPortA_A	541629489	2912447	0	0
gen_wmask[3].MaskCheckPortA_A	541629489	2912447	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541629489	2912447	0	0
T1	621535	8737	0	0
T2	81800	0	0	0
T3	26482	832	0	0
T4	322734	832	0	0
T5	1302420	20372	0	0
T6	1190558	11167	0	0
T7	151406	832	0	0
T8	586206	832	0	0
T9	81166	832	0	0
T10	41732	832	0	0
T12	0	6916	0	0
T22	0	4341	0	0
T31	0	104	0	0
T33	0	5278	0	0
T35	0	1068	0	0
T36	0	3	0	0
T40	0	16177	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541629489	2912447	0	0
T1	621535	8737	0	0
T2	81800	0	0	0
T3	26482	832	0	0
T4	322734	832	0	0
T5	1302420	20372	0	0
T6	1190558	11167	0	0
T7	151406	832	0	0
T8	586206	832	0	0
T9	81166	832	0	0
T10	41732	832	0	0
T12	0	6916	0	0
T22	0	4341	0	0
T31	0	104	0	0
T33	0	5278	0	0
T35	0	1068	0	0
T36	0	3	0	0
T40	0	16177	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541629489	2912447	0	0
T1	621535	8737	0	0
T2	81800	0	0	0
T3	26482	832	0	0
T4	322734	832	0	0
T5	1302420	20372	0	0
T6	1190558	11167	0	0
T7	151406	832	0	0
T8	586206	832	0	0
T9	81166	832	0	0
T10	41732	832	0	0
T12	0	6916	0	0
T22	0	4341	0	0
T31	0	104	0	0
T33	0	5278	0	0
T35	0	1068	0	0
T36	0	3	0	0
T40	0	16177	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541629489	2912447	0	0
T1	621535	8737	0	0
T2	81800	0	0	0
T3	26482	832	0	0
T4	322734	832	0	0
T5	1302420	20372	0	0
T6	1190558	11167	0	0
T7	151406	832	0	0
T8	586206	832	0	0
T9	81166	832	0	0
T10	41732	832	0	0
T12	0	6916	0	0
T22	0	4341	0	0
T31	0	104	0	0
T33	0	5278	0	0
T35	0	1068	0	0
T36	0	3	0	0
T40	0	16177	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	408910168	1809582	0	0
gen_wmask[1].MaskCheckPortA_A	408910168	1809582	0	0
gen_wmask[2].MaskCheckPortA_A	408910168	1809582	0	0
gen_wmask[3].MaskCheckPortA_A	408910168	1809582	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408910168	1809582	0	0
T1	317016	2785	0	0
T2	42721	0	0	0
T3	22066	832	0	0
T4	287304	832	0	0
T5	305173	11889	0	0
T6	409157	7660	0	0
T7	135008	832	0	0
T8	469677	832	0	0
T9	42502	832	0	0
T10	36244	832	0	0
T31	0	3	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408910168	1809582	0	0
T1	317016	2785	0	0
T2	42721	0	0	0
T3	22066	832	0	0
T4	287304	832	0	0
T5	305173	11889	0	0
T6	409157	7660	0	0
T7	135008	832	0	0
T8	469677	832	0	0
T9	42502	832	0	0
T10	36244	832	0	0
T31	0	3	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408910168	1809582	0	0
T1	317016	2785	0	0
T2	42721	0	0	0
T3	22066	832	0	0
T4	287304	832	0	0
T5	305173	11889	0	0
T6	409157	7660	0	0
T7	135008	832	0	0
T8	469677	832	0	0
T9	42502	832	0	0
T10	36244	832	0	0
T31	0	3	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408910168	1809582	0	0
T1	317016	2785	0	0
T2	42721	0	0	0
T3	22066	832	0	0
T4	287304	832	0	0
T5	305173	11889	0	0
T6	409157	7660	0	0
T7	135008	832	0	0
T8	469677	832	0	0
T9	42502	832	0	0
T10	36244	832	0	0
T31	0	3	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	132719321	1102865	0	0
gen_wmask[1].MaskCheckPortA_A	132719321	1102865	0	0
gen_wmask[2].MaskCheckPortA_A	132719321	1102865	0	0
gen_wmask[3].MaskCheckPortA_A	132719321	1102865	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	1102865	0	0
T1	304519	5952	0	0
T2	39079	0	0	0
T3	4416	0	0	0
T4	35430	0	0	0
T5	997247	8483	0	0
T6	781401	3507	0	0
T7	16398	0	0	0
T8	116529	0	0	0
T9	38664	0	0	0
T10	5488	0	0	0
T12	0	6916	0	0
T22	0	4341	0	0
T31	0	101	0	0
T33	0	5278	0	0
T35	0	1068	0	0
T36	0	3	0	0
T40	0	16177	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	1102865	0	0
T1	304519	5952	0	0
T2	39079	0	0	0
T3	4416	0	0	0
T4	35430	0	0	0
T5	997247	8483	0	0
T6	781401	3507	0	0
T7	16398	0	0	0
T8	116529	0	0	0
T9	38664	0	0	0
T10	5488	0	0	0
T12	0	6916	0	0
T22	0	4341	0	0
T31	0	101	0	0
T33	0	5278	0	0
T35	0	1068	0	0
T36	0	3	0	0
T40	0	16177	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	1102865	0	0
T1	304519	5952	0	0
T2	39079	0	0	0
T3	4416	0	0	0
T4	35430	0	0	0
T5	997247	8483	0	0
T6	781401	3507	0	0
T7	16398	0	0	0
T8	116529	0	0	0
T9	38664	0	0	0
T10	5488	0	0	0
T12	0	6916	0	0
T22	0	4341	0	0
T31	0	101	0	0
T33	0	5278	0	0
T35	0	1068	0	0
T36	0	3	0	0
T40	0	16177	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	1102865	0	0
T1	304519	5952	0	0
T2	39079	0	0	0
T3	4416	0	0	0
T4	35430	0	0	0
T5	997247	8483	0	0
T6	781401	3507	0	0
T7	16398	0	0	0
T8	116529	0	0	0
T9	38664	0	0	0
T10	5488	0	0	0
T12	0	6916	0	0
T22	0	4341	0	0
T31	0	101	0	0
T33	0	5278	0	0
T35	0	1068	0	0
T36	0	3	0	0
T40	0	16177	0	0