Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411185669	2481511	0	0
DepthKnown_A	411185669	411054559	0	0
RvalidKnown_A	411185669	411054559	0	0
WreadyKnown_A	411185669	411054559	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	2481511	0	0
T1	317016	2495	0	0
T2	42721	0	0	0
T3	22066	1663	0	0
T4	287304	1663	0	0
T5	305173	14142	0	0
T6	409157	10819	0	0
T7	135008	1663	0	0
T8	469677	1671	0	0
T9	42502	832	0	0
T10	36244	1663	0	0
T11	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	411054559	0	0
T1	317016	316936	0	0
T2	42721	42629	0	0
T3	22066	21978	0	0
T4	287304	287239	0	0
T5	305173	305096	0	0
T6	409157	409090	0	0
T7	135008	134940	0	0
T8	469677	469597	0	0
T9	42502	42405	0	0
T10	36244	36164	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	411054559	0	0
T1	317016	316936	0	0
T2	42721	42629	0	0
T3	22066	21978	0	0
T4	287304	287239	0	0
T5	305173	305096	0	0
T6	409157	409090	0	0
T7	135008	134940	0	0
T8	469677	469597	0	0
T9	42502	42405	0	0
T10	36244	36164	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	411054559	0	0
T1	317016	316936	0	0
T2	42721	42629	0	0
T3	22066	21978	0	0
T4	287304	287239	0	0
T5	305173	305096	0	0
T6	409157	409090	0	0
T7	135008	134940	0	0
T8	469677	469597	0	0
T9	42502	42405	0	0
T10	36244	36164	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411185669	2761409	0	0
DepthKnown_A	411185669	411054559	0	0
RvalidKnown_A	411185669	411054559	0	0
WreadyKnown_A	411185669	411054559	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	2761409	0	0
T1	317016	1664	0	0
T2	42721	0	0	0
T3	22066	832	0	0
T4	287304	832	0	0
T5	305173	31587	0	0
T6	409157	11936	0	0
T7	135008	832	0	0
T8	469677	840	0	0
T9	42502	832	0	0
T10	36244	832	0	0
T11	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	411054559	0	0
T1	317016	316936	0	0
T2	42721	42629	0	0
T3	22066	21978	0	0
T4	287304	287239	0	0
T5	305173	305096	0	0
T6	409157	409090	0	0
T7	135008	134940	0	0
T8	469677	469597	0	0
T9	42502	42405	0	0
T10	36244	36164	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	411054559	0	0
T1	317016	316936	0	0
T2	42721	42629	0	0
T3	22066	21978	0	0
T4	287304	287239	0	0
T5	305173	305096	0	0
T6	409157	409090	0	0
T7	135008	134940	0	0
T8	469677	469597	0	0
T9	42502	42405	0	0
T10	36244	36164	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	411054559	0	0
T1	317016	316936	0	0
T2	42721	42629	0	0
T3	22066	21978	0	0
T4	287304	287239	0	0
T5	305173	305096	0	0
T6	409157	409090	0	0
T7	135008	134940	0	0
T8	469677	469597	0	0
T9	42502	42405	0	0
T10	36244	36164	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411185669	173114	0	0
DepthKnown_A	411185669	411054559	0	0
RvalidKnown_A	411185669	411054559	0	0
WreadyKnown_A	411185669	411054559	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	173114	0	0
T1	317016	811	0	0
T2	42721	0	0	0
T3	22066	0	0	0
T4	287304	0	0	0
T5	305173	1506	0	0
T6	409157	842	0	0
T7	135008	0	0	0
T8	469677	0	0	0
T9	42502	0	0	0
T10	36244	0	0	0
T12	0	870	0	0
T22	0	739	0	0
T31	0	26	0	0
T33	0	681	0	0
T35	0	275	0	0
T36	0	1	0	0
T40	0	772	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	411054559	0	0
T1	317016	316936	0	0
T2	42721	42629	0	0
T3	22066	21978	0	0
T4	287304	287239	0	0
T5	305173	305096	0	0
T6	409157	409090	0	0
T7	135008	134940	0	0
T8	469677	469597	0	0
T9	42502	42405	0	0
T10	36244	36164	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	411054559	0	0
T1	317016	316936	0	0
T2	42721	42629	0	0
T3	22066	21978	0	0
T4	287304	287239	0	0
T5	305173	305096	0	0
T6	409157	409090	0	0
T7	135008	134940	0	0
T8	469677	469597	0	0
T9	42502	42405	0	0
T10	36244	36164	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	411054559	0	0
T1	317016	316936	0	0
T2	42721	42629	0	0
T3	22066	21978	0	0
T4	287304	287239	0	0
T5	305173	305096	0	0
T6	409157	409090	0	0
T7	135008	134940	0	0
T8	469677	469597	0	0
T9	42502	42405	0	0
T10	36244	36164	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411185669	389126	0	0
DepthKnown_A	411185669	411054559	0	0
RvalidKnown_A	411185669	411054559	0	0
WreadyKnown_A	411185669	411054559	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	389126	0	0
T1	317016	3526	0	0
T2	42721	0	0	0
T3	22066	0	0	0
T4	287304	0	0	0
T5	305173	6716	0	0
T6	409157	2638	0	0
T7	135008	0	0	0
T8	469677	0	0	0
T9	42502	0	0	0
T10	36244	0	0	0
T12	0	870	0	0
T22	0	2309	0	0
T31	0	26	0	0
T33	0	681	0	0
T35	0	275	0	0
T36	0	1	0	0
T40	0	772	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	411054559	0	0
T1	317016	316936	0	0
T2	42721	42629	0	0
T3	22066	21978	0	0
T4	287304	287239	0	0
T5	305173	305096	0	0
T6	409157	409090	0	0
T7	135008	134940	0	0
T8	469677	469597	0	0
T9	42502	42405	0	0
T10	36244	36164	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	411054559	0	0
T1	317016	316936	0	0
T2	42721	42629	0	0
T3	22066	21978	0	0
T4	287304	287239	0	0
T5	305173	305096	0	0
T6	409157	409090	0	0
T7	135008	134940	0	0
T8	469677	469597	0	0
T9	42502	42405	0	0
T10	36244	36164	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	411054559	0	0
T1	317016	316936	0	0
T2	42721	42629	0	0
T3	22066	21978	0	0
T4	287304	287239	0	0
T5	305173	305096	0	0
T6	409157	409090	0	0
T7	135008	134940	0	0
T8	469677	469597	0	0
T9	42502	42405	0	0
T10	36244	36164	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411185669	6476111	0	0
DepthKnown_A	411185669	411054559	0	0
RvalidKnown_A	411185669	411054559	0	0
WreadyKnown_A	411185669	411054559	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	6476111	0	0
T1	317016	8321	0	0
T2	42721	195	0	0
T3	22066	587	0	0
T4	287304	443	0	0
T5	305173	9887	0	0
T6	409157	9548	0	0
T7	135008	6192	0	0
T8	469677	66	0	0
T9	42502	2212	0	0
T10	36244	1847	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	411054559	0	0
T1	317016	316936	0	0
T2	42721	42629	0	0
T3	22066	21978	0	0
T4	287304	287239	0	0
T5	305173	305096	0	0
T6	409157	409090	0	0
T7	135008	134940	0	0
T8	469677	469597	0	0
T9	42502	42405	0	0
T10	36244	36164	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	411054559	0	0
T1	317016	316936	0	0
T2	42721	42629	0	0
T3	22066	21978	0	0
T4	287304	287239	0	0
T5	305173	305096	0	0
T6	409157	409090	0	0
T7	135008	134940	0	0
T8	469677	469597	0	0
T9	42502	42405	0	0
T10	36244	36164	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	411054559	0	0
T1	317016	316936	0	0
T2	42721	42629	0	0
T3	22066	21978	0	0
T4	287304	287239	0	0
T5	305173	305096	0	0
T6	409157	409090	0	0
T7	135008	134940	0	0
T8	469677	469597	0	0
T9	42502	42405	0	0
T10	36244	36164	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411185669	13722837	0	0
DepthKnown_A	411185669	411054559	0	0
RvalidKnown_A	411185669	411054559	0	0
WreadyKnown_A	411185669	411054559	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	13722837	0	0
T1	317016	28666	0	0
T2	42721	195	0	0
T3	22066	1755	0	0
T4	287304	442	0	0
T5	305173	38699	0	0
T6	409157	27840	0	0
T7	135008	6192	0	0
T8	469677	263	0	0
T9	42502	2212	0	0
T10	36244	1846	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	411054559	0	0
T1	317016	316936	0	0
T2	42721	42629	0	0
T3	22066	21978	0	0
T4	287304	287239	0	0
T5	305173	305096	0	0
T6	409157	409090	0	0
T7	135008	134940	0	0
T8	469677	469597	0	0
T9	42502	42405	0	0
T10	36244	36164	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	411054559	0	0
T1	317016	316936	0	0
T2	42721	42629	0	0
T3	22066	21978	0	0
T4	287304	287239	0	0
T5	305173	305096	0	0
T6	409157	409090	0	0
T7	135008	134940	0	0
T8	469677	469597	0	0
T9	42502	42405	0	0
T10	36244	36164	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411185669	411054559	0	0
T1	317016	316936	0	0
T2	42721	42629	0	0
T3	22066	21978	0	0
T4	287304	287239	0	0
T5	305173	305096	0	0
T6	409157	409090	0	0
T7	135008	134940	0	0
T8	469677	469597	0	0
T9	42502	42405	0	0
T10	36244	36164	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0