Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Unreachable
1	1	Covered	T1,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T1,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	674348810	540291543	0	0
CheckNGreaterZero_A	2718	2718	0	0
GntImpliesReady_A	674348810	3279722	0	0
GntImpliesValid_A	674348810	3279722	0	0
GrantKnown_A	674348810	540291543	0	0
IdxKnown_A	674348810	540291543	0	0
IndexIsCorrect_A	674348810	3279722	0	0
LockArbDecision_A	674348810	0	0	0
NoReadyValidNoGrant_A	674348810	0	0	0
ReadyAndValidImplyGrant_A	674348810	3279722	0	0
ReqAndReadyImplyGrant_A	674348810	3279722	0	0
ReqImpliesValid_A	674348810	3279722	0	0
ReqStaysHighUntilGranted0_M	674348810	0	0	0
RoundRobin_A	674348810	4	0	906
ValidKnown_A	674348810	540291543	0	0
gen_data_port_assertion.DataFlow_A	674348810	3279722	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674348810	540291543	0	0
T1	926054	617707	0	0
T2	120879	79893	0	0
T3	30898	26394	0	0
T4	358164	322669	0	0
T5	2299667	1293744	0	0
T6	1971959	1184363	0	0
T7	167804	151338	0	0
T8	702735	585973	0	0
T9	119830	80925	0	0
T10	47220	41652	0	0
T11	0	8759	0	0
T12	0	461688	0	0
T31	0	1360	0	0
T32	0	26632	0	0
T33	0	31328	0	0
T35	0	31288	0	0
T36	0	64	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2718	2718	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674348810	3279722	0	0
T1	926054	10781	0	0
T2	120879	0	0	0
T3	30898	832	0	0
T4	358164	832	0	0
T5	2299667	23912	0	0
T6	1971959	13137	0	0
T7	167804	832	0	0
T8	702735	832	0	0
T9	119830	832	0	0
T10	47220	832	0	0
T12	0	8437	0	0
T22	0	5410	0	0
T23	0	6680	0	0
T31	0	135	0	0
T33	0	5786	0	0
T35	0	1429	0	0
T36	0	3	0	0
T40	0	16177	0	0
T44	0	6113	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674348810	3279722	0	0
T1	926054	10781	0	0
T2	120879	0	0	0
T3	30898	832	0	0
T4	358164	832	0	0
T5	2299667	23912	0	0
T6	1971959	13137	0	0
T7	167804	832	0	0
T8	702735	832	0	0
T9	119830	832	0	0
T10	47220	832	0	0
T12	0	8437	0	0
T22	0	5410	0	0
T23	0	6680	0	0
T31	0	135	0	0
T33	0	5786	0	0
T35	0	1429	0	0
T36	0	3	0	0
T40	0	16177	0	0
T44	0	6113	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674348810	540291543	0	0
T1	926054	617707	0	0
T2	120879	79893	0	0
T3	30898	26394	0	0
T4	358164	322669	0	0
T5	2299667	1293744	0	0
T6	1971959	1184363	0	0
T7	167804	151338	0	0
T8	702735	585973	0	0
T9	119830	80925	0	0
T10	47220	41652	0	0
T11	0	8759	0	0
T12	0	461688	0	0
T31	0	1360	0	0
T32	0	26632	0	0
T33	0	31328	0	0
T35	0	31288	0	0
T36	0	64	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674348810	540291543	0	0
T1	926054	617707	0	0
T2	120879	79893	0	0
T3	30898	26394	0	0
T4	358164	322669	0	0
T5	2299667	1293744	0	0
T6	1971959	1184363	0	0
T7	167804	151338	0	0
T8	702735	585973	0	0
T9	119830	80925	0	0
T10	47220	41652	0	0
T11	0	8759	0	0
T12	0	461688	0	0
T31	0	1360	0	0
T32	0	26632	0	0
T33	0	31328	0	0
T35	0	31288	0	0
T36	0	64	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674348810	3279722	0	0
T1	926054	10781	0	0
T2	120879	0	0	0
T3	30898	832	0	0
T4	358164	832	0	0
T5	2299667	23912	0	0
T6	1971959	13137	0	0
T7	167804	832	0	0
T8	702735	832	0	0
T9	119830	832	0	0
T10	47220	832	0	0
T12	0	8437	0	0
T22	0	5410	0	0
T23	0	6680	0	0
T31	0	135	0	0
T33	0	5786	0	0
T35	0	1429	0	0
T36	0	3	0	0
T40	0	16177	0	0
T44	0	6113	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674348810	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674348810	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674348810	3279722	0	0
T1	926054	10781	0	0
T2	120879	0	0	0
T3	30898	832	0	0
T4	358164	832	0	0
T5	2299667	23912	0	0
T6	1971959	13137	0	0
T7	167804	832	0	0
T8	702735	832	0	0
T9	119830	832	0	0
T10	47220	832	0	0
T12	0	8437	0	0
T22	0	5410	0	0
T23	0	6680	0	0
T31	0	135	0	0
T33	0	5786	0	0
T35	0	1429	0	0
T36	0	3	0	0
T40	0	16177	0	0
T44	0	6113	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674348810	3279722	0	0
T1	926054	10781	0	0
T2	120879	0	0	0
T3	30898	832	0	0
T4	358164	832	0	0
T5	2299667	23912	0	0
T6	1971959	13137	0	0
T7	167804	832	0	0
T8	702735	832	0	0
T9	119830	832	0	0
T10	47220	832	0	0
T12	0	8437	0	0
T22	0	5410	0	0
T23	0	6680	0	0
T31	0	135	0	0
T33	0	5786	0	0
T35	0	1429	0	0
T36	0	3	0	0
T40	0	16177	0	0
T44	0	6113	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674348810	3279722	0	0
T1	926054	10781	0	0
T2	120879	0	0	0
T3	30898	832	0	0
T4	358164	832	0	0
T5	2299667	23912	0	0
T6	1971959	13137	0	0
T7	167804	832	0	0
T8	702735	832	0	0
T9	119830	832	0	0
T10	47220	832	0	0
T12	0	8437	0	0
T22	0	5410	0	0
T23	0	6680	0	0
T31	0	135	0	0
T33	0	5786	0	0
T35	0	1429	0	0
T36	0	3	0	0
T40	0	16177	0	0
T44	0	6113	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	674348810	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674348810	4	0	906
T49	350708	1	0	1
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	200844	0	0	1
T54	138554	0	0	1
T55	429818	0	0	1
T56	317177	0	0	1
T57	548187	0	0	1
T58	8604	0	0	1
T59	568460	0	0	1
T60	48639	0	0	1
T61	687524	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674348810	540291543	0	0
T1	926054	617707	0	0
T2	120879	79893	0	0
T3	30898	26394	0	0
T4	358164	322669	0	0
T5	2299667	1293744	0	0
T6	1971959	1184363	0	0
T7	167804	151338	0	0
T8	702735	585973	0	0
T9	119830	80925	0	0
T10	47220	41652	0	0
T11	0	8759	0	0
T12	0	461688	0	0
T31	0	1360	0	0
T32	0	26632	0	0
T33	0	31328	0	0
T35	0	31288	0	0
T36	0	64	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674348810	3279722	0	0
T1	926054	10781	0	0
T2	120879	0	0	0
T3	30898	832	0	0
T4	358164	832	0	0
T5	2299667	23912	0	0
T6	1971959	13137	0	0
T7	167804	832	0	0
T8	702735	832	0	0
T9	119830	832	0	0
T10	47220	832	0	0
T12	0	8437	0	0
T22	0	5410	0	0
T23	0	6680	0	0
T31	0	135	0	0
T33	0	5786	0	0
T35	0	1429	0	0
T36	0	3	0	0
T40	0	16177	0	0
T44	0	6113	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Unreachable
1	1	Covered	T1,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	132719321	26868548	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	132719321	608886	0	0
GntImpliesValid_A	132719321	608886	0	0
GrantKnown_A	132719321	26868548	0	0
IdxKnown_A	132719321	26868548	0	0
IndexIsCorrect_A	132719321	608886	0	0
LockArbDecision_A	132719321	0	0	0
NoReadyValidNoGrant_A	132719321	0	0	0
ReadyAndValidImplyGrant_A	132719321	608886	0	0
ReqAndReadyImplyGrant_A	132719321	608886	0	0
ReqImpliesValid_A	132719321	608886	0	0
ReqStaysHighUntilGranted0_M	132719321	0	0	0
RoundRobin_A	132719321	0	0	0
ValidKnown_A	132719321	26868548	0	0
gen_data_port_assertion.DataFlow_A	132719321	608886	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	26868548	0	0
T1	304519	160368	0	0
T2	39079	37264	0	0
T3	4416	0	0	0
T4	35430	0	0	0
T5	997247	580512	0	0
T6	781401	214208	0	0
T7	16398	0	0	0
T8	116529	0	0	0
T9	38664	0	0	0
T10	5488	0	0	0
T12	0	461688	0	0
T31	0	1360	0	0
T32	0	26632	0	0
T33	0	31328	0	0
T35	0	31288	0	0
T36	0	64	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	608886	0	0
T1	304519	3855	0	0
T2	39079	0	0	0
T3	4416	0	0	0
T4	35430	0	0	0
T5	997247	5007	0	0
T6	781401	3369	0	0
T7	16398	0	0	0
T8	116529	0	0	0
T9	38664	0	0	0
T10	5488	0	0	0
T12	0	4366	0	0
T22	0	3388	0	0
T23	0	4442	0	0
T31	0	106	0	0
T33	0	1549	0	0
T35	0	1171	0	0
T36	0	3	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	608886	0	0
T1	304519	3855	0	0
T2	39079	0	0	0
T3	4416	0	0	0
T4	35430	0	0	0
T5	997247	5007	0	0
T6	781401	3369	0	0
T7	16398	0	0	0
T8	116529	0	0	0
T9	38664	0	0	0
T10	5488	0	0	0
T12	0	4366	0	0
T22	0	3388	0	0
T23	0	4442	0	0
T31	0	106	0	0
T33	0	1549	0	0
T35	0	1171	0	0
T36	0	3	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	26868548	0	0
T1	304519	160368	0	0
T2	39079	37264	0	0
T3	4416	0	0	0
T4	35430	0	0	0
T5	997247	580512	0	0
T6	781401	214208	0	0
T7	16398	0	0	0
T8	116529	0	0	0
T9	38664	0	0	0
T10	5488	0	0	0
T12	0	461688	0	0
T31	0	1360	0	0
T32	0	26632	0	0
T33	0	31328	0	0
T35	0	31288	0	0
T36	0	64	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	26868548	0	0
T1	304519	160368	0	0
T2	39079	37264	0	0
T3	4416	0	0	0
T4	35430	0	0	0
T5	997247	580512	0	0
T6	781401	214208	0	0
T7	16398	0	0	0
T8	116529	0	0	0
T9	38664	0	0	0
T10	5488	0	0	0
T12	0	461688	0	0
T31	0	1360	0	0
T32	0	26632	0	0
T33	0	31328	0	0
T35	0	31288	0	0
T36	0	64	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	608886	0	0
T1	304519	3855	0	0
T2	39079	0	0	0
T3	4416	0	0	0
T4	35430	0	0	0
T5	997247	5007	0	0
T6	781401	3369	0	0
T7	16398	0	0	0
T8	116529	0	0	0
T9	38664	0	0	0
T10	5488	0	0	0
T12	0	4366	0	0
T22	0	3388	0	0
T23	0	4442	0	0
T31	0	106	0	0
T33	0	1549	0	0
T35	0	1171	0	0
T36	0	3	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	608886	0	0
T1	304519	3855	0	0
T2	39079	0	0	0
T3	4416	0	0	0
T4	35430	0	0	0
T5	997247	5007	0	0
T6	781401	3369	0	0
T7	16398	0	0	0
T8	116529	0	0	0
T9	38664	0	0	0
T10	5488	0	0	0
T12	0	4366	0	0
T22	0	3388	0	0
T23	0	4442	0	0
T31	0	106	0	0
T33	0	1549	0	0
T35	0	1171	0	0
T36	0	3	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	608886	0	0
T1	304519	3855	0	0
T2	39079	0	0	0
T3	4416	0	0	0
T4	35430	0	0	0
T5	997247	5007	0	0
T6	781401	3369	0	0
T7	16398	0	0	0
T8	116529	0	0	0
T9	38664	0	0	0
T10	5488	0	0	0
T12	0	4366	0	0
T22	0	3388	0	0
T23	0	4442	0	0
T31	0	106	0	0
T33	0	1549	0	0
T35	0	1171	0	0
T36	0	3	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	608886	0	0
T1	304519	3855	0	0
T2	39079	0	0	0
T3	4416	0	0	0
T4	35430	0	0	0
T5	997247	5007	0	0
T6	781401	3369	0	0
T7	16398	0	0	0
T8	116529	0	0	0
T9	38664	0	0	0
T10	5488	0	0	0
T12	0	4366	0	0
T22	0	3388	0	0
T23	0	4442	0	0
T31	0	106	0	0
T33	0	1549	0	0
T35	0	1171	0	0
T36	0	3	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	26868548	0	0
T1	304519	160368	0	0
T2	39079	37264	0	0
T3	4416	0	0	0
T4	35430	0	0	0
T5	997247	580512	0	0
T6	781401	214208	0	0
T7	16398	0	0	0
T8	116529	0	0	0
T9	38664	0	0	0
T10	5488	0	0	0
T12	0	461688	0	0
T31	0	1360	0	0
T32	0	26632	0	0
T33	0	31328	0	0
T35	0	31288	0	0
T36	0	64	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	608886	0	0
T1	304519	3855	0	0
T2	39079	0	0	0
T3	4416	0	0	0
T4	35430	0	0	0
T5	997247	5007	0	0
T6	781401	3369	0	0
T7	16398	0	0	0
T8	116529	0	0	0
T9	38664	0	0	0
T10	5488	0	0	0
T12	0	4366	0	0
T22	0	3388	0	0
T23	0	4442	0	0
T31	0	106	0	0
T33	0	1549	0	0
T35	0	1171	0	0
T36	0	3	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T1,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	132719321	104598055	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	132719321	696742	0	0
GntImpliesValid_A	132719321	696742	0	0
GrantKnown_A	132719321	104598055	0	0
IdxKnown_A	132719321	104598055	0	0
IndexIsCorrect_A	132719321	696742	0	0
LockArbDecision_A	132719321	0	0	0
NoReadyValidNoGrant_A	132719321	0	0	0
ReadyAndValidImplyGrant_A	132719321	696742	0	0
ReqAndReadyImplyGrant_A	132719321	696742	0	0
ReqImpliesValid_A	132719321	696742	0	0
ReqStaysHighUntilGranted0_M	132719321	0	0	0
RoundRobin_A	132719321	0	0	0
ValidKnown_A	132719321	104598055	0	0
gen_data_port_assertion.DataFlow_A	132719321	696742	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	104598055	0	0
T1	304519	140403	0	0
T2	39079	0	0	0
T3	4416	4416	0	0
T4	35430	35430	0	0
T5	997247	408136	0	0
T6	781401	561065	0	0
T7	16398	16398	0	0
T8	116529	116376	0	0
T9	38664	38520	0	0
T10	5488	5488	0	0
T11	0	8759	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	696742	0	0
T1	304519	3318	0	0
T2	39079	0	0	0
T3	4416	0	0	0
T4	35430	0	0	0
T5	997247	5553	0	0
T6	781401	1244	0	0
T7	16398	0	0	0
T8	116529	0	0	0
T9	38664	0	0	0
T10	5488	0	0	0
T12	0	4071	0	0
T22	0	2022	0	0
T23	0	2238	0	0
T33	0	4237	0	0
T35	0	258	0	0
T40	0	16177	0	0
T44	0	6113	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	696742	0	0
T1	304519	3318	0	0
T2	39079	0	0	0
T3	4416	0	0	0
T4	35430	0	0	0
T5	997247	5553	0	0
T6	781401	1244	0	0
T7	16398	0	0	0
T8	116529	0	0	0
T9	38664	0	0	0
T10	5488	0	0	0
T12	0	4071	0	0
T22	0	2022	0	0
T23	0	2238	0	0
T33	0	4237	0	0
T35	0	258	0	0
T40	0	16177	0	0
T44	0	6113	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	104598055	0	0
T1	304519	140403	0	0
T2	39079	0	0	0
T3	4416	4416	0	0
T4	35430	35430	0	0
T5	997247	408136	0	0
T6	781401	561065	0	0
T7	16398	16398	0	0
T8	116529	116376	0	0
T9	38664	38520	0	0
T10	5488	5488	0	0
T11	0	8759	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	104598055	0	0
T1	304519	140403	0	0
T2	39079	0	0	0
T3	4416	4416	0	0
T4	35430	35430	0	0
T5	997247	408136	0	0
T6	781401	561065	0	0
T7	16398	16398	0	0
T8	116529	116376	0	0
T9	38664	38520	0	0
T10	5488	5488	0	0
T11	0	8759	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	696742	0	0
T1	304519	3318	0	0
T2	39079	0	0	0
T3	4416	0	0	0
T4	35430	0	0	0
T5	997247	5553	0	0
T6	781401	1244	0	0
T7	16398	0	0	0
T8	116529	0	0	0
T9	38664	0	0	0
T10	5488	0	0	0
T12	0	4071	0	0
T22	0	2022	0	0
T23	0	2238	0	0
T33	0	4237	0	0
T35	0	258	0	0
T40	0	16177	0	0
T44	0	6113	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	696742	0	0
T1	304519	3318	0	0
T2	39079	0	0	0
T3	4416	0	0	0
T4	35430	0	0	0
T5	997247	5553	0	0
T6	781401	1244	0	0
T7	16398	0	0	0
T8	116529	0	0	0
T9	38664	0	0	0
T10	5488	0	0	0
T12	0	4071	0	0
T22	0	2022	0	0
T23	0	2238	0	0
T33	0	4237	0	0
T35	0	258	0	0
T40	0	16177	0	0
T44	0	6113	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	696742	0	0
T1	304519	3318	0	0
T2	39079	0	0	0
T3	4416	0	0	0
T4	35430	0	0	0
T5	997247	5553	0	0
T6	781401	1244	0	0
T7	16398	0	0	0
T8	116529	0	0	0
T9	38664	0	0	0
T10	5488	0	0	0
T12	0	4071	0	0
T22	0	2022	0	0
T23	0	2238	0	0
T33	0	4237	0	0
T35	0	258	0	0
T40	0	16177	0	0
T44	0	6113	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	696742	0	0
T1	304519	3318	0	0
T2	39079	0	0	0
T3	4416	0	0	0
T4	35430	0	0	0
T5	997247	5553	0	0
T6	781401	1244	0	0
T7	16398	0	0	0
T8	116529	0	0	0
T9	38664	0	0	0
T10	5488	0	0	0
T12	0	4071	0	0
T22	0	2022	0	0
T23	0	2238	0	0
T33	0	4237	0	0
T35	0	258	0	0
T40	0	16177	0	0
T44	0	6113	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	104598055	0	0
T1	304519	140403	0	0
T2	39079	0	0	0
T3	4416	4416	0	0
T4	35430	35430	0	0
T5	997247	408136	0	0
T6	781401	561065	0	0
T7	16398	16398	0	0
T8	116529	116376	0	0
T9	38664	38520	0	0
T10	5488	5488	0	0
T11	0	8759	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132719321	696742	0	0
T1	304519	3318	0	0
T2	39079	0	0	0
T3	4416	0	0	0
T4	35430	0	0	0
T5	997247	5553	0	0
T6	781401	1244	0	0
T7	16398	0	0	0
T8	116529	0	0	0
T9	38664	0	0	0
T10	5488	0	0	0
T12	0	4071	0	0
T22	0	2022	0	0
T23	0	2238	0	0
T33	0	4237	0	0
T35	0	258	0	0
T40	0	16177	0	0
T44	0	6113	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408910168	408824940	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	408910168	1974094	0	0
GntImpliesValid_A	408910168	1974094	0	0
GrantKnown_A	408910168	408824940	0	0
IdxKnown_A	408910168	408824940	0	0
IndexIsCorrect_A	408910168	1974094	0	0
LockArbDecision_A	408910168	0	0	0
NoReadyValidNoGrant_A	408910168	0	0	0
ReadyAndValidImplyGrant_A	408910168	1974094	0	0
ReqAndReadyImplyGrant_A	408910168	1974094	0	0
ReqImpliesValid_A	408910168	1974094	0	0
ReqStaysHighUntilGranted0_M	408910168	0	0	0
RoundRobin_A	408910168	4	0	906
ValidKnown_A	408910168	408824940	0	0
gen_data_port_assertion.DataFlow_A	408910168	1974094	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408910168	408824940	0	0
T1	317016	316936	0	0
T2	42721	42629	0	0
T3	22066	21978	0	0
T4	287304	287239	0	0
T5	305173	305096	0	0
T6	409157	409090	0	0
T7	135008	134940	0	0
T8	469677	469597	0	0
T9	42502	42405	0	0
T10	36244	36164	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408910168	1974094	0	0
T1	317016	3608	0	0
T2	42721	0	0	0
T3	22066	832	0	0
T4	287304	832	0	0
T5	305173	13352	0	0
T6	409157	8524	0	0
T7	135008	832	0	0
T8	469677	832	0	0
T9	42502	832	0	0
T10	36244	832	0	0
T31	0	29	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408910168	1974094	0	0
T1	317016	3608	0	0
T2	42721	0	0	0
T3	22066	832	0	0
T4	287304	832	0	0
T5	305173	13352	0	0
T6	409157	8524	0	0
T7	135008	832	0	0
T8	469677	832	0	0
T9	42502	832	0	0
T10	36244	832	0	0
T31	0	29	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408910168	408824940	0	0
T1	317016	316936	0	0
T2	42721	42629	0	0
T3	22066	21978	0	0
T4	287304	287239	0	0
T5	305173	305096	0	0
T6	409157	409090	0	0
T7	135008	134940	0	0
T8	469677	469597	0	0
T9	42502	42405	0	0
T10	36244	36164	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408910168	408824940	0	0
T1	317016	316936	0	0
T2	42721	42629	0	0
T3	22066	21978	0	0
T4	287304	287239	0	0
T5	305173	305096	0	0
T6	409157	409090	0	0
T7	135008	134940	0	0
T8	469677	469597	0	0
T9	42502	42405	0	0
T10	36244	36164	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408910168	1974094	0	0
T1	317016	3608	0	0
T2	42721	0	0	0
T3	22066	832	0	0
T4	287304	832	0	0
T5	305173	13352	0	0
T6	409157	8524	0	0
T7	135008	832	0	0
T8	469677	832	0	0
T9	42502	832	0	0
T10	36244	832	0	0
T31	0	29	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408910168	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408910168	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408910168	1974094	0	0
T1	317016	3608	0	0
T2	42721	0	0	0
T3	22066	832	0	0
T4	287304	832	0	0
T5	305173	13352	0	0
T6	409157	8524	0	0
T7	135008	832	0	0
T8	469677	832	0	0
T9	42502	832	0	0
T10	36244	832	0	0
T31	0	29	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408910168	1974094	0	0
T1	317016	3608	0	0
T2	42721	0	0	0
T3	22066	832	0	0
T4	287304	832	0	0
T5	305173	13352	0	0
T6	409157	8524	0	0
T7	135008	832	0	0
T8	469677	832	0	0
T9	42502	832	0	0
T10	36244	832	0	0
T31	0	29	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408910168	1974094	0	0
T1	317016	3608	0	0
T2	42721	0	0	0
T3	22066	832	0	0
T4	287304	832	0	0
T5	305173	13352	0	0
T6	409157	8524	0	0
T7	135008	832	0	0
T8	469677	832	0	0
T9	42502	832	0	0
T10	36244	832	0	0
T31	0	29	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408910168	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408910168	4	0	906
T49	350708	1	0	1
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	200844	0	0	1
T54	138554	0	0	1
T55	429818	0	0	1
T56	317177	0	0	1
T57	548187	0	0	1
T58	8604	0	0	1
T59	568460	0	0	1
T60	48639	0	0	1
T61	687524	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408910168	408824940	0	0
T1	317016	316936	0	0
T2	42721	42629	0	0
T3	22066	21978	0	0
T4	287304	287239	0	0
T5	305173	305096	0	0
T6	409157	409090	0	0
T7	135008	134940	0	0
T8	469677	469597	0	0
T9	42502	42405	0	0
T10	36244	36164	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408910168	1974094	0	0
T1	317016	3608	0	0
T2	42721	0	0	0
T3	22066	832	0	0
T4	287304	832	0	0
T5	305173	13352	0	0
T6	409157	8524	0	0
T7	135008	832	0	0
T8	469677	832	0	0
T9	42502	832	0	0
T10	36244	832	0	0
T31	0	29	0	0