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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.25


Total test records in report: 1081
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T1015 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2626165652 Jun 24 04:35:21 PM PDT 24 Jun 24 04:35:22 PM PDT 24 15169418 ps
T1016 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1290857663 Jun 24 04:34:55 PM PDT 24 Jun 24 04:34:58 PM PDT 24 23121494 ps
T1017 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3378317054 Jun 24 04:35:20 PM PDT 24 Jun 24 04:35:24 PM PDT 24 82259318 ps
T1018 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4134591579 Jun 24 04:34:29 PM PDT 24 Jun 24 04:34:32 PM PDT 24 66920387 ps
T1019 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.220354313 Jun 24 04:34:55 PM PDT 24 Jun 24 04:34:58 PM PDT 24 43739365 ps
T1020 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3571089924 Jun 24 04:34:53 PM PDT 24 Jun 24 04:34:55 PM PDT 24 65148034 ps
T1021 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2615347421 Jun 24 04:34:52 PM PDT 24 Jun 24 04:34:55 PM PDT 24 256257880 ps
T1022 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.621056159 Jun 24 04:35:01 PM PDT 24 Jun 24 04:35:04 PM PDT 24 14069923 ps
T186 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.726451411 Jun 24 04:34:47 PM PDT 24 Jun 24 04:34:56 PM PDT 24 111521857 ps
T1023 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2216001786 Jun 24 04:35:15 PM PDT 24 Jun 24 04:35:18 PM PDT 24 11095408 ps
T188 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3348786828 Jun 24 04:34:55 PM PDT 24 Jun 24 04:35:22 PM PDT 24 4130497435 ps
T1024 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3334541821 Jun 24 04:34:34 PM PDT 24 Jun 24 04:34:44 PM PDT 24 628094548 ps
T109 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2563091254 Jun 24 04:35:07 PM PDT 24 Jun 24 04:35:11 PM PDT 24 261210219 ps
T1025 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2301973578 Jun 24 04:34:43 PM PDT 24 Jun 24 04:34:46 PM PDT 24 11787662 ps
T110 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.637020221 Jun 24 04:34:41 PM PDT 24 Jun 24 04:34:46 PM PDT 24 309954001 ps
T1026 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.992203887 Jun 24 04:35:10 PM PDT 24 Jun 24 04:35:12 PM PDT 24 16661025 ps
T1027 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.985930995 Jun 24 04:34:34 PM PDT 24 Jun 24 04:34:55 PM PDT 24 1855005915 ps
T1028 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2295014131 Jun 24 04:34:53 PM PDT 24 Jun 24 04:34:55 PM PDT 24 38356219 ps
T1029 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1410807514 Jun 24 04:34:45 PM PDT 24 Jun 24 04:34:48 PM PDT 24 13956993 ps
T1030 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.845359296 Jun 24 04:34:53 PM PDT 24 Jun 24 04:34:56 PM PDT 24 16849378 ps
T1031 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.73043242 Jun 24 04:34:57 PM PDT 24 Jun 24 04:35:00 PM PDT 24 16277718 ps
T1032 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2566576000 Jun 24 04:34:51 PM PDT 24 Jun 24 04:34:59 PM PDT 24 112747069 ps
T1033 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2071783415 Jun 24 04:34:57 PM PDT 24 Jun 24 04:35:00 PM PDT 24 15345714 ps
T125 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1578964145 Jun 24 04:34:53 PM PDT 24 Jun 24 04:34:56 PM PDT 24 69217794 ps
T126 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1828930082 Jun 24 04:34:46 PM PDT 24 Jun 24 04:35:09 PM PDT 24 320739118 ps
T1034 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1141898553 Jun 24 04:35:01 PM PDT 24 Jun 24 04:35:04 PM PDT 24 33445638 ps
T1035 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1867004984 Jun 24 04:34:45 PM PDT 24 Jun 24 04:34:51 PM PDT 24 152872564 ps
T1036 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.650517359 Jun 24 04:34:46 PM PDT 24 Jun 24 04:35:14 PM PDT 24 1259784109 ps
T1037 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4115014853 Jun 24 04:34:53 PM PDT 24 Jun 24 04:35:05 PM PDT 24 27756698 ps
T127 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1584059518 Jun 24 04:34:51 PM PDT 24 Jun 24 04:34:55 PM PDT 24 106670236 ps
T1038 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1153687392 Jun 24 04:34:49 PM PDT 24 Jun 24 04:34:53 PM PDT 24 1135451202 ps
T1039 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1304065135 Jun 24 04:35:00 PM PDT 24 Jun 24 04:35:05 PM PDT 24 244951376 ps
T187 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3945189191 Jun 24 04:34:44 PM PDT 24 Jun 24 04:35:11 PM PDT 24 1990515928 ps
T185 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.880662672 Jun 24 04:34:47 PM PDT 24 Jun 24 04:35:13 PM PDT 24 3983976851 ps
T128 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.976283618 Jun 24 04:34:48 PM PDT 24 Jun 24 04:34:52 PM PDT 24 71420542 ps
T1040 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3802107039 Jun 24 04:34:54 PM PDT 24 Jun 24 04:35:01 PM PDT 24 262396766 ps
T129 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3961334521 Jun 24 04:34:56 PM PDT 24 Jun 24 04:35:00 PM PDT 24 24536042 ps
T1041 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4247841812 Jun 24 04:34:55 PM PDT 24 Jun 24 04:35:05 PM PDT 24 1082621058 ps
T1042 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.994589333 Jun 24 04:34:42 PM PDT 24 Jun 24 04:35:06 PM PDT 24 4066246538 ps
T86 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.845122466 Jun 24 04:34:29 PM PDT 24 Jun 24 04:34:31 PM PDT 24 31911588 ps
T130 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3753933344 Jun 24 04:34:47 PM PDT 24 Jun 24 04:34:51 PM PDT 24 322116487 ps
T1043 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2746335772 Jun 24 04:34:55 PM PDT 24 Jun 24 04:34:58 PM PDT 24 21124346 ps
T1044 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3828458264 Jun 24 04:34:49 PM PDT 24 Jun 24 04:34:52 PM PDT 24 11489519 ps
T1045 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.786540068 Jun 24 04:34:53 PM PDT 24 Jun 24 04:34:56 PM PDT 24 14526310 ps
T1046 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.30021450 Jun 24 04:35:10 PM PDT 24 Jun 24 04:35:12 PM PDT 24 75917046 ps
T1047 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2405358930 Jun 24 04:34:52 PM PDT 24 Jun 24 04:35:17 PM PDT 24 1030651074 ps
T1048 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.187836021 Jun 24 04:34:43 PM PDT 24 Jun 24 04:34:47 PM PDT 24 61838859 ps
T1049 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3190783513 Jun 24 04:34:47 PM PDT 24 Jun 24 04:34:50 PM PDT 24 13509315 ps
T1050 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1912503940 Jun 24 04:34:36 PM PDT 24 Jun 24 04:35:12 PM PDT 24 1069526480 ps
T1051 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2994920784 Jun 24 04:34:55 PM PDT 24 Jun 24 04:35:01 PM PDT 24 137382935 ps
T1052 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3811546351 Jun 24 04:34:36 PM PDT 24 Jun 24 04:34:39 PM PDT 24 302746836 ps
T1053 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2198241808 Jun 24 04:34:45 PM PDT 24 Jun 24 04:34:48 PM PDT 24 21337379 ps
T1054 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2495345982 Jun 24 04:34:41 PM PDT 24 Jun 24 04:34:44 PM PDT 24 28991438 ps
T1055 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2220233125 Jun 24 04:34:33 PM PDT 24 Jun 24 04:34:36 PM PDT 24 42582020 ps
T1056 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1071178215 Jun 24 04:34:43 PM PDT 24 Jun 24 04:34:46 PM PDT 24 51859838 ps
T1057 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2079324617 Jun 24 04:34:37 PM PDT 24 Jun 24 04:34:46 PM PDT 24 280969304 ps
T1058 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.874169670 Jun 24 04:34:41 PM PDT 24 Jun 24 04:34:45 PM PDT 24 321181721 ps
T1059 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3826443608 Jun 24 04:34:44 PM PDT 24 Jun 24 04:34:49 PM PDT 24 199594871 ps
T1060 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3325300991 Jun 24 04:34:54 PM PDT 24 Jun 24 04:35:00 PM PDT 24 374046095 ps
T1061 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2482664658 Jun 24 04:34:38 PM PDT 24 Jun 24 04:34:40 PM PDT 24 124874242 ps
T1062 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1726273618 Jun 24 04:34:42 PM PDT 24 Jun 24 04:34:46 PM PDT 24 332745669 ps
T1063 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.243895406 Jun 24 04:34:45 PM PDT 24 Jun 24 04:34:49 PM PDT 24 54410270 ps
T1064 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3322036427 Jun 24 04:35:10 PM PDT 24 Jun 24 04:35:18 PM PDT 24 112329934 ps
T1065 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2060716141 Jun 24 04:34:45 PM PDT 24 Jun 24 04:34:49 PM PDT 24 93355271 ps
T1066 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1336043920 Jun 24 04:34:36 PM PDT 24 Jun 24 04:34:38 PM PDT 24 46998751 ps
T1067 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4073806398 Jun 24 04:34:34 PM PDT 24 Jun 24 04:35:03 PM PDT 24 22536538449 ps
T1068 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4069201908 Jun 24 04:34:42 PM PDT 24 Jun 24 04:34:45 PM PDT 24 454969144 ps
T1069 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1960810288 Jun 24 04:35:15 PM PDT 24 Jun 24 04:35:18 PM PDT 24 19792184 ps
T189 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3747418676 Jun 24 04:34:35 PM PDT 24 Jun 24 04:35:00 PM PDT 24 4079848499 ps
T1070 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1073521924 Jun 24 04:34:45 PM PDT 24 Jun 24 04:34:50 PM PDT 24 41009616 ps
T1071 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.708979771 Jun 24 04:35:32 PM PDT 24 Jun 24 04:35:34 PM PDT 24 30952472 ps
T1072 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2076587535 Jun 24 04:34:55 PM PDT 24 Jun 24 04:35:00 PM PDT 24 31166589 ps
T1073 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1933165060 Jun 24 04:34:59 PM PDT 24 Jun 24 04:35:02 PM PDT 24 43863358 ps
T1074 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2011861359 Jun 24 04:34:36 PM PDT 24 Jun 24 04:34:41 PM PDT 24 61190238 ps
T1075 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3317021255 Jun 24 04:34:52 PM PDT 24 Jun 24 04:34:56 PM PDT 24 161655690 ps
T1076 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2370386823 Jun 24 04:34:52 PM PDT 24 Jun 24 04:34:54 PM PDT 24 55624940 ps
T1077 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1398562686 Jun 24 04:35:23 PM PDT 24 Jun 24 04:35:26 PM PDT 24 1136074706 ps
T1078 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4172075437 Jun 24 04:34:47 PM PDT 24 Jun 24 04:34:51 PM PDT 24 41630285 ps
T1079 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1253032571 Jun 24 04:35:10 PM PDT 24 Jun 24 04:35:12 PM PDT 24 59873783 ps
T1080 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3658136893 Jun 24 04:34:55 PM PDT 24 Jun 24 04:35:03 PM PDT 24 412086652 ps
T1081 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3429122783 Jun 24 04:34:57 PM PDT 24 Jun 24 04:35:03 PM PDT 24 129411947 ps

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1134045894
Short name T6
Test name
Test status
Simulation time 34096356398 ps
CPU time 91.57 seconds
Started Jun 24 04:41:51 PM PDT 24
Finished Jun 24 04:43:33 PM PDT 24
Peak memory 251324 kb
Host smart-85f38eba-d49a-4ed9-ad94-4a75e9dfefa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134045894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1134045894
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.910705761
Short name T12
Test name
Test status
Simulation time 15767290208 ps
CPU time 128.99 seconds
Started Jun 24 04:41:29 PM PDT 24
Finished Jun 24 04:43:47 PM PDT 24
Peak memory 271116 kb
Host smart-e6c4283e-d60b-4ebc-a7d4-1818a7d50bb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910705761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.910705761
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.4225208496
Short name T68
Test name
Test status
Simulation time 19426326665 ps
CPU time 228.83 seconds
Started Jun 24 04:41:56 PM PDT 24
Finished Jun 24 04:45:55 PM PDT 24
Peak memory 257512 kb
Host smart-2949a726-7cb7-4489-aabd-0fe42240a537
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225208496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.4225208496
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1702958970
Short name T42
Test name
Test status
Simulation time 106583298121 ps
CPU time 541.6 seconds
Started Jun 24 04:41:44 PM PDT 24
Finished Jun 24 04:50:55 PM PDT 24
Peak memory 283472 kb
Host smart-0d7c268d-657c-4536-902c-15230ac9dd5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702958970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1702958970
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3701320223
Short name T106
Test name
Test status
Simulation time 297578591 ps
CPU time 3.76 seconds
Started Jun 24 04:34:45 PM PDT 24
Finished Jun 24 04:34:51 PM PDT 24
Peak memory 217348 kb
Host smart-fbe00289-4615-4481-a6af-325560ff58d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701320223 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3701320223
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3066322366
Short name T247
Test name
Test status
Simulation time 499800390973 ps
CPU time 1039.75 seconds
Started Jun 24 04:42:41 PM PDT 24
Finished Jun 24 05:00:07 PM PDT 24
Peak memory 282028 kb
Host smart-656146bb-c718-4ece-9540-5bf95fa99366
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066322366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3066322366
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.605868265
Short name T69
Test name
Test status
Simulation time 35442900 ps
CPU time 0.78 seconds
Started Jun 24 04:40:04 PM PDT 24
Finished Jun 24 04:40:32 PM PDT 24
Peak memory 215936 kb
Host smart-603b8b0b-1051-4701-b7f5-4982a6b81bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605868265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.605868265
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3677166368
Short name T166
Test name
Test status
Simulation time 65005961896 ps
CPU time 727.62 seconds
Started Jun 24 04:40:35 PM PDT 24
Finished Jun 24 04:52:52 PM PDT 24
Peak memory 273848 kb
Host smart-ad7b5ebe-d6e7-4d04-824d-257855fd841c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677166368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3677166368
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3916073323
Short name T18
Test name
Test status
Simulation time 131062805 ps
CPU time 1.07 seconds
Started Jun 24 04:40:11 PM PDT 24
Finished Jun 24 04:40:35 PM PDT 24
Peak memory 236216 kb
Host smart-492ec3a3-7cc9-4f50-ace7-3a64521f7fa5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916073323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3916073323
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.470220280
Short name T40
Test name
Test status
Simulation time 261811215608 ps
CPU time 471.81 seconds
Started Jun 24 04:40:55 PM PDT 24
Finished Jun 24 04:48:50 PM PDT 24
Peak memory 266264 kb
Host smart-51060d63-ad9c-4df6-bd75-fd067cb55b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470220280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.470220280
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3936042680
Short name T148
Test name
Test status
Simulation time 5189236789 ps
CPU time 38.34 seconds
Started Jun 24 04:40:58 PM PDT 24
Finished Jun 24 04:41:43 PM PDT 24
Peak memory 232808 kb
Host smart-4577b236-d81b-4b1d-a36b-c16dc8189e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936042680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3936042680
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.4149398956
Short name T143
Test name
Test status
Simulation time 129925732825 ps
CPU time 406.39 seconds
Started Jun 24 04:42:25 PM PDT 24
Finished Jun 24 04:49:23 PM PDT 24
Peak memory 290224 kb
Host smart-2a5561cc-0ee5-4035-8279-15ba427db92b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149398956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.4149398956
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1594210190
Short name T183
Test name
Test status
Simulation time 33490844291 ps
CPU time 100.09 seconds
Started Jun 24 04:41:55 PM PDT 24
Finished Jun 24 04:43:46 PM PDT 24
Peak memory 256192 kb
Host smart-500e4c8a-d6dd-45b8-9e2d-e2015c1d91f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594210190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1594210190
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2748093382
Short name T111
Test name
Test status
Simulation time 1107636773 ps
CPU time 17.14 seconds
Started Jun 24 04:34:46 PM PDT 24
Finished Jun 24 04:35:05 PM PDT 24
Peak memory 215912 kb
Host smart-c4b7fefb-efef-478b-8498-7a945ef827b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748093382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2748093382
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.354154497
Short name T246
Test name
Test status
Simulation time 333749626657 ps
CPU time 592.63 seconds
Started Jun 24 04:42:25 PM PDT 24
Finished Jun 24 04:52:29 PM PDT 24
Peak memory 261920 kb
Host smart-624265ab-8c83-4bbb-be1a-4ef6b416714b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354154497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.354154497
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3036592287
Short name T48
Test name
Test status
Simulation time 84908060786 ps
CPU time 450.64 seconds
Started Jun 24 04:41:45 PM PDT 24
Finished Jun 24 04:49:25 PM PDT 24
Peak memory 254116 kb
Host smart-bb04a16d-9820-4e49-a850-aefc8f39f0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036592287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3036592287
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1572661900
Short name T84
Test name
Test status
Simulation time 179237940 ps
CPU time 1.46 seconds
Started Jun 24 04:34:40 PM PDT 24
Finished Jun 24 04:34:42 PM PDT 24
Peak memory 216788 kb
Host smart-09b9c682-a593-4fa1-a326-eaa188f17692
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572661900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1572661900
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3145450981
Short name T99
Test name
Test status
Simulation time 83729071 ps
CPU time 5.68 seconds
Started Jun 24 04:34:43 PM PDT 24
Finished Jun 24 04:34:50 PM PDT 24
Peak memory 215956 kb
Host smart-d04a9a10-cef1-4ea6-913c-56aa6b23770f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145450981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3145450981
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1243358854
Short name T44
Test name
Test status
Simulation time 60309361353 ps
CPU time 303.44 seconds
Started Jun 24 04:40:39 PM PDT 24
Finished Jun 24 04:45:49 PM PDT 24
Peak memory 273640 kb
Host smart-780e11f4-e1a3-4a35-ae2f-7132580ba0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243358854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1243358854
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.520018565
Short name T49
Test name
Test status
Simulation time 35070979644 ps
CPU time 84.03 seconds
Started Jun 24 04:40:28 PM PDT 24
Finished Jun 24 04:42:05 PM PDT 24
Peak memory 257456 kb
Host smart-a08f6e30-f14f-4f3f-9614-74ec3f658921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520018565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.520018565
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3257032636
Short name T20
Test name
Test status
Simulation time 77258192917 ps
CPU time 427 seconds
Started Jun 24 04:41:49 PM PDT 24
Finished Jun 24 04:49:06 PM PDT 24
Peak memory 262188 kb
Host smart-224b9c1c-7735-4d2e-9c7e-1f7df27d5129
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257032636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3257032636
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3547881003
Short name T201
Test name
Test status
Simulation time 6589736701 ps
CPU time 112.58 seconds
Started Jun 24 04:41:14 PM PDT 24
Finished Jun 24 04:43:17 PM PDT 24
Peak memory 273220 kb
Host smart-249766b5-e465-4ec2-9916-51c5e5efe9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547881003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3547881003
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2603741986
Short name T62
Test name
Test status
Simulation time 37221723 ps
CPU time 0.76 seconds
Started Jun 24 04:41:01 PM PDT 24
Finished Jun 24 04:41:10 PM PDT 24
Peak memory 205324 kb
Host smart-8b185dad-71ff-4255-8bcc-696c24d59df4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603741986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2603741986
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2009475552
Short name T205
Test name
Test status
Simulation time 8282335018 ps
CPU time 132.84 seconds
Started Jun 24 04:41:13 PM PDT 24
Finished Jun 24 04:43:36 PM PDT 24
Peak memory 255856 kb
Host smart-d139ab8b-a56d-44bd-950f-929069342548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009475552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2009475552
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2582972791
Short name T178
Test name
Test status
Simulation time 7889028174 ps
CPU time 84.55 seconds
Started Jun 24 04:40:55 PM PDT 24
Finished Jun 24 04:42:23 PM PDT 24
Peak memory 257400 kb
Host smart-6345d7bb-6081-4765-af5c-e16dc1ca2fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582972791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2582972791
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1473741477
Short name T23
Test name
Test status
Simulation time 13651298695 ps
CPU time 120.53 seconds
Started Jun 24 04:41:30 PM PDT 24
Finished Jun 24 04:43:41 PM PDT 24
Peak memory 249804 kb
Host smart-424345c8-413c-4b56-997f-730810528458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473741477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1473741477
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1674198205
Short name T195
Test name
Test status
Simulation time 17667222498 ps
CPU time 196.81 seconds
Started Jun 24 04:42:05 PM PDT 24
Finished Jun 24 04:45:33 PM PDT 24
Peak memory 283520 kb
Host smart-60a38132-8c0a-4c89-9710-e8d282333597
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674198205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1674198205
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2749820691
Short name T303
Test name
Test status
Simulation time 6639473385 ps
CPU time 43.52 seconds
Started Jun 24 04:40:49 PM PDT 24
Finished Jun 24 04:41:36 PM PDT 24
Peak memory 232784 kb
Host smart-35080458-ccb9-48c3-9efd-9b21dd5ae398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749820691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2749820691
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.838352231
Short name T179
Test name
Test status
Simulation time 102169029134 ps
CPU time 199.97 seconds
Started Jun 24 04:41:11 PM PDT 24
Finished Jun 24 04:44:41 PM PDT 24
Peak memory 232868 kb
Host smart-558287cc-a970-4ea8-bae1-da4405592082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838352231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.838352231
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3736949903
Short name T270
Test name
Test status
Simulation time 260786096807 ps
CPU time 481.66 seconds
Started Jun 24 04:41:29 PM PDT 24
Finished Jun 24 04:49:41 PM PDT 24
Peak memory 273832 kb
Host smart-2ad20f56-a195-4159-a89b-6c46e6af0d39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736949903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3736949903
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2590410005
Short name T180
Test name
Test status
Simulation time 132945636529 ps
CPU time 238.56 seconds
Started Jun 24 04:40:35 PM PDT 24
Finished Jun 24 04:44:43 PM PDT 24
Peak memory 257376 kb
Host smart-06813e48-b594-4734-afef-8f6294b57263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590410005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2590410005
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.884427082
Short name T234
Test name
Test status
Simulation time 3908165444 ps
CPU time 100.57 seconds
Started Jun 24 04:42:28 PM PDT 24
Finished Jun 24 04:44:19 PM PDT 24
Peak memory 265628 kb
Host smart-4dff4aab-0e54-457b-8792-cad59c361764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884427082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.884427082
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4178273413
Short name T102
Test name
Test status
Simulation time 545682774 ps
CPU time 3.85 seconds
Started Jun 24 04:34:50 PM PDT 24
Finished Jun 24 04:34:56 PM PDT 24
Peak memory 215920 kb
Host smart-2157e58b-be3b-4608-b851-bfab9cd454a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178273413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.4
178273413
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4247841812
Short name T1041
Test name
Test status
Simulation time 1082621058 ps
CPU time 7.99 seconds
Started Jun 24 04:34:55 PM PDT 24
Finished Jun 24 04:35:05 PM PDT 24
Peak memory 215972 kb
Host smart-ee95083c-314d-4647-9987-8401d874622a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247841812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.4247841812
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.528211722
Short name T271
Test name
Test status
Simulation time 39669526658 ps
CPU time 315.38 seconds
Started Jun 24 04:41:13 PM PDT 24
Finished Jun 24 04:46:39 PM PDT 24
Peak memory 265536 kb
Host smart-b1c5fd80-a99d-4664-9cf5-45fad50e85e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528211722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.528211722
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2680912722
Short name T290
Test name
Test status
Simulation time 30813739933 ps
CPU time 394.37 seconds
Started Jun 24 04:42:30 PM PDT 24
Finished Jun 24 04:49:14 PM PDT 24
Peak memory 273840 kb
Host smart-ed53d4d1-55f7-432b-95f5-40189141a6ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680912722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2680912722
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2417516176
Short name T91
Test name
Test status
Simulation time 908856306 ps
CPU time 4.56 seconds
Started Jun 24 04:41:13 PM PDT 24
Finished Jun 24 04:41:27 PM PDT 24
Peak memory 222560 kb
Host smart-eb65d5d1-7f66-4ee0-af94-0a18e51d02ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2417516176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2417516176
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2405358930
Short name T1047
Test name
Test status
Simulation time 1030651074 ps
CPU time 22.62 seconds
Started Jun 24 04:34:52 PM PDT 24
Finished Jun 24 04:35:17 PM PDT 24
Peak memory 215772 kb
Host smart-1d8c13c4-daee-4b1e-ab51-e8aa46bdee43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405358930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2405358930
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.797326189
Short name T112
Test name
Test status
Simulation time 813171433 ps
CPU time 12.98 seconds
Started Jun 24 04:34:54 PM PDT 24
Finished Jun 24 04:35:08 PM PDT 24
Peak memory 215848 kb
Host smart-7ed2bc78-7c5e-4ae4-8d77-5e27ea4f8ac5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797326189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.797326189
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1045240514
Short name T947
Test name
Test status
Simulation time 431007080 ps
CPU time 7.02 seconds
Started Jun 24 04:40:11 PM PDT 24
Finished Jun 24 04:40:41 PM PDT 24
Peak memory 224404 kb
Host smart-0e27fcf5-f1a5-4f16-b36c-5a8add8a7805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045240514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1045240514
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.108190586
Short name T311
Test name
Test status
Simulation time 1010962104 ps
CPU time 7.09 seconds
Started Jun 24 04:40:59 PM PDT 24
Finished Jun 24 04:41:14 PM PDT 24
Peak memory 234000 kb
Host smart-5e0dd696-218f-4db3-8135-f98da06f7655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108190586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.108190586
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1480938795
Short name T210
Test name
Test status
Simulation time 19719907464 ps
CPU time 105.86 seconds
Started Jun 24 04:41:12 PM PDT 24
Finished Jun 24 04:43:08 PM PDT 24
Peak memory 265892 kb
Host smart-65b0f798-4602-40a6-ae89-072ea03306e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480938795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1480938795
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2420657679
Short name T307
Test name
Test status
Simulation time 130907523 ps
CPU time 7.11 seconds
Started Jun 24 04:41:13 PM PDT 24
Finished Jun 24 04:41:29 PM PDT 24
Peak memory 240448 kb
Host smart-2fe19921-ccdd-4f5b-92dc-9fcebf9d352c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420657679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2420657679
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2697691608
Short name T304
Test name
Test status
Simulation time 6614562181 ps
CPU time 29.14 seconds
Started Jun 24 04:40:20 PM PDT 24
Finished Jun 24 04:41:07 PM PDT 24
Peak memory 232828 kb
Host smart-d9b10ec0-f73f-4400-8564-361f79e86daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697691608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2697691608
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2825994423
Short name T287
Test name
Test status
Simulation time 40089676341 ps
CPU time 400.24 seconds
Started Jun 24 04:42:11 PM PDT 24
Finished Jun 24 04:49:02 PM PDT 24
Peak memory 255920 kb
Host smart-1bbdba45-7d06-403a-a8e3-66eeb4ad4372
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825994423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2825994423
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.736389432
Short name T170
Test name
Test status
Simulation time 49163613053 ps
CPU time 397.38 seconds
Started Jun 24 04:42:16 PM PDT 24
Finished Jun 24 04:49:04 PM PDT 24
Peak memory 262284 kb
Host smart-adeaaca4-4730-4421-8c49-e0d0a4bea7f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736389432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.736389432
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3425283747
Short name T9
Test name
Test status
Simulation time 708422799 ps
CPU time 7.88 seconds
Started Jun 24 04:40:21 PM PDT 24
Finished Jun 24 04:40:45 PM PDT 24
Peak memory 224476 kb
Host smart-4fa0ca2c-e465-4b2e-beba-86b2b23ab18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425283747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3425283747
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3325300991
Short name T1060
Test name
Test status
Simulation time 374046095 ps
CPU time 4.68 seconds
Started Jun 24 04:34:54 PM PDT 24
Finished Jun 24 04:35:00 PM PDT 24
Peak memory 215100 kb
Host smart-d1db610c-1b04-4f2e-941c-21dcec038021
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325300991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3325300991
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.715370500
Short name T39
Test name
Test status
Simulation time 271700164774 ps
CPU time 380.69 seconds
Started Jun 24 04:41:39 PM PDT 24
Finished Jun 24 04:48:08 PM PDT 24
Peak memory 256184 kb
Host smart-16cd0efd-742f-4aa6-8776-ff1ce0efddde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715370500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.715370500
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_upload.321380536
Short name T92
Test name
Test status
Simulation time 25429272331 ps
CPU time 22.7 seconds
Started Jun 24 04:40:47 PM PDT 24
Finished Jun 24 04:41:12 PM PDT 24
Peak memory 224904 kb
Host smart-0ec2c208-25ac-4031-9ca5-fd35fc7024e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321380536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.321380536
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1828930082
Short name T126
Test name
Test status
Simulation time 320739118 ps
CPU time 21.72 seconds
Started Jun 24 04:34:46 PM PDT 24
Finished Jun 24 04:35:09 PM PDT 24
Peak memory 215724 kb
Host smart-12d04970-d1a0-4582-ae5c-d62f90d05277
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828930082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1828930082
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4073806398
Short name T1067
Test name
Test status
Simulation time 22536538449 ps
CPU time 28.77 seconds
Started Jun 24 04:34:34 PM PDT 24
Finished Jun 24 04:35:03 PM PDT 24
Peak memory 215692 kb
Host smart-742f2709-aa59-4103-837b-f95f4021e6b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073806398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.4073806398
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.845122466
Short name T86
Test name
Test status
Simulation time 31911588 ps
CPU time 1.15 seconds
Started Jun 24 04:34:29 PM PDT 24
Finished Jun 24 04:34:31 PM PDT 24
Peak memory 207444 kb
Host smart-0ae13055-8b0c-4084-9101-1f143af3e0d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845122466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.845122466
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2906451993
Short name T96
Test name
Test status
Simulation time 186051419 ps
CPU time 1.72 seconds
Started Jun 24 04:34:39 PM PDT 24
Finished Jun 24 04:34:41 PM PDT 24
Peak memory 215784 kb
Host smart-c75ab21c-b05e-4b3d-b5ed-6a59e2ccc8b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906451993 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2906451993
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4134591579
Short name T1018
Test name
Test status
Simulation time 66920387 ps
CPU time 1.36 seconds
Started Jun 24 04:34:29 PM PDT 24
Finished Jun 24 04:34:32 PM PDT 24
Peak memory 215736 kb
Host smart-9f90d2b0-6c6f-4733-8ed0-13046c032416
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134591579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.4
134591579
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2626165652
Short name T1015
Test name
Test status
Simulation time 15169418 ps
CPU time 0.75 seconds
Started Jun 24 04:35:21 PM PDT 24
Finished Jun 24 04:35:22 PM PDT 24
Peak memory 204136 kb
Host smart-f201ba10-1ff0-4657-867a-5342dd53a065
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626165652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
626165652
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2933870302
Short name T118
Test name
Test status
Simulation time 40841035 ps
CPU time 1.58 seconds
Started Jun 24 04:34:29 PM PDT 24
Finished Jun 24 04:34:32 PM PDT 24
Peak memory 216096 kb
Host smart-4bbaeae3-46d4-4f0c-a093-b1be09945d40
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933870302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2933870302
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2216001786
Short name T1023
Test name
Test status
Simulation time 11095408 ps
CPU time 0.66 seconds
Started Jun 24 04:35:15 PM PDT 24
Finished Jun 24 04:35:18 PM PDT 24
Peak memory 204020 kb
Host smart-068377d1-faa8-47b6-bf68-e64f42aefedb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216001786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2216001786
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2011861359
Short name T1074
Test name
Test status
Simulation time 61190238 ps
CPU time 3.91 seconds
Started Jun 24 04:34:36 PM PDT 24
Finished Jun 24 04:34:41 PM PDT 24
Peak memory 215752 kb
Host smart-acab9a88-0a00-4630-ac07-b4611309a1af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011861359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2011861359
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1533205604
Short name T101
Test name
Test status
Simulation time 121623530 ps
CPU time 2.86 seconds
Started Jun 24 04:34:33 PM PDT 24
Finished Jun 24 04:34:37 PM PDT 24
Peak memory 215184 kb
Host smart-5cb0a62b-d56c-4dfe-9e6d-1642ff3b75eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533205604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
533205604
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2365180792
Short name T67
Test name
Test status
Simulation time 1385883233 ps
CPU time 19.02 seconds
Started Jun 24 04:34:29 PM PDT 24
Finished Jun 24 04:34:49 PM PDT 24
Peak memory 215836 kb
Host smart-b5183cc0-d4b1-46fb-add5-a18a37278606
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365180792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2365180792
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.985930995
Short name T1027
Test name
Test status
Simulation time 1855005915 ps
CPU time 21.09 seconds
Started Jun 24 04:34:34 PM PDT 24
Finished Jun 24 04:34:55 PM PDT 24
Peak memory 215720 kb
Host smart-295479da-e04f-4f07-b12c-a0ad509821a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985930995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.985930995
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3129217263
Short name T974
Test name
Test status
Simulation time 202881886 ps
CPU time 11.83 seconds
Started Jun 24 04:34:40 PM PDT 24
Finished Jun 24 04:34:53 PM PDT 24
Peak memory 207504 kb
Host smart-f33210b5-2ab3-40c6-8335-c6b22fe0dd78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129217263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3129217263
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2482664658
Short name T1061
Test name
Test status
Simulation time 124874242 ps
CPU time 1.21 seconds
Started Jun 24 04:34:38 PM PDT 24
Finished Jun 24 04:34:40 PM PDT 24
Peak memory 207472 kb
Host smart-570bba02-2922-41d0-ae8b-dbff858b0462
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482664658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2482664658
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.874169670
Short name T1058
Test name
Test status
Simulation time 321181721 ps
CPU time 3.69 seconds
Started Jun 24 04:34:41 PM PDT 24
Finished Jun 24 04:34:45 PM PDT 24
Peak memory 217780 kb
Host smart-4a708d26-e1c9-4341-9d57-9e441a4c727e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874169670 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.874169670
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.997097669
Short name T120
Test name
Test status
Simulation time 42667906 ps
CPU time 1.36 seconds
Started Jun 24 04:34:47 PM PDT 24
Finished Jun 24 04:34:50 PM PDT 24
Peak memory 207604 kb
Host smart-1c9e6aba-65fb-47a6-a15f-2e494c37c82b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997097669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.997097669
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1336043920
Short name T1066
Test name
Test status
Simulation time 46998751 ps
CPU time 0.79 seconds
Started Jun 24 04:34:36 PM PDT 24
Finished Jun 24 04:34:38 PM PDT 24
Peak memory 204496 kb
Host smart-1386f602-2366-4ec5-98dc-e5a7ea3ef12a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336043920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
336043920
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.57460523
Short name T122
Test name
Test status
Simulation time 60792549 ps
CPU time 2.27 seconds
Started Jun 24 04:34:44 PM PDT 24
Finished Jun 24 04:34:48 PM PDT 24
Peak memory 215740 kb
Host smart-73d85e75-b47c-47f7-a16e-becc6480b4a3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57460523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi
_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_d
evice_mem_partial_access.57460523
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1442128583
Short name T978
Test name
Test status
Simulation time 10358413 ps
CPU time 0.68 seconds
Started Jun 24 04:34:42 PM PDT 24
Finished Jun 24 04:34:44 PM PDT 24
Peak memory 204388 kb
Host smart-eb92b977-d03b-4454-bae9-af72a1bb8d66
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442128583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1442128583
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.913759587
Short name T145
Test name
Test status
Simulation time 137620669 ps
CPU time 1.71 seconds
Started Jun 24 04:34:46 PM PDT 24
Finished Jun 24 04:34:50 PM PDT 24
Peak memory 207476 kb
Host smart-a923e11c-89eb-40ff-97a9-568e18951f3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913759587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.913759587
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2079324617
Short name T1057
Test name
Test status
Simulation time 280969304 ps
CPU time 8.13 seconds
Started Jun 24 04:34:37 PM PDT 24
Finished Jun 24 04:34:46 PM PDT 24
Peak memory 215676 kb
Host smart-9cff60c1-020b-46c6-a18b-f33365e3ca97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079324617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2079324617
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2125754125
Short name T1005
Test name
Test status
Simulation time 368584508 ps
CPU time 1.82 seconds
Started Jun 24 04:34:51 PM PDT 24
Finished Jun 24 04:34:54 PM PDT 24
Peak memory 215784 kb
Host smart-ccde3cc4-2f60-49f5-8448-cd391a93ad05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125754125 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2125754125
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3390611516
Short name T123
Test name
Test status
Simulation time 36530866 ps
CPU time 2.54 seconds
Started Jun 24 04:34:45 PM PDT 24
Finished Jun 24 04:34:50 PM PDT 24
Peak memory 215736 kb
Host smart-0565a811-e724-4b47-8ca3-c44ff8a466f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390611516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3390611516
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.173349094
Short name T984
Test name
Test status
Simulation time 14233915 ps
CPU time 0.69 seconds
Started Jun 24 04:34:45 PM PDT 24
Finished Jun 24 04:34:48 PM PDT 24
Peak memory 204208 kb
Host smart-939a1333-6127-416f-a776-cf25528d824d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173349094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.173349094
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.243895406
Short name T1063
Test name
Test status
Simulation time 54410270 ps
CPU time 1.83 seconds
Started Jun 24 04:34:45 PM PDT 24
Finished Jun 24 04:34:49 PM PDT 24
Peak memory 215680 kb
Host smart-2d0dd1ac-39d5-4ce5-956f-e390331b6f1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243895406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.243895406
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.881885606
Short name T108
Test name
Test status
Simulation time 317306042 ps
CPU time 2.55 seconds
Started Jun 24 04:34:59 PM PDT 24
Finished Jun 24 04:35:04 PM PDT 24
Peak memory 217484 kb
Host smart-2026e523-3209-49b7-a5be-8257e8ebdb3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881885606 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.881885606
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4172075437
Short name T1078
Test name
Test status
Simulation time 41630285 ps
CPU time 1.36 seconds
Started Jun 24 04:34:47 PM PDT 24
Finished Jun 24 04:34:51 PM PDT 24
Peak memory 207552 kb
Host smart-e62d92ab-293b-4580-bdea-0c851392cfab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172075437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
4172075437
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1922954014
Short name T976
Test name
Test status
Simulation time 40197728 ps
CPU time 0.73 seconds
Started Jun 24 04:34:48 PM PDT 24
Finished Jun 24 04:34:51 PM PDT 24
Peak memory 204192 kb
Host smart-8856f165-926c-4315-8e4e-4665ac88e752
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922954014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1922954014
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3771028476
Short name T999
Test name
Test status
Simulation time 468266705 ps
CPU time 3.37 seconds
Started Jun 24 04:34:52 PM PDT 24
Finished Jun 24 04:34:56 PM PDT 24
Peak memory 215692 kb
Host smart-5b72c0c2-9e8e-48ad-b948-bff737f4c3c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771028476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3771028476
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2566576000
Short name T1032
Test name
Test status
Simulation time 112747069 ps
CPU time 6.97 seconds
Started Jun 24 04:34:51 PM PDT 24
Finished Jun 24 04:34:59 PM PDT 24
Peak memory 215764 kb
Host smart-6d0530fc-000d-434c-89cc-c4fc59a4f65d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566576000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2566576000
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2182936048
Short name T107
Test name
Test status
Simulation time 27814640 ps
CPU time 1.74 seconds
Started Jun 24 04:34:54 PM PDT 24
Finished Jun 24 04:34:58 PM PDT 24
Peak memory 215784 kb
Host smart-9987fa22-31fb-4d22-9360-664a51346a99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182936048 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2182936048
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1253032571
Short name T1079
Test name
Test status
Simulation time 59873783 ps
CPU time 1.21 seconds
Started Jun 24 04:35:10 PM PDT 24
Finished Jun 24 04:35:12 PM PDT 24
Peak memory 207536 kb
Host smart-36d8b976-cf3e-4868-970d-8057b5ec6928
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253032571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1253032571
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1389641485
Short name T1007
Test name
Test status
Simulation time 34559617 ps
CPU time 0.72 seconds
Started Jun 24 04:35:01 PM PDT 24
Finished Jun 24 04:35:03 PM PDT 24
Peak memory 204056 kb
Host smart-e22c4118-4551-42c4-92c9-a2ff31c7f294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389641485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1389641485
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1324948938
Short name T144
Test name
Test status
Simulation time 287560414 ps
CPU time 3.77 seconds
Started Jun 24 04:35:00 PM PDT 24
Finished Jun 24 04:35:06 PM PDT 24
Peak memory 215716 kb
Host smart-e68b58a2-445c-48f5-b0d4-b8637781362f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324948938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1324948938
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1082339829
Short name T65
Test name
Test status
Simulation time 112604695 ps
CPU time 3.13 seconds
Started Jun 24 04:34:51 PM PDT 24
Finished Jun 24 04:34:55 PM PDT 24
Peak memory 217060 kb
Host smart-f58bb354-384c-4978-b92c-86b79f5bfebd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082339829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1082339829
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2615347421
Short name T1021
Test name
Test status
Simulation time 256257880 ps
CPU time 1.86 seconds
Started Jun 24 04:34:52 PM PDT 24
Finished Jun 24 04:34:55 PM PDT 24
Peak memory 215748 kb
Host smart-4fe37b20-d9c8-4d8a-8325-caff7ea36930
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615347421 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2615347421
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.411969865
Short name T114
Test name
Test status
Simulation time 134569206 ps
CPU time 1.26 seconds
Started Jun 24 04:35:15 PM PDT 24
Finished Jun 24 04:35:19 PM PDT 24
Peak memory 207532 kb
Host smart-072cbf9a-81b0-4eb1-b6a2-d1f456ac8c02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411969865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.411969865
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.786540068
Short name T1045
Test name
Test status
Simulation time 14526310 ps
CPU time 0.81 seconds
Started Jun 24 04:34:53 PM PDT 24
Finished Jun 24 04:34:56 PM PDT 24
Peak memory 204180 kb
Host smart-68d7870f-8709-420e-a37e-5010ffc2908b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786540068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.786540068
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1398562686
Short name T1077
Test name
Test status
Simulation time 1136074706 ps
CPU time 1.75 seconds
Started Jun 24 04:35:23 PM PDT 24
Finished Jun 24 04:35:26 PM PDT 24
Peak memory 215780 kb
Host smart-7323c2d6-853d-4ab9-a810-42b28fa3880e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398562686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1398562686
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2563091254
Short name T109
Test name
Test status
Simulation time 261210219 ps
CPU time 3.21 seconds
Started Jun 24 04:35:07 PM PDT 24
Finished Jun 24 04:35:11 PM PDT 24
Peak memory 215888 kb
Host smart-f49927b4-5278-4c3f-a1e6-d0ee877e57a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563091254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2563091254
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3459299040
Short name T1009
Test name
Test status
Simulation time 207987308 ps
CPU time 1.8 seconds
Started Jun 24 04:34:48 PM PDT 24
Finished Jun 24 04:34:52 PM PDT 24
Peak memory 215844 kb
Host smart-52fa94ef-884c-4b18-b931-a87ec7f44566
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459299040 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3459299040
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1141898553
Short name T1034
Test name
Test status
Simulation time 33445638 ps
CPU time 1.23 seconds
Started Jun 24 04:35:01 PM PDT 24
Finished Jun 24 04:35:04 PM PDT 24
Peak memory 215656 kb
Host smart-8bf1c06a-2d5c-432f-8ca6-520501b1b8d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141898553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1141898553
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.73043242
Short name T1031
Test name
Test status
Simulation time 16277718 ps
CPU time 0.75 seconds
Started Jun 24 04:34:57 PM PDT 24
Finished Jun 24 04:35:00 PM PDT 24
Peak memory 204132 kb
Host smart-03b7d1da-b793-4e86-bed6-5bbb1a2dd009
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73043242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.73043242
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1432345731
Short name T972
Test name
Test status
Simulation time 170409302 ps
CPU time 2.9 seconds
Started Jun 24 04:34:56 PM PDT 24
Finished Jun 24 04:35:01 PM PDT 24
Peak memory 215756 kb
Host smart-0d589323-7cf5-4d6c-9e4c-75579867979e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432345731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1432345731
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3378317054
Short name T1017
Test name
Test status
Simulation time 82259318 ps
CPU time 2.71 seconds
Started Jun 24 04:35:20 PM PDT 24
Finished Jun 24 04:35:24 PM PDT 24
Peak memory 215960 kb
Host smart-01070862-f789-4ce4-9736-cc7dd84cf64e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378317054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3378317054
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3322036427
Short name T1064
Test name
Test status
Simulation time 112329934 ps
CPU time 6.62 seconds
Started Jun 24 04:35:10 PM PDT 24
Finished Jun 24 04:35:18 PM PDT 24
Peak memory 215840 kb
Host smart-4d0d9173-3c50-4049-9478-edbf787d7176
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322036427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3322036427
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2544618853
Short name T997
Test name
Test status
Simulation time 42529727 ps
CPU time 2.67 seconds
Started Jun 24 04:34:51 PM PDT 24
Finished Jun 24 04:34:55 PM PDT 24
Peak memory 217044 kb
Host smart-411c8918-1900-4665-a531-17a95637aeda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544618853 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2544618853
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.752104891
Short name T162
Test name
Test status
Simulation time 472270146 ps
CPU time 2.85 seconds
Started Jun 24 04:34:48 PM PDT 24
Finished Jun 24 04:34:52 PM PDT 24
Peak memory 215680 kb
Host smart-d57ad5ca-14db-4ed8-9419-e89edb429f0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752104891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.752104891
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1350229481
Short name T975
Test name
Test status
Simulation time 17280552 ps
CPU time 0.79 seconds
Started Jun 24 04:34:55 PM PDT 24
Finished Jun 24 04:34:58 PM PDT 24
Peak memory 203716 kb
Host smart-c88bf56f-848a-4aac-b93a-b15e8e6a8b3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350229481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1350229481
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1135863283
Short name T159
Test name
Test status
Simulation time 276778222 ps
CPU time 1.79 seconds
Started Jun 24 04:35:15 PM PDT 24
Finished Jun 24 04:35:19 PM PDT 24
Peak memory 207504 kb
Host smart-d8620d99-6b9e-4aa8-9762-3524fa9cc3bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135863283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1135863283
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4096244570
Short name T100
Test name
Test status
Simulation time 160296820 ps
CPU time 4.32 seconds
Started Jun 24 04:34:52 PM PDT 24
Finished Jun 24 04:34:57 PM PDT 24
Peak memory 215996 kb
Host smart-6900ff6d-5d50-4a63-a2e6-e17f456929c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096244570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
4096244570
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1221514351
Short name T164
Test name
Test status
Simulation time 1133855445 ps
CPU time 24.31 seconds
Started Jun 24 04:34:53 PM PDT 24
Finished Jun 24 04:35:19 PM PDT 24
Peak memory 215792 kb
Host smart-e0f3bbba-a6f8-4253-b963-5aeea88e5c88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221514351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1221514351
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.4274361814
Short name T93
Test name
Test status
Simulation time 107084388 ps
CPU time 3.98 seconds
Started Jun 24 04:35:11 PM PDT 24
Finished Jun 24 04:35:17 PM PDT 24
Peak memory 217484 kb
Host smart-0374e245-4c1d-4565-990f-7e3dd66c45c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274361814 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.4274361814
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.976283618
Short name T128
Test name
Test status
Simulation time 71420542 ps
CPU time 1.9 seconds
Started Jun 24 04:34:48 PM PDT 24
Finished Jun 24 04:34:52 PM PDT 24
Peak memory 215744 kb
Host smart-0bf5a2d0-badc-434e-a153-c1fcf62e7519
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976283618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.976283618
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3828458264
Short name T1044
Test name
Test status
Simulation time 11489519 ps
CPU time 0.79 seconds
Started Jun 24 04:34:49 PM PDT 24
Finished Jun 24 04:34:52 PM PDT 24
Peak memory 204124 kb
Host smart-f4c722b1-966e-40c7-b3b3-03d6927e313c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828458264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3828458264
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1308818697
Short name T146
Test name
Test status
Simulation time 25981850 ps
CPU time 1.72 seconds
Started Jun 24 04:34:55 PM PDT 24
Finished Jun 24 04:34:59 PM PDT 24
Peak memory 215704 kb
Host smart-f9d464bf-6b0d-4e07-892b-713e9761f3d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308818697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1308818697
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2370386823
Short name T1076
Test name
Test status
Simulation time 55624940 ps
CPU time 1.68 seconds
Started Jun 24 04:34:52 PM PDT 24
Finished Jun 24 04:34:54 PM PDT 24
Peak memory 215884 kb
Host smart-560c28f1-dba2-4fb8-85eb-df66f5c4699f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370386823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2370386823
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1425056591
Short name T184
Test name
Test status
Simulation time 372667502 ps
CPU time 7.96 seconds
Started Jun 24 04:35:16 PM PDT 24
Finished Jun 24 04:35:26 PM PDT 24
Peak memory 215704 kb
Host smart-433a39ac-d592-4a2a-9472-75748c77d526
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425056591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1425056591
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2994920784
Short name T1051
Test name
Test status
Simulation time 137382935 ps
CPU time 3.54 seconds
Started Jun 24 04:34:55 PM PDT 24
Finished Jun 24 04:35:01 PM PDT 24
Peak memory 217144 kb
Host smart-3ce1f489-f945-4722-90d9-a463590cfcce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994920784 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2994920784
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3495439160
Short name T165
Test name
Test status
Simulation time 56944140 ps
CPU time 1.51 seconds
Started Jun 24 04:34:55 PM PDT 24
Finished Jun 24 04:34:59 PM PDT 24
Peak memory 216148 kb
Host smart-e39447e1-33e8-46e8-b4d3-01f237a8fc6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495439160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3495439160
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1296061276
Short name T998
Test name
Test status
Simulation time 12522749 ps
CPU time 0.74 seconds
Started Jun 24 04:34:55 PM PDT 24
Finished Jun 24 04:34:58 PM PDT 24
Peak memory 204132 kb
Host smart-f47de434-0fcb-4bb4-85eb-d2db73fed952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296061276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1296061276
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2751884953
Short name T969
Test name
Test status
Simulation time 46305514 ps
CPU time 2.82 seconds
Started Jun 24 04:35:12 PM PDT 24
Finished Jun 24 04:35:17 PM PDT 24
Peak memory 215744 kb
Host smart-8ea18570-73f6-42cb-b470-06c7eb1d53d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751884953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2751884953
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1304065135
Short name T1039
Test name
Test status
Simulation time 244951376 ps
CPU time 3.05 seconds
Started Jun 24 04:35:00 PM PDT 24
Finished Jun 24 04:35:05 PM PDT 24
Peak memory 215940 kb
Host smart-2203f228-924f-41f7-9622-6c89451d0b2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304065135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1304065135
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.130545139
Short name T161
Test name
Test status
Simulation time 5802686764 ps
CPU time 7.94 seconds
Started Jun 24 04:35:09 PM PDT 24
Finished Jun 24 04:35:18 PM PDT 24
Peak memory 215956 kb
Host smart-b5f225b9-707a-4c1e-93a8-4e6b7f59bea2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130545139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.130545139
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2444479144
Short name T1010
Test name
Test status
Simulation time 66520832 ps
CPU time 2.01 seconds
Started Jun 24 04:34:55 PM PDT 24
Finished Jun 24 04:34:59 PM PDT 24
Peak memory 215812 kb
Host smart-2319d633-a54e-4b2b-8221-e155b50b268b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444479144 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2444479144
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1578964145
Short name T125
Test name
Test status
Simulation time 69217794 ps
CPU time 1.28 seconds
Started Jun 24 04:34:53 PM PDT 24
Finished Jun 24 04:34:56 PM PDT 24
Peak memory 215720 kb
Host smart-4ecdb2ed-6a00-4f4e-bae9-3f13238ed767
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578964145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1578964145
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.708979771
Short name T1071
Test name
Test status
Simulation time 30952472 ps
CPU time 0.83 seconds
Started Jun 24 04:35:32 PM PDT 24
Finished Jun 24 04:35:34 PM PDT 24
Peak memory 204568 kb
Host smart-11fc0b55-b6dc-499f-bbf2-e027eb485715
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708979771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.708979771
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3675467684
Short name T1004
Test name
Test status
Simulation time 178129789 ps
CPU time 3.92 seconds
Started Jun 24 04:34:55 PM PDT 24
Finished Jun 24 04:35:01 PM PDT 24
Peak memory 215816 kb
Host smart-17ab3dda-3cd7-4c6a-980b-4e7d38acf714
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675467684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3675467684
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3658136893
Short name T1080
Test name
Test status
Simulation time 412086652 ps
CPU time 5.21 seconds
Started Jun 24 04:34:55 PM PDT 24
Finished Jun 24 04:35:03 PM PDT 24
Peak memory 215948 kb
Host smart-5664f814-a9df-484e-82f9-d0264ef403d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658136893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3658136893
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3348786828
Short name T188
Test name
Test status
Simulation time 4130497435 ps
CPU time 24.68 seconds
Started Jun 24 04:34:55 PM PDT 24
Finished Jun 24 04:35:22 PM PDT 24
Peak memory 216820 kb
Host smart-f32da54a-9d66-4a43-8a9f-05e41b74503f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348786828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3348786828
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4167473118
Short name T1013
Test name
Test status
Simulation time 417062169 ps
CPU time 3.87 seconds
Started Jun 24 04:34:54 PM PDT 24
Finished Jun 24 04:35:00 PM PDT 24
Peak memory 217980 kb
Host smart-c8d443de-3509-40f4-8215-c2db0f020e72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167473118 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.4167473118
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2076587535
Short name T1072
Test name
Test status
Simulation time 31166589 ps
CPU time 1.98 seconds
Started Jun 24 04:34:55 PM PDT 24
Finished Jun 24 04:35:00 PM PDT 24
Peak memory 215752 kb
Host smart-b367b8d5-1d35-49e7-8a62-e4c55eb86570
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076587535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2076587535
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.4067146173
Short name T1014
Test name
Test status
Simulation time 52753595 ps
CPU time 0.8 seconds
Started Jun 24 04:34:55 PM PDT 24
Finished Jun 24 04:34:59 PM PDT 24
Peak memory 204140 kb
Host smart-695cd3d9-01f4-4e57-b9db-4884a3e2e6cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067146173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
4067146173
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1826404738
Short name T970
Test name
Test status
Simulation time 113796092 ps
CPU time 3.25 seconds
Started Jun 24 04:35:06 PM PDT 24
Finished Jun 24 04:35:10 PM PDT 24
Peak memory 215672 kb
Host smart-09719d19-e103-4d33-b9fc-795d01947fa4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826404738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1826404738
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2479565700
Short name T66
Test name
Test status
Simulation time 155450169 ps
CPU time 1.38 seconds
Started Jun 24 04:34:59 PM PDT 24
Finished Jun 24 04:35:02 PM PDT 24
Peak memory 215860 kb
Host smart-912c5db8-5b0b-4ef2-949a-c31db4d2e805
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479565700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2479565700
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2518466965
Short name T116
Test name
Test status
Simulation time 632723149 ps
CPU time 17.88 seconds
Started Jun 24 04:34:32 PM PDT 24
Finished Jun 24 04:34:50 PM PDT 24
Peak memory 207480 kb
Host smart-991486fa-e9ce-4405-bd9f-8af36098bc23
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518466965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2518466965
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2235845627
Short name T982
Test name
Test status
Simulation time 753359240 ps
CPU time 11.69 seconds
Started Jun 24 04:34:41 PM PDT 24
Finished Jun 24 04:34:55 PM PDT 24
Peak memory 206704 kb
Host smart-15be1a41-3ef2-42ec-8376-0bd3d408c7b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235845627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2235845627
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2198241808
Short name T1053
Test name
Test status
Simulation time 21337379 ps
CPU time 0.98 seconds
Started Jun 24 04:34:45 PM PDT 24
Finished Jun 24 04:34:48 PM PDT 24
Peak memory 207280 kb
Host smart-d13412bc-b4ba-421b-94dd-56cdfa2da1d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198241808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2198241808
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3873733024
Short name T104
Test name
Test status
Simulation time 373940416 ps
CPU time 2.59 seconds
Started Jun 24 04:34:34 PM PDT 24
Finished Jun 24 04:34:38 PM PDT 24
Peak memory 215372 kb
Host smart-6a197f66-9a9f-48d2-9fbd-c0646ff58b8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873733024 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3873733024
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.466634200
Short name T117
Test name
Test status
Simulation time 40563794 ps
CPU time 2.74 seconds
Started Jun 24 04:34:44 PM PDT 24
Finished Jun 24 04:34:49 PM PDT 24
Peak memory 215764 kb
Host smart-724b2696-d659-428e-b781-5d635cafe04a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466634200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.466634200
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3141388436
Short name T981
Test name
Test status
Simulation time 17558029 ps
CPU time 0.75 seconds
Started Jun 24 04:34:36 PM PDT 24
Finished Jun 24 04:34:38 PM PDT 24
Peak memory 204188 kb
Host smart-2c1c543d-1d99-4a77-a7fa-529c6f1d896e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141388436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
141388436
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3899353651
Short name T115
Test name
Test status
Simulation time 62065544 ps
CPU time 2.49 seconds
Started Jun 24 04:34:36 PM PDT 24
Finished Jun 24 04:34:39 PM PDT 24
Peak memory 216132 kb
Host smart-7a3077d0-ea2a-4607-bb74-4e74725ed09d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899353651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3899353651
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3190783513
Short name T1049
Test name
Test status
Simulation time 13509315 ps
CPU time 0.7 seconds
Started Jun 24 04:34:47 PM PDT 24
Finished Jun 24 04:34:50 PM PDT 24
Peak memory 204056 kb
Host smart-eed5b394-9136-43af-9b8c-ca2c84d66727
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190783513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3190783513
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1153687392
Short name T1038
Test name
Test status
Simulation time 1135451202 ps
CPU time 2.93 seconds
Started Jun 24 04:34:49 PM PDT 24
Finished Jun 24 04:34:53 PM PDT 24
Peak memory 215676 kb
Host smart-04101a15-048a-4fe3-9950-305e460ebbe6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153687392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1153687392
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3322654979
Short name T98
Test name
Test status
Simulation time 212992666 ps
CPU time 3.81 seconds
Started Jun 24 04:34:42 PM PDT 24
Finished Jun 24 04:34:47 PM PDT 24
Peak memory 215812 kb
Host smart-aaffa84d-bc34-4792-93e7-f3866fea6ee1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322654979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
322654979
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.994589333
Short name T1042
Test name
Test status
Simulation time 4066246538 ps
CPU time 22.08 seconds
Started Jun 24 04:34:42 PM PDT 24
Finished Jun 24 04:35:06 PM PDT 24
Peak memory 215908 kb
Host smart-c8ec35f7-cd7c-4846-97f5-9f43bfada6db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994589333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.994589333
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1933165060
Short name T1073
Test name
Test status
Simulation time 43863358 ps
CPU time 0.68 seconds
Started Jun 24 04:34:59 PM PDT 24
Finished Jun 24 04:35:02 PM PDT 24
Peak memory 204164 kb
Host smart-4cf69853-d812-4ca9-bbd8-d72e31107ed3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933165060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1933165060
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.621056159
Short name T1022
Test name
Test status
Simulation time 14069923 ps
CPU time 0.75 seconds
Started Jun 24 04:35:01 PM PDT 24
Finished Jun 24 04:35:04 PM PDT 24
Peak memory 203288 kb
Host smart-6206d401-2ec1-4b78-873b-c68e2a637bf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621056159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.621056159
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3336209128
Short name T977
Test name
Test status
Simulation time 44617160 ps
CPU time 0.72 seconds
Started Jun 24 04:35:00 PM PDT 24
Finished Jun 24 04:35:03 PM PDT 24
Peak memory 204136 kb
Host smart-eed21829-6135-4ff3-af88-1a93cb8298a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336209128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3336209128
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1888247916
Short name T979
Test name
Test status
Simulation time 15662438 ps
CPU time 0.77 seconds
Started Jun 24 04:34:58 PM PDT 24
Finished Jun 24 04:35:01 PM PDT 24
Peak memory 204520 kb
Host smart-1e75ae7a-0729-43f0-8f83-d98aa51e76ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888247916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1888247916
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1374834995
Short name T1011
Test name
Test status
Simulation time 16115638 ps
CPU time 0.69 seconds
Started Jun 24 04:35:15 PM PDT 24
Finished Jun 24 04:35:19 PM PDT 24
Peak memory 204504 kb
Host smart-a587aacc-33de-41cf-bedb-3eb4da6d7c56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374834995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1374834995
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4115014853
Short name T1037
Test name
Test status
Simulation time 27756698 ps
CPU time 0.73 seconds
Started Jun 24 04:34:53 PM PDT 24
Finished Jun 24 04:35:05 PM PDT 24
Peak memory 204508 kb
Host smart-149db136-a0d7-4068-a024-9e6f0c16f1ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115014853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
4115014853
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2126271850
Short name T985
Test name
Test status
Simulation time 15595814 ps
CPU time 0.79 seconds
Started Jun 24 04:34:55 PM PDT 24
Finished Jun 24 04:34:58 PM PDT 24
Peak memory 204120 kb
Host smart-16e15d30-d0d9-4893-bef2-ce053915279e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126271850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2126271850
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2609935185
Short name T1006
Test name
Test status
Simulation time 12337586 ps
CPU time 0.73 seconds
Started Jun 24 04:34:53 PM PDT 24
Finished Jun 24 04:34:55 PM PDT 24
Peak memory 204444 kb
Host smart-4897b02a-786c-42ab-8c3a-e025c50f8b66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609935185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2609935185
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.306625308
Short name T980
Test name
Test status
Simulation time 39164399 ps
CPU time 0.79 seconds
Started Jun 24 04:35:02 PM PDT 24
Finished Jun 24 04:35:05 PM PDT 24
Peak memory 204136 kb
Host smart-95392b16-813b-4d4d-8ba6-018af4eca16c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306625308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.306625308
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2071783415
Short name T1033
Test name
Test status
Simulation time 15345714 ps
CPU time 0.78 seconds
Started Jun 24 04:34:57 PM PDT 24
Finished Jun 24 04:35:00 PM PDT 24
Peak memory 204128 kb
Host smart-1541ad6e-782c-408f-9cdd-81c96c74e902
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071783415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2071783415
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3334541821
Short name T1024
Test name
Test status
Simulation time 628094548 ps
CPU time 8.93 seconds
Started Jun 24 04:34:34 PM PDT 24
Finished Jun 24 04:34:44 PM PDT 24
Peak memory 206812 kb
Host smart-be6727e9-c33b-4d7b-9e75-11cc7ab07ba5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334541821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3334541821
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1912503940
Short name T1050
Test name
Test status
Simulation time 1069526480 ps
CPU time 35.26 seconds
Started Jun 24 04:34:36 PM PDT 24
Finished Jun 24 04:35:12 PM PDT 24
Peak memory 207540 kb
Host smart-7ed04dd1-fdd2-4bae-8529-5ff3f40501bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912503940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1912503940
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2220233125
Short name T1055
Test name
Test status
Simulation time 42582020 ps
CPU time 2.78 seconds
Started Jun 24 04:34:33 PM PDT 24
Finished Jun 24 04:34:36 PM PDT 24
Peak memory 218668 kb
Host smart-a8dde55a-21e7-4761-88f3-6cae4dbfac8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220233125 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2220233125
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.548142385
Short name T121
Test name
Test status
Simulation time 202066450 ps
CPU time 2.57 seconds
Started Jun 24 04:34:36 PM PDT 24
Finished Jun 24 04:34:39 PM PDT 24
Peak memory 207464 kb
Host smart-ac5504b7-8f5d-45e0-b92c-5584d53c5da8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548142385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.548142385
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4046618747
Short name T993
Test name
Test status
Simulation time 15437196 ps
CPU time 0.76 seconds
Started Jun 24 04:34:36 PM PDT 24
Finished Jun 24 04:34:38 PM PDT 24
Peak memory 204200 kb
Host smart-a1df153e-4f6d-4e5a-9973-06a438a3cda0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046618747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.4
046618747
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1726273618
Short name T1062
Test name
Test status
Simulation time 332745669 ps
CPU time 2.16 seconds
Started Jun 24 04:34:42 PM PDT 24
Finished Jun 24 04:34:46 PM PDT 24
Peak memory 215728 kb
Host smart-d2826f78-d2eb-48d9-a548-f78da5c9253b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726273618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1726273618
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1482744571
Short name T1002
Test name
Test status
Simulation time 13914118 ps
CPU time 0.66 seconds
Started Jun 24 04:34:49 PM PDT 24
Finished Jun 24 04:34:51 PM PDT 24
Peak memory 204040 kb
Host smart-cdd6be18-4a47-4784-b8b0-f8a6d2838bbf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482744571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1482744571
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3811546351
Short name T1052
Test name
Test status
Simulation time 302746836 ps
CPU time 1.97 seconds
Started Jun 24 04:34:36 PM PDT 24
Finished Jun 24 04:34:39 PM PDT 24
Peak memory 207564 kb
Host smart-868ab9c5-9618-4c60-80c4-2c2a2fc1e25b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811546351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3811546351
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1639902524
Short name T103
Test name
Test status
Simulation time 135383659 ps
CPU time 2.36 seconds
Started Jun 24 04:34:42 PM PDT 24
Finished Jun 24 04:34:46 PM PDT 24
Peak memory 215892 kb
Host smart-a29836bf-74e0-4b57-928e-25158a82405d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639902524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
639902524
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3747418676
Short name T189
Test name
Test status
Simulation time 4079848499 ps
CPU time 23.93 seconds
Started Jun 24 04:34:35 PM PDT 24
Finished Jun 24 04:35:00 PM PDT 24
Peak memory 215776 kb
Host smart-81c6c0cf-f58d-4f2d-834f-1dc7c8055cb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747418676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3747418676
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3571089924
Short name T1020
Test name
Test status
Simulation time 65148034 ps
CPU time 0.75 seconds
Started Jun 24 04:34:53 PM PDT 24
Finished Jun 24 04:34:55 PM PDT 24
Peak memory 204140 kb
Host smart-234c4ad5-e303-4f6e-a11e-e64a2aad8b88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571089924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3571089924
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3357703862
Short name T968
Test name
Test status
Simulation time 17884343 ps
CPU time 0.78 seconds
Started Jun 24 04:34:56 PM PDT 24
Finished Jun 24 04:34:59 PM PDT 24
Peak memory 204516 kb
Host smart-56909133-26a3-4f90-8196-47e83fdee925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357703862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3357703862
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1071229371
Short name T983
Test name
Test status
Simulation time 28213765 ps
CPU time 0.76 seconds
Started Jun 24 04:35:02 PM PDT 24
Finished Jun 24 04:35:04 PM PDT 24
Peak memory 204448 kb
Host smart-efe01745-00f5-439f-a5e7-2ac1fbb188e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071229371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1071229371
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1290857663
Short name T1016
Test name
Test status
Simulation time 23121494 ps
CPU time 0.75 seconds
Started Jun 24 04:34:55 PM PDT 24
Finished Jun 24 04:34:58 PM PDT 24
Peak memory 203872 kb
Host smart-50a9abf2-bce3-4b04-bfe9-ffc0c2e5d355
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290857663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1290857663
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3057231027
Short name T996
Test name
Test status
Simulation time 38783148 ps
CPU time 0.73 seconds
Started Jun 24 04:34:54 PM PDT 24
Finished Jun 24 04:34:56 PM PDT 24
Peak memory 204132 kb
Host smart-3c87792a-763e-4674-af1d-cbeaee895c9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057231027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3057231027
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3357313127
Short name T995
Test name
Test status
Simulation time 15220092 ps
CPU time 0.76 seconds
Started Jun 24 04:34:59 PM PDT 24
Finished Jun 24 04:35:02 PM PDT 24
Peak memory 204448 kb
Host smart-93df8222-526e-4ffb-9260-45d98a8f22f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357313127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3357313127
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1960810288
Short name T1069
Test name
Test status
Simulation time 19792184 ps
CPU time 0.7 seconds
Started Jun 24 04:35:15 PM PDT 24
Finished Jun 24 04:35:18 PM PDT 24
Peak memory 204148 kb
Host smart-5e20fff8-de3a-451d-9896-0e5a66ce111c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960810288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1960810288
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4168433510
Short name T1000
Test name
Test status
Simulation time 33885538 ps
CPU time 0.72 seconds
Started Jun 24 04:34:55 PM PDT 24
Finished Jun 24 04:34:59 PM PDT 24
Peak memory 204448 kb
Host smart-24bdb429-365b-4230-95c3-7d07b27b6830
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168433510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
4168433510
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2295014131
Short name T1028
Test name
Test status
Simulation time 38356219 ps
CPU time 0.73 seconds
Started Jun 24 04:34:53 PM PDT 24
Finished Jun 24 04:34:55 PM PDT 24
Peak memory 204152 kb
Host smart-c3a86e73-b9a6-4678-bf6b-b848b8cdc491
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295014131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2295014131
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3369114926
Short name T1012
Test name
Test status
Simulation time 69778681 ps
CPU time 0.73 seconds
Started Jun 24 04:35:00 PM PDT 24
Finished Jun 24 04:35:03 PM PDT 24
Peak memory 204436 kb
Host smart-9a62cdac-b611-4845-9523-9feb39b52d3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369114926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3369114926
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.703461142
Short name T1003
Test name
Test status
Simulation time 311014857 ps
CPU time 8.52 seconds
Started Jun 24 04:34:49 PM PDT 24
Finished Jun 24 04:34:59 PM PDT 24
Peak memory 207388 kb
Host smart-cec03e59-008c-457c-b619-83e88ab8c9ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703461142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.703461142
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.650517359
Short name T1036
Test name
Test status
Simulation time 1259784109 ps
CPU time 25.67 seconds
Started Jun 24 04:34:46 PM PDT 24
Finished Jun 24 04:35:14 PM PDT 24
Peak memory 207504 kb
Host smart-62923502-b4cf-410b-9661-bdf0cbbf023a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650517359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.650517359
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2652183900
Short name T85
Test name
Test status
Simulation time 135767127 ps
CPU time 1.17 seconds
Started Jun 24 04:34:49 PM PDT 24
Finished Jun 24 04:34:52 PM PDT 24
Peak memory 207460 kb
Host smart-a31bb0de-ae6f-40d7-9eca-5617d60335ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652183900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2652183900
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3826443608
Short name T1059
Test name
Test status
Simulation time 199594871 ps
CPU time 3.76 seconds
Started Jun 24 04:34:44 PM PDT 24
Finished Jun 24 04:34:49 PM PDT 24
Peak memory 217876 kb
Host smart-c60707bc-82c2-4f84-81fb-f1e831d93b36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826443608 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3826443608
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4100699040
Short name T124
Test name
Test status
Simulation time 138415411 ps
CPU time 1.8 seconds
Started Jun 24 04:34:48 PM PDT 24
Finished Jun 24 04:34:52 PM PDT 24
Peak memory 207476 kb
Host smart-3d9edc7b-13b9-4c31-9e90-e9d4fdb9ac6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100699040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4
100699040
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1410807514
Short name T1029
Test name
Test status
Simulation time 13956993 ps
CPU time 0.81 seconds
Started Jun 24 04:34:45 PM PDT 24
Finished Jun 24 04:34:48 PM PDT 24
Peak memory 204496 kb
Host smart-9002cd01-5815-4ba4-9776-53d66c89d884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410807514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
410807514
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1578801237
Short name T119
Test name
Test status
Simulation time 53092149 ps
CPU time 1.18 seconds
Started Jun 24 04:34:46 PM PDT 24
Finished Jun 24 04:34:49 PM PDT 24
Peak memory 215664 kb
Host smart-760f667c-bcf3-4834-bb44-5b10d3dcb207
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578801237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1578801237
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2199384562
Short name T990
Test name
Test status
Simulation time 39275439 ps
CPU time 0.68 seconds
Started Jun 24 04:34:55 PM PDT 24
Finished Jun 24 04:35:02 PM PDT 24
Peak memory 204052 kb
Host smart-59f4c3de-ff69-4040-8ad0-9724f4a00b27
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199384562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2199384562
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1839661897
Short name T147
Test name
Test status
Simulation time 170768989 ps
CPU time 2.89 seconds
Started Jun 24 04:34:50 PM PDT 24
Finished Jun 24 04:34:54 PM PDT 24
Peak memory 215720 kb
Host smart-8e17d15b-6ef5-4f1f-934a-e57ccc59a380
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839661897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1839661897
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1071178215
Short name T1056
Test name
Test status
Simulation time 51859838 ps
CPU time 1.71 seconds
Started Jun 24 04:34:43 PM PDT 24
Finished Jun 24 04:34:46 PM PDT 24
Peak memory 216052 kb
Host smart-2be33bea-a1c9-497d-ba13-54ef452e7916
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071178215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
071178215
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.29463978
Short name T95
Test name
Test status
Simulation time 421048258 ps
CPU time 6.79 seconds
Started Jun 24 04:34:36 PM PDT 24
Finished Jun 24 04:34:44 PM PDT 24
Peak memory 215660 kb
Host smart-5abf2ca2-204d-488d-bcc6-80a6012e033f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29463978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_t
l_intg_err.29463978
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2154944517
Short name T989
Test name
Test status
Simulation time 15750762 ps
CPU time 0.74 seconds
Started Jun 24 04:34:56 PM PDT 24
Finished Jun 24 04:34:59 PM PDT 24
Peak memory 204140 kb
Host smart-099eb5c7-508c-45e0-a0d1-8211b9f6d8ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154944517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2154944517
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.865124805
Short name T991
Test name
Test status
Simulation time 18857644 ps
CPU time 0.7 seconds
Started Jun 24 04:35:15 PM PDT 24
Finished Jun 24 04:35:18 PM PDT 24
Peak memory 204188 kb
Host smart-64044038-a28a-4414-a613-edf82f4dcacd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865124805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.865124805
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.992203887
Short name T1026
Test name
Test status
Simulation time 16661025 ps
CPU time 0.83 seconds
Started Jun 24 04:35:10 PM PDT 24
Finished Jun 24 04:35:12 PM PDT 24
Peak memory 204124 kb
Host smart-807160f6-3ce7-4739-881c-b939f77ef3ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992203887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.992203887
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2746335772
Short name T1043
Test name
Test status
Simulation time 21124346 ps
CPU time 0.8 seconds
Started Jun 24 04:34:55 PM PDT 24
Finished Jun 24 04:34:58 PM PDT 24
Peak memory 204120 kb
Host smart-a288625c-b940-4b17-b516-87bb76d513c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746335772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2746335772
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.845359296
Short name T1030
Test name
Test status
Simulation time 16849378 ps
CPU time 0.79 seconds
Started Jun 24 04:34:53 PM PDT 24
Finished Jun 24 04:34:56 PM PDT 24
Peak memory 204500 kb
Host smart-6b273d89-7153-477e-a061-1979fd85f87b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845359296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.845359296
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.220354313
Short name T1019
Test name
Test status
Simulation time 43739365 ps
CPU time 0.71 seconds
Started Jun 24 04:34:55 PM PDT 24
Finished Jun 24 04:34:58 PM PDT 24
Peak memory 204128 kb
Host smart-818a9403-671c-4e99-a160-be540cdbbfed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220354313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.220354313
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.30021450
Short name T1046
Test name
Test status
Simulation time 75917046 ps
CPU time 0.79 seconds
Started Jun 24 04:35:10 PM PDT 24
Finished Jun 24 04:35:12 PM PDT 24
Peak memory 204152 kb
Host smart-57e6188b-a28a-49b7-942e-7ca00eeff6b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30021450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.30021450
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.341595854
Short name T971
Test name
Test status
Simulation time 29082573 ps
CPU time 0.74 seconds
Started Jun 24 04:34:59 PM PDT 24
Finished Jun 24 04:35:02 PM PDT 24
Peak memory 204084 kb
Host smart-a6ba8caa-06c7-41f8-9a66-f6dd0423e537
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341595854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.341595854
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2503718128
Short name T992
Test name
Test status
Simulation time 14186548 ps
CPU time 0.73 seconds
Started Jun 24 04:35:07 PM PDT 24
Finished Jun 24 04:35:08 PM PDT 24
Peak memory 204136 kb
Host smart-a8ab3653-18f6-4faa-aee2-923f18b6164b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503718128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2503718128
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.487952375
Short name T1008
Test name
Test status
Simulation time 19852226 ps
CPU time 0.75 seconds
Started Jun 24 04:34:59 PM PDT 24
Finished Jun 24 04:35:02 PM PDT 24
Peak memory 204136 kb
Host smart-3ebdc1a2-b1bf-4696-8067-0114ce83b12c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487952375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.487952375
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3753933344
Short name T130
Test name
Test status
Simulation time 322116487 ps
CPU time 2.08 seconds
Started Jun 24 04:34:47 PM PDT 24
Finished Jun 24 04:34:51 PM PDT 24
Peak memory 215816 kb
Host smart-0f62157a-77d2-4ca6-ae0b-2d57e7e3be5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753933344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
753933344
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2793190280
Short name T987
Test name
Test status
Simulation time 40887362 ps
CPU time 0.78 seconds
Started Jun 24 04:34:50 PM PDT 24
Finished Jun 24 04:34:53 PM PDT 24
Peak memory 204108 kb
Host smart-c1fdf87c-dd05-4fe7-9ec6-2339d0af2265
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793190280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
793190280
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1697376614
Short name T973
Test name
Test status
Simulation time 61777798 ps
CPU time 3.98 seconds
Started Jun 24 04:34:52 PM PDT 24
Finished Jun 24 04:34:57 PM PDT 24
Peak memory 215724 kb
Host smart-6616cf6e-1d26-43b6-80f3-1033a1a8a87e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697376614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1697376614
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2767530378
Short name T97
Test name
Test status
Simulation time 215855437 ps
CPU time 3.19 seconds
Started Jun 24 04:34:40 PM PDT 24
Finished Jun 24 04:34:44 PM PDT 24
Peak memory 219776 kb
Host smart-8a163fca-c6bc-46c6-a2e8-02e451ccc9de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767530378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
767530378
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.726451411
Short name T186
Test name
Test status
Simulation time 111521857 ps
CPU time 7.4 seconds
Started Jun 24 04:34:47 PM PDT 24
Finished Jun 24 04:34:56 PM PDT 24
Peak memory 215716 kb
Host smart-07f48c44-9bc8-467e-95ab-63f4c02d2ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726451411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.726451411
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3963704198
Short name T994
Test name
Test status
Simulation time 53250581 ps
CPU time 1.86 seconds
Started Jun 24 04:34:46 PM PDT 24
Finished Jun 24 04:34:50 PM PDT 24
Peak memory 215748 kb
Host smart-4874b37c-9955-4c36-b1d9-81a91b215b13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963704198 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3963704198
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1584059518
Short name T127
Test name
Test status
Simulation time 106670236 ps
CPU time 2.84 seconds
Started Jun 24 04:34:51 PM PDT 24
Finished Jun 24 04:34:55 PM PDT 24
Peak memory 207580 kb
Host smart-80724dca-ed91-402d-b787-46d320da3da1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584059518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
584059518
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4069567053
Short name T967
Test name
Test status
Simulation time 36674402 ps
CPU time 0.76 seconds
Started Jun 24 04:34:45 PM PDT 24
Finished Jun 24 04:34:48 PM PDT 24
Peak memory 204136 kb
Host smart-d5b5ae20-4acd-4e46-899c-29425c1878b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069567053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.4
069567053
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2495345982
Short name T1054
Test name
Test status
Simulation time 28991438 ps
CPU time 1.66 seconds
Started Jun 24 04:34:41 PM PDT 24
Finished Jun 24 04:34:44 PM PDT 24
Peak memory 215776 kb
Host smart-8197b862-c926-4f27-a3b6-761e0fce3812
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495345982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2495345982
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3802107039
Short name T1040
Test name
Test status
Simulation time 262396766 ps
CPU time 5.13 seconds
Started Jun 24 04:34:54 PM PDT 24
Finished Jun 24 04:35:01 PM PDT 24
Peak memory 215884 kb
Host smart-20df1520-2f95-466d-8e46-255ca516e453
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802107039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
802107039
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.880662672
Short name T185
Test name
Test status
Simulation time 3983976851 ps
CPU time 23.47 seconds
Started Jun 24 04:34:47 PM PDT 24
Finished Jun 24 04:35:13 PM PDT 24
Peak memory 216160 kb
Host smart-f7c42f15-41ea-488f-9440-18304c3d0bfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880662672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.880662672
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2060716141
Short name T1065
Test name
Test status
Simulation time 93355271 ps
CPU time 1.79 seconds
Started Jun 24 04:34:45 PM PDT 24
Finished Jun 24 04:34:49 PM PDT 24
Peak memory 215964 kb
Host smart-94a5b799-2e64-4660-b9e2-ad307dd780f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060716141 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2060716141
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2931729958
Short name T1001
Test name
Test status
Simulation time 76492112 ps
CPU time 1.34 seconds
Started Jun 24 04:34:46 PM PDT 24
Finished Jun 24 04:34:49 PM PDT 24
Peak memory 207516 kb
Host smart-ffd0fd28-d82b-479d-a7ef-af9507971081
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931729958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
931729958
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2301973578
Short name T1025
Test name
Test status
Simulation time 11787662 ps
CPU time 0.76 seconds
Started Jun 24 04:34:43 PM PDT 24
Finished Jun 24 04:34:46 PM PDT 24
Peak memory 204136 kb
Host smart-2e0a9500-517f-409c-b2f5-86928bebc984
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301973578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
301973578
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.187836021
Short name T1048
Test name
Test status
Simulation time 61838859 ps
CPU time 2.02 seconds
Started Jun 24 04:34:43 PM PDT 24
Finished Jun 24 04:34:47 PM PDT 24
Peak memory 215684 kb
Host smart-a5cfbdf9-0585-4cec-9c39-e1c9078a0f4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187836021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.187836021
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.637020221
Short name T110
Test name
Test status
Simulation time 309954001 ps
CPU time 4.17 seconds
Started Jun 24 04:34:41 PM PDT 24
Finished Jun 24 04:34:46 PM PDT 24
Peak memory 215860 kb
Host smart-2ad4dcb7-f857-43cf-b4a7-ca2e07166ab7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637020221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.637020221
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1708435348
Short name T94
Test name
Test status
Simulation time 1542479675 ps
CPU time 18.15 seconds
Started Jun 24 04:34:46 PM PDT 24
Finished Jun 24 04:35:06 PM PDT 24
Peak memory 215752 kb
Host smart-e81fa279-a7d5-404d-81fa-26ffa4146930
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708435348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1708435348
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1073521924
Short name T1070
Test name
Test status
Simulation time 41009616 ps
CPU time 3.35 seconds
Started Jun 24 04:34:45 PM PDT 24
Finished Jun 24 04:34:50 PM PDT 24
Peak memory 218240 kb
Host smart-e4def443-436e-41c1-a94c-e1ddf0624e81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073521924 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1073521924
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3317021255
Short name T1075
Test name
Test status
Simulation time 161655690 ps
CPU time 2.21 seconds
Started Jun 24 04:34:52 PM PDT 24
Finished Jun 24 04:34:56 PM PDT 24
Peak memory 215736 kb
Host smart-2cfa51a0-9ddb-4be8-9372-469b89c90aed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317021255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
317021255
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3880511277
Short name T988
Test name
Test status
Simulation time 26075156 ps
CPU time 0.77 seconds
Started Jun 24 04:34:46 PM PDT 24
Finished Jun 24 04:34:49 PM PDT 24
Peak memory 204124 kb
Host smart-96633f7c-e17c-4241-aa3d-14c6d454d9f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880511277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
880511277
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1609078404
Short name T160
Test name
Test status
Simulation time 75976761 ps
CPU time 2.08 seconds
Started Jun 24 04:34:46 PM PDT 24
Finished Jun 24 04:34:50 PM PDT 24
Peak memory 215688 kb
Host smart-f87031ca-59df-487e-b9de-2f35529b1d30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609078404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1609078404
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2661953014
Short name T105
Test name
Test status
Simulation time 409796374 ps
CPU time 2.75 seconds
Started Jun 24 04:34:45 PM PDT 24
Finished Jun 24 04:34:50 PM PDT 24
Peak memory 215940 kb
Host smart-944346a5-6b75-4efa-afb5-9eb34af32bf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661953014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
661953014
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3945189191
Short name T187
Test name
Test status
Simulation time 1990515928 ps
CPU time 25.53 seconds
Started Jun 24 04:34:44 PM PDT 24
Finished Jun 24 04:35:11 PM PDT 24
Peak memory 215884 kb
Host smart-c9e71ec5-6c1d-4e85-bcbe-52883d60b6df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945189191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3945189191
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3429122783
Short name T1081
Test name
Test status
Simulation time 129411947 ps
CPU time 3.86 seconds
Started Jun 24 04:34:57 PM PDT 24
Finished Jun 24 04:35:03 PM PDT 24
Peak memory 217212 kb
Host smart-fedaebc5-20bd-481a-8f68-a14dbd8b4961
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429122783 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3429122783
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3961334521
Short name T129
Test name
Test status
Simulation time 24536042 ps
CPU time 1.49 seconds
Started Jun 24 04:34:56 PM PDT 24
Finished Jun 24 04:35:00 PM PDT 24
Peak memory 207420 kb
Host smart-c2294822-1947-404e-8c98-13e282c9fd17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961334521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
961334521
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.310885741
Short name T986
Test name
Test status
Simulation time 26523029 ps
CPU time 0.76 seconds
Started Jun 24 04:34:46 PM PDT 24
Finished Jun 24 04:34:49 PM PDT 24
Peak memory 203300 kb
Host smart-cb5d512b-88f9-40d8-9780-0bdfbd9a49ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310885741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.310885741
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4069201908
Short name T1068
Test name
Test status
Simulation time 454969144 ps
CPU time 1.8 seconds
Started Jun 24 04:34:42 PM PDT 24
Finished Jun 24 04:34:45 PM PDT 24
Peak memory 215708 kb
Host smart-e599c890-cc8c-48ba-a4d9-b942e47567eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069201908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.4069201908
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1867004984
Short name T1035
Test name
Test status
Simulation time 152872564 ps
CPU time 4.09 seconds
Started Jun 24 04:34:45 PM PDT 24
Finished Jun 24 04:34:51 PM PDT 24
Peak memory 215888 kb
Host smart-61b5d70e-f36f-4844-a589-3dcfa530701b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867004984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
867004984
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.416344514
Short name T163
Test name
Test status
Simulation time 2783619937 ps
CPU time 15.75 seconds
Started Jun 24 04:34:50 PM PDT 24
Finished Jun 24 04:35:07 PM PDT 24
Peak memory 223924 kb
Host smart-d76dd16f-3d14-4702-a603-1d28fa6a8a19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416344514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.416344514
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1696347741
Short name T704
Test name
Test status
Simulation time 12589042 ps
CPU time 0.71 seconds
Started Jun 24 04:40:11 PM PDT 24
Finished Jun 24 04:40:34 PM PDT 24
Peak memory 204688 kb
Host smart-5aed0f3e-c261-4f1c-b149-e743559f1b49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696347741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
696347741
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3354697412
Short name T852
Test name
Test status
Simulation time 66868854 ps
CPU time 2.93 seconds
Started Jun 24 04:40:11 PM PDT 24
Finished Jun 24 04:40:37 PM PDT 24
Peak memory 224520 kb
Host smart-1baba167-dac1-4e2f-bf84-7256ab0bcf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354697412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3354697412
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3064716263
Short name T787
Test name
Test status
Simulation time 152094209 ps
CPU time 0.78 seconds
Started Jun 24 04:40:02 PM PDT 24
Finished Jun 24 04:40:31 PM PDT 24
Peak memory 205548 kb
Host smart-02d13bdc-9d2c-4e93-9eaf-105b8ec2f2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064716263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3064716263
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.4265133152
Short name T222
Test name
Test status
Simulation time 20916130225 ps
CPU time 164.66 seconds
Started Jun 24 04:40:12 PM PDT 24
Finished Jun 24 04:43:18 PM PDT 24
Peak memory 251604 kb
Host smart-724920ce-6ac1-482f-8424-9911f0f2db76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265133152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4265133152
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3254605339
Short name T558
Test name
Test status
Simulation time 62719750846 ps
CPU time 136.54 seconds
Started Jun 24 04:40:10 PM PDT 24
Finished Jun 24 04:42:50 PM PDT 24
Peak memory 241060 kb
Host smart-6a35dd6d-0c96-4c45-99b3-e0530f77bcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254605339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3254605339
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3659297057
Short name T579
Test name
Test status
Simulation time 78636512635 ps
CPU time 121.82 seconds
Started Jun 24 04:40:10 PM PDT 24
Finished Jun 24 04:42:35 PM PDT 24
Peak memory 259052 kb
Host smart-008d969a-addd-4637-98c6-86591086c315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659297057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3659297057
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1600440400
Short name T564
Test name
Test status
Simulation time 6694957258 ps
CPU time 17.4 seconds
Started Jun 24 04:40:11 PM PDT 24
Finished Jun 24 04:40:51 PM PDT 24
Peak memory 234116 kb
Host smart-0454673d-3ec4-49af-81d3-d4b405e6e9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600440400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1600440400
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.654623122
Short name T858
Test name
Test status
Simulation time 3008530660 ps
CPU time 21.58 seconds
Started Jun 24 04:40:19 PM PDT 24
Finished Jun 24 04:40:58 PM PDT 24
Peak memory 224580 kb
Host smart-4fec843c-b29c-4676-b557-84c91854330a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654623122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.654623122
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.4177433192
Short name T200
Test name
Test status
Simulation time 3040298494 ps
CPU time 25.19 seconds
Started Jun 24 04:40:20 PM PDT 24
Finished Jun 24 04:41:03 PM PDT 24
Peak memory 224592 kb
Host smart-7d5057eb-ccab-4578-8d75-d73d68f64ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177433192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.4177433192
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3480930130
Short name T953
Test name
Test status
Simulation time 3649811021 ps
CPU time 8.3 seconds
Started Jun 24 04:40:20 PM PDT 24
Finished Jun 24 04:40:45 PM PDT 24
Peak memory 232780 kb
Host smart-083ff73f-573f-468b-bce4-7dd6a205adf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480930130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3480930130
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2320525502
Short name T447
Test name
Test status
Simulation time 170211404 ps
CPU time 4.1 seconds
Started Jun 24 04:40:10 PM PDT 24
Finished Jun 24 04:40:38 PM PDT 24
Peak memory 220568 kb
Host smart-1f3e4cba-a73f-437f-b2b5-8e84c8ec97f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2320525502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2320525502
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1981126266
Short name T285
Test name
Test status
Simulation time 44008393951 ps
CPU time 406.95 seconds
Started Jun 24 04:40:11 PM PDT 24
Finished Jun 24 04:47:21 PM PDT 24
Peak memory 260396 kb
Host smart-77ebf160-9928-481a-9142-4619a1ccc5e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981126266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1981126266
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2432160995
Short name T907
Test name
Test status
Simulation time 5533250783 ps
CPU time 16.97 seconds
Started Jun 24 04:40:02 PM PDT 24
Finished Jun 24 04:40:47 PM PDT 24
Peak memory 216456 kb
Host smart-26d96825-2123-449e-a108-7bdd3220f6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432160995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2432160995
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2183833055
Short name T350
Test name
Test status
Simulation time 467315329 ps
CPU time 2.43 seconds
Started Jun 24 04:40:03 PM PDT 24
Finished Jun 24 04:40:33 PM PDT 24
Peak memory 216104 kb
Host smart-de885e77-e441-47ad-b45b-13cdca52f74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183833055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2183833055
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.4162698726
Short name T380
Test name
Test status
Simulation time 2316863890 ps
CPU time 7.24 seconds
Started Jun 24 04:40:11 PM PDT 24
Finished Jun 24 04:40:41 PM PDT 24
Peak memory 216280 kb
Host smart-d8de3a54-dde8-4382-9fa8-9c0ad4af80c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162698726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.4162698726
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.266740757
Short name T453
Test name
Test status
Simulation time 13597692 ps
CPU time 0.71 seconds
Started Jun 24 04:40:04 PM PDT 24
Finished Jun 24 04:40:32 PM PDT 24
Peak memory 205528 kb
Host smart-ec0160c5-e150-4c8f-91df-5f632838affc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266740757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.266740757
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2740377812
Short name T743
Test name
Test status
Simulation time 111669666 ps
CPU time 2.43 seconds
Started Jun 24 04:40:13 PM PDT 24
Finished Jun 24 04:40:36 PM PDT 24
Peak memory 223848 kb
Host smart-c03b29b0-c976-47cd-9ac7-a39ef7ba303a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740377812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2740377812
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3699060734
Short name T658
Test name
Test status
Simulation time 16015653 ps
CPU time 0.76 seconds
Started Jun 24 04:40:22 PM PDT 24
Finished Jun 24 04:40:38 PM PDT 24
Peak memory 204764 kb
Host smart-62431bd5-8269-4983-84d6-8266599c8683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699060734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
699060734
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3627205058
Short name T357
Test name
Test status
Simulation time 1186672951 ps
CPU time 10.87 seconds
Started Jun 24 04:40:18 PM PDT 24
Finished Jun 24 04:40:47 PM PDT 24
Peak memory 232696 kb
Host smart-d04a4b46-eb06-46c2-9255-7184b9b7a081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627205058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3627205058
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1102636595
Short name T604
Test name
Test status
Simulation time 15064862 ps
CPU time 0.76 seconds
Started Jun 24 04:40:19 PM PDT 24
Finished Jun 24 04:40:37 PM PDT 24
Peak memory 205076 kb
Host smart-f940d5fd-7805-405f-bc54-1e1060a8274f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102636595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1102636595
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1151387301
Short name T926
Test name
Test status
Simulation time 5345495711 ps
CPU time 36.81 seconds
Started Jun 24 04:40:18 PM PDT 24
Finished Jun 24 04:41:14 PM PDT 24
Peak memory 232864 kb
Host smart-baf66863-1450-4cc9-8c8f-7591ae802ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151387301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1151387301
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2185951012
Short name T622
Test name
Test status
Simulation time 740322119 ps
CPU time 12.83 seconds
Started Jun 24 04:40:18 PM PDT 24
Finished Jun 24 04:40:50 PM PDT 24
Peak memory 217440 kb
Host smart-23134d87-9980-4325-8022-845f2f54148f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185951012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2185951012
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1622873545
Short name T847
Test name
Test status
Simulation time 7188823650 ps
CPU time 51.12 seconds
Started Jun 24 04:40:18 PM PDT 24
Finished Jun 24 04:41:28 PM PDT 24
Peak memory 257476 kb
Host smart-ac53132d-d92f-4183-b279-3b19e6c379d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622873545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1622873545
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3356241321
Short name T444
Test name
Test status
Simulation time 103365868 ps
CPU time 3.92 seconds
Started Jun 24 04:40:18 PM PDT 24
Finished Jun 24 04:40:40 PM PDT 24
Peak memory 224500 kb
Host smart-c4e51d26-8118-4ecc-8a77-5d597473c216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356241321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3356241321
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2315723508
Short name T739
Test name
Test status
Simulation time 28214588658 ps
CPU time 43.12 seconds
Started Jun 24 04:40:18 PM PDT 24
Finished Jun 24 04:41:20 PM PDT 24
Peak memory 249168 kb
Host smart-29ff0868-80c2-42a3-ab7f-7ff9af60d66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315723508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2315723508
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1185574450
Short name T450
Test name
Test status
Simulation time 427425060 ps
CPU time 3.41 seconds
Started Jun 24 04:40:19 PM PDT 24
Finished Jun 24 04:40:40 PM PDT 24
Peak memory 232688 kb
Host smart-17783c78-18fe-4f38-80aa-627665a0e6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185574450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1185574450
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1515357895
Short name T580
Test name
Test status
Simulation time 4148483423 ps
CPU time 13.46 seconds
Started Jun 24 04:40:15 PM PDT 24
Finished Jun 24 04:40:48 PM PDT 24
Peak memory 224584 kb
Host smart-5b8d02de-9877-4a07-8349-0cd29d0c350d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515357895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1515357895
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3945723153
Short name T917
Test name
Test status
Simulation time 827105272 ps
CPU time 7.83 seconds
Started Jun 24 04:40:18 PM PDT 24
Finished Jun 24 04:40:44 PM PDT 24
Peak memory 219388 kb
Host smart-8da2075a-f5ce-4ac1-b997-dd6330702fae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3945723153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3945723153
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3132558669
Short name T73
Test name
Test status
Simulation time 321208129 ps
CPU time 1.14 seconds
Started Jun 24 04:40:19 PM PDT 24
Finished Jun 24 04:40:38 PM PDT 24
Peak memory 235216 kb
Host smart-534c40b4-c034-422e-8e29-cbf135ebe946
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132558669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3132558669
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.4280981131
Short name T913
Test name
Test status
Simulation time 38000605 ps
CPU time 0.9 seconds
Started Jun 24 04:40:19 PM PDT 24
Finished Jun 24 04:40:38 PM PDT 24
Peak memory 206660 kb
Host smart-b6befccb-98b5-4df8-97f6-8a1bc0e3f38c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280981131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.4280981131
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.872972536
Short name T901
Test name
Test status
Simulation time 1983359648 ps
CPU time 14.01 seconds
Started Jun 24 04:40:12 PM PDT 24
Finished Jun 24 04:40:48 PM PDT 24
Peak memory 216312 kb
Host smart-f5739c09-0d1a-4cb5-a05a-6de274773f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872972536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.872972536
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2046295915
Short name T836
Test name
Test status
Simulation time 10992379387 ps
CPU time 27.67 seconds
Started Jun 24 04:40:11 PM PDT 24
Finished Jun 24 04:41:01 PM PDT 24
Peak memory 216336 kb
Host smart-653264bf-ab2b-4e52-8ebe-405f56d1b73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046295915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2046295915
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1706058838
Short name T857
Test name
Test status
Simulation time 228791173 ps
CPU time 1.69 seconds
Started Jun 24 04:40:10 PM PDT 24
Finished Jun 24 04:40:35 PM PDT 24
Peak memory 216280 kb
Host smart-32e32ea4-b922-42ec-88f3-92154e72e298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706058838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1706058838
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3200138062
Short name T442
Test name
Test status
Simulation time 434196737 ps
CPU time 0.83 seconds
Started Jun 24 04:40:11 PM PDT 24
Finished Jun 24 04:40:34 PM PDT 24
Peak memory 205896 kb
Host smart-f3956635-3dac-4b46-a97c-bedee9cc3355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200138062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3200138062
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2369919501
Short name T253
Test name
Test status
Simulation time 199748550 ps
CPU time 3.59 seconds
Started Jun 24 04:40:18 PM PDT 24
Finished Jun 24 04:40:40 PM PDT 24
Peak memory 235316 kb
Host smart-d4e48821-0398-4c6c-b90e-bf4883e7d0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369919501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2369919501
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1780037891
Short name T573
Test name
Test status
Simulation time 27794731 ps
CPU time 0.72 seconds
Started Jun 24 04:40:55 PM PDT 24
Finished Jun 24 04:41:01 PM PDT 24
Peak memory 204732 kb
Host smart-c8d1f3d6-b253-41bc-862e-f734e0e2bf91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780037891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1780037891
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2747755397
Short name T614
Test name
Test status
Simulation time 2366307550 ps
CPU time 5.06 seconds
Started Jun 24 04:41:00 PM PDT 24
Finished Jun 24 04:41:12 PM PDT 24
Peak memory 232732 kb
Host smart-11b5ba9d-ee7d-4a65-91c6-98cbdf73fda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747755397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2747755397
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2697365167
Short name T370
Test name
Test status
Simulation time 65693538 ps
CPU time 0.78 seconds
Started Jun 24 04:40:57 PM PDT 24
Finished Jun 24 04:41:05 PM PDT 24
Peak memory 205756 kb
Host smart-74bf3529-de69-4aae-872d-19f114c3f38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697365167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2697365167
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1182118201
Short name T302
Test name
Test status
Simulation time 53311302279 ps
CPU time 479.74 seconds
Started Jun 24 04:40:56 PM PDT 24
Finished Jun 24 04:49:02 PM PDT 24
Peak memory 266268 kb
Host smart-182d7416-3ad9-455b-b473-bd6c0291670c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182118201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1182118201
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.731147681
Short name T424
Test name
Test status
Simulation time 171218300 ps
CPU time 4.01 seconds
Started Jun 24 04:40:55 PM PDT 24
Finished Jun 24 04:41:03 PM PDT 24
Peak memory 217412 kb
Host smart-eda46601-625d-4ec2-ac65-99ed8a7eb03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731147681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.731147681
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.178221889
Short name T966
Test name
Test status
Simulation time 527407116 ps
CPU time 5.97 seconds
Started Jun 24 04:40:54 PM PDT 24
Finished Jun 24 04:41:04 PM PDT 24
Peak memory 233740 kb
Host smart-389c6daf-7227-4fe5-bba3-68f23c42ad16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178221889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.178221889
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.214462285
Short name T811
Test name
Test status
Simulation time 33067672 ps
CPU time 2.43 seconds
Started Jun 24 04:40:59 PM PDT 24
Finished Jun 24 04:41:09 PM PDT 24
Peak memory 232372 kb
Host smart-e3ac40cf-0aed-4972-9b8a-2e505bc01900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214462285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.214462285
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2807409328
Short name T899
Test name
Test status
Simulation time 679810750 ps
CPU time 11.74 seconds
Started Jun 24 04:41:00 PM PDT 24
Finished Jun 24 04:41:19 PM PDT 24
Peak memory 240428 kb
Host smart-c4c2a8e3-b14b-436b-aa2a-34e0858aadca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807409328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2807409328
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.747672515
Short name T665
Test name
Test status
Simulation time 17643636035 ps
CPU time 14.27 seconds
Started Jun 24 04:40:56 PM PDT 24
Finished Jun 24 04:41:15 PM PDT 24
Peak memory 232756 kb
Host smart-5e09c01a-ce4e-4f51-80b6-daf457059fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747672515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.747672515
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.951123109
Short name T254
Test name
Test status
Simulation time 950558015 ps
CPU time 9.36 seconds
Started Jun 24 04:40:56 PM PDT 24
Finished Jun 24 04:41:12 PM PDT 24
Peak memory 240588 kb
Host smart-972009d3-8ff6-480c-ba74-383925960034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951123109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.951123109
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.888700622
Short name T786
Test name
Test status
Simulation time 227311316 ps
CPU time 4.66 seconds
Started Jun 24 04:40:55 PM PDT 24
Finished Jun 24 04:41:03 PM PDT 24
Peak memory 218876 kb
Host smart-053fbd60-89e3-4363-a445-ec28634139fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=888700622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.888700622
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2684935871
Short name T19
Test name
Test status
Simulation time 58914815 ps
CPU time 1.09 seconds
Started Jun 24 04:40:55 PM PDT 24
Finished Jun 24 04:41:00 PM PDT 24
Peak memory 207712 kb
Host smart-f73f40d4-f982-4de5-a44f-23a30fc6584f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684935871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2684935871
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3050393857
Short name T469
Test name
Test status
Simulation time 1931563113 ps
CPU time 7.39 seconds
Started Jun 24 04:40:54 PM PDT 24
Finished Jun 24 04:41:04 PM PDT 24
Peak memory 218208 kb
Host smart-9619e5cf-2113-4908-a6b1-11ac030e0c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050393857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3050393857
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.765231219
Short name T375
Test name
Test status
Simulation time 2423590620 ps
CPU time 6.91 seconds
Started Jun 24 04:40:58 PM PDT 24
Finished Jun 24 04:41:11 PM PDT 24
Peak memory 216360 kb
Host smart-1ab37b32-8e62-4496-9a43-25588958764d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765231219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.765231219
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1426524801
Short name T77
Test name
Test status
Simulation time 76334439 ps
CPU time 1.22 seconds
Started Jun 24 04:40:57 PM PDT 24
Finished Jun 24 04:41:05 PM PDT 24
Peak memory 216584 kb
Host smart-7bcbf4f8-6aaa-4046-8af6-936a3d9e50a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426524801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1426524801
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1815004290
Short name T629
Test name
Test status
Simulation time 192325354 ps
CPU time 0.77 seconds
Started Jun 24 04:40:54 PM PDT 24
Finished Jun 24 04:40:59 PM PDT 24
Peak memory 206304 kb
Host smart-f0384c69-fd08-42c4-9429-9fb67f817025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815004290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1815004290
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2336420857
Short name T61
Test name
Test status
Simulation time 6944700238 ps
CPU time 24.72 seconds
Started Jun 24 04:41:00 PM PDT 24
Finished Jun 24 04:41:32 PM PDT 24
Peak memory 232824 kb
Host smart-000df96e-9784-4033-a5e1-0a350aeab87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336420857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2336420857
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2963595914
Short name T651
Test name
Test status
Simulation time 28563041 ps
CPU time 2.12 seconds
Started Jun 24 04:41:00 PM PDT 24
Finished Jun 24 04:41:10 PM PDT 24
Peak memory 222940 kb
Host smart-5d15324d-662c-414a-a763-e3c6d0dac7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963595914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2963595914
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2821637192
Short name T489
Test name
Test status
Simulation time 237440540 ps
CPU time 0.83 seconds
Started Jun 24 04:40:55 PM PDT 24
Finished Jun 24 04:41:01 PM PDT 24
Peak memory 206536 kb
Host smart-257a663c-0f05-49ae-894d-e8da3a8a6485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821637192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2821637192
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2828241238
Short name T671
Test name
Test status
Simulation time 30758188173 ps
CPU time 102.01 seconds
Started Jun 24 04:40:59 PM PDT 24
Finished Jun 24 04:42:49 PM PDT 24
Peak memory 248244 kb
Host smart-5eadef7a-f369-4b81-b0b5-5123d542ba81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828241238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2828241238
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.623955937
Short name T910
Test name
Test status
Simulation time 19788592449 ps
CPU time 94.36 seconds
Started Jun 24 04:40:59 PM PDT 24
Finished Jun 24 04:42:41 PM PDT 24
Peak memory 273004 kb
Host smart-0c4d57f3-cac7-4860-8df9-cb9d7525cdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623955937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.623955937
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2190665791
Short name T781
Test name
Test status
Simulation time 52232686719 ps
CPU time 137.87 seconds
Started Jun 24 04:41:01 PM PDT 24
Finished Jun 24 04:43:26 PM PDT 24
Peak memory 257464 kb
Host smart-37e6ea5e-3a1b-416f-b8d2-f1604e64f5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190665791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2190665791
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3357613782
Short name T801
Test name
Test status
Simulation time 1561764752 ps
CPU time 16.97 seconds
Started Jun 24 04:40:52 PM PDT 24
Finished Jun 24 04:41:12 PM PDT 24
Peak memory 224516 kb
Host smart-878b9135-addd-4396-a255-b412cb3bbc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357613782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3357613782
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2321071470
Short name T630
Test name
Test status
Simulation time 273250551 ps
CPU time 7.57 seconds
Started Jun 24 04:40:52 PM PDT 24
Finished Jun 24 04:41:03 PM PDT 24
Peak memory 232660 kb
Host smart-84cddd9c-8903-4be6-86e8-b3198f31fc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321071470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2321071470
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2361940364
Short name T607
Test name
Test status
Simulation time 14482333090 ps
CPU time 13.54 seconds
Started Jun 24 04:40:55 PM PDT 24
Finished Jun 24 04:41:12 PM PDT 24
Peak memory 240384 kb
Host smart-3c03abb5-f156-44c6-a820-5ca12c09cb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361940364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2361940364
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3811018530
Short name T769
Test name
Test status
Simulation time 5399196098 ps
CPU time 5.7 seconds
Started Jun 24 04:40:53 PM PDT 24
Finished Jun 24 04:41:02 PM PDT 24
Peak memory 232768 kb
Host smart-2f60da19-6ba0-4656-95b2-8b7f25288c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811018530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3811018530
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1066076731
Short name T584
Test name
Test status
Simulation time 4922639939 ps
CPU time 9.53 seconds
Started Jun 24 04:41:03 PM PDT 24
Finished Jun 24 04:41:21 PM PDT 24
Peak memory 220448 kb
Host smart-79159a6a-89aa-4624-819d-c1ceccf00e0e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1066076731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1066076731
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.732635549
Short name T52
Test name
Test status
Simulation time 119708696538 ps
CPU time 399.7 seconds
Started Jun 24 04:41:05 PM PDT 24
Finished Jun 24 04:47:52 PM PDT 24
Peak memory 296884 kb
Host smart-8f44ce33-7cb8-4cd8-a780-5c6c27cc15d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732635549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.732635549
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1338116370
Short name T322
Test name
Test status
Simulation time 18741064921 ps
CPU time 27.6 seconds
Started Jun 24 04:40:54 PM PDT 24
Finished Jun 24 04:41:24 PM PDT 24
Peak memory 216380 kb
Host smart-b716a83f-1b47-402d-80ee-874fac768171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338116370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1338116370
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2826108263
Short name T24
Test name
Test status
Simulation time 5594184389 ps
CPU time 5.87 seconds
Started Jun 24 04:40:54 PM PDT 24
Finished Jun 24 04:41:03 PM PDT 24
Peak memory 216404 kb
Host smart-e9fdb881-b052-4734-b52b-afba648694ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826108263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2826108263
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1354852103
Short name T543
Test name
Test status
Simulation time 475264509 ps
CPU time 7.8 seconds
Started Jun 24 04:40:52 PM PDT 24
Finished Jun 24 04:41:02 PM PDT 24
Peak memory 216200 kb
Host smart-0b393e1c-2a27-4970-a39a-a562809ba30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354852103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1354852103
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2624360943
Short name T736
Test name
Test status
Simulation time 223756909 ps
CPU time 0.82 seconds
Started Jun 24 04:40:59 PM PDT 24
Finished Jun 24 04:41:07 PM PDT 24
Peak memory 205924 kb
Host smart-824d4ef7-690a-4999-a964-1719762f8e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624360943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2624360943
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.895913149
Short name T903
Test name
Test status
Simulation time 57363616 ps
CPU time 2.41 seconds
Started Jun 24 04:41:03 PM PDT 24
Finished Jun 24 04:41:13 PM PDT 24
Peak memory 224452 kb
Host smart-d7cb570d-5fde-4c56-acbc-34c608ae4126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895913149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.895913149
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.17349065
Short name T63
Test name
Test status
Simulation time 12947982 ps
CPU time 0.74 seconds
Started Jun 24 04:41:00 PM PDT 24
Finished Jun 24 04:41:08 PM PDT 24
Peak memory 205360 kb
Host smart-76c7410d-f916-4268-a38d-cc166b8f9d83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17349065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.17349065
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.4106950803
Short name T280
Test name
Test status
Simulation time 691156748 ps
CPU time 4.24 seconds
Started Jun 24 04:41:05 PM PDT 24
Finished Jun 24 04:41:18 PM PDT 24
Peak memory 224568 kb
Host smart-a37acbb1-b70f-472f-b3eb-7c5cb6f0c081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106950803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.4106950803
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2360945092
Short name T398
Test name
Test status
Simulation time 17980244 ps
CPU time 0.74 seconds
Started Jun 24 04:41:08 PM PDT 24
Finished Jun 24 04:41:17 PM PDT 24
Peak memory 205484 kb
Host smart-35850946-5102-4b8b-aa2d-b194de756521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360945092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2360945092
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.743357110
Short name T400
Test name
Test status
Simulation time 5642371173 ps
CPU time 73.6 seconds
Started Jun 24 04:41:02 PM PDT 24
Finished Jun 24 04:42:23 PM PDT 24
Peak memory 255512 kb
Host smart-b189ac21-eb8b-45f1-a8e2-4b24eae36951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743357110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.743357110
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.468431499
Short name T249
Test name
Test status
Simulation time 189750802757 ps
CPU time 401.21 seconds
Started Jun 24 04:41:06 PM PDT 24
Finished Jun 24 04:47:55 PM PDT 24
Peak memory 253396 kb
Host smart-615445a5-1e8c-441f-91fd-acdd7b4180a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468431499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.468431499
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3512216419
Short name T224
Test name
Test status
Simulation time 14357855715 ps
CPU time 125 seconds
Started Jun 24 04:41:06 PM PDT 24
Finished Jun 24 04:43:19 PM PDT 24
Peak memory 249264 kb
Host smart-a721af25-9193-4e9b-8934-56182a145266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512216419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3512216419
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3709191357
Short name T642
Test name
Test status
Simulation time 517072460 ps
CPU time 5.35 seconds
Started Jun 24 04:41:03 PM PDT 24
Finished Jun 24 04:41:16 PM PDT 24
Peak memory 239440 kb
Host smart-a74eee31-a103-43bc-8085-d2e38591a1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709191357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3709191357
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1543509845
Short name T7
Test name
Test status
Simulation time 1421114014 ps
CPU time 14.5 seconds
Started Jun 24 04:41:07 PM PDT 24
Finished Jun 24 04:41:30 PM PDT 24
Peak memory 232708 kb
Host smart-fd108a72-1738-43ba-b089-c3bd495f4532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543509845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1543509845
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3740072658
Short name T236
Test name
Test status
Simulation time 20006678337 ps
CPU time 81.53 seconds
Started Jun 24 04:41:02 PM PDT 24
Finished Jun 24 04:42:32 PM PDT 24
Peak memory 239508 kb
Host smart-f40921b8-fc75-4c65-a9a7-09958bb34a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740072658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3740072658
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3458312485
Short name T55
Test name
Test status
Simulation time 4477442666 ps
CPU time 13.76 seconds
Started Jun 24 04:41:04 PM PDT 24
Finished Jun 24 04:41:26 PM PDT 24
Peak memory 224612 kb
Host smart-35d36128-1acb-451e-811c-8e8d1f26723f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458312485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3458312485
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2164496731
Short name T752
Test name
Test status
Simulation time 239898967 ps
CPU time 4.36 seconds
Started Jun 24 04:41:02 PM PDT 24
Finished Jun 24 04:41:14 PM PDT 24
Peak memory 224864 kb
Host smart-9f4f7daa-643d-4ea7-94d2-0491cd9ca2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164496731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2164496731
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3744725569
Short name T927
Test name
Test status
Simulation time 4883002695 ps
CPU time 6.8 seconds
Started Jun 24 04:41:00 PM PDT 24
Finished Jun 24 04:41:14 PM PDT 24
Peak memory 220460 kb
Host smart-61d07db0-6848-4060-a1e1-cd39ff627be3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3744725569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3744725569
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3744908820
Short name T609
Test name
Test status
Simulation time 94890644 ps
CPU time 1.09 seconds
Started Jun 24 04:41:00 PM PDT 24
Finished Jun 24 04:41:08 PM PDT 24
Peak memory 207052 kb
Host smart-b9c98388-bcf0-48e0-87f0-2b569644b62a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744908820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3744908820
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.4293060539
Short name T833
Test name
Test status
Simulation time 1352687148 ps
CPU time 7.79 seconds
Started Jun 24 04:40:59 PM PDT 24
Finished Jun 24 04:41:13 PM PDT 24
Peak memory 216192 kb
Host smart-c5b42a7b-39e5-4242-8e26-7b0029b9583a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293060539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.4293060539
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3992733456
Short name T470
Test name
Test status
Simulation time 218034906 ps
CPU time 2.32 seconds
Started Jun 24 04:41:00 PM PDT 24
Finished Jun 24 04:41:10 PM PDT 24
Peak memory 216188 kb
Host smart-3acb4461-5cb1-4eb8-b065-f53095167972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992733456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3992733456
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3053041971
Short name T31
Test name
Test status
Simulation time 19341396 ps
CPU time 1.11 seconds
Started Jun 24 04:40:58 PM PDT 24
Finished Jun 24 04:41:06 PM PDT 24
Peak memory 216152 kb
Host smart-39474e8b-1ae0-4227-a5be-23fe40b65b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053041971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3053041971
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.4004240818
Short name T891
Test name
Test status
Simulation time 127451014 ps
CPU time 0.89 seconds
Started Jun 24 04:41:08 PM PDT 24
Finished Jun 24 04:41:18 PM PDT 24
Peak memory 206276 kb
Host smart-9720fcd2-f3a8-420c-8c64-9fb9f5d3ece4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004240818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.4004240818
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.621500802
Short name T540
Test name
Test status
Simulation time 2531024785 ps
CPU time 13.32 seconds
Started Jun 24 04:41:01 PM PDT 24
Finished Jun 24 04:41:22 PM PDT 24
Peak memory 248348 kb
Host smart-708c6116-4cbd-44c5-ab79-34c2796f91bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621500802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.621500802
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.4266600162
Short name T708
Test name
Test status
Simulation time 23947427 ps
CPU time 0.72 seconds
Started Jun 24 04:41:04 PM PDT 24
Finished Jun 24 04:41:13 PM PDT 24
Peak memory 205300 kb
Host smart-b8cf1aa6-5caa-4522-9697-2154261f0929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266600162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
4266600162
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2995895344
Short name T279
Test name
Test status
Simulation time 4803202266 ps
CPU time 10.01 seconds
Started Jun 24 04:41:08 PM PDT 24
Finished Jun 24 04:41:27 PM PDT 24
Peak memory 232696 kb
Host smart-354181b1-6d1a-4878-aaa1-7bd137ff74c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995895344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2995895344
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.602818711
Short name T686
Test name
Test status
Simulation time 16926352 ps
CPU time 0.79 seconds
Started Jun 24 04:41:03 PM PDT 24
Finished Jun 24 04:41:11 PM PDT 24
Peak memory 206520 kb
Host smart-5d3e7b23-7947-4df0-81d5-3731ad429433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602818711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.602818711
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2561212012
Short name T196
Test name
Test status
Simulation time 10223839724 ps
CPU time 101.95 seconds
Started Jun 24 04:41:03 PM PDT 24
Finished Jun 24 04:42:53 PM PDT 24
Peak memory 250792 kb
Host smart-4b194c2b-8d5d-427d-afd0-03904cdb0ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561212012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2561212012
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1459120020
Short name T139
Test name
Test status
Simulation time 1465263121 ps
CPU time 17.83 seconds
Started Jun 24 04:41:02 PM PDT 24
Finished Jun 24 04:41:27 PM PDT 24
Peak memory 240992 kb
Host smart-efce48af-abfe-4dd7-ae3f-c7d8c5e777d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459120020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1459120020
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1085895548
Short name T529
Test name
Test status
Simulation time 32110689242 ps
CPU time 276.8 seconds
Started Jun 24 04:41:02 PM PDT 24
Finished Jun 24 04:45:46 PM PDT 24
Peak memory 249248 kb
Host smart-ab3ad975-4c2d-47ee-9079-8bbcb569a534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085895548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1085895548
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.4017799498
Short name T402
Test name
Test status
Simulation time 253715685 ps
CPU time 9.75 seconds
Started Jun 24 04:41:01 PM PDT 24
Finished Jun 24 04:41:19 PM PDT 24
Peak memory 240804 kb
Host smart-c8d07a68-45b6-41e5-a20b-aa5ecf46d3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017799498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.4017799498
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1542409558
Short name T158
Test name
Test status
Simulation time 1662891891 ps
CPU time 13.47 seconds
Started Jun 24 04:41:04 PM PDT 24
Finished Jun 24 04:41:26 PM PDT 24
Peak memory 232680 kb
Host smart-1e4b7fa4-6f27-4c2f-8f40-8d6541b68dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542409558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1542409558
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2632945800
Short name T476
Test name
Test status
Simulation time 24257678195 ps
CPU time 79.22 seconds
Started Jun 24 04:40:59 PM PDT 24
Finished Jun 24 04:42:26 PM PDT 24
Peak memory 240860 kb
Host smart-41f9e5ba-8504-405a-9df1-20e1ec6c6133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632945800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2632945800
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3841191268
Short name T490
Test name
Test status
Simulation time 2449394212 ps
CPU time 3.73 seconds
Started Jun 24 04:41:05 PM PDT 24
Finished Jun 24 04:41:17 PM PDT 24
Peak memory 224564 kb
Host smart-eee2fdc8-8664-4325-a8bb-8cf90f524207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841191268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3841191268
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.395798165
Short name T8
Test name
Test status
Simulation time 10437179581 ps
CPU time 18.96 seconds
Started Jun 24 04:41:02 PM PDT 24
Finished Jun 24 04:41:28 PM PDT 24
Peak memory 248912 kb
Host smart-2810b75d-885e-4838-8f55-32d076a2a23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395798165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.395798165
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.717008877
Short name T592
Test name
Test status
Simulation time 749902442 ps
CPU time 6.15 seconds
Started Jun 24 04:41:01 PM PDT 24
Finished Jun 24 04:41:15 PM PDT 24
Peak memory 220288 kb
Host smart-71b96e52-4171-4e02-8c8e-01118b354471
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=717008877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.717008877
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.4004839471
Short name T13
Test name
Test status
Simulation time 85482578 ps
CPU time 0.91 seconds
Started Jun 24 04:41:04 PM PDT 24
Finished Jun 24 04:41:14 PM PDT 24
Peak memory 206872 kb
Host smart-4b02a4e3-6c44-4a22-b7f6-df48c1249485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004839471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.4004839471
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1317078576
Short name T890
Test name
Test status
Simulation time 667216765 ps
CPU time 3.05 seconds
Started Jun 24 04:41:07 PM PDT 24
Finished Jun 24 04:41:18 PM PDT 24
Peak memory 216268 kb
Host smart-418bbe99-828f-452d-bc75-d59e66e6dfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317078576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1317078576
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3296582977
Short name T394
Test name
Test status
Simulation time 22058760327 ps
CPU time 16.7 seconds
Started Jun 24 04:41:08 PM PDT 24
Finished Jun 24 04:41:33 PM PDT 24
Peak memory 216364 kb
Host smart-bd1b892c-e515-44c2-be3a-cb66a404ba17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296582977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3296582977
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3840554045
Short name T636
Test name
Test status
Simulation time 215197450 ps
CPU time 1.3 seconds
Started Jun 24 04:41:04 PM PDT 24
Finished Jun 24 04:41:13 PM PDT 24
Peak memory 216288 kb
Host smart-d4d87228-49b0-41ee-8462-59d3437c1c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840554045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3840554045
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1109304674
Short name T478
Test name
Test status
Simulation time 72220411 ps
CPU time 0.92 seconds
Started Jun 24 04:41:04 PM PDT 24
Finished Jun 24 04:41:12 PM PDT 24
Peak memory 206000 kb
Host smart-147b0145-d806-4fa3-97b5-a74e58b41cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109304674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1109304674
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2448424098
Short name T257
Test name
Test status
Simulation time 3755300493 ps
CPU time 11.43 seconds
Started Jun 24 04:41:02 PM PDT 24
Finished Jun 24 04:41:21 PM PDT 24
Peak memory 232848 kb
Host smart-64887c29-9651-438f-9061-1ef968251ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448424098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2448424098
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2092405094
Short name T570
Test name
Test status
Simulation time 50529317 ps
CPU time 0.69 seconds
Started Jun 24 04:41:10 PM PDT 24
Finished Jun 24 04:41:20 PM PDT 24
Peak memory 205372 kb
Host smart-34e2d284-8ba5-4e6e-bfc2-66c22ad294e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092405094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2092405094
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.68496536
Short name T620
Test name
Test status
Simulation time 746195449 ps
CPU time 5.48 seconds
Started Jun 24 04:41:12 PM PDT 24
Finished Jun 24 04:41:27 PM PDT 24
Peak memory 232692 kb
Host smart-304bc01d-426d-4068-b299-43eca02a26df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68496536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.68496536
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.343037050
Short name T466
Test name
Test status
Simulation time 25750932 ps
CPU time 0.73 seconds
Started Jun 24 04:41:01 PM PDT 24
Finished Jun 24 04:41:10 PM PDT 24
Peak memory 205888 kb
Host smart-579ba17c-f66c-4a7e-b01f-c4a08d15cdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343037050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.343037050
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.822061210
Short name T228
Test name
Test status
Simulation time 3697154268 ps
CPU time 70.01 seconds
Started Jun 24 04:41:11 PM PDT 24
Finished Jun 24 04:42:30 PM PDT 24
Peak memory 250224 kb
Host smart-acdff85f-346d-4ca0-a248-8b5c9c2fd55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822061210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.822061210
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3000990184
Short name T902
Test name
Test status
Simulation time 58414418461 ps
CPU time 150.17 seconds
Started Jun 24 04:41:14 PM PDT 24
Finished Jun 24 04:43:54 PM PDT 24
Peak memory 257808 kb
Host smart-75544b63-9fae-4acc-a584-95b7726fe0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000990184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3000990184
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1818745482
Short name T776
Test name
Test status
Simulation time 31268311086 ps
CPU time 51.79 seconds
Started Jun 24 04:41:09 PM PDT 24
Finished Jun 24 04:42:09 PM PDT 24
Peak memory 249260 kb
Host smart-04d552bc-5adc-405b-ac35-e663bfb9da74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818745482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1818745482
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1638281294
Short name T873
Test name
Test status
Simulation time 2310494862 ps
CPU time 35.73 seconds
Started Jun 24 04:41:20 PM PDT 24
Finished Jun 24 04:42:06 PM PDT 24
Peak memory 249184 kb
Host smart-edc209eb-5653-407f-a76a-3f3b89d7942b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638281294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1638281294
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1503427822
Short name T242
Test name
Test status
Simulation time 3575962840 ps
CPU time 20.96 seconds
Started Jun 24 04:41:12 PM PDT 24
Finished Jun 24 04:41:42 PM PDT 24
Peak memory 232900 kb
Host smart-e8903bec-c438-471f-8182-5de4e1f7582d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503427822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1503427822
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2236624919
Short name T438
Test name
Test status
Simulation time 91524414 ps
CPU time 2.14 seconds
Started Jun 24 04:41:10 PM PDT 24
Finished Jun 24 04:41:21 PM PDT 24
Peak memory 223128 kb
Host smart-f4979b2a-b60e-4e3c-8e4a-f9ff60259c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236624919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2236624919
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.369142599
Short name T799
Test name
Test status
Simulation time 1046719091 ps
CPU time 8.37 seconds
Started Jun 24 04:41:01 PM PDT 24
Finished Jun 24 04:41:17 PM PDT 24
Peak memory 232624 kb
Host smart-63a9fff8-8d7c-4ac5-92e7-425abc554bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369142599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.369142599
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.4282283126
Short name T229
Test name
Test status
Simulation time 48685901002 ps
CPU time 15.01 seconds
Started Jun 24 04:41:02 PM PDT 24
Finished Jun 24 04:41:24 PM PDT 24
Peak memory 224580 kb
Host smart-1a51b71e-0736-430f-b797-44470c0d06a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282283126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.4282283126
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.334437728
Short name T548
Test name
Test status
Simulation time 4977658893 ps
CPU time 28.06 seconds
Started Jun 24 04:41:01 PM PDT 24
Finished Jun 24 04:41:36 PM PDT 24
Peak memory 220088 kb
Host smart-dea1e69c-41fb-4451-8651-ef175599df8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334437728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.334437728
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.965370271
Short name T834
Test name
Test status
Simulation time 84496053 ps
CPU time 1.14 seconds
Started Jun 24 04:40:59 PM PDT 24
Finished Jun 24 04:41:08 PM PDT 24
Peak memory 207000 kb
Host smart-621808a3-e840-45ab-b7b0-8a7cebe83203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965370271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.965370271
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3922382962
Short name T623
Test name
Test status
Simulation time 15272969 ps
CPU time 0.69 seconds
Started Jun 24 04:41:01 PM PDT 24
Finished Jun 24 04:41:09 PM PDT 24
Peak memory 205540 kb
Host smart-537f9592-7941-47f1-a878-b7e63d0f890d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922382962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3922382962
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.4028020216
Short name T562
Test name
Test status
Simulation time 126974824 ps
CPU time 1.03 seconds
Started Jun 24 04:41:05 PM PDT 24
Finished Jun 24 04:41:14 PM PDT 24
Peak memory 205912 kb
Host smart-d3750c2e-ac12-40c0-8bec-26379e3deb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028020216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.4028020216
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1834133473
Short name T600
Test name
Test status
Simulation time 1686293575 ps
CPU time 3.31 seconds
Started Jun 24 04:41:13 PM PDT 24
Finished Jun 24 04:41:26 PM PDT 24
Peak memory 224496 kb
Host smart-2d8118c1-9d82-4658-93f6-2ad84d5b85c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834133473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1834133473
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.4277219899
Short name T546
Test name
Test status
Simulation time 16398660 ps
CPU time 0.72 seconds
Started Jun 24 04:41:08 PM PDT 24
Finished Jun 24 04:41:17 PM PDT 24
Peak memory 204824 kb
Host smart-5df2f2e0-27ec-45c9-9ab1-f5c4709e7e64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277219899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
4277219899
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3950894624
Short name T484
Test name
Test status
Simulation time 109277264 ps
CPU time 2.49 seconds
Started Jun 24 04:41:13 PM PDT 24
Finished Jun 24 04:41:25 PM PDT 24
Peak memory 232348 kb
Host smart-203648c9-1c70-408c-b427-32bc8a04a2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950894624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3950894624
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3113587982
Short name T173
Test name
Test status
Simulation time 50916460 ps
CPU time 0.76 seconds
Started Jun 24 04:41:13 PM PDT 24
Finished Jun 24 04:41:23 PM PDT 24
Peak memory 205928 kb
Host smart-d3d37a2e-cdc0-4a71-914d-e52c5cfb91ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113587982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3113587982
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2512723603
Short name T291
Test name
Test status
Simulation time 53125795136 ps
CPU time 109.04 seconds
Started Jun 24 04:41:14 PM PDT 24
Finished Jun 24 04:43:13 PM PDT 24
Peak memory 253092 kb
Host smart-5c61333f-8df5-46c9-bf6d-a73cd7aad47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512723603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2512723603
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1978270396
Short name T218
Test name
Test status
Simulation time 31311731515 ps
CPU time 136.3 seconds
Started Jun 24 04:41:11 PM PDT 24
Finished Jun 24 04:43:37 PM PDT 24
Peak memory 236436 kb
Host smart-e5520f16-cdd5-4469-b36e-ba58b8ea441e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978270396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1978270396
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3117889389
Short name T840
Test name
Test status
Simulation time 14726303964 ps
CPU time 84.29 seconds
Started Jun 24 04:41:13 PM PDT 24
Finished Jun 24 04:42:47 PM PDT 24
Peak memory 254552 kb
Host smart-6a0de1ef-e317-404e-92e6-e96be56a2f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117889389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3117889389
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1453038316
Short name T527
Test name
Test status
Simulation time 438708471 ps
CPU time 5.08 seconds
Started Jun 24 04:41:13 PM PDT 24
Finished Jun 24 04:41:27 PM PDT 24
Peak memory 228164 kb
Host smart-b1610421-4d16-47ee-94ca-99c00980dbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453038316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1453038316
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.511586419
Short name T274
Test name
Test status
Simulation time 11200075458 ps
CPU time 36.4 seconds
Started Jun 24 04:41:12 PM PDT 24
Finished Jun 24 04:41:58 PM PDT 24
Peak memory 224652 kb
Host smart-87caf3b8-431f-41cd-8015-be1e0e932ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511586419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.511586419
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1491303464
Short name T443
Test name
Test status
Simulation time 629582221 ps
CPU time 2.82 seconds
Started Jun 24 04:41:09 PM PDT 24
Finished Jun 24 04:41:21 PM PDT 24
Peak memory 224412 kb
Host smart-1b25cff0-cfcd-4057-91e4-a5ee03bc9db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491303464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1491303464
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2818022303
Short name T706
Test name
Test status
Simulation time 273259575 ps
CPU time 4.38 seconds
Started Jun 24 04:41:12 PM PDT 24
Finished Jun 24 04:41:25 PM PDT 24
Peak memory 232660 kb
Host smart-95715eeb-2f1e-4360-a05c-dde20bb36ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818022303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2818022303
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3968136936
Short name T530
Test name
Test status
Simulation time 213454159 ps
CPU time 5.19 seconds
Started Jun 24 04:41:13 PM PDT 24
Finished Jun 24 04:41:28 PM PDT 24
Peak memory 223156 kb
Host smart-cf350537-4415-4bf6-9d6c-6b705651666a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3968136936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3968136936
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3658608460
Short name T293
Test name
Test status
Simulation time 7118478449 ps
CPU time 73.29 seconds
Started Jun 24 04:41:13 PM PDT 24
Finished Jun 24 04:42:36 PM PDT 24
Peak memory 265668 kb
Host smart-efe0b3c1-f0e6-45d9-8ffc-bc1a4b75cd5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658608460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3658608460
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2257870310
Short name T481
Test name
Test status
Simulation time 4753151482 ps
CPU time 13.51 seconds
Started Jun 24 04:41:09 PM PDT 24
Finished Jun 24 04:41:32 PM PDT 24
Peak memory 216248 kb
Host smart-e88560a0-1264-4bc6-89da-a68b9d1cdcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257870310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2257870310
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2849387073
Short name T32
Test name
Test status
Simulation time 19265919482 ps
CPU time 5.88 seconds
Started Jun 24 04:41:12 PM PDT 24
Finished Jun 24 04:41:28 PM PDT 24
Peak memory 217648 kb
Host smart-92caf052-c4df-4352-b83f-022df6788d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849387073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2849387073
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3347335528
Short name T411
Test name
Test status
Simulation time 18647653 ps
CPU time 0.87 seconds
Started Jun 24 04:41:13 PM PDT 24
Finished Jun 24 04:41:24 PM PDT 24
Peak memory 206976 kb
Host smart-a748a03c-19eb-4c09-84b4-71cdaf8d3e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347335528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3347335528
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.4184944651
Short name T373
Test name
Test status
Simulation time 12271435 ps
CPU time 0.72 seconds
Started Jun 24 04:41:09 PM PDT 24
Finished Jun 24 04:41:18 PM PDT 24
Peak memory 205912 kb
Host smart-a1c00d0f-c25e-4166-8752-e10ef1b12047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184944651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.4184944651
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2448500972
Short name T761
Test name
Test status
Simulation time 377421148 ps
CPU time 3.8 seconds
Started Jun 24 04:41:10 PM PDT 24
Finished Jun 24 04:41:23 PM PDT 24
Peak memory 224500 kb
Host smart-c0d4c4fc-1c56-4826-b310-320e00124ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448500972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2448500972
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3287650453
Short name T583
Test name
Test status
Simulation time 25414304 ps
CPU time 0.74 seconds
Started Jun 24 04:41:12 PM PDT 24
Finished Jun 24 04:41:22 PM PDT 24
Peak memory 204732 kb
Host smart-6ae9ff64-8d51-4d0d-bc78-a7f9704af696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287650453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3287650453
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1095445273
Short name T691
Test name
Test status
Simulation time 4671591674 ps
CPU time 15.53 seconds
Started Jun 24 04:41:09 PM PDT 24
Finished Jun 24 04:41:33 PM PDT 24
Peak memory 224576 kb
Host smart-81b910bc-db21-4f10-a847-5fadadc9cf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095445273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1095445273
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2249077229
Short name T673
Test name
Test status
Simulation time 13971621 ps
CPU time 0.73 seconds
Started Jun 24 04:41:12 PM PDT 24
Finished Jun 24 04:41:22 PM PDT 24
Peak memory 205852 kb
Host smart-93f88045-944f-4ece-bf3d-7f00b2108c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249077229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2249077229
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3982072783
Short name T941
Test name
Test status
Simulation time 132279048347 ps
CPU time 344.79 seconds
Started Jun 24 04:41:19 PM PDT 24
Finished Jun 24 04:47:14 PM PDT 24
Peak memory 260236 kb
Host smart-6429656c-8300-47e8-ba80-211895e30de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982072783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3982072783
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3090352940
Short name T862
Test name
Test status
Simulation time 101544447397 ps
CPU time 253.17 seconds
Started Jun 24 04:41:12 PM PDT 24
Finished Jun 24 04:45:34 PM PDT 24
Peak memory 253868 kb
Host smart-a8e74440-3814-469d-b4f4-a884a6c5a6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090352940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3090352940
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2378600962
Short name T136
Test name
Test status
Simulation time 3272223700 ps
CPU time 28.65 seconds
Started Jun 24 04:41:12 PM PDT 24
Finished Jun 24 04:41:49 PM PDT 24
Peak memory 224540 kb
Host smart-1b11b42c-2b79-4ca2-9c78-96acef11293b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378600962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2378600962
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2680415664
Short name T134
Test name
Test status
Simulation time 276292971 ps
CPU time 6.1 seconds
Started Jun 24 04:41:14 PM PDT 24
Finished Jun 24 04:41:30 PM PDT 24
Peak memory 232676 kb
Host smart-f075894e-8299-400c-a5d6-5829f157fdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680415664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2680415664
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.923770177
Short name T738
Test name
Test status
Simulation time 12081727052 ps
CPU time 104.08 seconds
Started Jun 24 04:41:12 PM PDT 24
Finished Jun 24 04:43:05 PM PDT 24
Peak memory 240984 kb
Host smart-5f6618ee-8f90-427f-bb1d-d7c6861c6af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923770177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.923770177
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2251966243
Short name T226
Test name
Test status
Simulation time 1236686635 ps
CPU time 3.25 seconds
Started Jun 24 04:41:09 PM PDT 24
Finished Jun 24 04:41:22 PM PDT 24
Peak memory 224472 kb
Host smart-4363509f-4ad5-42e1-a426-5052105bb5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251966243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2251966243
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3823157438
Short name T209
Test name
Test status
Simulation time 942555097 ps
CPU time 3.77 seconds
Started Jun 24 04:41:15 PM PDT 24
Finished Jun 24 04:41:28 PM PDT 24
Peak memory 232716 kb
Host smart-f0cce457-1192-4508-9338-304fd5b9d3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823157438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3823157438
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.884039009
Short name T842
Test name
Test status
Simulation time 1118910216 ps
CPU time 4.73 seconds
Started Jun 24 04:41:12 PM PDT 24
Finished Jun 24 04:41:26 PM PDT 24
Peak memory 219284 kb
Host smart-a33ef4f7-7c1e-4555-a9b4-4f291879b923
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=884039009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.884039009
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.4226854573
Short name T213
Test name
Test status
Simulation time 34447809018 ps
CPU time 367.74 seconds
Started Jun 24 04:41:13 PM PDT 24
Finished Jun 24 04:47:30 PM PDT 24
Peak memory 269192 kb
Host smart-47eec9a7-54c6-4fe2-9fa9-a3f8882f51df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226854573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.4226854573
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1004170227
Short name T791
Test name
Test status
Simulation time 13245184341 ps
CPU time 38.06 seconds
Started Jun 24 04:41:12 PM PDT 24
Finished Jun 24 04:42:00 PM PDT 24
Peak memory 216296 kb
Host smart-1fb5aba9-adfe-40eb-aebc-b9ffa9697aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004170227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1004170227
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.4082897466
Short name T898
Test name
Test status
Simulation time 5780979347 ps
CPU time 7.91 seconds
Started Jun 24 04:41:07 PM PDT 24
Finished Jun 24 04:41:23 PM PDT 24
Peak memory 216368 kb
Host smart-4d6997a3-5498-4dbf-b3e6-6f3b322e11b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082897466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.4082897466
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2482239156
Short name T378
Test name
Test status
Simulation time 11508038 ps
CPU time 0.69 seconds
Started Jun 24 04:41:19 PM PDT 24
Finished Jun 24 04:41:30 PM PDT 24
Peak memory 205460 kb
Host smart-063ff50c-0fc3-4a76-88db-ec0256ae03b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482239156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2482239156
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.274550485
Short name T938
Test name
Test status
Simulation time 69981024 ps
CPU time 0.95 seconds
Started Jun 24 04:41:10 PM PDT 24
Finished Jun 24 04:41:20 PM PDT 24
Peak memory 206888 kb
Host smart-0ee5ddfd-4f6a-4f09-a241-01f3ece5b60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274550485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.274550485
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.4047334124
Short name T828
Test name
Test status
Simulation time 6467495349 ps
CPU time 20.53 seconds
Started Jun 24 04:41:15 PM PDT 24
Finished Jun 24 04:41:45 PM PDT 24
Peak memory 240048 kb
Host smart-8b50304b-ee24-4354-afcf-cf74ef81b37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047334124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.4047334124
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2239066177
Short name T720
Test name
Test status
Simulation time 13117992 ps
CPU time 0.7 seconds
Started Jun 24 04:41:12 PM PDT 24
Finished Jun 24 04:41:22 PM PDT 24
Peak memory 204776 kb
Host smart-798c9aa2-7f3c-44df-8950-8fd64376e0c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239066177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2239066177
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2571548149
Short name T435
Test name
Test status
Simulation time 1223861900 ps
CPU time 6.6 seconds
Started Jun 24 04:41:15 PM PDT 24
Finished Jun 24 04:41:32 PM PDT 24
Peak memory 232696 kb
Host smart-66a8ee6f-a05e-46c1-9491-542ce2a25472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571548149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2571548149
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.267339735
Short name T429
Test name
Test status
Simulation time 55785243 ps
CPU time 0.75 seconds
Started Jun 24 04:41:10 PM PDT 24
Finished Jun 24 04:41:19 PM PDT 24
Peak memory 205880 kb
Host smart-52b1ef9c-3356-4f3d-9085-7cfdbeb7fef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267339735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.267339735
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2413625447
Short name T627
Test name
Test status
Simulation time 60200448720 ps
CPU time 82.37 seconds
Started Jun 24 04:41:15 PM PDT 24
Finished Jun 24 04:42:48 PM PDT 24
Peak memory 253424 kb
Host smart-a3e93b7c-a031-4584-ad21-900cdb787fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413625447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2413625447
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3442937350
Short name T420
Test name
Test status
Simulation time 20025213652 ps
CPU time 160.13 seconds
Started Jun 24 04:41:08 PM PDT 24
Finished Jun 24 04:43:57 PM PDT 24
Peak memory 256476 kb
Host smart-de12e27b-787d-4c81-8512-2bab61dc61af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442937350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3442937350
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2223591135
Short name T810
Test name
Test status
Simulation time 266131673 ps
CPU time 7.86 seconds
Started Jun 24 04:41:10 PM PDT 24
Finished Jun 24 04:41:26 PM PDT 24
Peak memory 233796 kb
Host smart-73527b9d-9e59-4459-95a4-888a34914ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223591135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2223591135
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1981564526
Short name T589
Test name
Test status
Simulation time 3010153847 ps
CPU time 17.36 seconds
Started Jun 24 04:41:10 PM PDT 24
Finished Jun 24 04:41:36 PM PDT 24
Peak memory 232736 kb
Host smart-afb792aa-dbd5-4749-8cb9-ea290f2019bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981564526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1981564526
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.570693450
Short name T235
Test name
Test status
Simulation time 4496532286 ps
CPU time 42.63 seconds
Started Jun 24 04:41:12 PM PDT 24
Finished Jun 24 04:42:04 PM PDT 24
Peak memory 224592 kb
Host smart-80ed0326-5cdf-45b8-87ff-daeeaa8fb381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570693450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.570693450
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3166580197
Short name T384
Test name
Test status
Simulation time 10236124462 ps
CPU time 10.77 seconds
Started Jun 24 04:41:13 PM PDT 24
Finished Jun 24 04:41:33 PM PDT 24
Peak memory 224596 kb
Host smart-0ba320f1-4beb-46cc-b5cd-7fcc662ae2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166580197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3166580197
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.937919650
Short name T888
Test name
Test status
Simulation time 1112877612 ps
CPU time 8.71 seconds
Started Jun 24 04:41:10 PM PDT 24
Finished Jun 24 04:41:28 PM PDT 24
Peak memory 232652 kb
Host smart-39b0d2ae-14d0-4634-b982-0b6fc681ac93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937919650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.937919650
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3199241960
Short name T850
Test name
Test status
Simulation time 281932077 ps
CPU time 5.06 seconds
Started Jun 24 04:41:10 PM PDT 24
Finished Jun 24 04:41:24 PM PDT 24
Peak memory 222232 kb
Host smart-c2536d26-4f57-4b03-b880-42bc6394cc58
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3199241960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3199241960
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3892989553
Short name T474
Test name
Test status
Simulation time 130890980 ps
CPU time 1.11 seconds
Started Jun 24 04:41:12 PM PDT 24
Finished Jun 24 04:41:23 PM PDT 24
Peak memory 215960 kb
Host smart-ef532739-5a5d-439f-b907-0414af634fce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892989553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3892989553
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2689560885
Short name T559
Test name
Test status
Simulation time 45978741525 ps
CPU time 52.86 seconds
Started Jun 24 04:41:12 PM PDT 24
Finished Jun 24 04:42:14 PM PDT 24
Peak memory 216424 kb
Host smart-147d7c09-5be5-472e-86d8-54f10fde0ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689560885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2689560885
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2131611560
Short name T744
Test name
Test status
Simulation time 1931797159 ps
CPU time 9.46 seconds
Started Jun 24 04:41:11 PM PDT 24
Finished Jun 24 04:41:30 PM PDT 24
Peak memory 216224 kb
Host smart-e81e865a-fcf3-4c8b-b9a3-5bf9bc8096de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131611560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2131611560
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3021654469
Short name T812
Test name
Test status
Simulation time 24459066 ps
CPU time 1.33 seconds
Started Jun 24 04:41:10 PM PDT 24
Finished Jun 24 04:41:21 PM PDT 24
Peak memory 216300 kb
Host smart-b710534d-9674-4f82-8c96-8e40e740a3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021654469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3021654469
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3630692348
Short name T550
Test name
Test status
Simulation time 141585276 ps
CPU time 0.86 seconds
Started Jun 24 04:41:11 PM PDT 24
Finished Jun 24 04:41:20 PM PDT 24
Peak memory 205908 kb
Host smart-f6e0db91-6116-46d6-abd1-c3dde3bece98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630692348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3630692348
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1084851315
Short name T606
Test name
Test status
Simulation time 587970157 ps
CPU time 4.82 seconds
Started Jun 24 04:41:09 PM PDT 24
Finished Jun 24 04:41:23 PM PDT 24
Peak memory 224508 kb
Host smart-444aec09-5a2a-444e-b302-1c31d369c154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084851315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1084851315
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1675146484
Short name T950
Test name
Test status
Simulation time 13706527 ps
CPU time 0.72 seconds
Started Jun 24 04:41:13 PM PDT 24
Finished Jun 24 04:41:23 PM PDT 24
Peak memory 204684 kb
Host smart-fec5bc8c-429a-4048-b27a-44fa6a18341a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675146484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1675146484
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1448758677
Short name T652
Test name
Test status
Simulation time 6348269625 ps
CPU time 14.1 seconds
Started Jun 24 04:41:14 PM PDT 24
Finished Jun 24 04:41:38 PM PDT 24
Peak memory 232752 kb
Host smart-4336292a-12d7-4948-b1d8-7abf73e9d1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448758677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1448758677
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3913441346
Short name T349
Test name
Test status
Simulation time 31304606 ps
CPU time 0.78 seconds
Started Jun 24 04:41:12 PM PDT 24
Finished Jun 24 04:41:22 PM PDT 24
Peak memory 206860 kb
Host smart-0bb6d018-1a5b-4578-b9c8-14db66119490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913441346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3913441346
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1371338499
Short name T508
Test name
Test status
Simulation time 18071129406 ps
CPU time 176.62 seconds
Started Jun 24 04:41:18 PM PDT 24
Finished Jun 24 04:44:25 PM PDT 24
Peak memory 249264 kb
Host smart-87c636e1-79c5-4091-b0ff-0c2508461268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371338499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1371338499
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.4267362323
Short name T837
Test name
Test status
Simulation time 1751979236 ps
CPU time 5.76 seconds
Started Jun 24 04:41:17 PM PDT 24
Finished Jun 24 04:41:32 PM PDT 24
Peak memory 224416 kb
Host smart-9397be18-2d53-4e52-b12d-797d61192c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267362323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.4267362323
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.588202012
Short name T482
Test name
Test status
Simulation time 87194108 ps
CPU time 3.18 seconds
Started Jun 24 04:41:18 PM PDT 24
Finished Jun 24 04:41:31 PM PDT 24
Peak memory 224388 kb
Host smart-4b11740d-a0a6-48c0-a360-1245ffca108a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588202012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.588202012
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1402544245
Short name T248
Test name
Test status
Simulation time 671082826 ps
CPU time 7.74 seconds
Started Jun 24 04:41:15 PM PDT 24
Finished Jun 24 04:41:33 PM PDT 24
Peak memory 237768 kb
Host smart-2d4fffdf-d74a-459d-a760-30d1b679779b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402544245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1402544245
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1037831203
Short name T46
Test name
Test status
Simulation time 2166836560 ps
CPU time 12.92 seconds
Started Jun 24 04:41:15 PM PDT 24
Finished Jun 24 04:41:38 PM PDT 24
Peak memory 224432 kb
Host smart-a84ebdfb-1d77-4a8c-b6c9-3d294f9531f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037831203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1037831203
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1645888477
Short name T861
Test name
Test status
Simulation time 599725970 ps
CPU time 2.61 seconds
Started Jun 24 04:41:16 PM PDT 24
Finished Jun 24 04:41:29 PM PDT 24
Peak memory 224484 kb
Host smart-b1048471-99ef-4d9a-8b91-02f51dc141d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645888477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1645888477
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1574719714
Short name T864
Test name
Test status
Simulation time 461853255 ps
CPU time 4.69 seconds
Started Jun 24 04:41:18 PM PDT 24
Finished Jun 24 04:41:33 PM PDT 24
Peak memory 223112 kb
Host smart-9f6114cc-71db-45c9-bc26-3f1d789277da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1574719714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1574719714
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1816897230
Short name T428
Test name
Test status
Simulation time 17076859068 ps
CPU time 174.73 seconds
Started Jun 24 04:41:14 PM PDT 24
Finished Jun 24 04:44:18 PM PDT 24
Peak memory 264596 kb
Host smart-481fd70c-8863-4a9e-8e29-f0b7a1f8956a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816897230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1816897230
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.4113437137
Short name T393
Test name
Test status
Simulation time 12112569 ps
CPU time 0.73 seconds
Started Jun 24 04:41:15 PM PDT 24
Finished Jun 24 04:41:26 PM PDT 24
Peak memory 205600 kb
Host smart-d311532d-7870-4c38-b92a-2cf445c483e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113437137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.4113437137
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2343490818
Short name T360
Test name
Test status
Simulation time 19504792450 ps
CPU time 17.21 seconds
Started Jun 24 04:41:14 PM PDT 24
Finished Jun 24 04:41:42 PM PDT 24
Peak memory 216372 kb
Host smart-4c34cdf0-df35-4bf6-874c-3a928e6ceb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343490818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2343490818
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.461685096
Short name T625
Test name
Test status
Simulation time 471715082 ps
CPU time 1.67 seconds
Started Jun 24 04:41:14 PM PDT 24
Finished Jun 24 04:41:25 PM PDT 24
Peak memory 216184 kb
Host smart-047dc420-13be-4284-a065-0102e4dfe5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461685096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.461685096
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.679397818
Short name T391
Test name
Test status
Simulation time 792339969 ps
CPU time 0.92 seconds
Started Jun 24 04:41:20 PM PDT 24
Finished Jun 24 04:41:32 PM PDT 24
Peak memory 205896 kb
Host smart-7df7ece6-15bb-436a-95b4-a13ca4e5d6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679397818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.679397818
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1692131884
Short name T889
Test name
Test status
Simulation time 55704763 ps
CPU time 2.29 seconds
Started Jun 24 04:41:22 PM PDT 24
Finished Jun 24 04:41:35 PM PDT 24
Peak memory 232716 kb
Host smart-7836d55f-a95f-4507-8cf4-9196caad665f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692131884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1692131884
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.503430833
Short name T876
Test name
Test status
Simulation time 63720580 ps
CPU time 0.73 seconds
Started Jun 24 04:41:19 PM PDT 24
Finished Jun 24 04:41:30 PM PDT 24
Peak memory 204684 kb
Host smart-6b6c5c00-5908-4969-b193-008273aa9750
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503430833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.503430833
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1744776325
Short name T30
Test name
Test status
Simulation time 484920179 ps
CPU time 7.14 seconds
Started Jun 24 04:41:22 PM PDT 24
Finished Jun 24 04:41:41 PM PDT 24
Peak memory 232624 kb
Host smart-21fca6ae-74d2-45b6-9e2d-f308799ede0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744776325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1744776325
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3447970250
Short name T440
Test name
Test status
Simulation time 27254734 ps
CPU time 0.76 seconds
Started Jun 24 04:41:21 PM PDT 24
Finished Jun 24 04:41:32 PM PDT 24
Peak memory 206556 kb
Host smart-544c86c8-ac6e-411d-8a18-c152fe75ad1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447970250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3447970250
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3965887486
Short name T824
Test name
Test status
Simulation time 546856935 ps
CPU time 13.85 seconds
Started Jun 24 04:41:17 PM PDT 24
Finished Jun 24 04:41:41 PM PDT 24
Peak memory 234124 kb
Host smart-287a3632-f759-4e62-920a-636e5c82e922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965887486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3965887486
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.982640316
Short name T225
Test name
Test status
Simulation time 29241186750 ps
CPU time 86.57 seconds
Started Jun 24 04:41:21 PM PDT 24
Finished Jun 24 04:42:58 PM PDT 24
Peak memory 256656 kb
Host smart-cd0b3ba8-797a-4dc9-8152-be609bb94ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982640316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.982640316
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2415733228
Short name T826
Test name
Test status
Simulation time 13406000320 ps
CPU time 104.07 seconds
Started Jun 24 04:41:15 PM PDT 24
Finished Jun 24 04:43:09 PM PDT 24
Peak memory 269992 kb
Host smart-5ee04c45-5b6a-447c-b0e6-95d9108cc443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415733228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2415733228
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3140968794
Short name T675
Test name
Test status
Simulation time 2528313441 ps
CPU time 5.61 seconds
Started Jun 24 04:41:18 PM PDT 24
Finished Jun 24 04:41:34 PM PDT 24
Peak memory 232720 kb
Host smart-59044f62-5e35-4a1f-a593-72cfd9dcebdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140968794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3140968794
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1294348779
Short name T473
Test name
Test status
Simulation time 247471301 ps
CPU time 5.1 seconds
Started Jun 24 04:41:22 PM PDT 24
Finished Jun 24 04:41:38 PM PDT 24
Peak memory 224460 kb
Host smart-084428c2-d7b7-4b55-842c-01fc6f7aca73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294348779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1294348779
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1198886172
Short name T567
Test name
Test status
Simulation time 14033277499 ps
CPU time 40.89 seconds
Started Jun 24 04:41:14 PM PDT 24
Finished Jun 24 04:42:05 PM PDT 24
Peak memory 240544 kb
Host smart-1f33d4d0-12c4-46b7-8b71-215e90ce5e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198886172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1198886172
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1147567912
Short name T407
Test name
Test status
Simulation time 10716308084 ps
CPU time 12.38 seconds
Started Jun 24 04:41:18 PM PDT 24
Finished Jun 24 04:41:40 PM PDT 24
Peak memory 232792 kb
Host smart-dd72afa0-4dd7-4eeb-8a95-6b66570b2941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147567912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1147567912
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2647248688
Short name T461
Test name
Test status
Simulation time 459418193 ps
CPU time 3.89 seconds
Started Jun 24 04:41:14 PM PDT 24
Finished Jun 24 04:41:28 PM PDT 24
Peak memory 224500 kb
Host smart-467e0df8-7207-47a5-bffb-488bf799d2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647248688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2647248688
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1367255058
Short name T541
Test name
Test status
Simulation time 309894468 ps
CPU time 4.48 seconds
Started Jun 24 04:41:18 PM PDT 24
Finished Jun 24 04:41:33 PM PDT 24
Peak memory 220424 kb
Host smart-d112d7dd-e670-4331-9ed5-f33d5a0c680e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1367255058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1367255058
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1546966529
Short name T823
Test name
Test status
Simulation time 4976930681 ps
CPU time 49.6 seconds
Started Jun 24 04:41:18 PM PDT 24
Finished Jun 24 04:42:18 PM PDT 24
Peak memory 224668 kb
Host smart-2d4a9b4a-a31a-4ae8-9e78-f3f5d522ee99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546966529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1546966529
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.481802141
Short name T319
Test name
Test status
Simulation time 6338862228 ps
CPU time 30.96 seconds
Started Jun 24 04:41:20 PM PDT 24
Finished Jun 24 04:42:01 PM PDT 24
Peak memory 216324 kb
Host smart-b8f4421d-8def-47f2-a66b-626fc012f23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481802141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.481802141
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.383570739
Short name T835
Test name
Test status
Simulation time 1379790208 ps
CPU time 5.93 seconds
Started Jun 24 04:41:20 PM PDT 24
Finished Jun 24 04:41:37 PM PDT 24
Peak memory 216212 kb
Host smart-45f6e2cf-7758-4362-be75-205115538e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383570739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.383570739
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3427374097
Short name T171
Test name
Test status
Simulation time 45411584 ps
CPU time 1.31 seconds
Started Jun 24 04:41:18 PM PDT 24
Finished Jun 24 04:41:30 PM PDT 24
Peak memory 216220 kb
Host smart-6f99b970-376a-447f-907e-4855de498c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427374097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3427374097
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3637710472
Short name T480
Test name
Test status
Simulation time 38876396 ps
CPU time 0.7 seconds
Started Jun 24 04:41:12 PM PDT 24
Finished Jun 24 04:41:21 PM PDT 24
Peak memory 205604 kb
Host smart-f0a65428-74a7-4490-ac9c-471629da9176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637710472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3637710472
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.4012439193
Short name T233
Test name
Test status
Simulation time 312651444 ps
CPU time 6.47 seconds
Started Jun 24 04:41:22 PM PDT 24
Finished Jun 24 04:41:39 PM PDT 24
Peak memory 240644 kb
Host smart-17e2652f-3887-49fe-b501-589efec57c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012439193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.4012439193
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.929783126
Short name T693
Test name
Test status
Simulation time 21039733 ps
CPU time 0.73 seconds
Started Jun 24 04:40:27 PM PDT 24
Finished Jun 24 04:40:41 PM PDT 24
Peak memory 205348 kb
Host smart-60bab25c-934f-4b82-afc6-485b5db57603
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929783126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.929783126
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3894081167
Short name T843
Test name
Test status
Simulation time 247864322 ps
CPU time 2.95 seconds
Started Jun 24 04:40:21 PM PDT 24
Finished Jun 24 04:40:40 PM PDT 24
Peak memory 232740 kb
Host smart-ad0cce4d-b73a-4bd4-b74e-a168a6d1cc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894081167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3894081167
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.4070174507
Short name T135
Test name
Test status
Simulation time 153209794 ps
CPU time 0.73 seconds
Started Jun 24 04:40:18 PM PDT 24
Finished Jun 24 04:40:36 PM PDT 24
Peak memory 205536 kb
Host smart-39a9f90f-3134-437c-8bee-5012c19ac88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070174507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.4070174507
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1021709100
Short name T539
Test name
Test status
Simulation time 82692998388 ps
CPU time 173.46 seconds
Started Jun 24 04:40:25 PM PDT 24
Finished Jun 24 04:43:33 PM PDT 24
Peak memory 249188 kb
Host smart-e777e876-1706-4ed0-b160-66c42507eb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021709100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1021709100
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.34469566
Short name T212
Test name
Test status
Simulation time 91552824760 ps
CPU time 916.53 seconds
Started Jun 24 04:40:32 PM PDT 24
Finished Jun 24 04:55:59 PM PDT 24
Peak memory 271048 kb
Host smart-5cdcc070-1dbc-4018-a347-94971cec3d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34469566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.34469566
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1928219680
Short name T204
Test name
Test status
Simulation time 4407649523 ps
CPU time 19.77 seconds
Started Jun 24 04:40:18 PM PDT 24
Finished Jun 24 04:40:56 PM PDT 24
Peak memory 224572 kb
Host smart-6ded7dbc-b34e-4961-ac8f-08ac88501a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928219680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1928219680
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3779229864
Short name T206
Test name
Test status
Simulation time 1518620523 ps
CPU time 21.38 seconds
Started Jun 24 04:40:21 PM PDT 24
Finished Jun 24 04:40:59 PM PDT 24
Peak memory 240260 kb
Host smart-06748088-6b7b-4b09-aa20-1c7d2985f809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779229864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3779229864
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.738170063
Short name T299
Test name
Test status
Simulation time 4198393729 ps
CPU time 14.54 seconds
Started Jun 24 04:40:21 PM PDT 24
Finished Jun 24 04:40:52 PM PDT 24
Peak memory 224604 kb
Host smart-24bac00c-f1e3-4339-ab7d-e6f264d93348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738170063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
738170063
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2251699846
Short name T251
Test name
Test status
Simulation time 454400969 ps
CPU time 2.7 seconds
Started Jun 24 04:40:21 PM PDT 24
Finished Jun 24 04:40:40 PM PDT 24
Peak memory 232692 kb
Host smart-b197c592-dc0d-4487-ad3b-d44124aabfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251699846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2251699846
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1272435105
Short name T485
Test name
Test status
Simulation time 1478009457 ps
CPU time 13.72 seconds
Started Jun 24 04:40:19 PM PDT 24
Finished Jun 24 04:40:50 PM PDT 24
Peak memory 220452 kb
Host smart-861d3567-b303-486a-8331-b8ed15297126
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1272435105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1272435105
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1483284530
Short name T72
Test name
Test status
Simulation time 157298405 ps
CPU time 1.15 seconds
Started Jun 24 04:40:25 PM PDT 24
Finished Jun 24 04:40:40 PM PDT 24
Peak memory 235212 kb
Host smart-d8763f96-e321-48f3-be50-f85396f33570
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483284530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1483284530
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1692314851
Short name T59
Test name
Test status
Simulation time 23686134670 ps
CPU time 40.93 seconds
Started Jun 24 04:40:28 PM PDT 24
Finished Jun 24 04:41:21 PM PDT 24
Peak memory 234608 kb
Host smart-a8e76147-5b38-4b04-95be-d68cb95a6246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692314851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1692314851
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2507422854
Short name T666
Test name
Test status
Simulation time 96027422 ps
CPU time 2.5 seconds
Started Jun 24 04:40:17 PM PDT 24
Finished Jun 24 04:40:38 PM PDT 24
Peak memory 216248 kb
Host smart-ff60547f-2064-4b5e-9fff-42d4ffb001e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507422854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2507422854
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1888159398
Short name T561
Test name
Test status
Simulation time 1855534148 ps
CPU time 5.13 seconds
Started Jun 24 04:40:19 PM PDT 24
Finished Jun 24 04:40:42 PM PDT 24
Peak memory 216288 kb
Host smart-002b3549-cd90-4ed3-b379-ab27c82a0ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888159398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1888159398
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2767759536
Short name T893
Test name
Test status
Simulation time 59798880 ps
CPU time 0.85 seconds
Started Jun 24 04:40:18 PM PDT 24
Finished Jun 24 04:40:38 PM PDT 24
Peak memory 205904 kb
Host smart-e8ba8904-3ab8-4854-8952-4559a831854c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767759536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2767759536
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2423438427
Short name T870
Test name
Test status
Simulation time 51134996 ps
CPU time 0.82 seconds
Started Jun 24 04:40:20 PM PDT 24
Finished Jun 24 04:40:38 PM PDT 24
Peak memory 205888 kb
Host smart-17f03fa2-3765-4b13-8489-04e1421958fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423438427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2423438427
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3432015599
Short name T79
Test name
Test status
Simulation time 12213454576 ps
CPU time 39.39 seconds
Started Jun 24 04:40:21 PM PDT 24
Finished Jun 24 04:41:17 PM PDT 24
Peak memory 224580 kb
Host smart-5b69800a-d4c1-4dd3-9e43-f8aca5d35dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432015599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3432015599
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3983193480
Short name T132
Test name
Test status
Simulation time 24821785 ps
CPU time 0.72 seconds
Started Jun 24 04:41:21 PM PDT 24
Finished Jun 24 04:41:33 PM PDT 24
Peak memory 205252 kb
Host smart-41dc5d37-c539-43d8-9051-78206c2e638b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983193480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3983193480
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.216482228
Short name T780
Test name
Test status
Simulation time 862060750 ps
CPU time 3.58 seconds
Started Jun 24 04:41:22 PM PDT 24
Finished Jun 24 04:41:36 PM PDT 24
Peak memory 224528 kb
Host smart-711bfab5-5a1a-443a-b28d-281e69703f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216482228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.216482228
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.889807132
Short name T333
Test name
Test status
Simulation time 18083296 ps
CPU time 0.75 seconds
Started Jun 24 04:41:17 PM PDT 24
Finished Jun 24 04:41:28 PM PDT 24
Peak memory 206868 kb
Host smart-a70ec5c4-c986-4ee8-8a2d-61954d10fe92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889807132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.889807132
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2753336514
Short name T883
Test name
Test status
Simulation time 11877143442 ps
CPU time 82.16 seconds
Started Jun 24 04:41:24 PM PDT 24
Finished Jun 24 04:42:57 PM PDT 24
Peak memory 249208 kb
Host smart-491abd10-39f8-45c3-abba-b6f4086b12dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753336514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2753336514
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2427406346
Short name T663
Test name
Test status
Simulation time 22958928905 ps
CPU time 193.59 seconds
Started Jun 24 04:41:21 PM PDT 24
Finished Jun 24 04:44:45 PM PDT 24
Peak memory 249260 kb
Host smart-0c7364a1-5122-4554-88d5-321d19542b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427406346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2427406346
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.410349345
Short name T749
Test name
Test status
Simulation time 6916377595 ps
CPU time 70.1 seconds
Started Jun 24 04:41:21 PM PDT 24
Finished Jun 24 04:42:41 PM PDT 24
Peak memory 249280 kb
Host smart-1f7c25ae-32dd-4c36-8736-d1e4d12f459f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410349345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.410349345
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3086675652
Short name T151
Test name
Test status
Simulation time 1424659362 ps
CPU time 26.58 seconds
Started Jun 24 04:41:23 PM PDT 24
Finished Jun 24 04:42:00 PM PDT 24
Peak memory 224388 kb
Host smart-778fd014-79d4-4dfc-8b5c-148e5133128b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086675652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3086675652
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2276597796
Short name T203
Test name
Test status
Simulation time 2293707837 ps
CPU time 19.85 seconds
Started Jun 24 04:41:17 PM PDT 24
Finished Jun 24 04:41:46 PM PDT 24
Peak memory 232780 kb
Host smart-23dc9705-e691-425f-8359-009ebe6cd9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276597796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2276597796
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.4251206
Short name T919
Test name
Test status
Simulation time 3944678518 ps
CPU time 34.23 seconds
Started Jun 24 04:41:22 PM PDT 24
Finished Jun 24 04:42:07 PM PDT 24
Peak memory 240988 kb
Host smart-d00432ae-b864-4f3f-94b3-3b8a9297ca5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.4251206
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3011224736
Short name T648
Test name
Test status
Simulation time 7955543091 ps
CPU time 10.4 seconds
Started Jun 24 04:41:21 PM PDT 24
Finished Jun 24 04:41:42 PM PDT 24
Peak memory 224556 kb
Host smart-e8087530-9eab-4c99-813a-d0755dbfa08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011224736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3011224736
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2150244047
Short name T486
Test name
Test status
Simulation time 268024953 ps
CPU time 5.41 seconds
Started Jun 24 04:41:23 PM PDT 24
Finished Jun 24 04:41:40 PM PDT 24
Peak memory 232688 kb
Host smart-2ed7d38e-68a4-41f2-b620-7e39d670469e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150244047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2150244047
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.4248994434
Short name T909
Test name
Test status
Simulation time 1216815466 ps
CPU time 13.92 seconds
Started Jun 24 04:41:20 PM PDT 24
Finished Jun 24 04:41:44 PM PDT 24
Peak memory 220488 kb
Host smart-f6b54108-eb01-4a57-91ab-1edde2c44fb5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4248994434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.4248994434
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1202634881
Short name T230
Test name
Test status
Simulation time 76175539065 ps
CPU time 357.42 seconds
Started Jun 24 04:41:20 PM PDT 24
Finished Jun 24 04:47:29 PM PDT 24
Peak memory 256796 kb
Host smart-02bee8b9-e4b9-46e8-9efc-28cec6f263b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202634881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1202634881
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2238874741
Short name T323
Test name
Test status
Simulation time 8853726604 ps
CPU time 41.49 seconds
Started Jun 24 04:41:14 PM PDT 24
Finished Jun 24 04:42:06 PM PDT 24
Peak memory 216340 kb
Host smart-be6daed8-7d85-4329-9827-ddf61182b135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238874741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2238874741
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3792601480
Short name T401
Test name
Test status
Simulation time 40143581 ps
CPU time 0.72 seconds
Started Jun 24 04:41:13 PM PDT 24
Finished Jun 24 04:41:24 PM PDT 24
Peak memory 205600 kb
Host smart-37748861-4de7-413f-91bf-1c535424383e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792601480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3792601480
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.192090701
Short name T423
Test name
Test status
Simulation time 56846837 ps
CPU time 1.08 seconds
Started Jun 24 04:41:16 PM PDT 24
Finished Jun 24 04:41:27 PM PDT 24
Peak memory 207916 kb
Host smart-d269044d-3ee7-41f2-9b9a-6a911a1781c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192090701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.192090701
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.4263823467
Short name T555
Test name
Test status
Simulation time 35074037 ps
CPU time 0.78 seconds
Started Jun 24 04:41:15 PM PDT 24
Finished Jun 24 04:41:26 PM PDT 24
Peak memory 205944 kb
Host smart-37ce2e60-fa52-439f-b763-374c9366c135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263823467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.4263823467
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2952949042
Short name T216
Test name
Test status
Simulation time 6387670936 ps
CPU time 8.33 seconds
Started Jun 24 04:41:20 PM PDT 24
Finished Jun 24 04:41:40 PM PDT 24
Peak memory 224704 kb
Host smart-c263f259-633b-418a-8469-202f18cb9193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952949042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2952949042
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1763892103
Short name T601
Test name
Test status
Simulation time 12056349 ps
CPU time 0.77 seconds
Started Jun 24 04:41:20 PM PDT 24
Finished Jun 24 04:41:31 PM PDT 24
Peak memory 204684 kb
Host smart-7d7a387b-973f-4816-b74b-46879200f85c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763892103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1763892103
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2059005849
Short name T908
Test name
Test status
Simulation time 249809076 ps
CPU time 2.59 seconds
Started Jun 24 04:41:24 PM PDT 24
Finished Jun 24 04:41:37 PM PDT 24
Peak memory 224476 kb
Host smart-395da0ff-8e70-44ff-b59b-dcd27941df55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059005849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2059005849
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1797922487
Short name T409
Test name
Test status
Simulation time 15096666 ps
CPU time 0.76 seconds
Started Jun 24 04:41:24 PM PDT 24
Finished Jun 24 04:41:35 PM PDT 24
Peak memory 206600 kb
Host smart-2c0e76d9-7d5b-4324-8798-133b66167370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797922487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1797922487
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3744518423
Short name T699
Test name
Test status
Simulation time 42285764 ps
CPU time 0.72 seconds
Started Jun 24 04:41:25 PM PDT 24
Finished Jun 24 04:41:36 PM PDT 24
Peak memory 215788 kb
Host smart-df9e7138-c4a0-4d58-bdc6-19c02f197131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744518423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3744518423
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2289176050
Short name T682
Test name
Test status
Simulation time 3073694356 ps
CPU time 49.59 seconds
Started Jun 24 04:41:26 PM PDT 24
Finished Jun 24 04:42:25 PM PDT 24
Peak memory 255300 kb
Host smart-ca35f560-4e6c-4053-9408-8aa0fcb59cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289176050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2289176050
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.980944555
Short name T140
Test name
Test status
Simulation time 3425983209 ps
CPU time 40.41 seconds
Started Jun 24 04:41:19 PM PDT 24
Finished Jun 24 04:42:10 PM PDT 24
Peak memory 249328 kb
Host smart-2780d2ff-b1f8-4e83-a34a-36f4074fcbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980944555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.980944555
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1591100012
Short name T306
Test name
Test status
Simulation time 10315259210 ps
CPU time 86.2 seconds
Started Jun 24 04:41:23 PM PDT 24
Finished Jun 24 04:43:01 PM PDT 24
Peak memory 253660 kb
Host smart-14fd06fe-d4e5-4925-9694-9c248a93a969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591100012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1591100012
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.794003730
Short name T571
Test name
Test status
Simulation time 40965533 ps
CPU time 2.55 seconds
Started Jun 24 04:41:21 PM PDT 24
Finished Jun 24 04:41:34 PM PDT 24
Peak memory 232376 kb
Host smart-b052bc88-7df5-4f36-a0d7-b27db6e479dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794003730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.794003730
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2002560311
Short name T681
Test name
Test status
Simulation time 8489517545 ps
CPU time 34.77 seconds
Started Jun 24 04:41:24 PM PDT 24
Finished Jun 24 04:42:09 PM PDT 24
Peak memory 231640 kb
Host smart-760924d6-4cbd-4705-9222-8966764696b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002560311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2002560311
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3989707854
Short name T452
Test name
Test status
Simulation time 9085516179 ps
CPU time 5.77 seconds
Started Jun 24 04:41:21 PM PDT 24
Finished Jun 24 04:41:37 PM PDT 24
Peak memory 232772 kb
Host smart-8e060f61-97a0-4706-880f-5ee8e8a35db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989707854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3989707854
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.498665716
Short name T659
Test name
Test status
Simulation time 59041724 ps
CPU time 2.42 seconds
Started Jun 24 04:41:20 PM PDT 24
Finished Jun 24 04:41:33 PM PDT 24
Peak memory 224452 kb
Host smart-e636ce55-6da0-4217-9a83-f7a75998ea52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498665716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.498665716
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3447045175
Short name T431
Test name
Test status
Simulation time 772013808 ps
CPU time 6.98 seconds
Started Jun 24 04:41:19 PM PDT 24
Finished Jun 24 04:41:36 PM PDT 24
Peak memory 223124 kb
Host smart-b74b23d4-16b4-4e4f-9ce9-80047300e49c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3447045175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3447045175
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2899659890
Short name T17
Test name
Test status
Simulation time 9764707359 ps
CPU time 96.17 seconds
Started Jun 24 04:41:20 PM PDT 24
Finished Jun 24 04:43:07 PM PDT 24
Peak memory 250340 kb
Host smart-212fa446-16e4-4d3e-9212-0ee40f324b27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899659890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2899659890
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1088494333
Short name T845
Test name
Test status
Simulation time 5728107525 ps
CPU time 10.07 seconds
Started Jun 24 04:41:22 PM PDT 24
Finished Jun 24 04:41:43 PM PDT 24
Peak memory 216536 kb
Host smart-a9ddd9b2-66fe-45f5-a64c-e1bbcc1f77cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088494333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1088494333
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3593816346
Short name T471
Test name
Test status
Simulation time 616363633 ps
CPU time 4.32 seconds
Started Jun 24 04:41:22 PM PDT 24
Finished Jun 24 04:41:38 PM PDT 24
Peak memory 216232 kb
Host smart-e9cb4bb8-2444-48e3-b3b2-0b2e8eb1da6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593816346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3593816346
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2496915301
Short name T905
Test name
Test status
Simulation time 55441458 ps
CPU time 0.91 seconds
Started Jun 24 04:41:24 PM PDT 24
Finished Jun 24 04:41:36 PM PDT 24
Peak memory 206648 kb
Host smart-901af60a-50a4-4d85-aa40-b231a186b27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496915301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2496915301
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2094919314
Short name T758
Test name
Test status
Simulation time 69425076 ps
CPU time 0.77 seconds
Started Jun 24 04:41:23 PM PDT 24
Finished Jun 24 04:41:34 PM PDT 24
Peak memory 205952 kb
Host smart-b6464c41-427e-46b6-a851-89ba1a40c388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094919314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2094919314
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2814726916
Short name T770
Test name
Test status
Simulation time 8199140948 ps
CPU time 27.29 seconds
Started Jun 24 04:41:22 PM PDT 24
Finished Jun 24 04:42:00 PM PDT 24
Peak memory 240508 kb
Host smart-f993b164-cf1c-4a9a-970a-a09bb0f43fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814726916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2814726916
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1349974126
Short name T502
Test name
Test status
Simulation time 48508355 ps
CPU time 0.76 seconds
Started Jun 24 04:41:29 PM PDT 24
Finished Jun 24 04:41:39 PM PDT 24
Peak memory 204740 kb
Host smart-105dd969-52fb-4d3d-8f1e-317b508bb3b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349974126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1349974126
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3341127818
Short name T278
Test name
Test status
Simulation time 2872493377 ps
CPU time 6.16 seconds
Started Jun 24 04:41:32 PM PDT 24
Finished Jun 24 04:41:48 PM PDT 24
Peak memory 232804 kb
Host smart-aa8822a3-83ad-413e-b17f-c720ca4b3351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341127818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3341127818
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2061566439
Short name T560
Test name
Test status
Simulation time 43148863 ps
CPU time 0.8 seconds
Started Jun 24 04:41:20 PM PDT 24
Finished Jun 24 04:41:31 PM PDT 24
Peak memory 206564 kb
Host smart-43961410-6f35-414f-869e-f9a86e140a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061566439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2061566439
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3019152987
Short name T519
Test name
Test status
Simulation time 10414059594 ps
CPU time 75.44 seconds
Started Jun 24 04:41:27 PM PDT 24
Finished Jun 24 04:42:52 PM PDT 24
Peak memory 253032 kb
Host smart-9574681a-43c8-4411-bff6-d1a855081812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019152987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3019152987
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3834557460
Short name T45
Test name
Test status
Simulation time 26915424495 ps
CPU time 198.89 seconds
Started Jun 24 04:41:37 PM PDT 24
Finished Jun 24 04:45:05 PM PDT 24
Peak memory 253640 kb
Host smart-f7a1358e-ce65-4b53-894d-2bfcc41ec96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834557460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3834557460
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3234386036
Short name T797
Test name
Test status
Simulation time 37468351258 ps
CPU time 112.67 seconds
Started Jun 24 04:41:38 PM PDT 24
Finished Jun 24 04:43:39 PM PDT 24
Peak memory 256052 kb
Host smart-54b5cea0-eea5-4392-9ae1-864a9b086553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234386036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3234386036
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2422097277
Short name T844
Test name
Test status
Simulation time 544137501 ps
CPU time 6.03 seconds
Started Jun 24 04:41:29 PM PDT 24
Finished Jun 24 04:41:44 PM PDT 24
Peak memory 232688 kb
Host smart-0abb45f6-7ab8-4acc-a1cd-84f3c369ffb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422097277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2422097277
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2539580770
Short name T577
Test name
Test status
Simulation time 1196219767 ps
CPU time 13.26 seconds
Started Jun 24 04:41:21 PM PDT 24
Finished Jun 24 04:41:45 PM PDT 24
Peak memory 232784 kb
Host smart-d1cd3a79-27c7-4474-b71a-01700a1485a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539580770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2539580770
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.340288553
Short name T515
Test name
Test status
Simulation time 11792816847 ps
CPU time 68.48 seconds
Started Jun 24 04:41:23 PM PDT 24
Finished Jun 24 04:42:42 PM PDT 24
Peak memory 232784 kb
Host smart-9f2c9627-be7d-4f00-8a7c-0e91da787a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340288553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.340288553
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2839104724
Short name T174
Test name
Test status
Simulation time 106837686 ps
CPU time 2.21 seconds
Started Jun 24 04:41:25 PM PDT 24
Finished Jun 24 04:41:37 PM PDT 24
Peak memory 223664 kb
Host smart-86316bed-5840-4c0a-9849-d3a87ccef8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839104724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2839104724
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.4028910280
Short name T177
Test name
Test status
Simulation time 30249120846 ps
CPU time 21.62 seconds
Started Jun 24 04:41:20 PM PDT 24
Finished Jun 24 04:41:53 PM PDT 24
Peak memory 232864 kb
Host smart-e60a7e4d-fa6c-4f27-8901-a59c957f3faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028910280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.4028910280
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2131470286
Short name T766
Test name
Test status
Simulation time 2197123293 ps
CPU time 7.7 seconds
Started Jun 24 04:41:38 PM PDT 24
Finished Jun 24 04:41:54 PM PDT 24
Peak memory 219408 kb
Host smart-6f30f075-f360-404c-aca0-5d65758baa64
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2131470286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2131470286
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3508174344
Short name T667
Test name
Test status
Simulation time 3047494341 ps
CPU time 22.24 seconds
Started Jun 24 04:41:23 PM PDT 24
Finished Jun 24 04:41:57 PM PDT 24
Peak memory 216300 kb
Host smart-803b3f14-8511-4063-9360-80b270259ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508174344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3508174344
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.4076567496
Short name T757
Test name
Test status
Simulation time 375233145 ps
CPU time 1.55 seconds
Started Jun 24 04:41:22 PM PDT 24
Finished Jun 24 04:41:35 PM PDT 24
Peak memory 207940 kb
Host smart-fcfbff57-68cc-4d0f-9e12-f0e6b3e5b40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076567496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4076567496
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.998168637
Short name T392
Test name
Test status
Simulation time 1191958058 ps
CPU time 2.04 seconds
Started Jun 24 04:41:22 PM PDT 24
Finished Jun 24 04:41:35 PM PDT 24
Peak memory 216564 kb
Host smart-1c9227da-deeb-4270-a0ad-1ec7c1a2912c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998168637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.998168637
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.4077368392
Short name T371
Test name
Test status
Simulation time 87126501 ps
CPU time 0.72 seconds
Started Jun 24 04:41:24 PM PDT 24
Finished Jun 24 04:41:35 PM PDT 24
Peak memory 204908 kb
Host smart-ec5d619c-2f0a-45a7-ae8b-f2fdeedf11b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077368392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.4077368392
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.746983621
Short name T854
Test name
Test status
Simulation time 6101831483 ps
CPU time 7.05 seconds
Started Jun 24 04:41:22 PM PDT 24
Finished Jun 24 04:41:40 PM PDT 24
Peak memory 232812 kb
Host smart-778b0c82-0ab5-45c5-9214-c14b076f3823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746983621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.746983621
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1548277247
Short name T940
Test name
Test status
Simulation time 14109181 ps
CPU time 0.72 seconds
Started Jun 24 04:41:31 PM PDT 24
Finished Jun 24 04:41:41 PM PDT 24
Peak memory 205360 kb
Host smart-1148c4d6-c415-4a93-ae47-d74d10c72bfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548277247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1548277247
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1498361880
Short name T457
Test name
Test status
Simulation time 64476965 ps
CPU time 2.79 seconds
Started Jun 24 04:41:29 PM PDT 24
Finished Jun 24 04:41:42 PM PDT 24
Peak memory 224424 kb
Host smart-b7697fec-19aa-488a-afd7-611ba9066b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498361880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1498361880
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2206882494
Short name T339
Test name
Test status
Simulation time 14835936 ps
CPU time 0.76 seconds
Started Jun 24 04:41:29 PM PDT 24
Finished Jun 24 04:41:39 PM PDT 24
Peak memory 206872 kb
Host smart-4dd52d76-f70e-47db-ad4f-409348c8f570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206882494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2206882494
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1747400992
Short name T296
Test name
Test status
Simulation time 575825032692 ps
CPU time 334.73 seconds
Started Jun 24 04:41:38 PM PDT 24
Finished Jun 24 04:47:22 PM PDT 24
Peak memory 256588 kb
Host smart-790d950a-d167-44ff-9f47-74f6f245d881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747400992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1747400992
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2917447604
Short name T33
Test name
Test status
Simulation time 23149520173 ps
CPU time 219.82 seconds
Started Jun 24 04:41:30 PM PDT 24
Finished Jun 24 04:45:20 PM PDT 24
Peak memory 253824 kb
Host smart-b1acebef-031d-49e4-adb5-6ebf179f3757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917447604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2917447604
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2770410374
Short name T308
Test name
Test status
Simulation time 3314631125 ps
CPU time 33.54 seconds
Started Jun 24 04:41:27 PM PDT 24
Finished Jun 24 04:42:11 PM PDT 24
Peak memory 235580 kb
Host smart-863ae2ea-56fb-4e94-8119-2359c9dffe4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770410374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2770410374
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2046113035
Short name T724
Test name
Test status
Simulation time 4913288065 ps
CPU time 9.98 seconds
Started Jun 24 04:41:27 PM PDT 24
Finished Jun 24 04:41:47 PM PDT 24
Peak memory 224636 kb
Host smart-bcd83fcd-de02-4799-8dd5-052fbb144f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046113035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2046113035
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2391492773
Short name T676
Test name
Test status
Simulation time 33666464 ps
CPU time 2.23 seconds
Started Jun 24 04:41:28 PM PDT 24
Finished Jun 24 04:41:40 PM PDT 24
Peak memory 232380 kb
Host smart-635953b1-61ef-47bc-969c-c9d091e5e6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391492773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2391492773
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.353877132
Short name T822
Test name
Test status
Simulation time 5508894096 ps
CPU time 10.91 seconds
Started Jun 24 04:41:30 PM PDT 24
Finished Jun 24 04:41:50 PM PDT 24
Peak memory 224580 kb
Host smart-112367de-4c54-4b47-9c1a-95d6a98c4c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353877132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.353877132
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.4096924732
Short name T521
Test name
Test status
Simulation time 440565865 ps
CPU time 5.2 seconds
Started Jun 24 04:41:30 PM PDT 24
Finished Jun 24 04:41:45 PM PDT 24
Peak memory 240288 kb
Host smart-2c8e1877-ddec-4650-8d60-846af81a9537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096924732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4096924732
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.4253352856
Short name T640
Test name
Test status
Simulation time 128549639 ps
CPU time 3.72 seconds
Started Jun 24 04:41:29 PM PDT 24
Finished Jun 24 04:41:42 PM PDT 24
Peak memory 223088 kb
Host smart-ff763487-22c3-4682-a558-3f012aa6dc12
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4253352856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.4253352856
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.144493432
Short name T688
Test name
Test status
Simulation time 8403517619 ps
CPU time 14.2 seconds
Started Jun 24 04:41:31 PM PDT 24
Finished Jun 24 04:41:54 PM PDT 24
Peak memory 216372 kb
Host smart-dd4b2e47-d2de-4c3e-abfa-56605a5748e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144493432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.144493432
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1391011496
Short name T694
Test name
Test status
Simulation time 17738207538 ps
CPU time 10.84 seconds
Started Jun 24 04:41:29 PM PDT 24
Finished Jun 24 04:41:50 PM PDT 24
Peak memory 216440 kb
Host smart-43d76017-7fd8-43ba-850a-094fc3234154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391011496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1391011496
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2459402547
Short name T709
Test name
Test status
Simulation time 88788241 ps
CPU time 1.44 seconds
Started Jun 24 04:41:27 PM PDT 24
Finished Jun 24 04:41:39 PM PDT 24
Peak memory 216168 kb
Host smart-5946649c-46e3-4725-8224-133c80526478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459402547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2459402547
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2703973919
Short name T782
Test name
Test status
Simulation time 42862291 ps
CPU time 0.87 seconds
Started Jun 24 04:41:32 PM PDT 24
Finished Jun 24 04:41:42 PM PDT 24
Peak memory 205936 kb
Host smart-e40704f9-001f-4b47-8c37-d51cf7b55992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703973919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2703973919
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1758173919
Short name T711
Test name
Test status
Simulation time 390742491 ps
CPU time 5.41 seconds
Started Jun 24 04:41:30 PM PDT 24
Finished Jun 24 04:41:45 PM PDT 24
Peak memory 240484 kb
Host smart-3a2d6dc1-5a3d-4310-9978-75a7f633bf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758173919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1758173919
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.4092305532
Short name T685
Test name
Test status
Simulation time 36724290 ps
CPU time 0.72 seconds
Started Jun 24 04:41:39 PM PDT 24
Finished Jun 24 04:41:48 PM PDT 24
Peak memory 205716 kb
Host smart-0010442c-b734-474b-8678-fa15a7f5e93c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092305532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
4092305532
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.966963712
Short name T376
Test name
Test status
Simulation time 319137006 ps
CPU time 2.55 seconds
Started Jun 24 04:41:38 PM PDT 24
Finished Jun 24 04:41:49 PM PDT 24
Peak memory 232732 kb
Host smart-33b0b12e-05ee-45ea-a9f0-cb02a139ae1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966963712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.966963712
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3983418621
Short name T710
Test name
Test status
Simulation time 20460533 ps
CPU time 0.8 seconds
Started Jun 24 04:41:29 PM PDT 24
Finished Jun 24 04:41:40 PM PDT 24
Peak memory 206588 kb
Host smart-8d7f59bd-bd16-4c12-a270-c4fd4d47c8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983418621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3983418621
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3557901857
Short name T585
Test name
Test status
Simulation time 14848884587 ps
CPU time 51.95 seconds
Started Jun 24 04:41:41 PM PDT 24
Finished Jun 24 04:42:41 PM PDT 24
Peak memory 239816 kb
Host smart-564b24d1-4da1-4520-9fcc-0f14602cbfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557901857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3557901857
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3761359436
Short name T1
Test name
Test status
Simulation time 13209166292 ps
CPU time 43.75 seconds
Started Jun 24 04:41:38 PM PDT 24
Finished Jun 24 04:42:30 PM PDT 24
Peak memory 256268 kb
Host smart-90d496d6-e153-461e-8227-b3f84c0ec88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761359436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3761359436
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.448581261
Short name T310
Test name
Test status
Simulation time 97229853 ps
CPU time 3.24 seconds
Started Jun 24 04:41:41 PM PDT 24
Finished Jun 24 04:41:52 PM PDT 24
Peak memory 232624 kb
Host smart-8ec0fb71-c7a7-42e5-8ae2-eb6c4d8acb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448581261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.448581261
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1096760034
Short name T197
Test name
Test status
Simulation time 935347182 ps
CPU time 4.81 seconds
Started Jun 24 04:41:28 PM PDT 24
Finished Jun 24 04:41:43 PM PDT 24
Peak memory 232704 kb
Host smart-8d324002-0bab-4c3e-8ffe-d00244469618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096760034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1096760034
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1212536177
Short name T498
Test name
Test status
Simulation time 377707287 ps
CPU time 8.26 seconds
Started Jun 24 04:41:29 PM PDT 24
Finished Jun 24 04:41:47 PM PDT 24
Peak memory 224432 kb
Host smart-91fc37d5-17d1-4c88-a75a-21faed400b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212536177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1212536177
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.781212456
Short name T269
Test name
Test status
Simulation time 560996877 ps
CPU time 6.43 seconds
Started Jun 24 04:41:30 PM PDT 24
Finished Jun 24 04:41:47 PM PDT 24
Peak memory 224464 kb
Host smart-9267ba13-469c-4b38-a270-26ae09fb85b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781212456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.781212456
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3962928747
Short name T256
Test name
Test status
Simulation time 2465726134 ps
CPU time 8.68 seconds
Started Jun 24 04:41:29 PM PDT 24
Finished Jun 24 04:41:47 PM PDT 24
Peak memory 224536 kb
Host smart-b67cc86d-3e4f-4af4-bd34-90605efb1142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962928747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3962928747
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2073655978
Short name T156
Test name
Test status
Simulation time 10226781520 ps
CPU time 6.67 seconds
Started Jun 24 04:41:38 PM PDT 24
Finished Jun 24 04:41:54 PM PDT 24
Peak memory 223004 kb
Host smart-8b05b64f-43fd-4e1c-be6a-a35da6b38eaa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2073655978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2073655978
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.788841049
Short name T488
Test name
Test status
Simulation time 126547537 ps
CPU time 1.03 seconds
Started Jun 24 04:41:36 PM PDT 24
Finished Jun 24 04:41:45 PM PDT 24
Peak memory 207056 kb
Host smart-25955b37-c75e-4735-9dd0-7cfb9e9af6e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788841049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.788841049
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.987514855
Short name T934
Test name
Test status
Simulation time 1364698709 ps
CPU time 15.19 seconds
Started Jun 24 04:41:27 PM PDT 24
Finished Jun 24 04:41:53 PM PDT 24
Peak memory 216164 kb
Host smart-809441d7-53b5-44f1-a512-43909f27f4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987514855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.987514855
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2618108918
Short name T707
Test name
Test status
Simulation time 2570710476 ps
CPU time 11.81 seconds
Started Jun 24 04:41:38 PM PDT 24
Finished Jun 24 04:41:58 PM PDT 24
Peak memory 216396 kb
Host smart-363de139-7eff-442f-a4e0-b540141d084a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618108918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2618108918
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3506595789
Short name T434
Test name
Test status
Simulation time 94307160 ps
CPU time 2.24 seconds
Started Jun 24 04:41:28 PM PDT 24
Finished Jun 24 04:41:40 PM PDT 24
Peak memory 216224 kb
Host smart-47dfad4b-3a72-4bf8-85ee-cf4ff8c9373b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506595789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3506595789
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.4094088958
Short name T582
Test name
Test status
Simulation time 185472220 ps
CPU time 0.89 seconds
Started Jun 24 04:41:30 PM PDT 24
Finished Jun 24 04:41:41 PM PDT 24
Peak memory 205904 kb
Host smart-0961a23c-5718-407d-8ac9-0f0357412940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094088958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.4094088958
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3621820523
Short name T4
Test name
Test status
Simulation time 2902072700 ps
CPU time 10.49 seconds
Started Jun 24 04:41:28 PM PDT 24
Finished Jun 24 04:41:48 PM PDT 24
Peak memory 234052 kb
Host smart-3c44a49f-3738-453a-a2c7-770f3dc21489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621820523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3621820523
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2768185866
Short name T64
Test name
Test status
Simulation time 12204666 ps
CPU time 0.73 seconds
Started Jun 24 04:41:37 PM PDT 24
Finished Jun 24 04:41:46 PM PDT 24
Peak memory 205396 kb
Host smart-6a809d1e-ef87-409f-a971-829fe49b1f43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768185866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2768185866
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1320563270
Short name T386
Test name
Test status
Simulation time 204395431 ps
CPU time 2.54 seconds
Started Jun 24 04:41:40 PM PDT 24
Finished Jun 24 04:41:51 PM PDT 24
Peak memory 232692 kb
Host smart-9ce0683a-e609-4ede-b3e9-0c56f8326b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320563270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1320563270
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.236194957
Short name T503
Test name
Test status
Simulation time 21939748 ps
CPU time 0.9 seconds
Started Jun 24 04:41:41 PM PDT 24
Finished Jun 24 04:41:50 PM PDT 24
Peak memory 206564 kb
Host smart-f9c915fe-8050-4df0-a758-ae0774b657cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236194957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.236194957
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1082926669
Short name T915
Test name
Test status
Simulation time 1582358902 ps
CPU time 36.77 seconds
Started Jun 24 04:41:38 PM PDT 24
Finished Jun 24 04:42:24 PM PDT 24
Peak memory 253732 kb
Host smart-541f1c4c-46b3-4ab6-bbb0-232524785193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082926669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1082926669
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.306554900
Short name T316
Test name
Test status
Simulation time 38450430486 ps
CPU time 286.13 seconds
Started Jun 24 04:41:39 PM PDT 24
Finished Jun 24 04:46:34 PM PDT 24
Peak memory 240528 kb
Host smart-6bc5b35b-644d-4ed2-b129-0e611ee08cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306554900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.306554900
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.274728898
Short name T288
Test name
Test status
Simulation time 7248134975 ps
CPU time 38.09 seconds
Started Jun 24 04:41:39 PM PDT 24
Finished Jun 24 04:42:26 PM PDT 24
Peak memory 241132 kb
Host smart-8220404b-f7a5-4e7d-aff1-d497ddee2e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274728898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.274728898
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3135264429
Short name T754
Test name
Test status
Simulation time 290611740 ps
CPU time 5.56 seconds
Started Jun 24 04:41:40 PM PDT 24
Finished Jun 24 04:41:54 PM PDT 24
Peak memory 224484 kb
Host smart-9030ab73-2c84-4a8d-ae31-b95ce0e0b608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135264429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3135264429
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3436926920
Short name T701
Test name
Test status
Simulation time 5422182502 ps
CPU time 23.34 seconds
Started Jun 24 04:41:38 PM PDT 24
Finished Jun 24 04:42:10 PM PDT 24
Peak memory 232860 kb
Host smart-5c3ac375-5279-4bb2-b666-9758bdb3d357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436926920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3436926920
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3350774961
Short name T500
Test name
Test status
Simulation time 7033757005 ps
CPU time 33.11 seconds
Started Jun 24 04:41:37 PM PDT 24
Finished Jun 24 04:42:19 PM PDT 24
Peak memory 241016 kb
Host smart-9c61d466-c03e-4439-8ac4-6bbc3ea0b322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350774961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3350774961
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.4186781755
Short name T731
Test name
Test status
Simulation time 6639550284 ps
CPU time 5.9 seconds
Started Jun 24 04:41:38 PM PDT 24
Finished Jun 24 04:41:52 PM PDT 24
Peak memory 224616 kb
Host smart-d73fca77-1d2c-4514-aee4-b48312a2d17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186781755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.4186781755
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2774858368
Short name T717
Test name
Test status
Simulation time 8224374012 ps
CPU time 28.08 seconds
Started Jun 24 04:41:37 PM PDT 24
Finished Jun 24 04:42:13 PM PDT 24
Peak memory 232788 kb
Host smart-1d62f904-055b-4e1d-965f-4f6ae48c12bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774858368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2774858368
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3772508596
Short name T149
Test name
Test status
Simulation time 436953465 ps
CPU time 4.02 seconds
Started Jun 24 04:41:38 PM PDT 24
Finished Jun 24 04:41:51 PM PDT 24
Peak memory 222540 kb
Host smart-d3c07429-35b0-4780-b55d-15b1e7c3a33a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3772508596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3772508596
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3443282469
Short name T37
Test name
Test status
Simulation time 30022679183 ps
CPU time 182.84 seconds
Started Jun 24 04:41:38 PM PDT 24
Finished Jun 24 04:44:50 PM PDT 24
Peak memory 266032 kb
Host smart-b702b832-8703-4d42-bc77-a00266225c65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443282469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3443282469
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1960591604
Short name T960
Test name
Test status
Simulation time 403173746 ps
CPU time 2.74 seconds
Started Jun 24 04:41:38 PM PDT 24
Finished Jun 24 04:41:49 PM PDT 24
Peak memory 216220 kb
Host smart-90a6e8ab-b72d-4ef5-89c0-baabb0879839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960591604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1960591604
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1886467595
Short name T495
Test name
Test status
Simulation time 1262980719 ps
CPU time 2.3 seconds
Started Jun 24 04:41:38 PM PDT 24
Finished Jun 24 04:41:49 PM PDT 24
Peak memory 216480 kb
Host smart-a18d1ad2-0259-480c-a4fe-0b1b72d0e9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886467595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1886467595
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.649166423
Short name T325
Test name
Test status
Simulation time 144340356 ps
CPU time 1.82 seconds
Started Jun 24 04:41:39 PM PDT 24
Finished Jun 24 04:41:49 PM PDT 24
Peak memory 216252 kb
Host smart-bac933a4-56c1-4050-a000-1ff098e05b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649166423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.649166423
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2520873194
Short name T716
Test name
Test status
Simulation time 341795752 ps
CPU time 0.95 seconds
Started Jun 24 04:41:38 PM PDT 24
Finished Jun 24 04:41:48 PM PDT 24
Peak memory 205896 kb
Host smart-083e6c2b-70fc-4d70-af44-134fcf941bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520873194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2520873194
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.257064150
Short name T465
Test name
Test status
Simulation time 4288407607 ps
CPU time 8.58 seconds
Started Jun 24 04:41:40 PM PDT 24
Finished Jun 24 04:41:57 PM PDT 24
Peak memory 232848 kb
Host smart-ed87ebc0-66b9-44ce-8e45-ed6c99ef5219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257064150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.257064150
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2475779635
Short name T341
Test name
Test status
Simulation time 14070366 ps
CPU time 0.75 seconds
Started Jun 24 04:41:47 PM PDT 24
Finished Jun 24 04:41:57 PM PDT 24
Peak memory 205672 kb
Host smart-9323dc28-5030-4e76-a3b6-156b3ef7d4d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475779635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2475779635
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.591039767
Short name T632
Test name
Test status
Simulation time 94221804 ps
CPU time 2.34 seconds
Started Jun 24 04:41:41 PM PDT 24
Finished Jun 24 04:41:51 PM PDT 24
Peak memory 224512 kb
Host smart-6ebdbbb2-4007-49da-95b1-551a5b2cc362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591039767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.591039767
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.4104965703
Short name T422
Test name
Test status
Simulation time 16140667 ps
CPU time 0.83 seconds
Started Jun 24 04:41:40 PM PDT 24
Finished Jun 24 04:41:50 PM PDT 24
Peak memory 206628 kb
Host smart-42ca47ee-59db-426f-866f-c1b75567160e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104965703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.4104965703
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.148155018
Short name T866
Test name
Test status
Simulation time 108963050593 ps
CPU time 201.84 seconds
Started Jun 24 04:41:44 PM PDT 24
Finished Jun 24 04:45:14 PM PDT 24
Peak memory 255868 kb
Host smart-eb651434-744e-4220-ba00-7cd933b1d8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148155018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.148155018
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.151836835
Short name T284
Test name
Test status
Simulation time 239735640328 ps
CPU time 494.14 seconds
Started Jun 24 04:41:45 PM PDT 24
Finished Jun 24 04:50:09 PM PDT 24
Peak memory 265072 kb
Host smart-78fcdf33-54c4-45cb-b37f-04f432e50334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151836835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.151836835
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1534104352
Short name T298
Test name
Test status
Simulation time 8278760927 ps
CPU time 91.43 seconds
Started Jun 24 04:41:46 PM PDT 24
Finished Jun 24 04:43:27 PM PDT 24
Peak memory 257400 kb
Host smart-7755ad9d-b20d-4ac3-b428-8a5472d9a1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534104352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1534104352
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1320872186
Short name T602
Test name
Test status
Simulation time 259089425 ps
CPU time 2.95 seconds
Started Jun 24 04:41:40 PM PDT 24
Finished Jun 24 04:41:51 PM PDT 24
Peak memory 224800 kb
Host smart-e08ef7f0-15bf-44a5-a2a8-30fdb85e5cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320872186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1320872186
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2358842387
Short name T192
Test name
Test status
Simulation time 1617703073 ps
CPU time 3.48 seconds
Started Jun 24 04:41:39 PM PDT 24
Finished Jun 24 04:41:51 PM PDT 24
Peak memory 224464 kb
Host smart-f1b8b7a8-f88b-46ed-a0e1-72bbe84d3d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358842387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2358842387
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.141108829
Short name T468
Test name
Test status
Simulation time 17200494748 ps
CPU time 31.99 seconds
Started Jun 24 04:41:36 PM PDT 24
Finished Jun 24 04:42:17 PM PDT 24
Peak memory 238464 kb
Host smart-3aeac924-84b3-4a31-81af-a12bdc53a4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141108829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.141108829
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1890762815
Short name T634
Test name
Test status
Simulation time 111267455 ps
CPU time 2.59 seconds
Started Jun 24 04:41:38 PM PDT 24
Finished Jun 24 04:41:49 PM PDT 24
Peak memory 232396 kb
Host smart-eab9fb10-45b2-4613-8483-d290e04199f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890762815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1890762815
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2214893640
Short name T554
Test name
Test status
Simulation time 59519301 ps
CPU time 2.7 seconds
Started Jun 24 04:41:39 PM PDT 24
Finished Jun 24 04:41:51 PM PDT 24
Peak memory 232688 kb
Host smart-dfa8cf89-fdd7-4160-89ae-a0c0e3568909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214893640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2214893640
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.658470001
Short name T932
Test name
Test status
Simulation time 3116782177 ps
CPU time 6.18 seconds
Started Jun 24 04:41:42 PM PDT 24
Finished Jun 24 04:41:56 PM PDT 24
Peak memory 223168 kb
Host smart-e6e811e2-fad7-4c60-ae1f-304e0e21457b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=658470001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.658470001
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3092934194
Short name T647
Test name
Test status
Simulation time 26959132386 ps
CPU time 213.35 seconds
Started Jun 24 04:41:50 PM PDT 24
Finished Jun 24 04:45:34 PM PDT 24
Peak memory 241124 kb
Host smart-984e7720-174d-4d12-9d01-55f9aae0201a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092934194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3092934194
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.722953285
Short name T628
Test name
Test status
Simulation time 43676593 ps
CPU time 0.71 seconds
Started Jun 24 04:41:39 PM PDT 24
Finished Jun 24 04:41:48 PM PDT 24
Peak memory 205596 kb
Host smart-aa76dbe6-e9b5-4282-aeaa-30c6cf392c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722953285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.722953285
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2919550519
Short name T459
Test name
Test status
Simulation time 5748443779 ps
CPU time 4.87 seconds
Started Jun 24 04:41:39 PM PDT 24
Finished Jun 24 04:41:52 PM PDT 24
Peak memory 216368 kb
Host smart-e27b8a61-411a-44e4-acf3-3caf18d2a88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919550519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2919550519
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3530339900
Short name T832
Test name
Test status
Simulation time 101538938 ps
CPU time 2.19 seconds
Started Jun 24 04:41:39 PM PDT 24
Finished Jun 24 04:41:50 PM PDT 24
Peak memory 216292 kb
Host smart-30c372fe-b937-45a3-bc38-0ee9f10e89c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530339900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3530339900
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.932370167
Short name T385
Test name
Test status
Simulation time 417881541 ps
CPU time 0.98 seconds
Started Jun 24 04:41:40 PM PDT 24
Finished Jun 24 04:41:49 PM PDT 24
Peak memory 206232 kb
Host smart-a20557bc-70cc-4e67-ac7b-98f23494453b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932370167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.932370167
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1284403775
Short name T493
Test name
Test status
Simulation time 2331797606 ps
CPU time 9.2 seconds
Started Jun 24 04:41:38 PM PDT 24
Finished Jun 24 04:41:56 PM PDT 24
Peak memory 224592 kb
Host smart-99c8ea24-366d-41b3-b580-b4a382cda6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284403775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1284403775
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1457562200
Short name T395
Test name
Test status
Simulation time 11972728 ps
CPU time 0.71 seconds
Started Jun 24 04:41:44 PM PDT 24
Finished Jun 24 04:41:53 PM PDT 24
Peak memory 204756 kb
Host smart-71bd54e0-a988-4dc7-9093-b1fa8d90449d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457562200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1457562200
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.696992890
Short name T800
Test name
Test status
Simulation time 623998538 ps
CPU time 2.99 seconds
Started Jun 24 04:41:49 PM PDT 24
Finished Jun 24 04:42:02 PM PDT 24
Peak memory 224460 kb
Host smart-e1e10813-9356-4c48-b2b0-20299de87715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696992890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.696992890
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3879062150
Short name T587
Test name
Test status
Simulation time 69058679 ps
CPU time 0.81 seconds
Started Jun 24 04:41:44 PM PDT 24
Finished Jun 24 04:41:53 PM PDT 24
Peak memory 205592 kb
Host smart-8a65b2cf-90ce-4ac5-9038-e2462e7d55e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879062150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3879062150
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1262734906
Short name T821
Test name
Test status
Simulation time 7283404508 ps
CPU time 97.29 seconds
Started Jun 24 04:41:43 PM PDT 24
Finished Jun 24 04:43:28 PM PDT 24
Peak memory 257680 kb
Host smart-874e1d8b-a765-449a-89d0-7338e0f84e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262734906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1262734906
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1717874492
Short name T742
Test name
Test status
Simulation time 6594598455 ps
CPU time 98.4 seconds
Started Jun 24 04:41:44 PM PDT 24
Finished Jun 24 04:43:31 PM PDT 24
Peak memory 265144 kb
Host smart-aa7c7a60-bb95-4554-98c2-8978c1516592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717874492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1717874492
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1266535645
Short name T305
Test name
Test status
Simulation time 8553529120 ps
CPU time 17.24 seconds
Started Jun 24 04:41:44 PM PDT 24
Finished Jun 24 04:42:10 PM PDT 24
Peak memory 239752 kb
Host smart-07a70415-45c7-49fe-acc9-c2925fe75934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266535645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1266535645
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3846478395
Short name T765
Test name
Test status
Simulation time 598175527 ps
CPU time 5.16 seconds
Started Jun 24 04:41:43 PM PDT 24
Finished Jun 24 04:41:57 PM PDT 24
Peak memory 224496 kb
Host smart-b9f963da-7549-46a7-a48e-c64ea2d3f753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846478395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3846478395
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2837518759
Short name T56
Test name
Test status
Simulation time 8572398076 ps
CPU time 23.8 seconds
Started Jun 24 04:41:45 PM PDT 24
Finished Jun 24 04:42:18 PM PDT 24
Peak memory 232888 kb
Host smart-d28798a9-0e94-4a70-8aa3-2c144fb853b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837518759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2837518759
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.4181871008
Short name T638
Test name
Test status
Simulation time 50750179290 ps
CPU time 30.52 seconds
Started Jun 24 04:41:45 PM PDT 24
Finished Jun 24 04:42:24 PM PDT 24
Peak memory 240452 kb
Host smart-50402f9c-2b67-41b8-8673-c72d53b742fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181871008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.4181871008
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2460694016
Short name T223
Test name
Test status
Simulation time 13348665767 ps
CPU time 14.64 seconds
Started Jun 24 04:41:43 PM PDT 24
Finished Jun 24 04:42:06 PM PDT 24
Peak memory 224576 kb
Host smart-e93755ae-a5c2-4c48-a374-85b4cc91830a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460694016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2460694016
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1036425299
Short name T26
Test name
Test status
Simulation time 1251355478 ps
CPU time 14.82 seconds
Started Jun 24 04:41:41 PM PDT 24
Finished Jun 24 04:42:04 PM PDT 24
Peak memory 219864 kb
Host smart-3ecd3172-944d-48b3-af34-7ee609d809c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1036425299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1036425299
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.4221009153
Short name T511
Test name
Test status
Simulation time 38654551256 ps
CPU time 47.22 seconds
Started Jun 24 04:41:45 PM PDT 24
Finished Jun 24 04:42:41 PM PDT 24
Peak memory 216420 kb
Host smart-06f95dd3-924f-44ec-bc83-885ce9ab2620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221009153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.4221009153
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3423587261
Short name T88
Test name
Test status
Simulation time 14297760223 ps
CPU time 14.58 seconds
Started Jun 24 04:41:45 PM PDT 24
Finished Jun 24 04:42:09 PM PDT 24
Peak memory 216404 kb
Host smart-1fd0e964-c7a7-4f51-b1d0-340f924105bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423587261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3423587261
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3595538120
Short name T790
Test name
Test status
Simulation time 174523514 ps
CPU time 4.43 seconds
Started Jun 24 04:41:42 PM PDT 24
Finished Jun 24 04:41:55 PM PDT 24
Peak memory 216232 kb
Host smart-d7893184-9e06-4266-a87b-be4989639781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595538120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3595538120
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1101877959
Short name T347
Test name
Test status
Simulation time 435858101 ps
CPU time 1.05 seconds
Started Jun 24 04:41:50 PM PDT 24
Finished Jun 24 04:42:01 PM PDT 24
Peak memory 206956 kb
Host smart-d1a5f757-6d29-435c-b862-13b5227cde41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101877959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1101877959
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1820912256
Short name T783
Test name
Test status
Simulation time 1042918427 ps
CPU time 3.37 seconds
Started Jun 24 04:41:45 PM PDT 24
Finished Jun 24 04:41:57 PM PDT 24
Peak memory 224532 kb
Host smart-b893b753-49ea-48ab-9fe7-edf7f12c0e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820912256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1820912256
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.684906998
Short name T590
Test name
Test status
Simulation time 41121375 ps
CPU time 0.69 seconds
Started Jun 24 04:41:44 PM PDT 24
Finished Jun 24 04:41:53 PM PDT 24
Peak memory 204816 kb
Host smart-5f3644f4-2397-4998-857f-42675cce060d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684906998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.684906998
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1656975306
Short name T514
Test name
Test status
Simulation time 110949016 ps
CPU time 3.38 seconds
Started Jun 24 04:41:41 PM PDT 24
Finished Jun 24 04:41:52 PM PDT 24
Peak memory 232684 kb
Host smart-e227c48c-36d8-48e2-93f8-6296b586ff7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656975306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1656975306
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3504358469
Short name T34
Test name
Test status
Simulation time 62401006 ps
CPU time 0.84 seconds
Started Jun 24 04:41:43 PM PDT 24
Finished Jun 24 04:41:52 PM PDT 24
Peak memory 206552 kb
Host smart-dca7ac1d-d0b9-4642-82ca-5e8669c0531b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504358469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3504358469
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.835603431
Short name T220
Test name
Test status
Simulation time 986348473 ps
CPU time 22.02 seconds
Started Jun 24 04:41:50 PM PDT 24
Finished Jun 24 04:42:22 PM PDT 24
Peak memory 224440 kb
Host smart-cdd4276f-66b3-4b2c-adf4-5a4b1ffed331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835603431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.835603431
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.4196523162
Short name T38
Test name
Test status
Simulation time 4748903241 ps
CPU time 91.2 seconds
Started Jun 24 04:41:45 PM PDT 24
Finished Jun 24 04:43:26 PM PDT 24
Peak memory 257436 kb
Host smart-f1adc251-b274-4e15-99a4-4f1a19be7233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196523162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.4196523162
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3012764553
Short name T880
Test name
Test status
Simulation time 3589083250 ps
CPU time 50.37 seconds
Started Jun 24 04:41:50 PM PDT 24
Finished Jun 24 04:42:51 PM PDT 24
Peak memory 256976 kb
Host smart-aed2874e-a8a9-46d8-b93e-73dcdb8c3d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012764553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3012764553
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2140277467
Short name T674
Test name
Test status
Simulation time 471052689 ps
CPU time 3.21 seconds
Started Jun 24 04:41:46 PM PDT 24
Finished Jun 24 04:41:58 PM PDT 24
Peak memory 224484 kb
Host smart-8de3d545-c77f-48b5-9dfb-0a8334002311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140277467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2140277467
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.627758995
Short name T900
Test name
Test status
Simulation time 3285891779 ps
CPU time 5.68 seconds
Started Jun 24 04:41:43 PM PDT 24
Finished Jun 24 04:41:56 PM PDT 24
Peak memory 224596 kb
Host smart-0a31408b-2700-4a69-8a3e-24395d264e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627758995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.627758995
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2578400831
Short name T615
Test name
Test status
Simulation time 5637313550 ps
CPU time 26.54 seconds
Started Jun 24 04:41:45 PM PDT 24
Finished Jun 24 04:42:21 PM PDT 24
Peak memory 232848 kb
Host smart-14488b71-b526-4c8c-940e-477574018ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578400831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2578400831
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.41523941
Short name T520
Test name
Test status
Simulation time 5142706573 ps
CPU time 14.11 seconds
Started Jun 24 04:41:45 PM PDT 24
Finished Jun 24 04:42:08 PM PDT 24
Peak memory 232880 kb
Host smart-f6da7281-40bd-441f-b44b-cc043f33772f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41523941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.41523941
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2160904066
Short name T252
Test name
Test status
Simulation time 3647577236 ps
CPU time 12.04 seconds
Started Jun 24 04:41:44 PM PDT 24
Finished Jun 24 04:42:05 PM PDT 24
Peak memory 232776 kb
Host smart-5c9a0eaf-5f72-4ecd-a205-675ce97e51a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160904066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2160904066
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1087051076
Short name T878
Test name
Test status
Simulation time 4730695610 ps
CPU time 12.46 seconds
Started Jun 24 04:41:44 PM PDT 24
Finished Jun 24 04:42:05 PM PDT 24
Peak memory 219500 kb
Host smart-e52be8a3-fe52-4c70-97ba-e182c2732d8a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1087051076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1087051076
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1702588408
Short name T855
Test name
Test status
Simulation time 1933419293 ps
CPU time 28.63 seconds
Started Jun 24 04:41:42 PM PDT 24
Finished Jun 24 04:42:19 PM PDT 24
Peak memory 224636 kb
Host smart-f8913e7d-0ee6-418a-bc03-88f38ccfcb90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702588408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1702588408
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2055672164
Short name T315
Test name
Test status
Simulation time 2527755086 ps
CPU time 19.46 seconds
Started Jun 24 04:41:50 PM PDT 24
Finished Jun 24 04:42:20 PM PDT 24
Peak memory 216320 kb
Host smart-72686b45-69d7-4951-bcd4-d8f3232eb8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055672164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2055672164
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1560083687
Short name T381
Test name
Test status
Simulation time 4509789016 ps
CPU time 9.78 seconds
Started Jun 24 04:41:46 PM PDT 24
Finished Jun 24 04:42:05 PM PDT 24
Peak memory 216308 kb
Host smart-46d478a2-a0dc-467a-987e-8c0998a63cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560083687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1560083687
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2784942501
Short name T785
Test name
Test status
Simulation time 80105818 ps
CPU time 1.32 seconds
Started Jun 24 04:41:43 PM PDT 24
Finished Jun 24 04:41:52 PM PDT 24
Peak memory 216196 kb
Host smart-3fca08ba-a367-4a81-b6f0-97709209f3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784942501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2784942501
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.969774429
Short name T345
Test name
Test status
Simulation time 23838293 ps
CPU time 0.81 seconds
Started Jun 24 04:41:47 PM PDT 24
Finished Jun 24 04:41:57 PM PDT 24
Peak memory 205932 kb
Host smart-a1e53c98-8bb0-4b26-98f7-f0cb8c5db053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969774429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.969774429
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1574999737
Short name T753
Test name
Test status
Simulation time 41685327 ps
CPU time 2.67 seconds
Started Jun 24 04:41:46 PM PDT 24
Finished Jun 24 04:41:58 PM PDT 24
Peak memory 235384 kb
Host smart-95845264-f970-4611-ac84-d00fb85d5ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574999737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1574999737
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.4195913088
Short name T565
Test name
Test status
Simulation time 15588779 ps
CPU time 0.75 seconds
Started Jun 24 04:41:49 PM PDT 24
Finished Jun 24 04:42:00 PM PDT 24
Peak memory 204768 kb
Host smart-a269cd8d-3d56-4716-8dcd-6c2a20ea1e53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195913088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
4195913088
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.348858337
Short name T258
Test name
Test status
Simulation time 32372612 ps
CPU time 2.46 seconds
Started Jun 24 04:41:54 PM PDT 24
Finished Jun 24 04:42:06 PM PDT 24
Peak memory 232700 kb
Host smart-27c78565-df1d-495a-aa47-6335b1fc719d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348858337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.348858337
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2180113727
Short name T618
Test name
Test status
Simulation time 24555610 ps
CPU time 0.76 seconds
Started Jun 24 04:41:45 PM PDT 24
Finished Jun 24 04:41:55 PM PDT 24
Peak memory 206576 kb
Host smart-572e000c-cd43-4bcc-bfd7-62a7a0d8c653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180113727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2180113727
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2765107702
Short name T860
Test name
Test status
Simulation time 103976362440 ps
CPU time 191.1 seconds
Started Jun 24 04:41:53 PM PDT 24
Finished Jun 24 04:45:14 PM PDT 24
Peak memory 255528 kb
Host smart-677e5a9a-fc19-4a68-b8e0-48ff84e0a2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765107702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2765107702
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.706003342
Short name T198
Test name
Test status
Simulation time 138570779501 ps
CPU time 209.47 seconds
Started Jun 24 04:41:52 PM PDT 24
Finished Jun 24 04:45:32 PM PDT 24
Peak memory 252780 kb
Host smart-48dfe343-6592-4a52-a6be-3c88874ad959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706003342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.706003342
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3452588984
Short name T403
Test name
Test status
Simulation time 1821532531 ps
CPU time 13.87 seconds
Started Jun 24 04:41:53 PM PDT 24
Finished Jun 24 04:42:16 PM PDT 24
Peak memory 224480 kb
Host smart-65c7686e-e2af-40a2-a3b6-cbfc4d8d95c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452588984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3452588984
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.243606386
Short name T741
Test name
Test status
Simulation time 361612259 ps
CPU time 4.87 seconds
Started Jun 24 04:41:50 PM PDT 24
Finished Jun 24 04:42:04 PM PDT 24
Peak memory 224480 kb
Host smart-2c55d3db-29bc-4263-b7f6-26194c5c62b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243606386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.243606386
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.345352579
Short name T419
Test name
Test status
Simulation time 165855907 ps
CPU time 3.09 seconds
Started Jun 24 04:41:51 PM PDT 24
Finished Jun 24 04:42:04 PM PDT 24
Peak memory 224448 kb
Host smart-19eda837-b6c7-46b3-8028-680f80a23897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345352579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.345352579
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2551813552
Short name T268
Test name
Test status
Simulation time 5547534853 ps
CPU time 13.43 seconds
Started Jun 24 04:41:50 PM PDT 24
Finished Jun 24 04:42:13 PM PDT 24
Peak memory 232680 kb
Host smart-6a34760b-5eef-4e4d-bc11-6e341e4f87f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551813552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2551813552
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3705375823
Short name T525
Test name
Test status
Simulation time 17762688416 ps
CPU time 14.25 seconds
Started Jun 24 04:41:45 PM PDT 24
Finished Jun 24 04:42:08 PM PDT 24
Peak memory 241012 kb
Host smart-4ef3d3f5-1d1b-44b8-8eff-2564d63ad2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705375823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3705375823
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1062509084
Short name T713
Test name
Test status
Simulation time 1003734273 ps
CPU time 8.73 seconds
Started Jun 24 04:41:49 PM PDT 24
Finished Jun 24 04:42:07 PM PDT 24
Peak memory 220500 kb
Host smart-23134679-5845-4c20-b0a6-783fd720839e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1062509084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1062509084
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2394093361
Short name T399
Test name
Test status
Simulation time 4109367770 ps
CPU time 17.77 seconds
Started Jun 24 04:41:47 PM PDT 24
Finished Jun 24 04:42:14 PM PDT 24
Peak memory 219976 kb
Host smart-f4fe0356-3da5-4c8a-9bcd-9991f70b673f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394093361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2394093361
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2735235571
Short name T650
Test name
Test status
Simulation time 1046052003 ps
CPU time 6.86 seconds
Started Jun 24 04:41:47 PM PDT 24
Finished Jun 24 04:42:03 PM PDT 24
Peak memory 216212 kb
Host smart-1ce089c9-3ece-462f-aaa8-33456177e62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735235571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2735235571
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.350398885
Short name T702
Test name
Test status
Simulation time 98929656 ps
CPU time 0.89 seconds
Started Jun 24 04:41:46 PM PDT 24
Finished Jun 24 04:41:56 PM PDT 24
Peak memory 207908 kb
Host smart-483e2384-edcb-40b6-abec-d12dbecfe6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350398885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.350398885
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2133803596
Short name T412
Test name
Test status
Simulation time 98555139 ps
CPU time 0.8 seconds
Started Jun 24 04:41:44 PM PDT 24
Finished Jun 24 04:41:53 PM PDT 24
Peak memory 205948 kb
Host smart-e294378d-3b12-417b-a471-96ce6cf508de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133803596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2133803596
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1273674211
Short name T277
Test name
Test status
Simulation time 1023818025 ps
CPU time 2.76 seconds
Started Jun 24 04:41:49 PM PDT 24
Finished Jun 24 04:42:01 PM PDT 24
Peak memory 224424 kb
Host smart-3976dbc6-a246-4d1b-bd46-dd65a4992a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273674211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1273674211
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.4127657252
Short name T506
Test name
Test status
Simulation time 44178464 ps
CPU time 0.73 seconds
Started Jun 24 04:40:29 PM PDT 24
Finished Jun 24 04:40:41 PM PDT 24
Peak memory 205344 kb
Host smart-25931acb-2c21-4943-a7d2-74cb0a9a407c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127657252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.4
127657252
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.547589590
Short name T80
Test name
Test status
Simulation time 1420751995 ps
CPU time 14.6 seconds
Started Jun 24 04:40:24 PM PDT 24
Finished Jun 24 04:40:53 PM PDT 24
Peak memory 224500 kb
Host smart-a264b262-fc0c-45a2-a7af-62d72591cc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547589590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.547589590
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3584261506
Short name T545
Test name
Test status
Simulation time 17783185 ps
CPU time 0.77 seconds
Started Jun 24 04:40:26 PM PDT 24
Finished Jun 24 04:40:40 PM PDT 24
Peak memory 205560 kb
Host smart-61303cbe-8682-4414-8b25-36fe069e292f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584261506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3584261506
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3046916018
Short name T300
Test name
Test status
Simulation time 1535055673 ps
CPU time 10.26 seconds
Started Jun 24 04:40:26 PM PDT 24
Finished Jun 24 04:40:49 PM PDT 24
Peak memory 249080 kb
Host smart-347ec94f-e589-4753-89ea-1829cc1dc925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046916018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3046916018
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3835115221
Short name T141
Test name
Test status
Simulation time 32116668929 ps
CPU time 146.61 seconds
Started Jun 24 04:40:29 PM PDT 24
Finished Jun 24 04:43:07 PM PDT 24
Peak memory 250272 kb
Host smart-84bdb439-15a3-449c-9954-51870bca618a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835115221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3835115221
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.139620731
Short name T208
Test name
Test status
Simulation time 15022595111 ps
CPU time 94.59 seconds
Started Jun 24 04:40:26 PM PDT 24
Finished Jun 24 04:42:14 PM PDT 24
Peak memory 263672 kb
Host smart-0dcc431a-dd81-4e1e-8802-c69b2ac71eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139620731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
139620731
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3858778902
Short name T309
Test name
Test status
Simulation time 1038341826 ps
CPU time 13.14 seconds
Started Jun 24 04:40:28 PM PDT 24
Finished Jun 24 04:40:53 PM PDT 24
Peak memory 235064 kb
Host smart-7aa7da3d-b65d-48b8-886e-e178f8d84ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858778902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3858778902
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3774569027
Short name T259
Test name
Test status
Simulation time 14369388594 ps
CPU time 18.66 seconds
Started Jun 24 04:40:26 PM PDT 24
Finished Jun 24 04:40:58 PM PDT 24
Peak memory 232828 kb
Host smart-06808e58-7c4b-494a-8206-a80b98fed9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774569027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3774569027
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.4042984546
Short name T261
Test name
Test status
Simulation time 8120324595 ps
CPU time 29.04 seconds
Started Jun 24 04:40:27 PM PDT 24
Finished Jun 24 04:41:09 PM PDT 24
Peak memory 232844 kb
Host smart-63073672-ee87-4077-93c5-305081a94988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042984546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.4042984546
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3841881793
Short name T243
Test name
Test status
Simulation time 5282367586 ps
CPU time 8.27 seconds
Started Jun 24 04:40:28 PM PDT 24
Finished Jun 24 04:40:49 PM PDT 24
Peak memory 232752 kb
Host smart-98ef6c68-f23e-432e-ae60-852b23e96e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841881793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3841881793
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.909843360
Short name T830
Test name
Test status
Simulation time 28730729980 ps
CPU time 22.35 seconds
Started Jun 24 04:40:27 PM PDT 24
Finished Jun 24 04:41:03 PM PDT 24
Peak memory 224596 kb
Host smart-73c9b5ce-e217-449f-bdb6-e2f2957f704c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909843360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.909843360
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1342630770
Short name T794
Test name
Test status
Simulation time 2815088804 ps
CPU time 9.55 seconds
Started Jun 24 04:40:26 PM PDT 24
Finished Jun 24 04:40:49 PM PDT 24
Peak memory 223148 kb
Host smart-9df2e355-081f-45df-9bca-0531936e29df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1342630770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1342630770
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2026981876
Short name T71
Test name
Test status
Simulation time 62896960 ps
CPU time 1.11 seconds
Started Jun 24 04:40:25 PM PDT 24
Finished Jun 24 04:40:40 PM PDT 24
Peak memory 234748 kb
Host smart-9d8bab6c-3bb7-4839-a582-a95cea589762
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026981876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2026981876
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2871555980
Short name T795
Test name
Test status
Simulation time 51840833277 ps
CPU time 120.71 seconds
Started Jun 24 04:40:26 PM PDT 24
Finished Jun 24 04:42:41 PM PDT 24
Peak memory 273840 kb
Host smart-b808af41-c83c-4371-9ac2-42f10b4cc1a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871555980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2871555980
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1763921252
Short name T563
Test name
Test status
Simulation time 3947206370 ps
CPU time 11.6 seconds
Started Jun 24 04:40:28 PM PDT 24
Finished Jun 24 04:40:52 PM PDT 24
Peak memory 216476 kb
Host smart-e8230f48-b0e3-4c46-9491-1639e84bb9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763921252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1763921252
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.816880070
Short name T593
Test name
Test status
Simulation time 14077575316 ps
CPU time 20.79 seconds
Started Jun 24 04:40:27 PM PDT 24
Finished Jun 24 04:41:01 PM PDT 24
Peak memory 216388 kb
Host smart-ebd01c5e-d675-42e7-97d6-f7503e25e3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816880070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.816880070
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.769453195
Short name T497
Test name
Test status
Simulation time 309896227 ps
CPU time 1.54 seconds
Started Jun 24 04:40:26 PM PDT 24
Finished Jun 24 04:40:41 PM PDT 24
Peak memory 216240 kb
Host smart-7259ffb6-4e4e-4ac8-a803-251cbbd7c9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769453195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.769453195
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.4276067805
Short name T29
Test name
Test status
Simulation time 280654533 ps
CPU time 0.9 seconds
Started Jun 24 04:40:26 PM PDT 24
Finished Jun 24 04:40:40 PM PDT 24
Peak memory 205876 kb
Host smart-c629e8b0-84ae-445b-a00d-a72e61967d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276067805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.4276067805
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1734530883
Short name T730
Test name
Test status
Simulation time 8707274418 ps
CPU time 15.51 seconds
Started Jun 24 04:40:28 PM PDT 24
Finished Jun 24 04:40:56 PM PDT 24
Peak memory 232704 kb
Host smart-dd3bd1fc-fdcf-4e0d-ae9a-f3b96a901112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734530883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1734530883
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2197318215
Short name T684
Test name
Test status
Simulation time 14929696 ps
CPU time 0.74 seconds
Started Jun 24 04:41:49 PM PDT 24
Finished Jun 24 04:41:59 PM PDT 24
Peak memory 204808 kb
Host smart-04d91978-4bdb-45b9-81fd-987f0538b38c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197318215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2197318215
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2398607910
Short name T377
Test name
Test status
Simulation time 82060342 ps
CPU time 2.39 seconds
Started Jun 24 04:41:52 PM PDT 24
Finished Jun 24 04:42:05 PM PDT 24
Peak memory 224492 kb
Host smart-91daec7a-7906-45f5-acb7-d981cf3056d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398607910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2398607910
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2473412734
Short name T329
Test name
Test status
Simulation time 36772002 ps
CPU time 0.78 seconds
Started Jun 24 04:41:53 PM PDT 24
Finished Jun 24 04:42:03 PM PDT 24
Peak memory 205528 kb
Host smart-a528ca94-1eb8-49be-86d0-00035ca7c153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473412734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2473412734
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2965781442
Short name T255
Test name
Test status
Simulation time 1550568568 ps
CPU time 15.52 seconds
Started Jun 24 04:41:51 PM PDT 24
Finished Jun 24 04:42:16 PM PDT 24
Peak memory 236836 kb
Host smart-0f3c3252-b467-4727-ae79-c04b9aee5e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965781442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2965781442
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2669104655
Short name T819
Test name
Test status
Simulation time 1775821066 ps
CPU time 9.8 seconds
Started Jun 24 04:41:52 PM PDT 24
Finished Jun 24 04:42:12 PM PDT 24
Peak memory 217464 kb
Host smart-bc6a0c46-fab3-4f3a-a752-b7535b20e608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669104655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2669104655
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2789983563
Short name T697
Test name
Test status
Simulation time 67097339 ps
CPU time 0.82 seconds
Started Jun 24 04:41:54 PM PDT 24
Finished Jun 24 04:42:05 PM PDT 24
Peak memory 217376 kb
Host smart-5c434214-d4aa-4eb5-a3e2-75dec853ba39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789983563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2789983563
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.4059079660
Short name T313
Test name
Test status
Simulation time 807706899 ps
CPU time 16.9 seconds
Started Jun 24 04:41:51 PM PDT 24
Finished Jun 24 04:42:18 PM PDT 24
Peak memory 249096 kb
Host smart-66941ba0-295b-4436-bf68-a7b11a56f842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059079660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.4059079660
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3563308327
Short name T542
Test name
Test status
Simulation time 511740268 ps
CPU time 6.25 seconds
Started Jun 24 04:41:54 PM PDT 24
Finished Jun 24 04:42:10 PM PDT 24
Peak memory 224516 kb
Host smart-35dc25e5-10c4-4e26-b30a-6b7c5f83fd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563308327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3563308327
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2334479253
Short name T946
Test name
Test status
Simulation time 4266219163 ps
CPU time 23.48 seconds
Started Jun 24 04:41:50 PM PDT 24
Finished Jun 24 04:42:23 PM PDT 24
Peak memory 232752 kb
Host smart-d6736a0d-c973-46a4-b19b-23dc433dbfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334479253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2334479253
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3286746936
Short name T683
Test name
Test status
Simulation time 385044528 ps
CPU time 2.63 seconds
Started Jun 24 04:41:50 PM PDT 24
Finished Jun 24 04:42:02 PM PDT 24
Peak memory 232700 kb
Host smart-d6da2738-4e38-4391-a13f-7a4585e2692c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286746936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3286746936
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2747109737
Short name T696
Test name
Test status
Simulation time 2101584727 ps
CPU time 8.39 seconds
Started Jun 24 04:41:51 PM PDT 24
Finished Jun 24 04:42:09 PM PDT 24
Peak memory 232716 kb
Host smart-8c24af07-a2bd-4f9c-a222-655b5a3fff09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747109737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2747109737
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3327393115
Short name T150
Test name
Test status
Simulation time 872412844 ps
CPU time 10.36 seconds
Started Jun 24 04:41:52 PM PDT 24
Finished Jun 24 04:42:12 PM PDT 24
Peak memory 220952 kb
Host smart-9e598b48-0451-4c31-a811-1631717c9c25
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3327393115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3327393115
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.708918876
Short name T656
Test name
Test status
Simulation time 56091517 ps
CPU time 0.95 seconds
Started Jun 24 04:41:49 PM PDT 24
Finished Jun 24 04:41:59 PM PDT 24
Peak memory 207416 kb
Host smart-09005f16-b036-49b3-9821-ecc0f51aa9d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708918876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.708918876
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3546116367
Short name T586
Test name
Test status
Simulation time 4652682823 ps
CPU time 18.81 seconds
Started Jun 24 04:41:54 PM PDT 24
Finished Jun 24 04:42:23 PM PDT 24
Peak memory 216456 kb
Host smart-ff551d2f-f7ea-4379-ae9d-9d75d0f71eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546116367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3546116367
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2966400312
Short name T332
Test name
Test status
Simulation time 16200629083 ps
CPU time 11.5 seconds
Started Jun 24 04:41:50 PM PDT 24
Finished Jun 24 04:42:12 PM PDT 24
Peak memory 216300 kb
Host smart-b5c171de-0c10-4240-bfc8-a62b349766e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966400312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2966400312
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2611770473
Short name T798
Test name
Test status
Simulation time 117985646 ps
CPU time 1.96 seconds
Started Jun 24 04:41:50 PM PDT 24
Finished Jun 24 04:42:01 PM PDT 24
Peak memory 216244 kb
Host smart-a9ab63ae-07c5-4242-9ed3-de4fa38675c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611770473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2611770473
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3368066236
Short name T892
Test name
Test status
Simulation time 71885901 ps
CPU time 0.75 seconds
Started Jun 24 04:41:52 PM PDT 24
Finished Jun 24 04:42:03 PM PDT 24
Peak memory 205920 kb
Host smart-5f129729-8187-4977-8ccf-e25ea8457996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368066236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3368066236
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.635503812
Short name T945
Test name
Test status
Simulation time 3132895151 ps
CPU time 13.54 seconds
Started Jun 24 04:41:53 PM PDT 24
Finished Jun 24 04:42:16 PM PDT 24
Peak memory 238916 kb
Host smart-89114457-09d2-46bf-906a-f8832aedd78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635503812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.635503812
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3025934493
Short name T760
Test name
Test status
Simulation time 37116042 ps
CPU time 0.73 seconds
Started Jun 24 04:41:49 PM PDT 24
Finished Jun 24 04:41:59 PM PDT 24
Peak memory 205332 kb
Host smart-769c0177-eb4b-4b13-8f86-c6d5eb3876a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025934493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3025934493
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3045419622
Short name T89
Test name
Test status
Simulation time 178740169 ps
CPU time 3.01 seconds
Started Jun 24 04:41:50 PM PDT 24
Finished Jun 24 04:42:03 PM PDT 24
Peak memory 224428 kb
Host smart-b1282689-c906-4aad-a646-0d8937b1a1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045419622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3045419622
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2455972477
Short name T25
Test name
Test status
Simulation time 51704107 ps
CPU time 0.79 seconds
Started Jun 24 04:41:51 PM PDT 24
Finished Jun 24 04:42:02 PM PDT 24
Peak memory 206908 kb
Host smart-f14e0e20-a856-4e47-98e5-eb2b6b95803a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455972477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2455972477
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.491927531
Short name T221
Test name
Test status
Simulation time 100526881034 ps
CPU time 178.99 seconds
Started Jun 24 04:41:54 PM PDT 24
Finished Jun 24 04:45:03 PM PDT 24
Peak memory 249260 kb
Host smart-1693ce8c-4c7a-4d39-b4ce-3351913fca7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491927531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.491927531
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.597428640
Short name T289
Test name
Test status
Simulation time 26970679032 ps
CPU time 181.45 seconds
Started Jun 24 04:41:53 PM PDT 24
Finished Jun 24 04:45:05 PM PDT 24
Peak memory 250268 kb
Host smart-406def37-9ac4-4b27-bca1-01d7f187cedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597428640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.597428640
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2399023196
Short name T292
Test name
Test status
Simulation time 304372748499 ps
CPU time 495.19 seconds
Started Jun 24 04:41:50 PM PDT 24
Finished Jun 24 04:50:15 PM PDT 24
Peak memory 267636 kb
Host smart-d08227ca-3b04-40a7-b873-1d52a2093387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399023196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2399023196
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2273637131
Short name T729
Test name
Test status
Simulation time 7759743019 ps
CPU time 38.62 seconds
Started Jun 24 04:41:51 PM PDT 24
Finished Jun 24 04:42:40 PM PDT 24
Peak memory 240740 kb
Host smart-cb3e8323-b337-4230-9240-8fbd6f3e9d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273637131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2273637131
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.4061130714
Short name T202
Test name
Test status
Simulation time 3148907651 ps
CPU time 8.38 seconds
Started Jun 24 04:41:53 PM PDT 24
Finished Jun 24 04:42:11 PM PDT 24
Peak memory 224580 kb
Host smart-07ad783e-2ac6-4556-9152-1798b6a3d516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061130714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.4061130714
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.924396867
Short name T655
Test name
Test status
Simulation time 10574678334 ps
CPU time 107.08 seconds
Started Jun 24 04:41:49 PM PDT 24
Finished Jun 24 04:43:46 PM PDT 24
Peak memory 240780 kb
Host smart-07210547-0407-45f0-b673-375509531020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924396867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.924396867
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.207799985
Short name T475
Test name
Test status
Simulation time 163968120 ps
CPU time 3.82 seconds
Started Jun 24 04:41:53 PM PDT 24
Finished Jun 24 04:42:07 PM PDT 24
Peak memory 232652 kb
Host smart-baaec83c-7965-4c00-b865-664045ea6444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207799985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.207799985
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3330164511
Short name T633
Test name
Test status
Simulation time 20145860133 ps
CPU time 15.44 seconds
Started Jun 24 04:41:51 PM PDT 24
Finished Jun 24 04:42:16 PM PDT 24
Peak memory 232832 kb
Host smart-81642b1b-1d4f-456a-bf70-47a78b50aa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330164511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3330164511
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2226522080
Short name T153
Test name
Test status
Simulation time 6154276687 ps
CPU time 15.03 seconds
Started Jun 24 04:41:53 PM PDT 24
Finished Jun 24 04:42:18 PM PDT 24
Peak memory 220316 kb
Host smart-f6188044-dc5b-4924-9178-902b45175f98
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2226522080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2226522080
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1551800196
Short name T297
Test name
Test status
Simulation time 480838084678 ps
CPU time 603.76 seconds
Started Jun 24 04:41:52 PM PDT 24
Finished Jun 24 04:52:06 PM PDT 24
Peak memory 266568 kb
Host smart-e3e45da1-3f0d-48da-9bbb-ab80d72e32bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551800196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1551800196
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3484003298
Short name T549
Test name
Test status
Simulation time 9334541720 ps
CPU time 17.41 seconds
Started Jun 24 04:41:54 PM PDT 24
Finished Jun 24 04:42:21 PM PDT 24
Peak memory 216376 kb
Host smart-1129119a-2802-4add-8d7b-31c3ae5059bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484003298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3484003298
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1699531709
Short name T732
Test name
Test status
Simulation time 1744971070 ps
CPU time 10.3 seconds
Started Jun 24 04:41:52 PM PDT 24
Finished Jun 24 04:42:12 PM PDT 24
Peak memory 216216 kb
Host smart-7f5fe59d-0912-4222-99ea-61585c85910e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699531709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1699531709
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1877561255
Short name T939
Test name
Test status
Simulation time 423253965 ps
CPU time 1.12 seconds
Started Jun 24 04:41:50 PM PDT 24
Finished Jun 24 04:42:01 PM PDT 24
Peak memory 207988 kb
Host smart-741363a1-a9d7-48e2-b5ba-312b5fdbc210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877561255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1877561255
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2172988603
Short name T352
Test name
Test status
Simulation time 116892986 ps
CPU time 0.8 seconds
Started Jun 24 04:41:54 PM PDT 24
Finished Jun 24 04:42:04 PM PDT 24
Peak memory 205992 kb
Host smart-d4cc5a6c-a50b-43d7-aaf2-6c6afde0d767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172988603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2172988603
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2097991305
Short name T53
Test name
Test status
Simulation time 2114106433 ps
CPU time 8.57 seconds
Started Jun 24 04:41:51 PM PDT 24
Finished Jun 24 04:42:10 PM PDT 24
Peak memory 224480 kb
Host smart-80f219e3-3aac-4131-a2e9-998c3fee36ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097991305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2097991305
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1214693025
Short name T865
Test name
Test status
Simulation time 12983161 ps
CPU time 0.71 seconds
Started Jun 24 04:41:55 PM PDT 24
Finished Jun 24 04:42:06 PM PDT 24
Peak memory 205392 kb
Host smart-7b68854b-c0d8-4e46-83be-e796d9a553b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214693025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1214693025
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.4045083694
Short name T962
Test name
Test status
Simulation time 373159369 ps
CPU time 5.71 seconds
Started Jun 24 04:42:01 PM PDT 24
Finished Jun 24 04:42:17 PM PDT 24
Peak memory 224568 kb
Host smart-548797d5-6506-4243-a661-debde2933025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045083694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.4045083694
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.4234971061
Short name T928
Test name
Test status
Simulation time 27782110 ps
CPU time 0.78 seconds
Started Jun 24 04:41:54 PM PDT 24
Finished Jun 24 04:42:04 PM PDT 24
Peak memory 205864 kb
Host smart-cf6febb8-e1da-4596-aef7-e09084c2d00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234971061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.4234971061
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1208438237
Short name T194
Test name
Test status
Simulation time 8100318794 ps
CPU time 102.33 seconds
Started Jun 24 04:41:57 PM PDT 24
Finished Jun 24 04:43:51 PM PDT 24
Peak memory 269012 kb
Host smart-4dd77023-bee6-4261-bcdc-edad99e36376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208438237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1208438237
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.632236349
Short name T83
Test name
Test status
Simulation time 94667494764 ps
CPU time 211.14 seconds
Started Jun 24 04:41:54 PM PDT 24
Finished Jun 24 04:45:35 PM PDT 24
Peak memory 265212 kb
Host smart-659b5c8d-fe82-4873-80ae-596b7aaae2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632236349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.632236349
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1619605458
Short name T5
Test name
Test status
Simulation time 12715702532 ps
CPU time 90.6 seconds
Started Jun 24 04:41:56 PM PDT 24
Finished Jun 24 04:43:37 PM PDT 24
Peak memory 257028 kb
Host smart-ef4076a8-5232-4756-ab80-9f293a60e338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619605458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1619605458
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3590640059
Short name T154
Test name
Test status
Simulation time 3296820195 ps
CPU time 34.17 seconds
Started Jun 24 04:41:56 PM PDT 24
Finished Jun 24 04:42:41 PM PDT 24
Peak memory 249200 kb
Host smart-6bb56029-a4c6-40d8-b297-105f4eddc817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590640059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3590640059
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2239626264
Short name T441
Test name
Test status
Simulation time 1696132977 ps
CPU time 17.07 seconds
Started Jun 24 04:41:55 PM PDT 24
Finished Jun 24 04:42:22 PM PDT 24
Peak memory 224480 kb
Host smart-5d90a89a-d782-4a33-a53d-761701ff7d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239626264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2239626264
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3070226916
Short name T737
Test name
Test status
Simulation time 903839275 ps
CPU time 14.46 seconds
Started Jun 24 04:41:55 PM PDT 24
Finished Jun 24 04:42:20 PM PDT 24
Peak memory 224420 kb
Host smart-719a1578-0a9b-418f-8d9b-fd0aebbc984b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070226916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3070226916
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.547787806
Short name T922
Test name
Test status
Simulation time 9854092697 ps
CPU time 13.56 seconds
Started Jun 24 04:41:54 PM PDT 24
Finished Jun 24 04:42:17 PM PDT 24
Peak memory 232740 kb
Host smart-cf3a0993-342c-42e1-9a47-cd9bb5ca5ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547787806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.547787806
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1289055835
Short name T547
Test name
Test status
Simulation time 8925050675 ps
CPU time 22.52 seconds
Started Jun 24 04:41:56 PM PDT 24
Finished Jun 24 04:42:29 PM PDT 24
Peak memory 232880 kb
Host smart-b115e1dc-2a6b-455a-a61f-11fa8d02326d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289055835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1289055835
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2670206617
Short name T641
Test name
Test status
Simulation time 2200719275 ps
CPU time 3.12 seconds
Started Jun 24 04:41:55 PM PDT 24
Finished Jun 24 04:42:08 PM PDT 24
Peak memory 219544 kb
Host smart-f43adc2f-92fa-4503-869b-e9720526bcdd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2670206617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2670206617
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1287607916
Short name T649
Test name
Test status
Simulation time 166697360 ps
CPU time 0.95 seconds
Started Jun 24 04:41:57 PM PDT 24
Finished Jun 24 04:42:08 PM PDT 24
Peak memory 206900 kb
Host smart-a8cd3e92-e01c-4b31-b0a0-4de570ae9d7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287607916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1287607916
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1021546596
Short name T838
Test name
Test status
Simulation time 52640111 ps
CPU time 0.71 seconds
Started Jun 24 04:41:56 PM PDT 24
Finished Jun 24 04:42:07 PM PDT 24
Peak memory 205668 kb
Host smart-255d44fe-2474-4149-a8ed-8be72988addb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021546596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1021546596
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3982797002
Short name T808
Test name
Test status
Simulation time 5919715127 ps
CPU time 16.75 seconds
Started Jun 24 04:42:02 PM PDT 24
Finished Jun 24 04:42:28 PM PDT 24
Peak memory 216324 kb
Host smart-f8dffeee-2bf9-47ad-9ae9-b689a250a2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982797002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3982797002
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.616967411
Short name T721
Test name
Test status
Simulation time 23495471 ps
CPU time 0.95 seconds
Started Jun 24 04:42:01 PM PDT 24
Finished Jun 24 04:42:12 PM PDT 24
Peak memory 216172 kb
Host smart-c447d69c-b3ec-43e6-9ac8-e2eb9405a7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616967411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.616967411
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2039621723
Short name T512
Test name
Test status
Simulation time 146179146 ps
CPU time 0.81 seconds
Started Jun 24 04:41:54 PM PDT 24
Finished Jun 24 04:42:05 PM PDT 24
Peak memory 205952 kb
Host smart-655866d9-e3a4-4cea-bc48-5cf9f0a904a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039621723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2039621723
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2054097780
Short name T355
Test name
Test status
Simulation time 291095310 ps
CPU time 2.56 seconds
Started Jun 24 04:41:57 PM PDT 24
Finished Jun 24 04:42:10 PM PDT 24
Peak memory 232712 kb
Host smart-9d2c5008-6d5f-40e0-bcf2-6d82dd86afcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054097780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2054097780
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1529803649
Short name T364
Test name
Test status
Simulation time 22699714 ps
CPU time 0.71 seconds
Started Jun 24 04:41:54 PM PDT 24
Finished Jun 24 04:42:05 PM PDT 24
Peak memory 204724 kb
Host smart-71a42958-efd5-4dfe-b08f-e55920de4447
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529803649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1529803649
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.4017360706
Short name T487
Test name
Test status
Simulation time 250690185 ps
CPU time 2.92 seconds
Started Jun 24 04:41:58 PM PDT 24
Finished Jun 24 04:42:12 PM PDT 24
Peak memory 232624 kb
Host smart-32e47662-e897-4d85-b77c-e5197ed29063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017360706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.4017360706
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.4021507266
Short name T820
Test name
Test status
Simulation time 13686562 ps
CPU time 0.83 seconds
Started Jun 24 04:41:55 PM PDT 24
Finished Jun 24 04:42:06 PM PDT 24
Peak memory 206560 kb
Host smart-124a34f6-2be7-4c40-a148-3bacccc6bc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021507266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.4021507266
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3676677455
Short name T353
Test name
Test status
Simulation time 70401205 ps
CPU time 0.76 seconds
Started Jun 24 04:41:57 PM PDT 24
Finished Jun 24 04:42:08 PM PDT 24
Peak memory 215808 kb
Host smart-5d9bc0cb-1e3d-4c45-9a2b-ac8a5926efcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676677455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3676677455
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1134463104
Short name T231
Test name
Test status
Simulation time 46494393909 ps
CPU time 430.22 seconds
Started Jun 24 04:42:02 PM PDT 24
Finished Jun 24 04:49:22 PM PDT 24
Peak memory 255404 kb
Host smart-9d812ea7-c1c1-46f6-b386-99f849932bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134463104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1134463104
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.509347780
Short name T895
Test name
Test status
Simulation time 3319372786 ps
CPU time 31.02 seconds
Started Jun 24 04:41:56 PM PDT 24
Finished Jun 24 04:42:38 PM PDT 24
Peak memory 249152 kb
Host smart-e588c149-31b0-4bae-9f2d-05df7e9617e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509347780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.509347780
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2489571064
Short name T199
Test name
Test status
Simulation time 11062226889 ps
CPU time 21.63 seconds
Started Jun 24 04:41:55 PM PDT 24
Finished Jun 24 04:42:26 PM PDT 24
Peak memory 232840 kb
Host smart-861f1396-1a6c-49d6-b26d-f66c67caaa3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489571064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2489571064
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1710146342
Short name T74
Test name
Test status
Simulation time 12571123440 ps
CPU time 35.26 seconds
Started Jun 24 04:41:55 PM PDT 24
Finished Jun 24 04:42:40 PM PDT 24
Peak memory 224648 kb
Host smart-890caf82-d050-484c-8b15-99a25645a0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710146342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1710146342
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.615904962
Short name T955
Test name
Test status
Simulation time 1440646581 ps
CPU time 7.87 seconds
Started Jun 24 04:41:56 PM PDT 24
Finished Jun 24 04:42:14 PM PDT 24
Peak memory 224484 kb
Host smart-ee451c73-db65-467a-9f68-ce5fcfe62f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615904962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.615904962
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.4069272553
Short name T557
Test name
Test status
Simulation time 3755731589 ps
CPU time 14.58 seconds
Started Jun 24 04:41:59 PM PDT 24
Finished Jun 24 04:42:24 PM PDT 24
Peak memory 232832 kb
Host smart-3d4d6816-3ae9-4561-a6b1-e0d582e91112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069272553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.4069272553
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1708282474
Short name T501
Test name
Test status
Simulation time 558881928 ps
CPU time 4.49 seconds
Started Jun 24 04:41:56 PM PDT 24
Finished Jun 24 04:42:11 PM PDT 24
Peak memory 220380 kb
Host smart-ad643f82-91a9-426a-bb91-d442511ad95b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1708282474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1708282474
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2365870779
Short name T320
Test name
Test status
Simulation time 5732148603 ps
CPU time 30.95 seconds
Started Jun 24 04:41:58 PM PDT 24
Finished Jun 24 04:42:39 PM PDT 24
Peak memory 216376 kb
Host smart-2b5647f7-8978-40ee-abd4-bbac4b3b1572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365870779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2365870779
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.4137557258
Short name T914
Test name
Test status
Simulation time 2648626465 ps
CPU time 5.81 seconds
Started Jun 24 04:41:58 PM PDT 24
Finished Jun 24 04:42:14 PM PDT 24
Peak memory 216668 kb
Host smart-12045967-4bc0-4a89-ae22-dec52b214b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137557258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.4137557258
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3242508592
Short name T692
Test name
Test status
Simulation time 40543769 ps
CPU time 0.82 seconds
Started Jun 24 04:41:55 PM PDT 24
Finished Jun 24 04:42:06 PM PDT 24
Peak memory 206624 kb
Host smart-9ddf4e0c-805f-4591-838c-ccf5dee3adc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242508592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3242508592
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1066722347
Short name T598
Test name
Test status
Simulation time 24675061 ps
CPU time 0.82 seconds
Started Jun 24 04:41:57 PM PDT 24
Finished Jun 24 04:42:08 PM PDT 24
Peak memory 205912 kb
Host smart-78187191-5363-4f50-a439-d956130d8f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066722347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1066722347
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2011570792
Short name T621
Test name
Test status
Simulation time 274984502 ps
CPU time 2.68 seconds
Started Jun 24 04:41:55 PM PDT 24
Finished Jun 24 04:42:08 PM PDT 24
Peak memory 235284 kb
Host smart-eb087588-888b-4fd7-8f98-ebe73aa9572e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011570792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2011570792
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3072127732
Short name T897
Test name
Test status
Simulation time 12215965 ps
CPU time 0.73 seconds
Started Jun 24 04:42:05 PM PDT 24
Finished Jun 24 04:42:17 PM PDT 24
Peak memory 205324 kb
Host smart-03364823-1896-4e79-a992-eff68054fdad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072127732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3072127732
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3819102178
Short name T396
Test name
Test status
Simulation time 130489108 ps
CPU time 3.19 seconds
Started Jun 24 04:42:01 PM PDT 24
Finished Jun 24 04:42:14 PM PDT 24
Peak memory 232744 kb
Host smart-89e40245-8e87-4d44-b1e7-c970ec20c86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819102178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3819102178
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3112880130
Short name T839
Test name
Test status
Simulation time 14557321 ps
CPU time 0.79 seconds
Started Jun 24 04:41:57 PM PDT 24
Finished Jun 24 04:42:08 PM PDT 24
Peak memory 206572 kb
Host smart-b29a7e37-60fe-43df-9d36-74dbc9083232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112880130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3112880130
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.232407506
Short name T723
Test name
Test status
Simulation time 7693372498 ps
CPU time 38.56 seconds
Started Jun 24 04:42:06 PM PDT 24
Finished Jun 24 04:42:54 PM PDT 24
Peak memory 249192 kb
Host smart-8c02a6c4-178c-443f-aaca-31deba318aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232407506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.232407506
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.150841308
Short name T507
Test name
Test status
Simulation time 9901211878 ps
CPU time 63.43 seconds
Started Jun 24 04:42:05 PM PDT 24
Finished Jun 24 04:43:19 PM PDT 24
Peak memory 256152 kb
Host smart-5d922010-d1ca-46fa-aaa0-badd88998255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150841308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.150841308
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3594704661
Short name T885
Test name
Test status
Simulation time 57133776383 ps
CPU time 328.57 seconds
Started Jun 24 04:42:04 PM PDT 24
Finished Jun 24 04:47:43 PM PDT 24
Peak memory 257212 kb
Host smart-cdd42f00-7af9-4baf-a555-d872f3200268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594704661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3594704661
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3839718826
Short name T886
Test name
Test status
Simulation time 99155666 ps
CPU time 5.09 seconds
Started Jun 24 04:41:56 PM PDT 24
Finished Jun 24 04:42:11 PM PDT 24
Peak memory 235564 kb
Host smart-9085c1c9-e1be-42f0-876c-5fd68f439d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839718826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3839718826
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1345228349
Short name T133
Test name
Test status
Simulation time 2517776465 ps
CPU time 9.23 seconds
Started Jun 24 04:42:00 PM PDT 24
Finished Jun 24 04:42:19 PM PDT 24
Peak memory 224680 kb
Host smart-13d4dbca-7e06-4f97-bb9f-bd669e7c7270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345228349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1345228349
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3920201019
Short name T568
Test name
Test status
Simulation time 18346365273 ps
CPU time 17.13 seconds
Started Jun 24 04:41:55 PM PDT 24
Finished Jun 24 04:42:23 PM PDT 24
Peak memory 248776 kb
Host smart-192daf09-3d43-4b96-a89a-6ffccedc7eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920201019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3920201019
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.285642821
Short name T263
Test name
Test status
Simulation time 487779733 ps
CPU time 3.03 seconds
Started Jun 24 04:41:55 PM PDT 24
Finished Jun 24 04:42:08 PM PDT 24
Peak memory 224428 kb
Host smart-accd43c3-1d07-42db-b2ed-eb65e495b6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285642821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.285642821
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3546714786
Short name T416
Test name
Test status
Simulation time 5008809313 ps
CPU time 14.71 seconds
Started Jun 24 04:41:56 PM PDT 24
Finished Jun 24 04:42:21 PM PDT 24
Peak memory 218772 kb
Host smart-be5dd519-81e3-447d-bc56-c34dbacad141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546714786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3546714786
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.18087522
Short name T155
Test name
Test status
Simulation time 1139924635 ps
CPU time 4.6 seconds
Started Jun 24 04:41:56 PM PDT 24
Finished Jun 24 04:42:11 PM PDT 24
Peak memory 218844 kb
Host smart-fe5bc220-4bf9-4a23-bf44-e3c82628341d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=18087522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direc
t.18087522
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.4245887274
Short name T771
Test name
Test status
Simulation time 5185014875 ps
CPU time 22.33 seconds
Started Jun 24 04:41:54 PM PDT 24
Finished Jun 24 04:42:26 PM PDT 24
Peak memory 216364 kb
Host smart-7cdd074e-e44a-4600-89af-068142b8d4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245887274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.4245887274
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2067554316
Short name T404
Test name
Test status
Simulation time 1534689368 ps
CPU time 4 seconds
Started Jun 24 04:41:58 PM PDT 24
Finished Jun 24 04:42:13 PM PDT 24
Peak memory 216560 kb
Host smart-e2d5854f-cfc7-4623-9a8c-69694fa3b6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067554316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2067554316
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.250389338
Short name T367
Test name
Test status
Simulation time 31726065 ps
CPU time 0.94 seconds
Started Jun 24 04:41:58 PM PDT 24
Finished Jun 24 04:42:09 PM PDT 24
Peak memory 206804 kb
Host smart-451420ff-0f31-4a0d-a2ba-e0f6df886522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250389338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.250389338
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1370026764
Short name T572
Test name
Test status
Simulation time 81318286 ps
CPU time 0.92 seconds
Started Jun 24 04:42:01 PM PDT 24
Finished Jun 24 04:42:12 PM PDT 24
Peak memory 205992 kb
Host smart-96bad4aa-d779-49c1-adb2-8993bd1a62f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370026764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1370026764
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.916039270
Short name T426
Test name
Test status
Simulation time 22628575415 ps
CPU time 21.02 seconds
Started Jun 24 04:41:56 PM PDT 24
Finished Jun 24 04:42:28 PM PDT 24
Peak memory 239816 kb
Host smart-2509d532-324d-401b-91db-739eb8ee769f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916039270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.916039270
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2721336228
Short name T331
Test name
Test status
Simulation time 11834062 ps
CPU time 0.72 seconds
Started Jun 24 04:42:04 PM PDT 24
Finished Jun 24 04:42:15 PM PDT 24
Peak memory 205316 kb
Host smart-91280f4d-a7bf-4879-b1e1-b7311ffd1287
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721336228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2721336228
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.153642456
Short name T829
Test name
Test status
Simulation time 541116891 ps
CPU time 6.71 seconds
Started Jun 24 04:42:06 PM PDT 24
Finished Jun 24 04:42:23 PM PDT 24
Peak memory 232760 kb
Host smart-201fdec0-1ef5-475a-b1fe-73b2485a80bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153642456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.153642456
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1785494405
Short name T330
Test name
Test status
Simulation time 21939742 ps
CPU time 0.8 seconds
Started Jun 24 04:42:01 PM PDT 24
Finished Jun 24 04:42:12 PM PDT 24
Peak memory 206552 kb
Host smart-dc943a8e-c599-4ce5-bfa2-226db591b5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785494405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1785494405
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1377902630
Short name T264
Test name
Test status
Simulation time 64599305981 ps
CPU time 78.59 seconds
Started Jun 24 04:42:03 PM PDT 24
Finished Jun 24 04:43:32 PM PDT 24
Peak memory 249540 kb
Host smart-f1844a7b-80a0-4d35-9252-51558e97f81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377902630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1377902630
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2253842902
Short name T283
Test name
Test status
Simulation time 15038509813 ps
CPU time 41.57 seconds
Started Jun 24 04:42:06 PM PDT 24
Finished Jun 24 04:42:57 PM PDT 24
Peak memory 249216 kb
Host smart-082cfca4-9668-4146-9d23-6b350b274110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253842902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2253842902
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3181250604
Short name T871
Test name
Test status
Simulation time 5621362558 ps
CPU time 26.53 seconds
Started Jun 24 04:42:05 PM PDT 24
Finished Jun 24 04:42:42 PM PDT 24
Peak memory 217528 kb
Host smart-4ffd2557-02ba-4ca6-828b-8653bbcbbb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181250604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3181250604
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.879714320
Short name T58
Test name
Test status
Simulation time 165494248 ps
CPU time 2.94 seconds
Started Jun 24 04:42:04 PM PDT 24
Finished Jun 24 04:42:17 PM PDT 24
Peak memory 224428 kb
Host smart-e7fdd19a-f1c4-4ca3-8a8e-17153ea4d0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879714320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.879714320
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1831928753
Short name T217
Test name
Test status
Simulation time 8414530383 ps
CPU time 20.76 seconds
Started Jun 24 04:42:02 PM PDT 24
Finished Jun 24 04:42:34 PM PDT 24
Peak memory 232804 kb
Host smart-cd9e2509-f070-4359-8c14-a2cbfa8f5881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831928753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1831928753
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1674029775
Short name T848
Test name
Test status
Simulation time 821429119 ps
CPU time 11.65 seconds
Started Jun 24 04:42:03 PM PDT 24
Finished Jun 24 04:42:25 PM PDT 24
Peak memory 224472 kb
Host smart-fce7c120-aa9f-4cb0-ac06-68407b1b2fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674029775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1674029775
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3493811897
Short name T733
Test name
Test status
Simulation time 4899803635 ps
CPU time 16.75 seconds
Started Jun 24 04:42:05 PM PDT 24
Finished Jun 24 04:42:33 PM PDT 24
Peak memory 232804 kb
Host smart-fb586d1d-54f4-483a-a7b8-9d76e8bc2b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493811897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3493811897
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.82883054
Short name T948
Test name
Test status
Simulation time 348263512 ps
CPU time 3.56 seconds
Started Jun 24 04:42:05 PM PDT 24
Finished Jun 24 04:42:19 PM PDT 24
Peak memory 234864 kb
Host smart-c192b79c-8e9b-4e90-a277-71336497cb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82883054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.82883054
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.683183917
Short name T43
Test name
Test status
Simulation time 491349689 ps
CPU time 4.68 seconds
Started Jun 24 04:42:02 PM PDT 24
Finished Jun 24 04:42:16 PM PDT 24
Peak memory 223080 kb
Host smart-bb58898f-9685-45f8-8f80-f54ef5723ac4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=683183917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.683183917
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.758363280
Short name T695
Test name
Test status
Simulation time 126815415 ps
CPU time 0.91 seconds
Started Jun 24 04:42:12 PM PDT 24
Finished Jun 24 04:42:24 PM PDT 24
Peak memory 206876 kb
Host smart-075aa809-01a8-43e1-b742-09d065a11568
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758363280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.758363280
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3038315175
Short name T894
Test name
Test status
Simulation time 22816592997 ps
CPU time 25.63 seconds
Started Jun 24 04:42:03 PM PDT 24
Finished Jun 24 04:42:39 PM PDT 24
Peak memory 216540 kb
Host smart-756b57d5-481c-4fa1-b1a6-1592c97ffbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038315175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3038315175
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1406010764
Short name T807
Test name
Test status
Simulation time 16610697245 ps
CPU time 14.62 seconds
Started Jun 24 04:42:04 PM PDT 24
Finished Jun 24 04:42:29 PM PDT 24
Peak memory 216348 kb
Host smart-c4f444e2-87e6-40b3-9b9f-ff847b6aeaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406010764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1406010764
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2620080272
Short name T750
Test name
Test status
Simulation time 28124244 ps
CPU time 1.11 seconds
Started Jun 24 04:42:05 PM PDT 24
Finished Jun 24 04:42:16 PM PDT 24
Peak memory 208284 kb
Host smart-e52a1cc1-40f7-415b-8300-29d870687254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620080272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2620080272
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3249579800
Short name T952
Test name
Test status
Simulation time 120470745 ps
CPU time 0.95 seconds
Started Jun 24 04:42:04 PM PDT 24
Finished Jun 24 04:42:15 PM PDT 24
Peak memory 205888 kb
Host smart-9f3f66c4-c7e8-43f3-8543-2ccd5870b47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249579800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3249579800
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3608936320
Short name T430
Test name
Test status
Simulation time 20033043822 ps
CPU time 16.25 seconds
Started Jun 24 04:42:03 PM PDT 24
Finished Jun 24 04:42:29 PM PDT 24
Peak memory 232832 kb
Host smart-6612eb37-ac1f-46e2-a335-9756c66e89d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608936320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3608936320
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.993452636
Short name T388
Test name
Test status
Simulation time 12125506 ps
CPU time 0.73 seconds
Started Jun 24 04:42:03 PM PDT 24
Finished Jun 24 04:42:14 PM PDT 24
Peak memory 205348 kb
Host smart-7055765c-7927-4353-a3a9-857c851e3011
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993452636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.993452636
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.94092589
Short name T477
Test name
Test status
Simulation time 340906253 ps
CPU time 4.8 seconds
Started Jun 24 04:42:04 PM PDT 24
Finished Jun 24 04:42:19 PM PDT 24
Peak memory 232720 kb
Host smart-a52c0c94-8401-403b-a817-d97b5066270c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94092589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.94092589
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3150625046
Short name T327
Test name
Test status
Simulation time 17262281 ps
CPU time 0.82 seconds
Started Jun 24 04:42:01 PM PDT 24
Finished Jun 24 04:42:12 PM PDT 24
Peak memory 206624 kb
Host smart-f3005bf8-836e-4430-a43d-5c6527bd6582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150625046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3150625046
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2597269971
Short name T436
Test name
Test status
Simulation time 1631118027 ps
CPU time 11.5 seconds
Started Jun 24 04:42:02 PM PDT 24
Finished Jun 24 04:42:23 PM PDT 24
Peak memory 224496 kb
Host smart-ce929794-1ae4-47be-822a-756ec82da076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597269971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2597269971
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3021888487
Short name T802
Test name
Test status
Simulation time 3269425354 ps
CPU time 61.78 seconds
Started Jun 24 04:42:05 PM PDT 24
Finished Jun 24 04:43:17 PM PDT 24
Peak memory 241068 kb
Host smart-34f3d15b-7f67-41fe-8fcd-098b3d2f6e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021888487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3021888487
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3345841296
Short name T294
Test name
Test status
Simulation time 118957658043 ps
CPU time 563.04 seconds
Started Jun 24 04:42:03 PM PDT 24
Finished Jun 24 04:51:38 PM PDT 24
Peak memory 263264 kb
Host smart-55107f96-4c8e-4904-a6be-bced630cf877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345841296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3345841296
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.884215913
Short name T700
Test name
Test status
Simulation time 485889841 ps
CPU time 4.05 seconds
Started Jun 24 04:42:04 PM PDT 24
Finished Jun 24 04:42:18 PM PDT 24
Peak memory 218788 kb
Host smart-43c90183-62e3-4224-8bc8-08c350ce37ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884215913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.884215913
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3902323268
Short name T813
Test name
Test status
Simulation time 10048493582 ps
CPU time 34.88 seconds
Started Jun 24 04:42:04 PM PDT 24
Finished Jun 24 04:42:49 PM PDT 24
Peak memory 219976 kb
Host smart-c112f328-f3aa-434b-a486-49f66fa21f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902323268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3902323268
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2349824782
Short name T456
Test name
Test status
Simulation time 8402058469 ps
CPU time 22.72 seconds
Started Jun 24 04:42:07 PM PDT 24
Finished Jun 24 04:42:39 PM PDT 24
Peak memory 236008 kb
Host smart-0518a361-f17d-45ad-b15f-3409175b3d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349824782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2349824782
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2680939990
Short name T328
Test name
Test status
Simulation time 32202405 ps
CPU time 2.18 seconds
Started Jun 24 04:42:02 PM PDT 24
Finished Jun 24 04:42:14 PM PDT 24
Peak memory 222688 kb
Host smart-893b27ec-35e9-4362-8c99-ad2707221f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680939990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2680939990
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2013436685
Short name T930
Test name
Test status
Simulation time 102106319 ps
CPU time 2.14 seconds
Started Jun 24 04:42:05 PM PDT 24
Finished Jun 24 04:42:18 PM PDT 24
Peak memory 222836 kb
Host smart-87e97a07-be80-4385-9393-767fdfac4398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013436685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2013436685
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2507537190
Short name T534
Test name
Test status
Simulation time 879699550 ps
CPU time 9.54 seconds
Started Jun 24 04:42:04 PM PDT 24
Finished Jun 24 04:42:24 PM PDT 24
Peak memory 222676 kb
Host smart-c95ccfd0-4858-4370-a6c5-3d77f8d77814
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2507537190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2507537190
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2571938994
Short name T21
Test name
Test status
Simulation time 3501673384 ps
CPU time 82.46 seconds
Started Jun 24 04:42:04 PM PDT 24
Finished Jun 24 04:43:37 PM PDT 24
Peak memory 253900 kb
Host smart-384a73ac-c6ab-4acc-9ab0-177ec0ec5f86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571938994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2571938994
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3576302830
Short name T660
Test name
Test status
Simulation time 5910335859 ps
CPU time 36.73 seconds
Started Jun 24 04:42:03 PM PDT 24
Finished Jun 24 04:42:50 PM PDT 24
Peak memory 216288 kb
Host smart-fefd67d4-317c-4fcb-b95c-17ca805f13a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576302830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3576302830
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2239071896
Short name T715
Test name
Test status
Simulation time 4606322290 ps
CPU time 5.32 seconds
Started Jun 24 04:42:05 PM PDT 24
Finished Jun 24 04:42:21 PM PDT 24
Peak memory 216436 kb
Host smart-f015ab8b-8e07-47d4-9027-f0fbb935572e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239071896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2239071896
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1578922117
Short name T815
Test name
Test status
Simulation time 35150506 ps
CPU time 0.82 seconds
Started Jun 24 04:42:05 PM PDT 24
Finished Jun 24 04:42:16 PM PDT 24
Peak memory 206288 kb
Host smart-025a630f-22af-4ad4-b44f-d1bf8ac43164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578922117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1578922117
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3231837016
Short name T348
Test name
Test status
Simulation time 262206309 ps
CPU time 1.02 seconds
Started Jun 24 04:42:06 PM PDT 24
Finished Jun 24 04:42:17 PM PDT 24
Peak memory 207016 kb
Host smart-7fcbdd22-7b92-4603-a76f-adcbf408a424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231837016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3231837016
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.36373948
Short name T227
Test name
Test status
Simulation time 2674827605 ps
CPU time 4.01 seconds
Started Jun 24 04:42:05 PM PDT 24
Finished Jun 24 04:42:19 PM PDT 24
Peak memory 232844 kb
Host smart-0c3ffc2b-8d3d-4c00-96e9-f96802b1ad22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36373948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.36373948
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1693517199
Short name T75
Test name
Test status
Simulation time 21393056 ps
CPU time 0.71 seconds
Started Jun 24 04:42:13 PM PDT 24
Finished Jun 24 04:42:24 PM PDT 24
Peak memory 204744 kb
Host smart-1e6e093f-a01b-492f-b4d8-7fe5617858de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693517199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1693517199
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1591445215
Short name T763
Test name
Test status
Simulation time 506008389 ps
CPU time 2.23 seconds
Started Jun 24 04:42:07 PM PDT 24
Finished Jun 24 04:42:19 PM PDT 24
Peak memory 224472 kb
Host smart-1fa89814-874a-4343-bc7a-7b59027c4d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591445215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1591445215
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3375925862
Short name T374
Test name
Test status
Simulation time 23487597 ps
CPU time 0.84 seconds
Started Jun 24 04:42:09 PM PDT 24
Finished Jun 24 04:42:21 PM PDT 24
Peak memory 206548 kb
Host smart-6a8a2e01-9223-42be-a0ad-3c9d9f50ce5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375925862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3375925862
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1026051602
Short name T942
Test name
Test status
Simulation time 195035098 ps
CPU time 4.83 seconds
Started Jun 24 04:42:14 PM PDT 24
Finished Jun 24 04:42:29 PM PDT 24
Peak memory 236232 kb
Host smart-d975780c-01d7-45fb-a389-dff80dc065c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026051602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1026051602
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1189697975
Short name T670
Test name
Test status
Simulation time 24277915 ps
CPU time 0.85 seconds
Started Jun 24 04:42:12 PM PDT 24
Finished Jun 24 04:42:23 PM PDT 24
Peak memory 217752 kb
Host smart-264182b5-a189-43ed-af26-935f319f58cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189697975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1189697975
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2046253107
Short name T22
Test name
Test status
Simulation time 20861830372 ps
CPU time 172.05 seconds
Started Jun 24 04:42:14 PM PDT 24
Finished Jun 24 04:45:16 PM PDT 24
Peak memory 251792 kb
Host smart-4eba0424-f4d6-4645-8f71-797da35a8904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046253107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2046253107
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.403117339
Short name T690
Test name
Test status
Simulation time 1125118087 ps
CPU time 6.86 seconds
Started Jun 24 04:42:10 PM PDT 24
Finished Jun 24 04:42:26 PM PDT 24
Peak memory 232704 kb
Host smart-62a22fe9-55c3-48ab-a83b-bb224950f761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403117339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.403117339
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1366509026
Short name T172
Test name
Test status
Simulation time 790762263 ps
CPU time 7.55 seconds
Started Jun 24 04:42:14 PM PDT 24
Finished Jun 24 04:42:32 PM PDT 24
Peak memory 232716 kb
Host smart-a2a5358f-a87e-4660-851f-fce6eb6256ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366509026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1366509026
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2977814217
Short name T603
Test name
Test status
Simulation time 10977190734 ps
CPU time 36.03 seconds
Started Jun 24 04:42:15 PM PDT 24
Finished Jun 24 04:43:01 PM PDT 24
Peak memory 241008 kb
Host smart-3a48188c-2d9e-436a-b428-48e164727605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977814217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2977814217
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1429339240
Short name T718
Test name
Test status
Simulation time 61014572 ps
CPU time 2.47 seconds
Started Jun 24 04:42:15 PM PDT 24
Finished Jun 24 04:42:28 PM PDT 24
Peak memory 232416 kb
Host smart-6bc0b0ac-5c21-433d-9df5-caaadcee3819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429339240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1429339240
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2610805954
Short name T240
Test name
Test status
Simulation time 8617773776 ps
CPU time 8.28 seconds
Started Jun 24 04:42:13 PM PDT 24
Finished Jun 24 04:42:32 PM PDT 24
Peak memory 240960 kb
Host smart-3dd0f78a-17f1-4cc7-acd4-bd2c8526c3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610805954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2610805954
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3128084882
Short name T613
Test name
Test status
Simulation time 291310548 ps
CPU time 3.85 seconds
Started Jun 24 04:42:09 PM PDT 24
Finished Jun 24 04:42:23 PM PDT 24
Peak memory 222808 kb
Host smart-75db8d1c-ff63-436a-bff9-9943d473b62c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3128084882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3128084882
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3619492352
Short name T318
Test name
Test status
Simulation time 39918385875 ps
CPU time 26.02 seconds
Started Jun 24 04:42:09 PM PDT 24
Finished Jun 24 04:42:46 PM PDT 24
Peak memory 216484 kb
Host smart-749e7d8a-18a3-43c6-beac-61f84da7c487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619492352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3619492352
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2556673833
Short name T624
Test name
Test status
Simulation time 32680994854 ps
CPU time 21.94 seconds
Started Jun 24 04:42:10 PM PDT 24
Finished Jun 24 04:42:43 PM PDT 24
Peak memory 217600 kb
Host smart-ef7fd891-0599-492c-9b7a-c45020fdf9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556673833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2556673833
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3200994169
Short name T368
Test name
Test status
Simulation time 104319612 ps
CPU time 1.84 seconds
Started Jun 24 04:42:08 PM PDT 24
Finished Jun 24 04:42:20 PM PDT 24
Peak memory 216260 kb
Host smart-52910d5e-6997-4129-a5ea-a90060c90008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200994169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3200994169
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.795407603
Short name T588
Test name
Test status
Simulation time 11389336 ps
CPU time 0.7 seconds
Started Jun 24 04:42:11 PM PDT 24
Finished Jun 24 04:42:22 PM PDT 24
Peak memory 205512 kb
Host smart-5c51058e-23dc-4164-aed1-239f8e943067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795407603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.795407603
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2116300327
Short name T747
Test name
Test status
Simulation time 1584065346 ps
CPU time 8.4 seconds
Started Jun 24 04:42:14 PM PDT 24
Finished Jun 24 04:42:33 PM PDT 24
Peak memory 224596 kb
Host smart-79aba385-498b-4817-ac57-b99560a1241c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116300327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2116300327
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.4194989065
Short name T338
Test name
Test status
Simulation time 19407868 ps
CPU time 0.72 seconds
Started Jun 24 04:42:10 PM PDT 24
Finished Jun 24 04:42:21 PM PDT 24
Peak memory 205688 kb
Host smart-619d14c7-1e84-4b72-8772-119a541ec1b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194989065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
4194989065
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2567136849
Short name T517
Test name
Test status
Simulation time 3786244784 ps
CPU time 10.4 seconds
Started Jun 24 04:42:12 PM PDT 24
Finished Jun 24 04:42:33 PM PDT 24
Peak memory 224648 kb
Host smart-8ff6a4b8-0342-4440-a120-f433b4ab94b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567136849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2567136849
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.339159303
Short name T532
Test name
Test status
Simulation time 13583685 ps
CPU time 0.74 seconds
Started Jun 24 04:42:12 PM PDT 24
Finished Jun 24 04:42:24 PM PDT 24
Peak memory 205864 kb
Host smart-680c3114-cfc5-43fc-ae26-1e842f572fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339159303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.339159303
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2179810268
Short name T47
Test name
Test status
Simulation time 14751959988 ps
CPU time 112.66 seconds
Started Jun 24 04:42:15 PM PDT 24
Finished Jun 24 04:44:18 PM PDT 24
Peak memory 250316 kb
Host smart-dad9e0ce-22dc-48f6-ab64-45b40f2abd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179810268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2179810268
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3990495261
Short name T925
Test name
Test status
Simulation time 6923174718 ps
CPU time 64.96 seconds
Started Jun 24 04:42:11 PM PDT 24
Finished Jun 24 04:43:26 PM PDT 24
Peak memory 257212 kb
Host smart-3fb91c0e-a039-4609-86d4-5868169eecfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990495261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3990495261
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1824769640
Short name T705
Test name
Test status
Simulation time 11439418853 ps
CPU time 125.38 seconds
Started Jun 24 04:42:09 PM PDT 24
Finished Jun 24 04:44:24 PM PDT 24
Peak memory 252272 kb
Host smart-1224bd82-903e-4b64-869f-8c5833bf4bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824769640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1824769640
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3421168320
Short name T483
Test name
Test status
Simulation time 2757610025 ps
CPU time 32.73 seconds
Started Jun 24 04:42:08 PM PDT 24
Finished Jun 24 04:42:51 PM PDT 24
Peak memory 224548 kb
Host smart-88d20f16-827f-45bb-9c99-6436bf9bc255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421168320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3421168320
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.356242383
Short name T421
Test name
Test status
Simulation time 821192704 ps
CPU time 3.18 seconds
Started Jun 24 04:42:11 PM PDT 24
Finished Jun 24 04:42:25 PM PDT 24
Peak memory 224508 kb
Host smart-3314b76e-455a-403d-8b38-aecd6d517a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356242383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.356242383
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1947690140
Short name T879
Test name
Test status
Simulation time 1282600748 ps
CPU time 17.25 seconds
Started Jun 24 04:42:14 PM PDT 24
Finished Jun 24 04:42:42 PM PDT 24
Peak memory 232656 kb
Host smart-9626ce37-8ee4-4575-b32a-5f7a88280c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947690140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1947690140
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1687246925
Short name T662
Test name
Test status
Simulation time 146710119 ps
CPU time 3.22 seconds
Started Jun 24 04:42:11 PM PDT 24
Finished Jun 24 04:42:25 PM PDT 24
Peak memory 232728 kb
Host smart-da448d13-d7c2-4775-bc5a-06d4b027b068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687246925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1687246925
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2332127827
Short name T518
Test name
Test status
Simulation time 19014828420 ps
CPU time 8.78 seconds
Started Jun 24 04:42:09 PM PDT 24
Finished Jun 24 04:42:28 PM PDT 24
Peak memory 224624 kb
Host smart-d7d9c984-6dd3-4a7d-8bc1-6b1a2b6ffc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332127827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2332127827
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2810372433
Short name T853
Test name
Test status
Simulation time 90920636 ps
CPU time 4.13 seconds
Started Jun 24 04:42:08 PM PDT 24
Finished Jun 24 04:42:22 PM PDT 24
Peak memory 222572 kb
Host smart-9eded4dc-626c-44a0-b190-0055e86827a8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2810372433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2810372433
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2002885032
Short name T467
Test name
Test status
Simulation time 133111960316 ps
CPU time 340.48 seconds
Started Jun 24 04:42:11 PM PDT 24
Finished Jun 24 04:48:02 PM PDT 24
Peak memory 257016 kb
Host smart-699e5b7b-4eb6-472f-91cc-549822fdd497
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002885032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2002885032
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1446270035
Short name T324
Test name
Test status
Simulation time 10731266059 ps
CPU time 11.45 seconds
Started Jun 24 04:42:15 PM PDT 24
Finished Jun 24 04:42:36 PM PDT 24
Peak memory 216344 kb
Host smart-cfe0cfd0-27c0-48a4-a977-a8aab15a0386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446270035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1446270035
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3030621137
Short name T764
Test name
Test status
Simulation time 3070380137 ps
CPU time 6.58 seconds
Started Jun 24 04:42:15 PM PDT 24
Finished Jun 24 04:42:31 PM PDT 24
Peak memory 216400 kb
Host smart-6597d65a-8c47-41fe-92df-0a34bb69212c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030621137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3030621137
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1889024525
Short name T36
Test name
Test status
Simulation time 19662859 ps
CPU time 0.77 seconds
Started Jun 24 04:42:10 PM PDT 24
Finished Jun 24 04:42:21 PM PDT 24
Peak memory 205948 kb
Host smart-20644698-f818-4feb-9bb0-4fde1db85a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889024525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1889024525
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3330891037
Short name T463
Test name
Test status
Simulation time 16730123 ps
CPU time 0.74 seconds
Started Jun 24 04:42:12 PM PDT 24
Finished Jun 24 04:42:23 PM PDT 24
Peak memory 205928 kb
Host smart-3c0e3d2c-d643-4cdc-b741-9e062d26c11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330891037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3330891037
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.426205493
Short name T841
Test name
Test status
Simulation time 1120102040 ps
CPU time 4.99 seconds
Started Jun 24 04:42:12 PM PDT 24
Finished Jun 24 04:42:27 PM PDT 24
Peak memory 224476 kb
Host smart-cfc6aedc-bb69-42b9-b19a-88ffb76bbbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426205493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.426205493
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2007311446
Short name T460
Test name
Test status
Simulation time 13203166 ps
CPU time 0.7 seconds
Started Jun 24 04:42:17 PM PDT 24
Finished Jun 24 04:42:28 PM PDT 24
Peak memory 205432 kb
Host smart-e566c32d-234f-45e1-9aca-50492ddd63d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007311446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2007311446
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.129971927
Short name T3
Test name
Test status
Simulation time 232289089 ps
CPU time 3.51 seconds
Started Jun 24 04:42:14 PM PDT 24
Finished Jun 24 04:42:28 PM PDT 24
Peak memory 232792 kb
Host smart-67d3ecd3-f185-43c1-bb96-900916f8afe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129971927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.129971927
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2540523068
Short name T617
Test name
Test status
Simulation time 13633391 ps
CPU time 0.81 seconds
Started Jun 24 04:42:14 PM PDT 24
Finished Jun 24 04:42:25 PM PDT 24
Peak memory 206564 kb
Host smart-5209ca1a-18d8-4f66-8b4a-6d0f69425d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540523068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2540523068
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.173081149
Short name T734
Test name
Test status
Simulation time 51880953232 ps
CPU time 184.11 seconds
Started Jun 24 04:42:14 PM PDT 24
Finished Jun 24 04:45:28 PM PDT 24
Peak memory 249196 kb
Host smart-219abf91-03af-4110-99aa-05fa0a7e8217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173081149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.173081149
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2833594498
Short name T232
Test name
Test status
Simulation time 26372854712 ps
CPU time 268.64 seconds
Started Jun 24 04:42:19 PM PDT 24
Finished Jun 24 04:46:59 PM PDT 24
Peak memory 256812 kb
Host smart-775db597-852b-4655-98fb-a16f0cb78cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833594498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2833594498
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.4173043662
Short name T535
Test name
Test status
Simulation time 21350603014 ps
CPU time 173.81 seconds
Started Jun 24 04:42:10 PM PDT 24
Finished Jun 24 04:45:15 PM PDT 24
Peak memory 251320 kb
Host smart-bf8bc016-8be4-451c-aa58-96c9d9e7fddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173043662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.4173043662
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.4087012485
Short name T346
Test name
Test status
Simulation time 618380209 ps
CPU time 10.76 seconds
Started Jun 24 04:42:14 PM PDT 24
Finished Jun 24 04:42:35 PM PDT 24
Peak memory 233708 kb
Host smart-c1c4a99f-c2d6-433e-bf14-abb4c4fa416e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087012485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.4087012485
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2628334343
Short name T816
Test name
Test status
Simulation time 9398456106 ps
CPU time 20.97 seconds
Started Jun 24 04:42:10 PM PDT 24
Finished Jun 24 04:42:41 PM PDT 24
Peak memory 232808 kb
Host smart-d847506e-1147-446c-b1c2-da58247929b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628334343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2628334343
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.4280980212
Short name T944
Test name
Test status
Simulation time 62155408558 ps
CPU time 62.52 seconds
Started Jun 24 04:42:09 PM PDT 24
Finished Jun 24 04:43:21 PM PDT 24
Peak memory 232804 kb
Host smart-42ca0f4c-9453-4314-bc03-7accf05f26f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280980212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4280980212
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.422029105
Short name T27
Test name
Test status
Simulation time 325814694 ps
CPU time 3.04 seconds
Started Jun 24 04:42:11 PM PDT 24
Finished Jun 24 04:42:25 PM PDT 24
Peak memory 232748 kb
Host smart-2756fa81-082c-43a8-af8b-a800d5571188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422029105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.422029105
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3114622860
Short name T454
Test name
Test status
Simulation time 2344793739 ps
CPU time 7.9 seconds
Started Jun 24 04:42:14 PM PDT 24
Finished Jun 24 04:42:32 PM PDT 24
Peak memory 232776 kb
Host smart-cef2d9df-a2ec-473f-851d-0a00275e5643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114622860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3114622860
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3020032902
Short name T887
Test name
Test status
Simulation time 12467860413 ps
CPU time 12.3 seconds
Started Jun 24 04:42:17 PM PDT 24
Finished Jun 24 04:42:40 PM PDT 24
Peak memory 223160 kb
Host smart-35541b21-7d77-44d3-8951-a86b7a9b7bf7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3020032902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3020032902
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.855674903
Short name T773
Test name
Test status
Simulation time 70903047700 ps
CPU time 286.12 seconds
Started Jun 24 04:42:15 PM PDT 24
Finished Jun 24 04:47:11 PM PDT 24
Peak memory 272892 kb
Host smart-540c729a-5110-4d90-9774-311794d69495
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855674903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.855674903
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.871304927
Short name T425
Test name
Test status
Simulation time 6576888055 ps
CPU time 17.01 seconds
Started Jun 24 04:42:12 PM PDT 24
Finished Jun 24 04:42:40 PM PDT 24
Peak memory 216416 kb
Host smart-ba850d4f-b812-4d1f-a65f-f299ec4031cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871304927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.871304927
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3713221922
Short name T362
Test name
Test status
Simulation time 822916247 ps
CPU time 5.9 seconds
Started Jun 24 04:42:11 PM PDT 24
Finished Jun 24 04:42:27 PM PDT 24
Peak memory 216260 kb
Host smart-e3ff66a3-2869-41f6-9e26-601a881fcac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713221922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3713221922
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3422422345
Short name T851
Test name
Test status
Simulation time 924820555 ps
CPU time 5.48 seconds
Started Jun 24 04:42:08 PM PDT 24
Finished Jun 24 04:42:24 PM PDT 24
Peak memory 216192 kb
Host smart-c805eaf6-92ca-4388-9b3c-f23c579f4fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422422345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3422422345
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.590901368
Short name T779
Test name
Test status
Simulation time 270072527 ps
CPU time 0.91 seconds
Started Jun 24 04:42:10 PM PDT 24
Finished Jun 24 04:42:21 PM PDT 24
Peak memory 206956 kb
Host smart-bd352b2a-7b0d-4034-9cb9-35a657d6df51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590901368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.590901368
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.502149567
Short name T479
Test name
Test status
Simulation time 508865998 ps
CPU time 5.46 seconds
Started Jun 24 04:42:14 PM PDT 24
Finished Jun 24 04:42:30 PM PDT 24
Peak memory 232752 kb
Host smart-1a5ceb51-eaf9-4ab8-a05e-96a6e437dd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502149567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.502149567
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.703057736
Short name T677
Test name
Test status
Simulation time 12381928 ps
CPU time 0.71 seconds
Started Jun 24 04:40:37 PM PDT 24
Finished Jun 24 04:40:45 PM PDT 24
Peak memory 205728 kb
Host smart-1b1cb5ef-b00d-45cc-82f4-309af281cd89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703057736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.703057736
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3586549464
Short name T767
Test name
Test status
Simulation time 31493987 ps
CPU time 2.59 seconds
Started Jun 24 04:40:34 PM PDT 24
Finished Jun 24 04:40:46 PM PDT 24
Peak memory 232372 kb
Host smart-8668d41c-b0a2-4ce5-9380-50d6cbc360fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586549464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3586549464
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.4124958381
Short name T439
Test name
Test status
Simulation time 43066416 ps
CPU time 0.78 seconds
Started Jun 24 04:40:36 PM PDT 24
Finished Jun 24 04:40:45 PM PDT 24
Peak memory 205532 kb
Host smart-ef056e94-4b3b-4b66-96b2-ef0f334d5d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124958381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.4124958381
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3039646509
Short name T282
Test name
Test status
Simulation time 27964905845 ps
CPU time 261.9 seconds
Started Jun 24 04:40:34 PM PDT 24
Finished Jun 24 04:45:05 PM PDT 24
Peak memory 257424 kb
Host smart-e236a064-f200-4947-835f-c002ebdc0e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039646509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3039646509
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.4277096170
Short name T611
Test name
Test status
Simulation time 6499145244 ps
CPU time 27.73 seconds
Started Jun 24 04:40:37 PM PDT 24
Finished Jun 24 04:41:12 PM PDT 24
Peak memory 232836 kb
Host smart-fbdae67f-e0f6-4a4b-84a6-77a6d4f2a19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277096170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.4277096170
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1583080167
Short name T516
Test name
Test status
Simulation time 30784497 ps
CPU time 2.63 seconds
Started Jun 24 04:40:38 PM PDT 24
Finished Jun 24 04:40:47 PM PDT 24
Peak memory 232392 kb
Host smart-476aed05-ba44-499f-818c-7ad13a038bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583080167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1583080167
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.513568659
Short name T912
Test name
Test status
Simulation time 2136134889 ps
CPU time 15.1 seconds
Started Jun 24 04:40:35 PM PDT 24
Finished Jun 24 04:40:59 PM PDT 24
Peak memory 240900 kb
Host smart-cab8daa0-235e-47c7-91a8-9ea99fb84ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513568659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.513568659
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.4012718416
Short name T301
Test name
Test status
Simulation time 302933193 ps
CPU time 3.27 seconds
Started Jun 24 04:40:36 PM PDT 24
Finished Jun 24 04:40:48 PM PDT 24
Peak memory 232648 kb
Host smart-c1a9acfc-291d-4b7e-8178-909c85be89b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012718416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.4012718416
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2274017975
Short name T238
Test name
Test status
Simulation time 50931711860 ps
CPU time 22.57 seconds
Started Jun 24 04:40:35 PM PDT 24
Finished Jun 24 04:41:06 PM PDT 24
Peak memory 232772 kb
Host smart-f1346f8b-67cb-42f6-8042-b41f43c3af89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274017975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2274017975
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1509894606
Short name T387
Test name
Test status
Simulation time 1535260783 ps
CPU time 9.35 seconds
Started Jun 24 04:40:38 PM PDT 24
Finished Jun 24 04:40:54 PM PDT 24
Peak memory 223096 kb
Host smart-723db1bb-fe19-402c-b41e-3e0839a3939f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1509894606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1509894606
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2107675220
Short name T70
Test name
Test status
Simulation time 1133829068 ps
CPU time 1.1 seconds
Started Jun 24 04:40:36 PM PDT 24
Finished Jun 24 04:40:45 PM PDT 24
Peak memory 234744 kb
Host smart-19b0abe0-4342-4486-a984-cd9d87656442
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107675220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2107675220
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3583774093
Short name T28
Test name
Test status
Simulation time 4455913585 ps
CPU time 20.68 seconds
Started Jun 24 04:40:35 PM PDT 24
Finished Jun 24 04:41:05 PM PDT 24
Peak memory 216388 kb
Host smart-12e3b547-e78c-49b7-8c35-8221645617d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583774093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3583774093
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3940046334
Short name T359
Test name
Test status
Simulation time 238738159 ps
CPU time 1.39 seconds
Started Jun 24 04:40:39 PM PDT 24
Finished Jun 24 04:40:46 PM PDT 24
Peak memory 207264 kb
Host smart-829c847f-4c87-4d9c-9c3c-d6808a8c11c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940046334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3940046334
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1709707481
Short name T745
Test name
Test status
Simulation time 242236837 ps
CPU time 2.86 seconds
Started Jun 24 04:40:34 PM PDT 24
Finished Jun 24 04:40:46 PM PDT 24
Peak memory 216172 kb
Host smart-888ed463-bdda-4d5f-a6c4-7866851483bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709707481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1709707481
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3583253065
Short name T410
Test name
Test status
Simulation time 73460689 ps
CPU time 0.97 seconds
Started Jun 24 04:40:36 PM PDT 24
Finished Jun 24 04:40:45 PM PDT 24
Peak memory 207328 kb
Host smart-16222ef9-30d0-4f2d-91bf-ccdf8ce36b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583253065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3583253065
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3992998615
Short name T937
Test name
Test status
Simulation time 1833857665 ps
CPU time 6.48 seconds
Started Jun 24 04:40:39 PM PDT 24
Finished Jun 24 04:40:52 PM PDT 24
Peak memory 232676 kb
Host smart-bf6d85d0-62ed-46b3-8e59-60b7f94eb8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992998615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3992998615
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.540134957
Short name T448
Test name
Test status
Simulation time 20291480 ps
CPU time 0.72 seconds
Started Jun 24 04:42:17 PM PDT 24
Finished Jun 24 04:42:29 PM PDT 24
Peak memory 205652 kb
Host smart-f3b6cbd7-33ae-439e-a993-0cf2298e0492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540134957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.540134957
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2403619781
Short name T537
Test name
Test status
Simulation time 1095279638 ps
CPU time 8.08 seconds
Started Jun 24 04:42:18 PM PDT 24
Finished Jun 24 04:42:37 PM PDT 24
Peak memory 232636 kb
Host smart-526e005b-bb7c-4cda-85fa-2d30138df34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403619781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2403619781
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1575493681
Short name T451
Test name
Test status
Simulation time 17021668 ps
CPU time 0.77 seconds
Started Jun 24 04:42:19 PM PDT 24
Finished Jun 24 04:42:31 PM PDT 24
Peak memory 205544 kb
Host smart-0409ebae-bb00-448d-b1dd-879bff6485f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575493681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1575493681
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.330725152
Short name T762
Test name
Test status
Simulation time 2700868714 ps
CPU time 50.49 seconds
Started Jun 24 04:42:17 PM PDT 24
Finished Jun 24 04:43:18 PM PDT 24
Peak memory 252516 kb
Host smart-18d640c0-98e2-4233-933c-d6bdba646601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330725152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.330725152
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1096413189
Short name T959
Test name
Test status
Simulation time 6723120057 ps
CPU time 27.95 seconds
Started Jun 24 04:42:15 PM PDT 24
Finished Jun 24 04:42:53 PM PDT 24
Peak memory 237628 kb
Host smart-3cf1a738-53a7-4e6b-b3a1-98fbe4685338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096413189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1096413189
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.429765249
Short name T317
Test name
Test status
Simulation time 14746139217 ps
CPU time 138.87 seconds
Started Jun 24 04:42:16 PM PDT 24
Finished Jun 24 04:44:45 PM PDT 24
Peak memory 249260 kb
Host smart-18799414-2732-4dd3-a5ef-cfff1e6559df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429765249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.429765249
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.4236646438
Short name T372
Test name
Test status
Simulation time 784755241 ps
CPU time 10.31 seconds
Started Jun 24 04:42:19 PM PDT 24
Finished Jun 24 04:42:41 PM PDT 24
Peak memory 232680 kb
Host smart-f5732b14-2c5a-4c81-a535-7f03d193c18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236646438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.4236646438
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2931792740
Short name T176
Test name
Test status
Simulation time 2958116509 ps
CPU time 8.7 seconds
Started Jun 24 04:42:17 PM PDT 24
Finished Jun 24 04:42:36 PM PDT 24
Peak memory 232756 kb
Host smart-a7aec8c6-6b30-445c-b1a2-78623c7fee3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931792740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2931792740
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1749075849
Short name T817
Test name
Test status
Simulation time 19312191874 ps
CPU time 35.53 seconds
Started Jun 24 04:42:17 PM PDT 24
Finished Jun 24 04:43:03 PM PDT 24
Peak memory 240608 kb
Host smart-6c3f89b3-1109-49c6-8596-92698a0e6d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749075849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1749075849
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.36672600
Short name T237
Test name
Test status
Simulation time 10203094563 ps
CPU time 13.3 seconds
Started Jun 24 04:42:16 PM PDT 24
Finished Jun 24 04:42:41 PM PDT 24
Peak memory 224628 kb
Host smart-75e27542-6585-4057-b790-44f2d9f00b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36672600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.36672600
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.4066220714
Short name T354
Test name
Test status
Simulation time 8478698147 ps
CPU time 8.64 seconds
Started Jun 24 04:42:18 PM PDT 24
Finished Jun 24 04:42:38 PM PDT 24
Peak memory 240948 kb
Host smart-17bd4731-2a06-4a08-ad61-6adb23b05229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066220714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4066220714
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3307756981
Short name T472
Test name
Test status
Simulation time 836151107 ps
CPU time 4.31 seconds
Started Jun 24 04:42:17 PM PDT 24
Finished Jun 24 04:42:33 PM PDT 24
Peak memory 223192 kb
Host smart-aeb1e1c4-9ca7-4a2f-9be7-0c831521b8f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3307756981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3307756981
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.463799314
Short name T168
Test name
Test status
Simulation time 75282526 ps
CPU time 1.16 seconds
Started Jun 24 04:42:16 PM PDT 24
Finished Jun 24 04:42:27 PM PDT 24
Peak memory 207616 kb
Host smart-9e2e49a9-5e18-4fba-b828-08be5afadd60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463799314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.463799314
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3881967002
Short name T538
Test name
Test status
Simulation time 1605367314 ps
CPU time 21.42 seconds
Started Jun 24 04:42:26 PM PDT 24
Finished Jun 24 04:42:58 PM PDT 24
Peak memory 216316 kb
Host smart-6104da9f-9db9-45b2-b24e-4d72b2f0bb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881967002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3881967002
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3956420729
Short name T335
Test name
Test status
Simulation time 2991370670 ps
CPU time 8.46 seconds
Started Jun 24 04:42:17 PM PDT 24
Finished Jun 24 04:42:36 PM PDT 24
Peak memory 216364 kb
Host smart-40834cff-8aef-4add-958a-d0e1e5918e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956420729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3956420729
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3701911080
Short name T645
Test name
Test status
Simulation time 24504336 ps
CPU time 1.42 seconds
Started Jun 24 04:42:19 PM PDT 24
Finished Jun 24 04:42:32 PM PDT 24
Peak memory 216332 kb
Host smart-33519e36-6259-4802-93f3-f36da944f01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701911080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3701911080
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2457926747
Short name T504
Test name
Test status
Simulation time 164989602 ps
CPU time 0.91 seconds
Started Jun 24 04:42:26 PM PDT 24
Finished Jun 24 04:42:38 PM PDT 24
Peak memory 205904 kb
Host smart-8d3af1a8-0ac8-4676-9d9e-8ef8af13ff56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457926747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2457926747
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2321971561
Short name T574
Test name
Test status
Simulation time 17000273227 ps
CPU time 14.06 seconds
Started Jun 24 04:42:18 PM PDT 24
Finished Jun 24 04:42:43 PM PDT 24
Peak memory 224588 kb
Host smart-02dd9b1e-4d66-4948-bfa3-81cf586df00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321971561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2321971561
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1334634854
Short name T789
Test name
Test status
Simulation time 15002843 ps
CPU time 0.71 seconds
Started Jun 24 04:42:26 PM PDT 24
Finished Jun 24 04:42:38 PM PDT 24
Peak memory 205296 kb
Host smart-9d46e3ba-edb7-4cf6-9ced-07256e5522d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334634854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1334634854
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1805333833
Short name T494
Test name
Test status
Simulation time 677617903 ps
CPU time 8.8 seconds
Started Jun 24 04:42:18 PM PDT 24
Finished Jun 24 04:42:38 PM PDT 24
Peak memory 224392 kb
Host smart-02c94629-eca0-4be0-8c83-64790474cdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805333833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1805333833
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3722353910
Short name T552
Test name
Test status
Simulation time 82729039 ps
CPU time 0.83 seconds
Started Jun 24 04:42:16 PM PDT 24
Finished Jun 24 04:42:28 PM PDT 24
Peak memory 206584 kb
Host smart-0d3745e8-77b2-4a58-88b8-4997119ab4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722353910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3722353910
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.421944128
Short name T244
Test name
Test status
Simulation time 460403081 ps
CPU time 6.7 seconds
Started Jun 24 04:42:26 PM PDT 24
Finished Jun 24 04:42:44 PM PDT 24
Peak memory 224428 kb
Host smart-acff6f32-7520-4cf0-9435-11538e0d9d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421944128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.421944128
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.343996587
Short name T241
Test name
Test status
Simulation time 2476992638 ps
CPU time 23.41 seconds
Started Jun 24 04:42:26 PM PDT 24
Finished Jun 24 04:43:00 PM PDT 24
Peak memory 241048 kb
Host smart-c5c3ab25-b1dd-4201-a366-a8b7aa309150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343996587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.343996587
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2788555030
Short name T314
Test name
Test status
Simulation time 208982149 ps
CPU time 8.54 seconds
Started Jun 24 04:42:19 PM PDT 24
Finished Jun 24 04:42:39 PM PDT 24
Peak memory 248752 kb
Host smart-784143df-dbe5-4431-9b44-f97bb2a554e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788555030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2788555030
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2880147014
Short name T916
Test name
Test status
Simulation time 3140292255 ps
CPU time 12.55 seconds
Started Jun 24 04:42:18 PM PDT 24
Finished Jun 24 04:42:42 PM PDT 24
Peak memory 228096 kb
Host smart-3e0a847a-f098-4679-a642-5775a42adfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880147014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2880147014
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.350421777
Short name T726
Test name
Test status
Simulation time 415805493 ps
CPU time 3.45 seconds
Started Jun 24 04:42:16 PM PDT 24
Finished Jun 24 04:42:30 PM PDT 24
Peak memory 224472 kb
Host smart-6b3c844f-3946-4184-9c26-380e4d7c25d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350421777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.350421777
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1791580444
Short name T755
Test name
Test status
Simulation time 3320741409 ps
CPU time 10.63 seconds
Started Jun 24 04:42:15 PM PDT 24
Finished Jun 24 04:42:35 PM PDT 24
Peak memory 232788 kb
Host smart-020482fa-3d1e-40a4-b8a7-70c0fb792632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791580444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1791580444
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1776164290
Short name T806
Test name
Test status
Simulation time 5727935017 ps
CPU time 19.45 seconds
Started Jun 24 04:42:20 PM PDT 24
Finished Jun 24 04:42:50 PM PDT 24
Peak memory 232768 kb
Host smart-ed368ba7-ccd7-4e71-b067-8a9e686064a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776164290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1776164290
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.15592183
Short name T657
Test name
Test status
Simulation time 1943102759 ps
CPU time 7.21 seconds
Started Jun 24 04:42:18 PM PDT 24
Finished Jun 24 04:42:37 PM PDT 24
Peak memory 221624 kb
Host smart-a4f60f53-4b90-4058-be23-cffdbdf2df97
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=15592183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direc
t.15592183
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1139028822
Short name T326
Test name
Test status
Simulation time 16265638638 ps
CPU time 30.41 seconds
Started Jun 24 04:42:17 PM PDT 24
Finished Jun 24 04:42:59 PM PDT 24
Peak memory 216660 kb
Host smart-11d8c43d-76dc-4853-9dd5-dc741b32d590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139028822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1139028822
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3535964773
Short name T369
Test name
Test status
Simulation time 7581846160 ps
CPU time 6.78 seconds
Started Jun 24 04:42:16 PM PDT 24
Finished Jun 24 04:42:32 PM PDT 24
Peak memory 216316 kb
Host smart-2f0ff31a-ce61-4af9-ad2f-a6b8eca87a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535964773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3535964773
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3848122346
Short name T643
Test name
Test status
Simulation time 58069734 ps
CPU time 1.36 seconds
Started Jun 24 04:42:17 PM PDT 24
Finished Jun 24 04:42:29 PM PDT 24
Peak memory 208012 kb
Host smart-c622f4a6-973e-4884-a3ca-74c141d137c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848122346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3848122346
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3613944378
Short name T931
Test name
Test status
Simulation time 95804946 ps
CPU time 0.99 seconds
Started Jun 24 04:42:17 PM PDT 24
Finished Jun 24 04:42:29 PM PDT 24
Peak memory 206224 kb
Host smart-6f220abd-dd87-4d80-9efa-a488124083c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613944378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3613944378
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.940781408
Short name T746
Test name
Test status
Simulation time 1897587030 ps
CPU time 5.82 seconds
Started Jun 24 04:42:16 PM PDT 24
Finished Jun 24 04:42:32 PM PDT 24
Peak memory 224448 kb
Host smart-6ba3dbb5-2910-46b0-b7b0-711e2cfb66ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940781408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.940781408
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.222615913
Short name T698
Test name
Test status
Simulation time 11126547 ps
CPU time 0.74 seconds
Started Jun 24 04:42:25 PM PDT 24
Finished Jun 24 04:42:37 PM PDT 24
Peak memory 205336 kb
Host smart-84a357c7-a456-4d67-b1d7-d10955c3f9df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222615913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.222615913
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3079514197
Short name T722
Test name
Test status
Simulation time 107659333 ps
CPU time 3.2 seconds
Started Jun 24 04:42:26 PM PDT 24
Finished Jun 24 04:42:40 PM PDT 24
Peak memory 224444 kb
Host smart-43141d2a-3e26-4da2-b26f-94764e09f52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079514197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3079514197
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.184004635
Short name T867
Test name
Test status
Simulation time 64253503 ps
CPU time 0.76 seconds
Started Jun 24 04:42:23 PM PDT 24
Finished Jun 24 04:42:34 PM PDT 24
Peak memory 206872 kb
Host smart-3c6cff62-7710-4f50-9c2c-5fc00cbbac50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184004635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.184004635
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.206461900
Short name T531
Test name
Test status
Simulation time 33160589146 ps
CPU time 237.27 seconds
Started Jun 24 04:42:25 PM PDT 24
Finished Jun 24 04:46:33 PM PDT 24
Peak memory 259756 kb
Host smart-cd0dc01b-2240-4d1b-9b31-b1cd2c3d6748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206461900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.206461900
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3107175008
Short name T669
Test name
Test status
Simulation time 7754780804 ps
CPU time 107.99 seconds
Started Jun 24 04:42:37 PM PDT 24
Finished Jun 24 04:44:33 PM PDT 24
Peak memory 249288 kb
Host smart-60fb43cf-59c0-4c4c-9fd9-2c4dd795d50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107175008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3107175008
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2446889218
Short name T906
Test name
Test status
Simulation time 1382500565 ps
CPU time 15.72 seconds
Started Jun 24 04:42:24 PM PDT 24
Finished Jun 24 04:42:51 PM PDT 24
Peak memory 224484 kb
Host smart-2a9e34ed-8a33-4afe-b4e4-44147a6c7fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446889218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2446889218
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.4159961207
Short name T958
Test name
Test status
Simulation time 2103398866 ps
CPU time 16.94 seconds
Started Jun 24 04:42:23 PM PDT 24
Finished Jun 24 04:42:51 PM PDT 24
Peak memory 232688 kb
Host smart-d8872152-f482-4ef3-8d35-0e392156525d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159961207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.4159961207
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.536514175
Short name T772
Test name
Test status
Simulation time 997989143 ps
CPU time 10.05 seconds
Started Jun 24 04:42:32 PM PDT 24
Finished Jun 24 04:42:52 PM PDT 24
Peak memory 240032 kb
Host smart-2fd8df64-08c5-4e24-8760-c6a2bbf98119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536514175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.536514175
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2027412709
Short name T605
Test name
Test status
Simulation time 23366619742 ps
CPU time 19.88 seconds
Started Jun 24 04:42:23 PM PDT 24
Finished Jun 24 04:42:54 PM PDT 24
Peak memory 232768 kb
Host smart-37f58f18-8be0-468a-bcf0-1a6be188062d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027412709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2027412709
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3733523874
Short name T131
Test name
Test status
Simulation time 649222111 ps
CPU time 3.97 seconds
Started Jun 24 04:42:32 PM PDT 24
Finished Jun 24 04:42:46 PM PDT 24
Peak memory 224272 kb
Host smart-b25b1b20-cd7a-4a8a-99a8-09feed33925b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733523874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3733523874
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2804601897
Short name T11
Test name
Test status
Simulation time 270304420 ps
CPU time 4.6 seconds
Started Jun 24 04:42:24 PM PDT 24
Finished Jun 24 04:42:40 PM PDT 24
Peak memory 223112 kb
Host smart-84ce97cb-c37f-40a1-9c24-ff05d8dc3163
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2804601897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2804601897
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.852533813
Short name T728
Test name
Test status
Simulation time 71554611895 ps
CPU time 227.6 seconds
Started Jun 24 04:42:31 PM PDT 24
Finished Jun 24 04:46:29 PM PDT 24
Peak memory 252164 kb
Host smart-2e80b13a-1676-4973-8d75-dabdcee68db4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852533813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.852533813
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3281325437
Short name T81
Test name
Test status
Simulation time 5572255204 ps
CPU time 20.28 seconds
Started Jun 24 04:42:25 PM PDT 24
Finished Jun 24 04:42:57 PM PDT 24
Peak memory 216688 kb
Host smart-ec53811c-00df-4ac4-98d2-f22c8411258b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281325437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3281325437
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1104786693
Short name T492
Test name
Test status
Simulation time 600591587 ps
CPU time 2.31 seconds
Started Jun 24 04:42:23 PM PDT 24
Finished Jun 24 04:42:36 PM PDT 24
Peak memory 207948 kb
Host smart-7b62b430-1ab6-45f1-acf2-3730cc4192cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104786693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1104786693
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.4139284451
Short name T965
Test name
Test status
Simulation time 537525798 ps
CPU time 1.77 seconds
Started Jun 24 04:42:27 PM PDT 24
Finished Jun 24 04:42:39 PM PDT 24
Peak memory 216272 kb
Host smart-a224e2a9-4014-4c56-91b2-e5603fd4b612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139284451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.4139284451
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.680298055
Short name T343
Test name
Test status
Simulation time 21733295 ps
CPU time 0.76 seconds
Started Jun 24 04:42:31 PM PDT 24
Finished Jun 24 04:42:42 PM PDT 24
Peak memory 205928 kb
Host smart-dc23182b-afe9-46be-a02c-030663525be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680298055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.680298055
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2208703188
Short name T551
Test name
Test status
Simulation time 5533664716 ps
CPU time 15.36 seconds
Started Jun 24 04:42:23 PM PDT 24
Finished Jun 24 04:42:49 PM PDT 24
Peak memory 224632 kb
Host smart-345c0770-ba36-456f-971b-1dda8bb8db46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208703188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2208703188
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1730165456
Short name T957
Test name
Test status
Simulation time 39618804 ps
CPU time 0.73 seconds
Started Jun 24 04:42:29 PM PDT 24
Finished Jun 24 04:42:39 PM PDT 24
Peak memory 205396 kb
Host smart-0274d22a-34dc-4fac-93cb-67d3aebaea6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730165456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1730165456
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.245595008
Short name T191
Test name
Test status
Simulation time 92816833 ps
CPU time 2.73 seconds
Started Jun 24 04:42:32 PM PDT 24
Finished Jun 24 04:42:45 PM PDT 24
Peak memory 224492 kb
Host smart-0fe42afd-1e0e-4987-8a71-405bf17ff139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245595008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.245595008
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.626947137
Short name T413
Test name
Test status
Simulation time 48427791 ps
CPU time 0.78 seconds
Started Jun 24 04:42:25 PM PDT 24
Finished Jun 24 04:42:37 PM PDT 24
Peak memory 206872 kb
Host smart-265b4373-5121-4432-9e93-72f32c844536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626947137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.626947137
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3547624313
Short name T964
Test name
Test status
Simulation time 106515340 ps
CPU time 0.77 seconds
Started Jun 24 04:42:22 PM PDT 24
Finished Jun 24 04:42:34 PM PDT 24
Peak memory 215876 kb
Host smart-77160498-7ef7-45be-b180-ffe05f004edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547624313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3547624313
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1136088198
Short name T536
Test name
Test status
Simulation time 56386684560 ps
CPU time 154.8 seconds
Started Jun 24 04:42:22 PM PDT 24
Finished Jun 24 04:45:07 PM PDT 24
Peak memory 254320 kb
Host smart-05801f70-6ed8-4c07-9e38-110aa36d6922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136088198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1136088198
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2443674502
Short name T207
Test name
Test status
Simulation time 19080970430 ps
CPU time 88.06 seconds
Started Jun 24 04:42:24 PM PDT 24
Finished Jun 24 04:44:03 PM PDT 24
Peak memory 257336 kb
Host smart-85899a97-7e00-4416-ac91-2ef36fc64c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443674502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2443674502
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1559738515
Short name T875
Test name
Test status
Simulation time 1462411155 ps
CPU time 10.54 seconds
Started Jun 24 04:42:24 PM PDT 24
Finished Jun 24 04:42:46 PM PDT 24
Peak memory 240880 kb
Host smart-c413e653-aacc-468f-9979-a94675b28891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559738515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1559738515
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.894411118
Short name T608
Test name
Test status
Simulation time 652720968 ps
CPU time 8.36 seconds
Started Jun 24 04:42:23 PM PDT 24
Finished Jun 24 04:42:42 PM PDT 24
Peak memory 227840 kb
Host smart-0ce8f6b7-7137-4938-b07e-3cecc47ff8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894411118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.894411118
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3312827167
Short name T846
Test name
Test status
Simulation time 8156650114 ps
CPU time 6.81 seconds
Started Jun 24 04:42:23 PM PDT 24
Finished Jun 24 04:42:41 PM PDT 24
Peak memory 224572 kb
Host smart-1ce4a7d5-06bc-4e39-a3ad-88a859477de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312827167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3312827167
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1062138971
Short name T612
Test name
Test status
Simulation time 7467739856 ps
CPU time 12.13 seconds
Started Jun 24 04:42:24 PM PDT 24
Finished Jun 24 04:42:47 PM PDT 24
Peak memory 232768 kb
Host smart-ae26f7c0-dc3d-426b-a817-d11e5937fe4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062138971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1062138971
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2131867499
Short name T446
Test name
Test status
Simulation time 962805977 ps
CPU time 2.82 seconds
Started Jun 24 04:42:23 PM PDT 24
Finished Jun 24 04:42:36 PM PDT 24
Peak memory 232704 kb
Host smart-1df31b01-ed1d-4203-b5c3-464f972b2024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131867499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2131867499
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.4254585292
Short name T687
Test name
Test status
Simulation time 966985381 ps
CPU time 4.29 seconds
Started Jun 24 04:42:22 PM PDT 24
Finished Jun 24 04:42:37 PM PDT 24
Peak memory 219952 kb
Host smart-cc9c7177-4fc4-4e4f-8c29-259d68e814be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4254585292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.4254585292
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3783059281
Short name T553
Test name
Test status
Simulation time 6417302437 ps
CPU time 26.6 seconds
Started Jun 24 04:42:22 PM PDT 24
Finished Jun 24 04:42:59 PM PDT 24
Peak memory 216436 kb
Host smart-d000ff61-ce83-4920-9c68-11303d678a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783059281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3783059281
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.174390766
Short name T449
Test name
Test status
Simulation time 2779031056 ps
CPU time 4.73 seconds
Started Jun 24 04:42:23 PM PDT 24
Finished Jun 24 04:42:39 PM PDT 24
Peak memory 216400 kb
Host smart-1bc42ac8-120c-4841-8b4f-3e1ab46fecb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174390766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.174390766
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.112364235
Short name T351
Test name
Test status
Simulation time 497240759 ps
CPU time 4.58 seconds
Started Jun 24 04:42:25 PM PDT 24
Finished Jun 24 04:42:41 PM PDT 24
Peak memory 216272 kb
Host smart-93c580ed-0aa1-4864-87b6-c78ca2a4c264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112364235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.112364235
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.768968042
Short name T363
Test name
Test status
Simulation time 92850220 ps
CPU time 0.78 seconds
Started Jun 24 04:42:25 PM PDT 24
Finished Jun 24 04:42:37 PM PDT 24
Peak memory 205996 kb
Host smart-f961e298-9c03-488f-9cea-6419f63e0b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768968042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.768968042
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2829203739
Short name T703
Test name
Test status
Simulation time 445134927 ps
CPU time 3.28 seconds
Started Jun 24 04:42:24 PM PDT 24
Finished Jun 24 04:42:37 PM PDT 24
Peak memory 232692 kb
Host smart-c1511746-4889-4668-87d3-4458e7552d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829203739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2829203739
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.282888859
Short name T756
Test name
Test status
Simulation time 63317869 ps
CPU time 0.71 seconds
Started Jun 24 04:42:29 PM PDT 24
Finished Jun 24 04:42:39 PM PDT 24
Peak memory 204752 kb
Host smart-3b9e7ab2-c84b-491c-b3cc-04bf7c9db061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282888859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.282888859
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.946204508
Short name T637
Test name
Test status
Simulation time 53843549 ps
CPU time 2.25 seconds
Started Jun 24 04:42:31 PM PDT 24
Finished Jun 24 04:42:44 PM PDT 24
Peak memory 232404 kb
Host smart-0fb23fe0-0140-4d14-91db-c88795a24a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946204508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.946204508
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1957292496
Short name T825
Test name
Test status
Simulation time 29738110 ps
CPU time 0.77 seconds
Started Jun 24 04:42:30 PM PDT 24
Finished Jun 24 04:42:41 PM PDT 24
Peak memory 206544 kb
Host smart-aa9dcb46-4272-47b6-b6a4-6e8edc078506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957292496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1957292496
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3769771875
Short name T458
Test name
Test status
Simulation time 22520417090 ps
CPU time 96.88 seconds
Started Jun 24 04:42:31 PM PDT 24
Finished Jun 24 04:44:18 PM PDT 24
Peak memory 250356 kb
Host smart-f8eaf50d-4a03-4044-84bd-84584cc9164b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769771875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3769771875
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.836721904
Short name T51
Test name
Test status
Simulation time 12129280729 ps
CPU time 130.25 seconds
Started Jun 24 04:42:30 PM PDT 24
Finished Jun 24 04:44:51 PM PDT 24
Peak memory 249232 kb
Host smart-d7aab53e-8014-46c3-b8fc-0e3a44e649ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836721904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.836721904
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2503409373
Short name T578
Test name
Test status
Simulation time 3968170271 ps
CPU time 59.68 seconds
Started Jun 24 04:42:33 PM PDT 24
Finished Jun 24 04:43:42 PM PDT 24
Peak memory 249480 kb
Host smart-fdbcbb96-61df-49c9-ad30-8f8e255fd450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503409373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2503409373
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.625712808
Short name T881
Test name
Test status
Simulation time 1938377070 ps
CPU time 13.48 seconds
Started Jun 24 04:42:32 PM PDT 24
Finished Jun 24 04:42:55 PM PDT 24
Peak memory 219752 kb
Host smart-2ad2803f-2463-4958-b5ce-713e071573f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625712808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.625712808
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2852205514
Short name T214
Test name
Test status
Simulation time 299271805 ps
CPU time 3.21 seconds
Started Jun 24 04:42:30 PM PDT 24
Finished Jun 24 04:42:44 PM PDT 24
Peak memory 224528 kb
Host smart-ab75c92c-cce2-4997-912f-7bc8f2712538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852205514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2852205514
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2344548086
Short name T735
Test name
Test status
Simulation time 4042906364 ps
CPU time 21.63 seconds
Started Jun 24 04:42:32 PM PDT 24
Finished Jun 24 04:43:04 PM PDT 24
Peak memory 224568 kb
Host smart-36271012-cef9-4c2a-81a8-040e6767577d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344548086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2344548086
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3762493382
Short name T445
Test name
Test status
Simulation time 198553256 ps
CPU time 4.67 seconds
Started Jun 24 04:42:31 PM PDT 24
Finished Jun 24 04:42:46 PM PDT 24
Peak memory 224472 kb
Host smart-043a3c56-0d6d-43c0-a29f-01f00c49bf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762493382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3762493382
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2211369009
Short name T366
Test name
Test status
Simulation time 543658179 ps
CPU time 4.14 seconds
Started Jun 24 04:42:32 PM PDT 24
Finished Jun 24 04:42:46 PM PDT 24
Peak memory 224500 kb
Host smart-19bd28fb-1c5a-4e19-ad26-890efb05beb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211369009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2211369009
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1908170635
Short name T566
Test name
Test status
Simulation time 2785851349 ps
CPU time 7.96 seconds
Started Jun 24 04:42:30 PM PDT 24
Finished Jun 24 04:42:48 PM PDT 24
Peak memory 223236 kb
Host smart-49e68c84-01c3-4071-a867-39c93e85c71b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1908170635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1908170635
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1552374802
Short name T616
Test name
Test status
Simulation time 1877065933 ps
CPU time 20.46 seconds
Started Jun 24 04:42:30 PM PDT 24
Finished Jun 24 04:43:01 PM PDT 24
Peak memory 216256 kb
Host smart-4753e377-c6de-4861-ab93-077f0621d5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552374802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1552374802
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2329374765
Short name T653
Test name
Test status
Simulation time 13520097503 ps
CPU time 9.1 seconds
Started Jun 24 04:42:32 PM PDT 24
Finished Jun 24 04:42:51 PM PDT 24
Peak memory 216756 kb
Host smart-e26a29f4-cb30-4de9-a1ca-a0414b6198a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329374765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2329374765
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.329865607
Short name T405
Test name
Test status
Simulation time 527501413 ps
CPU time 1.81 seconds
Started Jun 24 04:42:32 PM PDT 24
Finished Jun 24 04:42:44 PM PDT 24
Peak memory 216288 kb
Host smart-11042e9b-3bb9-422d-8961-5dfbedaccc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329865607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.329865607
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1355305513
Short name T672
Test name
Test status
Simulation time 276079118 ps
CPU time 0.83 seconds
Started Jun 24 04:42:32 PM PDT 24
Finished Jun 24 04:42:43 PM PDT 24
Peak memory 205912 kb
Host smart-d59f0097-1975-4031-843a-9c487d4dd9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355305513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1355305513
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3946028752
Short name T581
Test name
Test status
Simulation time 38091385472 ps
CPU time 16.91 seconds
Started Jun 24 04:42:31 PM PDT 24
Finished Jun 24 04:42:58 PM PDT 24
Peak memory 232848 kb
Host smart-c6e08d73-0ecd-4657-891b-0fb7f71dab52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946028752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3946028752
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.725289821
Short name T358
Test name
Test status
Simulation time 13003321 ps
CPU time 0.77 seconds
Started Jun 24 04:42:32 PM PDT 24
Finished Jun 24 04:42:43 PM PDT 24
Peak memory 205724 kb
Host smart-071e87c0-447c-479a-8043-d867c9b4fa29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725289821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.725289821
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.22851919
Short name T78
Test name
Test status
Simulation time 201465485 ps
CPU time 2.78 seconds
Started Jun 24 04:42:31 PM PDT 24
Finished Jun 24 04:42:44 PM PDT 24
Peak memory 232696 kb
Host smart-b7965166-849e-4312-8a5c-897ea95b579b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22851919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.22851919
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2403538463
Short name T455
Test name
Test status
Simulation time 14840586 ps
CPU time 0.76 seconds
Started Jun 24 04:42:32 PM PDT 24
Finished Jun 24 04:42:43 PM PDT 24
Peak memory 206536 kb
Host smart-7f158e08-7f17-4169-80b5-151691849e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403538463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2403538463
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3423530932
Short name T57
Test name
Test status
Simulation time 365460288975 ps
CPU time 405.08 seconds
Started Jun 24 04:42:32 PM PDT 24
Finished Jun 24 04:49:27 PM PDT 24
Peak memory 260652 kb
Host smart-4de143a9-4a1f-4154-91e3-b431e0759755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423530932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3423530932
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1254508446
Short name T827
Test name
Test status
Simulation time 31960651684 ps
CPU time 54.76 seconds
Started Jun 24 04:42:30 PM PDT 24
Finished Jun 24 04:43:35 PM PDT 24
Peak memory 224672 kb
Host smart-ec0b8d11-a41f-4b31-9c4a-0efe3ab18895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254508446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1254508446
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.934786290
Short name T265
Test name
Test status
Simulation time 70542251271 ps
CPU time 241.4 seconds
Started Jun 24 04:42:32 PM PDT 24
Finished Jun 24 04:46:43 PM PDT 24
Peak memory 252468 kb
Host smart-9f47ec3a-9ba8-4c3a-a03d-e88021c8f4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934786290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.934786290
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.4126213455
Short name T60
Test name
Test status
Simulation time 1945618458 ps
CPU time 10.95 seconds
Started Jun 24 04:42:30 PM PDT 24
Finished Jun 24 04:42:51 PM PDT 24
Peak memory 234268 kb
Host smart-798b8b16-1634-4d09-8989-e333e4aa64e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126213455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.4126213455
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.4093214251
Short name T575
Test name
Test status
Simulation time 1471056243 ps
CPU time 6.44 seconds
Started Jun 24 04:42:29 PM PDT 24
Finished Jun 24 04:42:45 PM PDT 24
Peak memory 224452 kb
Host smart-0b80b128-5c2a-45c1-b4c8-6e397218df78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093214251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.4093214251
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1363851720
Short name T831
Test name
Test status
Simulation time 893385759 ps
CPU time 12.66 seconds
Started Jun 24 04:42:32 PM PDT 24
Finished Jun 24 04:42:55 PM PDT 24
Peak memory 232652 kb
Host smart-ab496371-396a-4908-a774-7ab1c7ba93a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363851720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1363851720
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2259959929
Short name T275
Test name
Test status
Simulation time 168041099 ps
CPU time 2.66 seconds
Started Jun 24 04:42:32 PM PDT 24
Finished Jun 24 04:42:44 PM PDT 24
Peak memory 224436 kb
Host smart-dfabee84-00f0-4118-9d15-a17d88f9ca83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259959929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2259959929
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1598578413
Short name T719
Test name
Test status
Simulation time 4668356171 ps
CPU time 14.35 seconds
Started Jun 24 04:42:30 PM PDT 24
Finished Jun 24 04:42:55 PM PDT 24
Peak memory 232776 kb
Host smart-a3b747f8-62ef-467c-9c54-5f0f3f95d150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598578413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1598578413
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1167489277
Short name T524
Test name
Test status
Simulation time 240742024 ps
CPU time 4.99 seconds
Started Jun 24 04:42:32 PM PDT 24
Finished Jun 24 04:42:47 PM PDT 24
Peak memory 222552 kb
Host smart-53ccdf65-08f4-4b1a-8345-c61441a542ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1167489277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1167489277
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1053856309
Short name T14
Test name
Test status
Simulation time 26178663997 ps
CPU time 274.88 seconds
Started Jun 24 04:42:30 PM PDT 24
Finished Jun 24 04:47:15 PM PDT 24
Peak memory 253040 kb
Host smart-f1ea55e2-1e05-463f-bc21-0c18348036f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053856309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1053856309
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.980980297
Short name T768
Test name
Test status
Simulation time 2018579713 ps
CPU time 15.25 seconds
Started Jun 24 04:42:30 PM PDT 24
Finished Jun 24 04:42:55 PM PDT 24
Peak memory 216472 kb
Host smart-188f264a-9975-4e87-b947-34577c5003b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980980297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.980980297
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1995852504
Short name T505
Test name
Test status
Simulation time 13313371 ps
CPU time 0.72 seconds
Started Jun 24 04:42:31 PM PDT 24
Finished Jun 24 04:42:42 PM PDT 24
Peak memory 205596 kb
Host smart-8292a302-0a1b-4fc9-af92-ecbbf2f95c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995852504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1995852504
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1280867823
Short name T803
Test name
Test status
Simulation time 136745774 ps
CPU time 2.7 seconds
Started Jun 24 04:42:30 PM PDT 24
Finished Jun 24 04:42:43 PM PDT 24
Peak memory 216296 kb
Host smart-d861620b-cc45-476a-a7d0-4c5bf36459a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280867823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1280867823
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.4080449060
Short name T859
Test name
Test status
Simulation time 605564258 ps
CPU time 0.9 seconds
Started Jun 24 04:42:30 PM PDT 24
Finished Jun 24 04:42:40 PM PDT 24
Peak memory 205860 kb
Host smart-aa48686e-40bc-4f77-b91d-0265be0aa666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080449060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.4080449060
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.4136997820
Short name T635
Test name
Test status
Simulation time 308941272 ps
CPU time 4.92 seconds
Started Jun 24 04:42:33 PM PDT 24
Finished Jun 24 04:42:47 PM PDT 24
Peak memory 238896 kb
Host smart-f4e7da2f-0d8d-4d58-b0fb-08305213cf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136997820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.4136997820
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2067580451
Short name T796
Test name
Test status
Simulation time 18324204 ps
CPU time 0.76 seconds
Started Jun 24 04:42:36 PM PDT 24
Finished Jun 24 04:42:45 PM PDT 24
Peak memory 205332 kb
Host smart-e56a9f5d-de39-445b-8ab1-d5f0e1a792ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067580451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2067580451
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1690419061
Short name T90
Test name
Test status
Simulation time 128844614 ps
CPU time 2.89 seconds
Started Jun 24 04:42:30 PM PDT 24
Finished Jun 24 04:42:43 PM PDT 24
Peak memory 232696 kb
Host smart-d5508745-78ab-4af9-8e5c-4d7a945534c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690419061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1690419061
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.630577536
Short name T175
Test name
Test status
Simulation time 22437749 ps
CPU time 0.78 seconds
Started Jun 24 04:42:32 PM PDT 24
Finished Jun 24 04:42:43 PM PDT 24
Peak memory 205428 kb
Host smart-ab181b9e-ec5a-4dc0-9185-8db2bc82d082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630577536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.630577536
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1091970506
Short name T522
Test name
Test status
Simulation time 708130450 ps
CPU time 5.05 seconds
Started Jun 24 04:42:36 PM PDT 24
Finished Jun 24 04:42:49 PM PDT 24
Peak memory 224500 kb
Host smart-0007ff75-d119-4158-965b-8caede0910b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091970506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1091970506
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2573980867
Short name T528
Test name
Test status
Simulation time 12262479131 ps
CPU time 57.41 seconds
Started Jun 24 04:42:35 PM PDT 24
Finished Jun 24 04:43:41 PM PDT 24
Peak memory 249328 kb
Host smart-1a9e6110-d8f6-449b-9141-febc9d5e75d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573980867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2573980867
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.4233096983
Short name T35
Test name
Test status
Simulation time 63475937072 ps
CPU time 168 seconds
Started Jun 24 04:42:36 PM PDT 24
Finished Jun 24 04:45:33 PM PDT 24
Peak memory 249384 kb
Host smart-eec2df28-0b4b-4581-9c14-a8947db1ab24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233096983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.4233096983
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2202131305
Short name T949
Test name
Test status
Simulation time 812110954 ps
CPU time 5.83 seconds
Started Jun 24 04:42:32 PM PDT 24
Finished Jun 24 04:42:48 PM PDT 24
Peak memory 240828 kb
Host smart-06cec52c-b6ab-4c9c-8653-2a1a518af275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202131305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2202131305
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3224011278
Short name T250
Test name
Test status
Simulation time 999510485 ps
CPU time 8.51 seconds
Started Jun 24 04:42:31 PM PDT 24
Finished Jun 24 04:42:50 PM PDT 24
Peak memory 224444 kb
Host smart-a59b2266-044b-4964-ad92-fb6488b2249d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224011278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3224011278
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.887382735
Short name T748
Test name
Test status
Simulation time 50476428499 ps
CPU time 72.48 seconds
Started Jun 24 04:42:32 PM PDT 24
Finished Jun 24 04:43:54 PM PDT 24
Peak memory 249188 kb
Host smart-f0646088-31e8-4558-8daa-37b2fba2b2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887382735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.887382735
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1874206443
Short name T856
Test name
Test status
Simulation time 43422411226 ps
CPU time 24.96 seconds
Started Jun 24 04:42:29 PM PDT 24
Finished Jun 24 04:43:04 PM PDT 24
Peak memory 232828 kb
Host smart-b4fd49d4-4036-4802-9437-b29780d33ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874206443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1874206443
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2641266695
Short name T576
Test name
Test status
Simulation time 13890368864 ps
CPU time 5.52 seconds
Started Jun 24 04:42:32 PM PDT 24
Finished Jun 24 04:42:47 PM PDT 24
Peak memory 232712 kb
Host smart-80e7706b-281d-41ab-9835-132aee975e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641266695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2641266695
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1357721715
Short name T599
Test name
Test status
Simulation time 1570496082 ps
CPU time 7.43 seconds
Started Jun 24 04:42:37 PM PDT 24
Finished Jun 24 04:42:52 PM PDT 24
Peak memory 222576 kb
Host smart-93f6cf5f-efa6-4afc-b3a4-b607da4bde3e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1357721715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1357721715
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3167853277
Short name T321
Test name
Test status
Simulation time 823183964 ps
CPU time 7.67 seconds
Started Jun 24 04:42:34 PM PDT 24
Finished Jun 24 04:42:50 PM PDT 24
Peak memory 216304 kb
Host smart-c15fa1b3-8381-435d-b852-7ee7dfff1de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167853277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3167853277
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1352176160
Short name T784
Test name
Test status
Simulation time 735805190 ps
CPU time 5.28 seconds
Started Jun 24 04:42:30 PM PDT 24
Finished Jun 24 04:42:46 PM PDT 24
Peak memory 216184 kb
Host smart-6ecc5fba-dfc0-43b3-ac2a-4a65967c5721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352176160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1352176160
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1593702121
Short name T678
Test name
Test status
Simulation time 87682305 ps
CPU time 0.85 seconds
Started Jun 24 04:42:30 PM PDT 24
Finished Jun 24 04:42:41 PM PDT 24
Peak memory 206964 kb
Host smart-ef240222-43fc-4a8f-9825-30052154e325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593702121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1593702121
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2211987752
Short name T437
Test name
Test status
Simulation time 192456118 ps
CPU time 1.12 seconds
Started Jun 24 04:42:31 PM PDT 24
Finished Jun 24 04:42:43 PM PDT 24
Peak memory 206924 kb
Host smart-7cc9dd0f-7940-44cc-a13e-cd9c3440b2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211987752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2211987752
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2849100890
Short name T631
Test name
Test status
Simulation time 330225040 ps
CPU time 6.61 seconds
Started Jun 24 04:42:34 PM PDT 24
Finished Jun 24 04:42:50 PM PDT 24
Peak memory 235588 kb
Host smart-60e050b9-fb54-4e0a-9a31-c83780f8e7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849100890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2849100890
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2030280354
Short name T336
Test name
Test status
Simulation time 14468667 ps
CPU time 0.76 seconds
Started Jun 24 04:42:42 PM PDT 24
Finished Jun 24 04:42:48 PM PDT 24
Peak memory 205656 kb
Host smart-6719818e-1321-4e27-a29f-1fd0ce002ac3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030280354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2030280354
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3274876954
Short name T523
Test name
Test status
Simulation time 50858451 ps
CPU time 2.84 seconds
Started Jun 24 04:42:38 PM PDT 24
Finished Jun 24 04:42:48 PM PDT 24
Peak memory 232648 kb
Host smart-1c4fc458-c75a-4662-9869-569622327d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274876954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3274876954
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3935681840
Short name T869
Test name
Test status
Simulation time 17463371 ps
CPU time 0.8 seconds
Started Jun 24 04:42:42 PM PDT 24
Finished Jun 24 04:42:48 PM PDT 24
Peak memory 206868 kb
Host smart-895260e0-7396-438d-ad31-7e42c0a37c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935681840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3935681840
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3726449534
Short name T921
Test name
Test status
Simulation time 3493993360 ps
CPU time 31.43 seconds
Started Jun 24 04:42:36 PM PDT 24
Finished Jun 24 04:43:16 PM PDT 24
Peak memory 249668 kb
Host smart-fc27a6dd-fc30-4680-8e46-46bbf3fe6315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726449534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3726449534
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.609966644
Short name T805
Test name
Test status
Simulation time 4726271245 ps
CPU time 33.2 seconds
Started Jun 24 04:42:38 PM PDT 24
Finished Jun 24 04:43:19 PM PDT 24
Peak memory 250536 kb
Host smart-c19de787-fd53-4b32-a4b5-e9ac57cfb55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609966644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.609966644
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1185188165
Short name T50
Test name
Test status
Simulation time 25191505407 ps
CPU time 268.65 seconds
Started Jun 24 04:42:39 PM PDT 24
Finished Jun 24 04:47:15 PM PDT 24
Peak memory 273532 kb
Host smart-c7bc8a9e-c1d1-4901-a8ac-cee4655aa5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185188165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1185188165
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2673720798
Short name T809
Test name
Test status
Simulation time 342071590 ps
CPU time 5.21 seconds
Started Jun 24 04:42:41 PM PDT 24
Finished Jun 24 04:42:52 PM PDT 24
Peak memory 224876 kb
Host smart-e73d08f1-70ee-4cd1-a38f-04a3242a269a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673720798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2673720798
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1951834466
Short name T54
Test name
Test status
Simulation time 2771110899 ps
CPU time 15.04 seconds
Started Jun 24 04:42:37 PM PDT 24
Finished Jun 24 04:43:00 PM PDT 24
Peak memory 232840 kb
Host smart-4f242b18-ba3e-41c0-a075-ee106a95608a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951834466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1951834466
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3634588331
Short name T904
Test name
Test status
Simulation time 6435641918 ps
CPU time 52.8 seconds
Started Jun 24 04:42:39 PM PDT 24
Finished Jun 24 04:43:39 PM PDT 24
Peak memory 232760 kb
Host smart-3f36ce7c-6319-499f-a5d9-b93327783fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634588331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3634588331
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1004057727
Short name T295
Test name
Test status
Simulation time 156912251 ps
CPU time 3.4 seconds
Started Jun 24 04:42:37 PM PDT 24
Finished Jun 24 04:42:49 PM PDT 24
Peak memory 224496 kb
Host smart-4bc6c10b-89af-45a2-b86d-29ef93b5cd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004057727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1004057727
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2752458422
Short name T951
Test name
Test status
Simulation time 553708532 ps
CPU time 10.11 seconds
Started Jun 24 04:42:36 PM PDT 24
Finished Jun 24 04:42:55 PM PDT 24
Peak memory 249020 kb
Host smart-14504d50-927c-4891-a290-22e933683ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752458422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2752458422
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1493499745
Short name T408
Test name
Test status
Simulation time 1062922982 ps
CPU time 6.6 seconds
Started Jun 24 04:42:34 PM PDT 24
Finished Jun 24 04:42:50 PM PDT 24
Peak memory 223136 kb
Host smart-da3b596a-d074-4532-8746-aeb4773813f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1493499745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1493499745
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2750964278
Short name T877
Test name
Test status
Simulation time 4765056196 ps
CPU time 13.64 seconds
Started Jun 24 04:42:38 PM PDT 24
Finished Jun 24 04:43:00 PM PDT 24
Peak memory 224576 kb
Host smart-f33f7fc1-7f35-4e46-985a-6df4284c1a6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750964278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2750964278
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.938707562
Short name T556
Test name
Test status
Simulation time 17742528016 ps
CPU time 31.51 seconds
Started Jun 24 04:42:38 PM PDT 24
Finished Jun 24 04:43:17 PM PDT 24
Peak memory 216356 kb
Host smart-7a814851-7c60-4ec4-9628-477d96a876b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938707562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.938707562
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3993633689
Short name T2
Test name
Test status
Simulation time 5340417462 ps
CPU time 3.33 seconds
Started Jun 24 04:42:35 PM PDT 24
Finished Jun 24 04:42:47 PM PDT 24
Peak memory 216308 kb
Host smart-748760a0-7da6-4c25-9fde-eb8981725cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993633689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3993633689
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2547380413
Short name T510
Test name
Test status
Simulation time 18453357 ps
CPU time 1.13 seconds
Started Jun 24 04:42:39 PM PDT 24
Finished Jun 24 04:42:48 PM PDT 24
Peak memory 216184 kb
Host smart-57d96a22-4f40-48f4-8412-aac21c89868b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547380413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2547380413
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3654368805
Short name T432
Test name
Test status
Simulation time 10740322 ps
CPU time 0.72 seconds
Started Jun 24 04:42:36 PM PDT 24
Finished Jun 24 04:42:45 PM PDT 24
Peak memory 205520 kb
Host smart-1082455f-3202-4f2b-838d-b9d4df6b6655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654368805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3654368805
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.157165372
Short name T513
Test name
Test status
Simulation time 35850338 ps
CPU time 2.44 seconds
Started Jun 24 04:42:35 PM PDT 24
Finished Jun 24 04:42:46 PM PDT 24
Peak memory 224172 kb
Host smart-d02935f6-d6c5-4bb6-afbd-e1c0634792e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157165372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.157165372
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1696226523
Short name T943
Test name
Test status
Simulation time 55500099 ps
CPU time 0.7 seconds
Started Jun 24 04:42:42 PM PDT 24
Finished Jun 24 04:42:48 PM PDT 24
Peak memory 205380 kb
Host smart-432723db-be53-47da-b473-163fb959010b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696226523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1696226523
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.631864598
Short name T276
Test name
Test status
Simulation time 42687144 ps
CPU time 2.6 seconds
Started Jun 24 04:42:45 PM PDT 24
Finished Jun 24 04:42:52 PM PDT 24
Peak memory 232588 kb
Host smart-5845f913-94c7-4d97-8815-a5daf6dc1174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631864598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.631864598
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2494139831
Short name T337
Test name
Test status
Simulation time 13835907 ps
CPU time 0.86 seconds
Started Jun 24 04:42:43 PM PDT 24
Finished Jun 24 04:42:49 PM PDT 24
Peak memory 206868 kb
Host smart-f1e938d4-92d3-4972-ab45-88186a86822c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494139831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2494139831
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3077630509
Short name T397
Test name
Test status
Simulation time 6387907816 ps
CPU time 29.49 seconds
Started Jun 24 04:42:43 PM PDT 24
Finished Jun 24 04:43:18 PM PDT 24
Peak memory 253772 kb
Host smart-bc38310c-5f40-4852-8f57-cf7722bb2d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077630509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3077630509
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2127501300
Short name T182
Test name
Test status
Simulation time 37435752368 ps
CPU time 169.14 seconds
Started Jun 24 04:42:45 PM PDT 24
Finished Jun 24 04:45:38 PM PDT 24
Peak memory 254852 kb
Host smart-fc806c5b-a6e1-49a4-adbf-8c3552e78b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127501300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2127501300
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2004233076
Short name T142
Test name
Test status
Simulation time 116902207172 ps
CPU time 270.71 seconds
Started Jun 24 04:42:44 PM PDT 24
Finished Jun 24 04:47:20 PM PDT 24
Peak memory 249240 kb
Host smart-8fe97978-9390-4c57-8d78-87e782c6604f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004233076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2004233076
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.203979678
Short name T427
Test name
Test status
Simulation time 628121419 ps
CPU time 3.89 seconds
Started Jun 24 04:42:45 PM PDT 24
Finished Jun 24 04:42:53 PM PDT 24
Peak memory 224496 kb
Host smart-82f0558b-c5cb-474f-ae92-a17ea496a894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203979678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.203979678
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.723459779
Short name T113
Test name
Test status
Simulation time 269748678 ps
CPU time 4.17 seconds
Started Jun 24 04:42:37 PM PDT 24
Finished Jun 24 04:42:49 PM PDT 24
Peak memory 229444 kb
Host smart-c9f174ff-fb8c-41b5-baa6-1ed0c5cb49c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723459779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.723459779
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.109193393
Short name T872
Test name
Test status
Simulation time 3302998318 ps
CPU time 14.19 seconds
Started Jun 24 04:42:35 PM PDT 24
Finished Jun 24 04:42:58 PM PDT 24
Peak memory 232780 kb
Host smart-dfdf8521-fa09-46fb-8e31-f053863c0122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109193393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.109193393
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2307014711
Short name T272
Test name
Test status
Simulation time 5125511949 ps
CPU time 25.41 seconds
Started Jun 24 04:42:37 PM PDT 24
Finished Jun 24 04:43:10 PM PDT 24
Peak memory 245380 kb
Host smart-2cb3c3bd-54eb-4509-b6e7-6a4c999e9c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307014711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2307014711
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1493088937
Short name T933
Test name
Test status
Simulation time 1732320430 ps
CPU time 6.7 seconds
Started Jun 24 04:42:37 PM PDT 24
Finished Jun 24 04:42:52 PM PDT 24
Peak memory 232740 kb
Host smart-e6a8583d-a13d-4a2b-ba7c-e4415d818909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493088937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1493088937
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.785805636
Short name T76
Test name
Test status
Simulation time 9927733119 ps
CPU time 6.49 seconds
Started Jun 24 04:42:44 PM PDT 24
Finished Jun 24 04:42:55 PM PDT 24
Peak memory 218752 kb
Host smart-94143449-b4a3-46c6-aef9-748948b784a1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=785805636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.785805636
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2607199668
Short name T15
Test name
Test status
Simulation time 70891311986 ps
CPU time 81.71 seconds
Started Jun 24 04:42:42 PM PDT 24
Finished Jun 24 04:44:09 PM PDT 24
Peak memory 250336 kb
Host smart-d7c7fbbb-228a-43f8-9a9e-7396bedb07d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607199668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2607199668
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3145914552
Short name T740
Test name
Test status
Simulation time 26214832320 ps
CPU time 40.45 seconds
Started Jun 24 04:42:37 PM PDT 24
Finished Jun 24 04:43:26 PM PDT 24
Peak memory 216528 kb
Host smart-bd562a96-9f84-4f03-8303-7741075ea81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145914552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3145914552
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2716997623
Short name T433
Test name
Test status
Simulation time 20111949503 ps
CPU time 13.56 seconds
Started Jun 24 04:42:37 PM PDT 24
Finished Jun 24 04:42:59 PM PDT 24
Peak memory 216396 kb
Host smart-07842d21-0ffc-4d73-8894-97941b6afa33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716997623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2716997623
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3771556288
Short name T818
Test name
Test status
Simulation time 12929575 ps
CPU time 0.71 seconds
Started Jun 24 04:42:35 PM PDT 24
Finished Jun 24 04:42:44 PM PDT 24
Peak memory 205608 kb
Host smart-28f64884-61d9-4b55-b428-0d66be2e6023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771556288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3771556288
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.52544390
Short name T389
Test name
Test status
Simulation time 67628500 ps
CPU time 0.7 seconds
Started Jun 24 04:42:35 PM PDT 24
Finished Jun 24 04:42:44 PM PDT 24
Peak memory 205512 kb
Host smart-9dc679dd-ba7a-47a9-a9e6-7e4fd6de1ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52544390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.52544390
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2427865062
Short name T193
Test name
Test status
Simulation time 3516685093 ps
CPU time 15.1 seconds
Started Jun 24 04:42:41 PM PDT 24
Finished Jun 24 04:43:02 PM PDT 24
Peak memory 240908 kb
Host smart-2c8d95f3-7c13-4cf7-8a24-660503082226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427865062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2427865062
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.39942213
Short name T533
Test name
Test status
Simulation time 55271617 ps
CPU time 0.76 seconds
Started Jun 24 04:42:43 PM PDT 24
Finished Jun 24 04:42:49 PM PDT 24
Peak memory 204752 kb
Host smart-1158ef61-db09-483e-9667-4b5ca2e431a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39942213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.39942213
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.139951017
Short name T190
Test name
Test status
Simulation time 38549118 ps
CPU time 2.61 seconds
Started Jun 24 04:42:44 PM PDT 24
Finished Jun 24 04:42:51 PM PDT 24
Peak memory 232668 kb
Host smart-5c2e391f-d8ca-4bad-9455-81e28ef6674f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139951017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.139951017
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.4103200726
Short name T415
Test name
Test status
Simulation time 54988753 ps
CPU time 0.79 seconds
Started Jun 24 04:42:44 PM PDT 24
Finished Jun 24 04:42:50 PM PDT 24
Peak memory 206888 kb
Host smart-23c92599-74ff-43a6-a55f-07a306b39fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103200726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.4103200726
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3450493958
Short name T464
Test name
Test status
Simulation time 106936184348 ps
CPU time 181.98 seconds
Started Jun 24 04:42:45 PM PDT 24
Finished Jun 24 04:45:51 PM PDT 24
Peak memory 254468 kb
Host smart-5d48634d-46ec-4ce7-886e-6ae5009c3586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450493958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3450493958
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.4007721324
Short name T266
Test name
Test status
Simulation time 2916146433 ps
CPU time 16.61 seconds
Started Jun 24 04:42:45 PM PDT 24
Finished Jun 24 04:43:06 PM PDT 24
Peak memory 233024 kb
Host smart-8be760ba-9ec4-42af-b49c-e07e2c0adf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007721324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.4007721324
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3823811959
Short name T884
Test name
Test status
Simulation time 197500124862 ps
CPU time 417.93 seconds
Started Jun 24 04:42:44 PM PDT 24
Finished Jun 24 04:49:46 PM PDT 24
Peak memory 254412 kb
Host smart-1a8712c9-8a7a-4f70-8eda-e792265ad6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823811959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3823811959
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1185524793
Short name T312
Test name
Test status
Simulation time 1341528650 ps
CPU time 8.28 seconds
Started Jun 24 04:42:44 PM PDT 24
Finished Jun 24 04:42:57 PM PDT 24
Peak memory 232836 kb
Host smart-43d44651-9d79-4115-bc66-39a9c16b473c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185524793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1185524793
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.976266672
Short name T863
Test name
Test status
Simulation time 226349073 ps
CPU time 4.32 seconds
Started Jun 24 04:42:43 PM PDT 24
Finished Jun 24 04:42:53 PM PDT 24
Peak memory 224456 kb
Host smart-ce33eb24-3ba2-4731-a055-14d12e737a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976266672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.976266672
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2185539166
Short name T920
Test name
Test status
Simulation time 14877987642 ps
CPU time 40.27 seconds
Started Jun 24 04:42:45 PM PDT 24
Finished Jun 24 04:43:30 PM PDT 24
Peak memory 224340 kb
Host smart-3bfae7b0-2d51-4385-b54b-7b59d983de0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185539166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2185539166
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3753639021
Short name T544
Test name
Test status
Simulation time 44949306423 ps
CPU time 13.49 seconds
Started Jun 24 04:42:44 PM PDT 24
Finished Jun 24 04:43:02 PM PDT 24
Peak memory 232744 kb
Host smart-411c8759-1db2-4d84-a6e7-2805b4069ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753639021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3753639021
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.980039058
Short name T924
Test name
Test status
Simulation time 526664147 ps
CPU time 8.34 seconds
Started Jun 24 04:42:45 PM PDT 24
Finished Jun 24 04:42:57 PM PDT 24
Peak memory 240780 kb
Host smart-2d88fbc8-4ef6-41b6-84e2-07673599de43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980039058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.980039058
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.757410782
Short name T382
Test name
Test status
Simulation time 144147338 ps
CPU time 4.34 seconds
Started Jun 24 04:42:47 PM PDT 24
Finished Jun 24 04:42:54 PM PDT 24
Peak memory 223208 kb
Host smart-e601452a-2bdb-4b3f-8cb7-66eceb821b0b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=757410782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.757410782
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.542604679
Short name T169
Test name
Test status
Simulation time 40425558376 ps
CPU time 377.88 seconds
Started Jun 24 04:42:42 PM PDT 24
Finished Jun 24 04:49:05 PM PDT 24
Peak memory 265072 kb
Host smart-27d05a89-cfdd-43f5-8c4d-cc2edd446986
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542604679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.542604679
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3492209107
Short name T727
Test name
Test status
Simulation time 16605421176 ps
CPU time 45.4 seconds
Started Jun 24 04:42:42 PM PDT 24
Finished Jun 24 04:43:33 PM PDT 24
Peak memory 220384 kb
Host smart-62a2d271-c74c-4c36-a90b-467badb80f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492209107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3492209107
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1210193574
Short name T956
Test name
Test status
Simulation time 9899343710 ps
CPU time 14.77 seconds
Started Jun 24 04:42:43 PM PDT 24
Finished Jun 24 04:43:03 PM PDT 24
Peak memory 216460 kb
Host smart-e8ecbf8c-6772-4da7-bfe4-fb2f28475c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210193574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1210193574
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1360392875
Short name T379
Test name
Test status
Simulation time 161486152 ps
CPU time 1.36 seconds
Started Jun 24 04:43:16 PM PDT 24
Finished Jun 24 04:43:19 PM PDT 24
Peak memory 216272 kb
Host smart-6573d4b2-6ac6-4e25-8d42-8370144cc4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360392875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1360392875
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2984638294
Short name T689
Test name
Test status
Simulation time 59479986 ps
CPU time 0.75 seconds
Started Jun 24 04:42:45 PM PDT 24
Finished Jun 24 04:42:50 PM PDT 24
Peak memory 205948 kb
Host smart-fa19e501-e656-4bbb-bc2f-4ac03707bc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984638294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2984638294
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.559987975
Short name T414
Test name
Test status
Simulation time 1046137666 ps
CPU time 4.95 seconds
Started Jun 24 04:42:46 PM PDT 24
Finished Jun 24 04:42:54 PM PDT 24
Peak memory 232692 kb
Host smart-13c606ad-c170-4af0-828f-2cfcb3abfbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559987975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.559987975
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1096585249
Short name T882
Test name
Test status
Simulation time 14299923 ps
CPU time 0.76 seconds
Started Jun 24 04:40:47 PM PDT 24
Finished Jun 24 04:40:50 PM PDT 24
Peak memory 205340 kb
Host smart-7e558ebd-8f51-4cba-84a7-fb9974d37450
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096585249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
096585249
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3790158953
Short name T383
Test name
Test status
Simulation time 2948812549 ps
CPU time 23.54 seconds
Started Jun 24 04:40:46 PM PDT 24
Finished Jun 24 04:41:13 PM PDT 24
Peak memory 232808 kb
Host smart-de76c585-f42f-4132-8b85-9c0715e873d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790158953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3790158953
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2211905061
Short name T344
Test name
Test status
Simulation time 32248781 ps
CPU time 0.75 seconds
Started Jun 24 04:40:37 PM PDT 24
Finished Jun 24 04:40:45 PM PDT 24
Peak memory 205568 kb
Host smart-db8438f2-cecc-4bc9-8bc4-91b07e1d5eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211905061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2211905061
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.626628748
Short name T929
Test name
Test status
Simulation time 5865890563 ps
CPU time 39.1 seconds
Started Jun 24 04:40:46 PM PDT 24
Finished Jun 24 04:41:28 PM PDT 24
Peak memory 233864 kb
Host smart-802b35ea-e41d-4097-97a0-153f84580b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626628748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.626628748
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3691071487
Short name T181
Test name
Test status
Simulation time 24183512752 ps
CPU time 205.3 seconds
Started Jun 24 04:40:48 PM PDT 24
Finished Jun 24 04:44:16 PM PDT 24
Peak memory 254852 kb
Host smart-25eacf79-6a42-4e49-ab66-7c23bf354304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691071487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3691071487
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3061355076
Short name T751
Test name
Test status
Simulation time 30354763331 ps
CPU time 59.66 seconds
Started Jun 24 04:40:46 PM PDT 24
Finished Jun 24 04:41:49 PM PDT 24
Peak memory 241044 kb
Host smart-32b182cd-bdb9-4546-87bf-59a640ae214f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061355076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3061355076
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3776003785
Short name T239
Test name
Test status
Simulation time 144501838 ps
CPU time 4.83 seconds
Started Jun 24 04:40:47 PM PDT 24
Finished Jun 24 04:40:55 PM PDT 24
Peak memory 232696 kb
Host smart-4a8a9e8b-eced-463e-9f68-ff6877040b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776003785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3776003785
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1700915282
Short name T491
Test name
Test status
Simulation time 39722264443 ps
CPU time 91.17 seconds
Started Jun 24 04:40:46 PM PDT 24
Finished Jun 24 04:42:21 PM PDT 24
Peak memory 239808 kb
Host smart-2d1477bf-0fe7-44ed-bcf3-82713225d037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700915282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1700915282
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3082047939
Short name T281
Test name
Test status
Simulation time 41976447250 ps
CPU time 26.38 seconds
Started Jun 24 04:40:47 PM PDT 24
Finished Jun 24 04:41:16 PM PDT 24
Peak memory 232752 kb
Host smart-668d61fe-5677-430c-9e09-a1a3eacec253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082047939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3082047939
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2970106565
Short name T137
Test name
Test status
Simulation time 2723631350 ps
CPU time 6.32 seconds
Started Jun 24 04:40:43 PM PDT 24
Finished Jun 24 04:40:54 PM PDT 24
Peak memory 232764 kb
Host smart-3c21a3bc-3a68-447e-8d63-c5bdc9a68ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970106565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2970106565
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3462723618
Short name T596
Test name
Test status
Simulation time 602453315 ps
CPU time 6.21 seconds
Started Jun 24 04:40:46 PM PDT 24
Finished Jun 24 04:40:55 PM PDT 24
Peak memory 219228 kb
Host smart-384a04bc-20b1-418e-80de-e6ad95fd2ab1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3462723618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3462723618
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2277104
Short name T215
Test name
Test status
Simulation time 83156130886 ps
CPU time 205.56 seconds
Started Jun 24 04:40:47 PM PDT 24
Finished Jun 24 04:44:16 PM PDT 24
Peak memory 256724 kb
Host smart-dcb35f11-65fb-48b5-b2c5-9fef52391c3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_a
ll.2277104
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1505377963
Short name T775
Test name
Test status
Simulation time 1764691379 ps
CPU time 5.88 seconds
Started Jun 24 04:40:44 PM PDT 24
Finished Jun 24 04:40:54 PM PDT 24
Peak memory 216632 kb
Host smart-782d0f97-6260-4c9d-88e4-f718ba25b642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505377963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1505377963
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1307749731
Short name T793
Test name
Test status
Simulation time 5660021797 ps
CPU time 17.42 seconds
Started Jun 24 04:40:34 PM PDT 24
Finished Jun 24 04:41:01 PM PDT 24
Peak memory 216352 kb
Host smart-ee533ab7-84ec-4bb4-a8c0-f0f746191939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307749731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1307749731
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1480564159
Short name T496
Test name
Test status
Simulation time 11595579 ps
CPU time 0.7 seconds
Started Jun 24 04:40:45 PM PDT 24
Finished Jun 24 04:40:49 PM PDT 24
Peak memory 205572 kb
Host smart-3049aa5c-9878-49ee-ab95-5b71f3944ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480564159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1480564159
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3096060655
Short name T356
Test name
Test status
Simulation time 207108206 ps
CPU time 1.04 seconds
Started Jun 24 04:40:46 PM PDT 24
Finished Jun 24 04:40:50 PM PDT 24
Peak memory 205900 kb
Host smart-21d3f14c-0097-4b45-a998-123172a2c4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096060655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3096060655
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.900410459
Short name T591
Test name
Test status
Simulation time 11496275 ps
CPU time 0.72 seconds
Started Jun 24 04:40:50 PM PDT 24
Finished Jun 24 04:40:53 PM PDT 24
Peak memory 205692 kb
Host smart-7ea04275-ba5a-4d96-9b69-9f4ee7f64527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900410459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.900410459
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2897828876
Short name T661
Test name
Test status
Simulation time 357193046 ps
CPU time 5.07 seconds
Started Jun 24 04:40:50 PM PDT 24
Finished Jun 24 04:40:57 PM PDT 24
Peak memory 224436 kb
Host smart-e2e6cd86-590a-4188-932c-fcf81087e4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897828876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2897828876
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3654538248
Short name T342
Test name
Test status
Simulation time 47200291 ps
CPU time 0.75 seconds
Started Jun 24 04:40:47 PM PDT 24
Finished Jun 24 04:40:50 PM PDT 24
Peak memory 205516 kb
Host smart-3fe7bec4-90e0-4880-845c-d9c5b5edafa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654538248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3654538248
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2572760918
Short name T954
Test name
Test status
Simulation time 1470227090 ps
CPU time 3.16 seconds
Started Jun 24 04:40:56 PM PDT 24
Finished Jun 24 04:41:05 PM PDT 24
Peak memory 217628 kb
Host smart-719137c7-1fe9-430e-9b4e-5f7f9bfdfbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572760918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2572760918
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.4290770567
Short name T961
Test name
Test status
Simulation time 5191646098 ps
CPU time 28.39 seconds
Started Jun 24 04:40:51 PM PDT 24
Finished Jun 24 04:41:21 PM PDT 24
Peak memory 217516 kb
Host smart-cc5c9642-7c18-4c67-85ae-7533f7126d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290770567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.4290770567
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.515542424
Short name T152
Test name
Test status
Simulation time 4721355873 ps
CPU time 30 seconds
Started Jun 24 04:40:47 PM PDT 24
Finished Jun 24 04:41:20 PM PDT 24
Peak memory 224624 kb
Host smart-b6139a9e-650a-40c0-aaa7-b4a8bc2f9b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515542424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.515542424
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3126795576
Short name T211
Test name
Test status
Simulation time 3150692975 ps
CPU time 26.37 seconds
Started Jun 24 04:40:47 PM PDT 24
Finished Jun 24 04:41:17 PM PDT 24
Peak memory 232808 kb
Host smart-6d5d0aa3-a6be-4228-ae2e-84f4f5aee4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126795576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3126795576
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3213321735
Short name T340
Test name
Test status
Simulation time 3283442583 ps
CPU time 40.2 seconds
Started Jun 24 04:40:50 PM PDT 24
Finished Jun 24 04:41:33 PM PDT 24
Peak memory 232792 kb
Host smart-da12d4b7-116d-4bef-87dc-871615b3c1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213321735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3213321735
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3361439473
Short name T267
Test name
Test status
Simulation time 43319416459 ps
CPU time 20.02 seconds
Started Jun 24 04:40:49 PM PDT 24
Finished Jun 24 04:41:11 PM PDT 24
Peak memory 232784 kb
Host smart-9963e499-7668-41b5-b8f3-15062b231196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361439473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3361439473
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.4053391509
Short name T896
Test name
Test status
Simulation time 4791570203 ps
CPU time 9.06 seconds
Started Jun 24 04:40:51 PM PDT 24
Finished Jun 24 04:41:02 PM PDT 24
Peak memory 248896 kb
Host smart-f89ca7e6-b94d-446f-b7bc-6c21530b1bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053391509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.4053391509
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1188151358
Short name T157
Test name
Test status
Simulation time 1584442239 ps
CPU time 12.48 seconds
Started Jun 24 04:40:50 PM PDT 24
Finished Jun 24 04:41:05 PM PDT 24
Peak memory 223104 kb
Host smart-8b38d2bf-6f85-452e-904e-efe0a46cb3d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1188151358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1188151358
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2311813473
Short name T138
Test name
Test status
Simulation time 153176096 ps
CPU time 0.91 seconds
Started Jun 24 04:40:47 PM PDT 24
Finished Jun 24 04:40:51 PM PDT 24
Peak memory 206588 kb
Host smart-ab50405c-c6c5-4870-8dcc-2b5208f80f32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311813473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2311813473
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.4132244677
Short name T680
Test name
Test status
Simulation time 21518652335 ps
CPU time 20.41 seconds
Started Jun 24 04:40:47 PM PDT 24
Finished Jun 24 04:41:11 PM PDT 24
Peak memory 216444 kb
Host smart-07250d97-6dc3-497e-bee5-c034553804cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132244677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.4132244677
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.563297918
Short name T668
Test name
Test status
Simulation time 2631212090 ps
CPU time 4.28 seconds
Started Jun 24 04:40:46 PM PDT 24
Finished Jun 24 04:40:54 PM PDT 24
Peak memory 216232 kb
Host smart-e8713daf-4f18-42ad-b9a8-2fabce1330fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563297918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.563297918
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2031086746
Short name T911
Test name
Test status
Simulation time 46993763 ps
CPU time 0.88 seconds
Started Jun 24 04:40:48 PM PDT 24
Finished Jun 24 04:40:52 PM PDT 24
Peak memory 207272 kb
Host smart-874d80ab-4926-445e-909b-29c66a43dd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031086746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2031086746
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2730888505
Short name T365
Test name
Test status
Simulation time 97104610 ps
CPU time 0.9 seconds
Started Jun 24 04:40:50 PM PDT 24
Finished Jun 24 04:40:54 PM PDT 24
Peak memory 206952 kb
Host smart-38200a18-7e0e-4851-bc04-7ff7f58546d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730888505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2730888505
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.244656005
Short name T597
Test name
Test status
Simulation time 2956189532 ps
CPU time 5.49 seconds
Started Jun 24 04:40:49 PM PDT 24
Finished Jun 24 04:40:57 PM PDT 24
Peak memory 232776 kb
Host smart-69bcfab2-b1e1-46e8-a301-a4271d8e40b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244656005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.244656005
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.612606040
Short name T918
Test name
Test status
Simulation time 13170035 ps
CPU time 0.77 seconds
Started Jun 24 04:40:55 PM PDT 24
Finished Jun 24 04:41:00 PM PDT 24
Peak memory 205652 kb
Host smart-6753d5ec-3c4c-419d-b0a1-82abb7e2088e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612606040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.612606040
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3422220414
Short name T804
Test name
Test status
Simulation time 1216443694 ps
CPU time 6.24 seconds
Started Jun 24 04:40:52 PM PDT 24
Finished Jun 24 04:41:01 PM PDT 24
Peak memory 224464 kb
Host smart-62e9ac6c-1530-44af-b324-a9e2d86b816e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422220414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3422220414
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3771461158
Short name T868
Test name
Test status
Simulation time 37207230 ps
CPU time 0.86 seconds
Started Jun 24 04:40:56 PM PDT 24
Finished Jun 24 04:41:03 PM PDT 24
Peak memory 206868 kb
Host smart-228842ff-6a4b-4c64-8a8b-e83f50398713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771461158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3771461158
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2876636958
Short name T462
Test name
Test status
Simulation time 36156618439 ps
CPU time 28.17 seconds
Started Jun 24 04:40:56 PM PDT 24
Finished Jun 24 04:41:30 PM PDT 24
Peak memory 224564 kb
Host smart-b0022a72-2fc4-4965-b963-ae79c616eb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876636958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2876636958
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3220141523
Short name T923
Test name
Test status
Simulation time 3582586758 ps
CPU time 65.22 seconds
Started Jun 24 04:40:55 PM PDT 24
Finished Jun 24 04:42:05 PM PDT 24
Peak memory 252688 kb
Host smart-591e1573-af21-4f04-bf68-ace1471c28c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220141523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3220141523
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3691045803
Short name T361
Test name
Test status
Simulation time 18039453905 ps
CPU time 51.3 seconds
Started Jun 24 04:40:56 PM PDT 24
Finished Jun 24 04:41:54 PM PDT 24
Peak memory 232984 kb
Host smart-483a5756-29bd-4877-b6dc-9278edca6735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691045803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3691045803
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2374224954
Short name T334
Test name
Test status
Simulation time 2805396304 ps
CPU time 19.65 seconds
Started Jun 24 04:40:49 PM PDT 24
Finished Jun 24 04:41:11 PM PDT 24
Peak memory 224528 kb
Host smart-1354c2a3-1302-458e-8410-c8b8329531eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374224954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2374224954
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2187532895
Short name T245
Test name
Test status
Simulation time 802081849 ps
CPU time 10.03 seconds
Started Jun 24 04:40:54 PM PDT 24
Finished Jun 24 04:41:08 PM PDT 24
Peak memory 224532 kb
Host smart-5c5b5ee4-b2dd-4fea-84cc-af8542c3e8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187532895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2187532895
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2758529823
Short name T759
Test name
Test status
Simulation time 1455677210 ps
CPU time 7.92 seconds
Started Jun 24 04:40:53 PM PDT 24
Finished Jun 24 04:41:04 PM PDT 24
Peak memory 232752 kb
Host smart-8ed07bda-3f49-43f3-9e74-99fa9c928deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758529823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2758529823
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.522313641
Short name T273
Test name
Test status
Simulation time 2106213978 ps
CPU time 4.97 seconds
Started Jun 24 04:40:54 PM PDT 24
Finished Jun 24 04:41:03 PM PDT 24
Peak memory 224376 kb
Host smart-cc38b4f6-c06e-4a9f-8c69-e3bd9c7c28ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522313641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
522313641
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1899474285
Short name T963
Test name
Test status
Simulation time 8022474610 ps
CPU time 10.97 seconds
Started Jun 24 04:40:51 PM PDT 24
Finished Jun 24 04:41:05 PM PDT 24
Peak memory 240976 kb
Host smart-30861d1e-bb93-4ee4-becf-008ef723463a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899474285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1899474285
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2168924386
Short name T418
Test name
Test status
Simulation time 245789659 ps
CPU time 5.01 seconds
Started Jun 24 04:40:51 PM PDT 24
Finished Jun 24 04:41:00 PM PDT 24
Peak memory 223208 kb
Host smart-e1f418a3-4deb-487b-8e4e-11ec6552737b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2168924386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2168924386
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1235123881
Short name T167
Test name
Test status
Simulation time 147189665 ps
CPU time 0.98 seconds
Started Jun 24 04:40:54 PM PDT 24
Finished Jun 24 04:40:59 PM PDT 24
Peak memory 206516 kb
Host smart-f402c6dd-cf71-4ac8-a188-6c04696b664e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235123881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1235123881
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2709447990
Short name T646
Test name
Test status
Simulation time 4373617632 ps
CPU time 20.37 seconds
Started Jun 24 04:40:51 PM PDT 24
Finished Jun 24 04:41:14 PM PDT 24
Peak memory 216428 kb
Host smart-72a02c8d-68f0-447e-a60b-387db34cbfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709447990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2709447990
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2785729799
Short name T390
Test name
Test status
Simulation time 7726803833 ps
CPU time 21.91 seconds
Started Jun 24 04:40:54 PM PDT 24
Finished Jun 24 04:41:19 PM PDT 24
Peak memory 216300 kb
Host smart-51495211-b88a-415e-a698-0d67994c8524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785729799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2785729799
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1562423214
Short name T935
Test name
Test status
Simulation time 325782981 ps
CPU time 4.08 seconds
Started Jun 24 04:40:52 PM PDT 24
Finished Jun 24 04:40:59 PM PDT 24
Peak memory 216284 kb
Host smart-8a6b57b7-24f1-4f83-824e-2ad5e78bc288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562423214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1562423214
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2695157333
Short name T406
Test name
Test status
Simulation time 174635235 ps
CPU time 1.03 seconds
Started Jun 24 04:40:55 PM PDT 24
Finished Jun 24 04:41:01 PM PDT 24
Peak memory 206924 kb
Host smart-4c4e3c29-c93f-4327-8a96-b7e207dffe23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695157333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2695157333
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1306146940
Short name T595
Test name
Test status
Simulation time 3231739181 ps
CPU time 18.42 seconds
Started Jun 24 04:40:52 PM PDT 24
Finished Jun 24 04:41:13 PM PDT 24
Peak memory 240768 kb
Host smart-94ec1df2-a28a-4230-a02b-b0a3e773fb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306146940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1306146940
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3086635340
Short name T778
Test name
Test status
Simulation time 12108519 ps
CPU time 0.75 seconds
Started Jun 24 04:40:58 PM PDT 24
Finished Jun 24 04:41:05 PM PDT 24
Peak memory 205356 kb
Host smart-28e0e4ed-7726-49db-9635-ccf4e98e337f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086635340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
086635340
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3329075301
Short name T260
Test name
Test status
Simulation time 1269915759 ps
CPU time 3.83 seconds
Started Jun 24 04:40:58 PM PDT 24
Finished Jun 24 04:41:08 PM PDT 24
Peak memory 232692 kb
Host smart-f13cc77d-db0e-4202-a1f5-89a885d60ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329075301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3329075301
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2812684066
Short name T664
Test name
Test status
Simulation time 12749746 ps
CPU time 0.76 seconds
Started Jun 24 04:40:55 PM PDT 24
Finished Jun 24 04:40:59 PM PDT 24
Peak memory 205636 kb
Host smart-0a333b25-6cbb-48bd-98e7-5cfceaf607ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812684066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2812684066
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1957427385
Short name T219
Test name
Test status
Simulation time 22972042462 ps
CPU time 158.83 seconds
Started Jun 24 04:40:57 PM PDT 24
Finished Jun 24 04:43:42 PM PDT 24
Peak memory 249308 kb
Host smart-ce46b1fa-7b64-4a54-8cdd-02510f0f9296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957427385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1957427385
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1965417989
Short name T87
Test name
Test status
Simulation time 39672870503 ps
CPU time 94.59 seconds
Started Jun 24 04:40:58 PM PDT 24
Finished Jun 24 04:42:39 PM PDT 24
Peak memory 250652 kb
Host smart-b85f9bb8-cf85-44e2-a4c6-8b7aca9ac9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965417989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1965417989
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2468365137
Short name T82
Test name
Test status
Simulation time 60847844071 ps
CPU time 151.44 seconds
Started Jun 24 04:40:57 PM PDT 24
Finished Jun 24 04:43:35 PM PDT 24
Peak memory 252292 kb
Host smart-eade813e-70e6-4aa3-9ad1-5e25688aca00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468365137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2468365137
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1848672083
Short name T10
Test name
Test status
Simulation time 377588173 ps
CPU time 7.31 seconds
Started Jun 24 04:40:54 PM PDT 24
Finished Jun 24 04:41:05 PM PDT 24
Peak memory 241088 kb
Host smart-bc836f92-3964-4a61-a180-b8c8711a6a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848672083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1848672083
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.4041512270
Short name T679
Test name
Test status
Simulation time 349610819 ps
CPU time 5.79 seconds
Started Jun 24 04:41:00 PM PDT 24
Finished Jun 24 04:41:13 PM PDT 24
Peak memory 232712 kb
Host smart-da422057-d75e-4e32-b206-247015fb9c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041512270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.4041512270
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2643066067
Short name T792
Test name
Test status
Simulation time 877366908 ps
CPU time 11.2 seconds
Started Jun 24 04:40:57 PM PDT 24
Finished Jun 24 04:41:14 PM PDT 24
Peak memory 233856 kb
Host smart-2cedbbeb-a5c6-43a2-9c97-5d6657ef3e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643066067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2643066067
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.331529967
Short name T639
Test name
Test status
Simulation time 972503068 ps
CPU time 5 seconds
Started Jun 24 04:40:57 PM PDT 24
Finished Jun 24 04:41:08 PM PDT 24
Peak memory 232668 kb
Host smart-ab1eb2f0-a90c-4496-a23e-05f73ed91400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331529967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
331529967
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.741729873
Short name T499
Test name
Test status
Simulation time 880924843 ps
CPU time 4.36 seconds
Started Jun 24 04:40:56 PM PDT 24
Finished Jun 24 04:41:06 PM PDT 24
Peak memory 232684 kb
Host smart-3a3eb9de-82d7-4c15-acfd-2a5a3a2cc1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741729873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.741729873
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.4119260458
Short name T788
Test name
Test status
Simulation time 730296721 ps
CPU time 6.67 seconds
Started Jun 24 04:40:56 PM PDT 24
Finished Jun 24 04:41:09 PM PDT 24
Peak memory 220028 kb
Host smart-5f4f00ce-be7b-44ab-97aa-24eb97bd4c8b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4119260458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.4119260458
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3508080183
Short name T936
Test name
Test status
Simulation time 247784894007 ps
CPU time 184.17 seconds
Started Jun 24 04:40:54 PM PDT 24
Finished Jun 24 04:44:02 PM PDT 24
Peak memory 257512 kb
Host smart-fd65f127-2364-48fa-9829-ea631dea2648
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508080183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3508080183
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1138244148
Short name T644
Test name
Test status
Simulation time 2634261454 ps
CPU time 4.87 seconds
Started Jun 24 04:40:56 PM PDT 24
Finished Jun 24 04:41:06 PM PDT 24
Peak memory 216460 kb
Host smart-a9c31a57-8d84-4760-b786-ff1037be9ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138244148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1138244148
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3085352250
Short name T714
Test name
Test status
Simulation time 4750713568 ps
CPU time 10.27 seconds
Started Jun 24 04:41:02 PM PDT 24
Finished Jun 24 04:41:20 PM PDT 24
Peak memory 216320 kb
Host smart-fe5a1fcf-7954-4587-aeed-22a1ecc08a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085352250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3085352250
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.355274853
Short name T626
Test name
Test status
Simulation time 107234935 ps
CPU time 1.35 seconds
Started Jun 24 04:40:53 PM PDT 24
Finished Jun 24 04:40:57 PM PDT 24
Peak memory 207968 kb
Host smart-45ac5d69-4a6d-4741-ab56-a5f008d3f8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355274853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.355274853
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.430419521
Short name T569
Test name
Test status
Simulation time 137445296 ps
CPU time 0.79 seconds
Started Jun 24 04:40:55 PM PDT 24
Finished Jun 24 04:41:01 PM PDT 24
Peak memory 205904 kb
Host smart-515e5274-80cd-433d-b7d4-cadddc23a7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430419521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.430419521
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.789924263
Short name T774
Test name
Test status
Simulation time 787421578 ps
CPU time 3.08 seconds
Started Jun 24 04:40:58 PM PDT 24
Finished Jun 24 04:41:08 PM PDT 24
Peak memory 224548 kb
Host smart-68a53d89-643d-47e0-a183-e8b8efecce51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789924263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.789924263
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1325784036
Short name T526
Test name
Test status
Simulation time 27075297 ps
CPU time 0.7 seconds
Started Jun 24 04:41:00 PM PDT 24
Finished Jun 24 04:41:08 PM PDT 24
Peak memory 205668 kb
Host smart-0d1d5556-db44-4f3a-b6f4-eb963f4796bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325784036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
325784036
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1796557420
Short name T712
Test name
Test status
Simulation time 86180971 ps
CPU time 2.52 seconds
Started Jun 24 04:40:58 PM PDT 24
Finished Jun 24 04:41:07 PM PDT 24
Peak memory 224496 kb
Host smart-ee6b5a8d-34b8-46b1-a60b-160888903a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796557420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1796557420
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.4020759386
Short name T654
Test name
Test status
Simulation time 69208671 ps
CPU time 0.8 seconds
Started Jun 24 04:40:54 PM PDT 24
Finished Jun 24 04:40:59 PM PDT 24
Peak memory 206816 kb
Host smart-3c6204eb-9755-4d74-8879-17786cda43da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020759386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.4020759386
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3313709168
Short name T725
Test name
Test status
Simulation time 291633669 ps
CPU time 5.49 seconds
Started Jun 24 04:40:59 PM PDT 24
Finished Jun 24 04:41:12 PM PDT 24
Peak memory 232668 kb
Host smart-76ac5eed-9185-464b-8ceb-aa881732ae41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313709168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3313709168
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3155520412
Short name T262
Test name
Test status
Simulation time 44829153844 ps
CPU time 384.63 seconds
Started Jun 24 04:40:58 PM PDT 24
Finished Jun 24 04:47:29 PM PDT 24
Peak memory 257432 kb
Host smart-a5cc04b7-1307-41c9-ab84-47105b49b442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155520412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3155520412
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.4095991770
Short name T777
Test name
Test status
Simulation time 9199961531 ps
CPU time 68.9 seconds
Started Jun 24 04:40:56 PM PDT 24
Finished Jun 24 04:42:11 PM PDT 24
Peak memory 265108 kb
Host smart-8fa0496c-b4e1-45e6-be29-799437477f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095991770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.4095991770
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_intercept.683168557
Short name T417
Test name
Test status
Simulation time 939138733 ps
CPU time 11.26 seconds
Started Jun 24 04:40:58 PM PDT 24
Finished Jun 24 04:41:16 PM PDT 24
Peak memory 224432 kb
Host smart-b73a587f-9143-441d-85a8-ec5f81f23194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683168557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.683168557
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3547424922
Short name T594
Test name
Test status
Simulation time 22983182472 ps
CPU time 52.77 seconds
Started Jun 24 04:41:00 PM PDT 24
Finished Jun 24 04:42:00 PM PDT 24
Peak memory 249224 kb
Host smart-9ba70442-c5fe-4dc0-a494-bb30354c309c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547424922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3547424922
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3294148382
Short name T286
Test name
Test status
Simulation time 889714093 ps
CPU time 10 seconds
Started Jun 24 04:40:56 PM PDT 24
Finished Jun 24 04:41:13 PM PDT 24
Peak memory 237552 kb
Host smart-2e0937ae-d7cf-44ea-aa96-a0616aabcbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294148382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3294148382
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2168780254
Short name T874
Test name
Test status
Simulation time 4095911307 ps
CPU time 8.66 seconds
Started Jun 24 04:41:00 PM PDT 24
Finished Jun 24 04:41:16 PM PDT 24
Peak memory 232764 kb
Host smart-973f8557-3ef7-43a1-a22b-8965a8d7cda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168780254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2168780254
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.600389708
Short name T814
Test name
Test status
Simulation time 1938353017 ps
CPU time 8.11 seconds
Started Jun 24 04:40:56 PM PDT 24
Finished Jun 24 04:41:11 PM PDT 24
Peak memory 223152 kb
Host smart-21eb7375-9b22-4c7d-a0ec-e32148e0e66e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=600389708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.600389708
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3079341780
Short name T16
Test name
Test status
Simulation time 7786390089 ps
CPU time 54.67 seconds
Started Jun 24 04:40:59 PM PDT 24
Finished Jun 24 04:42:00 PM PDT 24
Peak memory 253844 kb
Host smart-d2ca3c4d-cd41-4a63-89a2-d906cfe18ef1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079341780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3079341780
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.4232921299
Short name T610
Test name
Test status
Simulation time 1968117082 ps
CPU time 9.79 seconds
Started Jun 24 04:41:00 PM PDT 24
Finished Jun 24 04:41:17 PM PDT 24
Peak memory 216220 kb
Host smart-fd1aefec-86da-4391-8419-a6fb7e108137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232921299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4232921299
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3511056565
Short name T509
Test name
Test status
Simulation time 1908386573 ps
CPU time 8.44 seconds
Started Jun 24 04:40:58 PM PDT 24
Finished Jun 24 04:41:13 PM PDT 24
Peak memory 216108 kb
Host smart-f5faddfd-627d-416e-bdd2-3e8c48879e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511056565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3511056565
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2675966624
Short name T849
Test name
Test status
Simulation time 37007417 ps
CPU time 0.78 seconds
Started Jun 24 04:41:02 PM PDT 24
Finished Jun 24 04:41:10 PM PDT 24
Peak memory 205928 kb
Host smart-e8f5028f-66be-4366-9f4d-7bd178106161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675966624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2675966624
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2489546419
Short name T619
Test name
Test status
Simulation time 19149675 ps
CPU time 0.69 seconds
Started Jun 24 04:40:57 PM PDT 24
Finished Jun 24 04:41:04 PM PDT 24
Peak memory 205524 kb
Host smart-c27482cd-870b-41cf-b75e-342af352fe3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489546419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2489546419
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.123605153
Short name T41
Test name
Test status
Simulation time 2048983210 ps
CPU time 4.95 seconds
Started Jun 24 04:40:53 PM PDT 24
Finished Jun 24 04:41:00 PM PDT 24
Peak memory 224484 kb
Host smart-a9efca27-95fc-403b-83f1-6200224ca0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123605153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.123605153
Directory /workspace/9.spi_device_upload/latest
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