Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3464766	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3792563

1

T1

8949

T2

24031

T3

875

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4072841	1			T1	3822		T2	29585		T3	4
values[0x0]	1591806	1			T1	3481		T2	11710		T3	432
values[0x1]	1592682	1			T1	3559		T2	11880		T3	443

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2451684	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4805645

1

T1

9321

T2

33175

T3

876

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27656	1			T2	251		T4	18		T5	116
valid_sources[0x01]	26382	1			T2	238		T5	104		T6	6
valid_sources[0x02]	27188	1			T2	198		T3	25		T5	94
valid_sources[0x03]	27175	1			T2	326		T4	28		T5	116
valid_sources[0x04]	29666	1			T2	164		T5	104		T6	4
valid_sources[0x05]	24915	1			T1	2		T2	193		T4	45
valid_sources[0x06]	32006	1			T2	219		T4	39		T5	96
valid_sources[0x07]	27990	1			T2	260		T4	19		T5	103
valid_sources[0x08]	26452	1			T2	207		T4	1		T5	101
valid_sources[0x09]	27857	1			T2	207		T5	100		T8	1
valid_sources[0x0a]	27872	1			T2	241		T4	6		T5	116
valid_sources[0x0b]	28693	1			T2	330		T5	102		T6	4
valid_sources[0x0c]	26538	1			T2	192		T3	19		T5	111
valid_sources[0x0d]	26092	1			T2	174		T3	35		T4	43
valid_sources[0x0e]	47163	1			T2	233		T4	55		T5	105
valid_sources[0x0f]	29803	1			T1	1033		T2	212		T4	20
valid_sources[0x10]	30176	1			T1	1		T2	262		T4	20
valid_sources[0x11]	29265	1			T2	266		T4	9		T5	90
valid_sources[0x12]	26834	1			T2	175		T4	23		T5	90
valid_sources[0x13]	25394	1			T2	173		T5	132		T6	13
valid_sources[0x14]	25111	1			T2	234		T3	6		T4	23
valid_sources[0x15]	36685	1			T2	192		T4	20		T5	109
valid_sources[0x16]	27718	1			T2	175		T4	4		T5	107
valid_sources[0x17]	26655	1			T2	115		T3	15		T4	30
valid_sources[0x18]	29202	1			T2	203		T4	10		T5	91
valid_sources[0x19]	29622	1			T2	217		T4	46		T5	115
valid_sources[0x1a]	25688	1			T2	263		T4	13		T5	108
valid_sources[0x1b]	53005	1			T2	278		T4	37		T5	102
valid_sources[0x1c]	28233	1			T2	229		T4	116		T5	89
valid_sources[0x1d]	25931	1			T2	286		T4	34		T5	116
valid_sources[0x1e]	30042	1			T2	159		T4	16		T5	97
valid_sources[0x1f]	26963	1			T2	234		T4	3		T5	102
valid_sources[0x20]	25324	1			T2	190		T4	4		T5	120
valid_sources[0x21]	26660	1			T2	212		T5	113		T6	5
valid_sources[0x22]	27290	1			T1	2		T2	187		T3	87
valid_sources[0x23]	25838	1			T1	1		T2	193		T4	19
valid_sources[0x24]	26730	1			T2	191		T5	107		T6	3
valid_sources[0x25]	25539	1			T2	178		T4	70		T5	119
valid_sources[0x26]	29243	1			T2	186		T4	33		T5	114
valid_sources[0x27]	28461	1			T1	1		T2	189		T3	9
valid_sources[0x28]	25832	1			T2	156		T3	14		T4	203
valid_sources[0x29]	26272	1			T2	221		T5	114		T6	7
valid_sources[0x2a]	26659	1			T2	198		T4	101		T5	124
valid_sources[0x2b]	29298	1			T1	889		T2	174		T5	101
valid_sources[0x2c]	24858	1			T2	178		T5	95		T6	3
valid_sources[0x2d]	27077	1			T2	247		T4	39		T5	106
valid_sources[0x2e]	24032	1			T2	222		T4	10		T5	98
valid_sources[0x2f]	32226	1			T2	212		T5	110		T6	21
valid_sources[0x30]	27013	1			T1	1		T2	183		T4	4
valid_sources[0x31]	27600	1			T2	280		T3	10		T4	29
valid_sources[0x32]	28217	1			T2	198		T4	38		T5	97
valid_sources[0x33]	26741	1			T2	157		T4	27		T5	104
valid_sources[0x34]	31171	1			T2	246		T3	11		T4	74
valid_sources[0x35]	30562	1			T2	144		T4	116		T5	110
valid_sources[0x36]	28061	1			T2	259		T3	9		T4	69
valid_sources[0x37]	24324	1			T2	151		T3	31		T4	52
valid_sources[0x38]	29157	1			T2	224		T4	115		T5	125
valid_sources[0x39]	29063	1			T2	166		T5	113		T6	9
valid_sources[0x3a]	27071	1			T1	1		T2	213		T4	96
valid_sources[0x3b]	24300	1			T2	92		T4	4		T5	117
valid_sources[0x3c]	29055	1			T2	176		T4	3		T5	124
valid_sources[0x3d]	30174	1			T2	199		T3	35		T4	71
valid_sources[0x3e]	26409	1			T2	150		T4	56		T5	83
valid_sources[0x3f]	28642	1			T2	224		T4	14		T5	91
valid_sources[0x40]	26355	1			T2	221		T4	78		T5	114
valid_sources[0x41]	33225	1			T2	155		T4	11		T5	113
valid_sources[0x42]	27792	1			T2	237		T5	138		T9	5
valid_sources[0x43]	29332	1			T2	286		T4	23		T5	97
valid_sources[0x44]	32589	1			T2	259		T4	25		T5	111
valid_sources[0x45]	26798	1			T2	237		T4	13		T5	100
valid_sources[0x46]	30100	1			T2	175		T4	24		T5	98
valid_sources[0x47]	23576	1			T1	1		T2	173		T4	35
valid_sources[0x48]	29601	1			T1	2		T2	196		T4	43
valid_sources[0x49]	27611	1			T2	298		T4	113		T5	125
valid_sources[0x4a]	28095	1			T2	175		T4	70		T5	105
valid_sources[0x4b]	26466	1			T2	185		T4	50		T5	129
valid_sources[0x4c]	28879	1			T2	205		T3	1		T4	10
valid_sources[0x4d]	28730	1			T2	198		T4	8		T5	114
valid_sources[0x4e]	26356	1			T2	195		T4	37		T5	91
valid_sources[0x4f]	38250	1			T2	171		T4	34		T5	122
valid_sources[0x50]	29063	1			T2	180		T4	4		T5	138
valid_sources[0x51]	30509	1			T2	222		T4	183		T5	101
valid_sources[0x52]	27093	1			T1	416		T2	230		T4	36
valid_sources[0x53]	26419	1			T1	416		T2	122		T4	12
valid_sources[0x54]	27699	1			T1	1605		T2	240		T4	4
valid_sources[0x55]	26269	1			T2	175		T3	41		T4	1
valid_sources[0x56]	26394	1			T2	167		T4	41		T5	113
valid_sources[0x57]	28020	1			T2	219		T4	4		T5	97
valid_sources[0x58]	27941	1			T2	210		T4	25		T5	97
valid_sources[0x59]	26881	1			T1	1080		T2	188		T4	5
valid_sources[0x5a]	26070	1			T2	275		T3	30		T4	92
valid_sources[0x5b]	28141	1			T2	178		T4	30		T5	113
valid_sources[0x5c]	23477	1			T2	253		T3	22		T4	14
valid_sources[0x5d]	26225	1			T2	225		T5	113		T6	7
valid_sources[0x5e]	28003	1			T2	211		T4	8		T5	112
valid_sources[0x5f]	31755	1			T2	213		T3	12		T4	77
valid_sources[0x60]	27193	1			T2	256		T3	24		T4	50
valid_sources[0x61]	24950	1			T2	183		T5	130		T6	16
valid_sources[0x62]	28973	1			T2	113		T4	42		T5	76
valid_sources[0x63]	46678	1			T2	170		T4	93		T5	129
valid_sources[0x64]	31089	1			T1	1		T2	217		T4	41
valid_sources[0x65]	29435	1			T2	158		T4	18		T5	91
valid_sources[0x66]	32775	1			T2	207		T4	3		T5	110
valid_sources[0x67]	27455	1			T2	257		T4	5		T5	92
valid_sources[0x68]	28588	1			T2	223		T4	172		T5	114
valid_sources[0x69]	30134	1			T2	149		T3	8		T4	12
valid_sources[0x6a]	29237	1			T2	226		T4	8		T5	82
valid_sources[0x6b]	27230	1			T2	279		T4	36		T5	119
valid_sources[0x6c]	41463	1			T2	124		T4	51		T5	144
valid_sources[0x6d]	25969	1			T2	237		T4	2		T5	122
valid_sources[0x6e]	26145	1			T2	180		T4	60		T5	96
valid_sources[0x6f]	24007	1			T2	172		T3	28		T4	35
valid_sources[0x70]	26499	1			T2	144		T4	19		T5	114
valid_sources[0x71]	27192	1			T1	1		T2	176		T4	17
valid_sources[0x72]	26347	1			T1	416		T2	193		T4	13
valid_sources[0x73]	28031	1			T2	188		T3	33		T4	117
valid_sources[0x74]	27151	1			T2	169		T3	11		T4	16
valid_sources[0x75]	26477	1			T2	258		T4	70		T5	108
valid_sources[0x76]	28104	1			T2	169		T4	65		T5	101
valid_sources[0x77]	28435	1			T1	55		T2	184		T4	27
valid_sources[0x78]	30582	1			T2	263		T5	127		T8	3
valid_sources[0x79]	32630	1			T1	1494		T2	266		T4	117
valid_sources[0x7a]	25559	1			T2	213		T4	3		T5	116
valid_sources[0x7b]	28155	1			T2	320		T5	122		T6	17
valid_sources[0x7c]	24965	1			T2	258		T4	73		T5	120
valid_sources[0x7d]	32690	1			T2	252		T4	3		T5	120
valid_sources[0x7e]	27072	1			T2	243		T4	21		T5	104
valid_sources[0x7f]	28532	1			T2	221		T4	112		T5	100
valid_sources[0x80]	26170	1			T2	258		T4	12		T5	100

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

934363

1

T1

1946

T2

3104

T3

2

values[0x0]

all_enables

biggest_size

1440221

1

T1

3470

T2

10401

T3

432

values[0x1]

all_enables

biggest_size

1417979

1

T1

3533

T2

10526

T3

441