Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3486293

1

T1

1913

T2

29144

T3

4

full_word

3793755

1

T1

8949

T2

24031

T3

875

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7279618	1			T1	10862		T2	53175		T3	879
auto[TlIntgErrCmd]	131	1			T53	7		T78	13		T79	6
auto[TlIntgErrData]	143	1			T53	10		T78	10		T79	1
auto[TlIntgErrBoth]	156	1			T53	3		T78	7		T79	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4076109

1

T1

3822

T2

29585

T3

4

auto[1]

3203939

1

T1

7040

T2

23590

T3

875

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3141282	1			T1	1876		T2	26481		T3	2
auto[TlIntgErrNone]	partial	auto[1]	344612	1			T1	37		T2	2663		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	934633	1			T1	1946		T2	3104		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	2859091	1			T1	7003		T2	20927		T3	873
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T53	3		T78	10		T79	2
auto[TlIntgErrCmd]	partial	auto[1]	77	1			T53	4		T78	2		T79	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T149	1		T150	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T78	1		T151	1		T150	1
auto[TlIntgErrData]	partial	auto[0]	73	1			T53	5		T78	6		T91	3
auto[TlIntgErrData]	partial	auto[1]	54	1			T53	3		T78	3		T79	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T53	1		T91	1		T124	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T53	1		T78	1		T91	2
auto[TlIntgErrBoth]	partial	auto[0]	61	1			T53	1		T78	1		T91	1
auto[TlIntgErrBoth]	partial	auto[1]	85	1			T53	2		T78	6		T79	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T152	1		T153	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T79	1		T149	1		T148	1