Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	408007305	2400661	0	0
DepthKnown_A	408007305	407875075	0	0
RvalidKnown_A	408007305	407875075	0	0
WreadyKnown_A	408007305	407875075	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	2400661	0	0
T1	252241	10811	0	0
T2	364151	10814	0	0
T3	15479	1663	0	0
T4	359769	0	0	0
T5	919395	8318	0	0
T6	15692	1663	0	0
T7	451307	832	0	0
T8	5151	1664	0	0
T9	14311	1663	0	0
T10	27433	832	0	0
T11	0	2685	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	407875075	0	0
T1	252241	252232	0	0
T2	364151	364142	0	0
T3	15479	15383	0	0
T4	359769	359705	0	0
T5	919395	919321	0	0
T6	15692	15599	0	0
T7	451307	451248	0	0
T8	5151	5055	0	0
T9	14311	14253	0	0
T10	27433	27379	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	407875075	0	0
T1	252241	252232	0	0
T2	364151	364142	0	0
T3	15479	15383	0	0
T4	359769	359705	0	0
T5	919395	919321	0	0
T6	15692	15599	0	0
T7	451307	451248	0	0
T8	5151	5055	0	0
T9	14311	14253	0	0
T10	27433	27379	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	407875075	0	0
T1	252241	252232	0	0
T2	364151	364142	0	0
T3	15479	15383	0	0
T4	359769	359705	0	0
T5	919395	919321	0	0
T6	15692	15599	0	0
T7	451307	451248	0	0
T8	5151	5055	0	0
T9	14311	14253	0	0
T10	27433	27379	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	408007305	2692546	0	0
DepthKnown_A	408007305	407875075	0	0
RvalidKnown_A	408007305	407875075	0	0
WreadyKnown_A	408007305	407875075	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	2692546	0	0
T1	252241	6656	0	0
T2	364151	25089	0	0
T3	15479	832	0	0
T4	359769	0	0	0
T5	919395	6656	0	0
T6	15692	832	0	0
T7	451307	3688	0	0
T8	5151	833	0	0
T9	14311	832	0	0
T10	27433	832	0	0
T11	0	1344	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	407875075	0	0
T1	252241	252232	0	0
T2	364151	364142	0	0
T3	15479	15383	0	0
T4	359769	359705	0	0
T5	919395	919321	0	0
T6	15692	15599	0	0
T7	451307	451248	0	0
T8	5151	5055	0	0
T9	14311	14253	0	0
T10	27433	27379	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	407875075	0	0
T1	252241	252232	0	0
T2	364151	364142	0	0
T3	15479	15383	0	0
T4	359769	359705	0	0
T5	919395	919321	0	0
T6	15692	15599	0	0
T7	451307	451248	0	0
T8	5151	5055	0	0
T9	14311	14253	0	0
T10	27433	27379	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	407875075	0	0
T1	252241	252232	0	0
T2	364151	364142	0	0
T3	15479	15383	0	0
T4	359769	359705	0	0
T5	919395	919321	0	0
T6	15692	15599	0	0
T7	451307	451248	0	0
T8	5151	5055	0	0
T9	14311	14253	0	0
T10	27433	27379	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	408007305	169954	0	0
DepthKnown_A	408007305	407875075	0	0
RvalidKnown_A	408007305	407875075	0	0
WreadyKnown_A	408007305	407875075	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	169954	0	0
T1	252241	126	0	0
T2	364151	439	0	0
T3	15479	0	0	0
T4	359769	851	0	0
T5	919395	1386	0	0
T6	15692	0	0	0
T7	451307	18	0	0
T8	5151	0	0	0
T9	14311	0	0	0
T10	27433	0	0	0
T12	0	32	0	0
T22	0	788	0	0
T23	0	852	0	0
T24	0	97	0	0
T31	0	839	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	407875075	0	0
T1	252241	252232	0	0
T2	364151	364142	0	0
T3	15479	15383	0	0
T4	359769	359705	0	0
T5	919395	919321	0	0
T6	15692	15599	0	0
T7	451307	451248	0	0
T8	5151	5055	0	0
T9	14311	14253	0	0
T10	27433	27379	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	407875075	0	0
T1	252241	252232	0	0
T2	364151	364142	0	0
T3	15479	15383	0	0
T4	359769	359705	0	0
T5	919395	919321	0	0
T6	15692	15599	0	0
T7	451307	451248	0	0
T8	5151	5055	0	0
T9	14311	14253	0	0
T10	27433	27379	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	407875075	0	0
T1	252241	252232	0	0
T2	364151	364142	0	0
T3	15479	15383	0	0
T4	359769	359705	0	0
T5	919395	919321	0	0
T6	15692	15599	0	0
T7	451307	451248	0	0
T8	5151	5055	0	0
T9	14311	14253	0	0
T10	27433	27379	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	408007305	407209	0	0
DepthKnown_A	408007305	407875075	0	0
RvalidKnown_A	408007305	407875075	0	0
WreadyKnown_A	408007305	407875075	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	407209	0	0
T1	252241	126	0	0
T2	364151	1419	0	0
T3	15479	0	0	0
T4	359769	2615	0	0
T5	919395	1383	0	0
T6	15692	0	0	0
T7	451307	113	0	0
T8	5151	0	0	0
T9	14311	0	0	0
T10	27433	0	0	0
T12	0	32	0	0
T22	0	3571	0	0
T23	0	852	0	0
T24	0	97	0	0
T31	0	839	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	407875075	0	0
T1	252241	252232	0	0
T2	364151	364142	0	0
T3	15479	15383	0	0
T4	359769	359705	0	0
T5	919395	919321	0	0
T6	15692	15599	0	0
T7	451307	451248	0	0
T8	5151	5055	0	0
T9	14311	14253	0	0
T10	27433	27379	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	407875075	0	0
T1	252241	252232	0	0
T2	364151	364142	0	0
T3	15479	15383	0	0
T4	359769	359705	0	0
T5	919395	919321	0	0
T6	15692	15599	0	0
T7	451307	451248	0	0
T8	5151	5055	0	0
T9	14311	14253	0	0
T10	27433	27379	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	407875075	0	0
T1	252241	252232	0	0
T2	364151	364142	0	0
T3	15479	15383	0	0
T4	359769	359705	0	0
T5	919395	919321	0	0
T6	15692	15599	0	0
T7	451307	451248	0	0
T8	5151	5055	0	0
T9	14311	14253	0	0
T10	27433	27379	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	408007305	6011925	0	0
DepthKnown_A	408007305	407875075	0	0
RvalidKnown_A	408007305	407875075	0	0
WreadyKnown_A	408007305	407875075	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	6011925	0	0
T1	252241	4082	0	0
T2	364151	46044	0	0
T3	15479	47	0	0
T4	359769	7549	0	0
T5	919395	20014	0	0
T6	15692	750	0	0
T7	451307	765	0	0
T8	5151	153	0	0
T9	14311	435	0	0
T10	27433	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	407875075	0	0
T1	252241	252232	0	0
T2	364151	364142	0	0
T3	15479	15383	0	0
T4	359769	359705	0	0
T5	919395	919321	0	0
T6	15692	15599	0	0
T7	451307	451248	0	0
T8	5151	5055	0	0
T9	14311	14253	0	0
T10	27433	27379	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	407875075	0	0
T1	252241	252232	0	0
T2	364151	364142	0	0
T3	15479	15383	0	0
T4	359769	359705	0	0
T5	919395	919321	0	0
T6	15692	15599	0	0
T7	451307	451248	0	0
T8	5151	5055	0	0
T9	14311	14253	0	0
T10	27433	27379	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	407875075	0	0
T1	252241	252232	0	0
T2	364151	364142	0	0
T3	15479	15383	0	0
T4	359769	359705	0	0
T5	919395	919321	0	0
T6	15692	15599	0	0
T7	451307	451248	0	0
T8	5151	5055	0	0
T9	14311	14253	0	0
T10	27433	27379	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	408007305	13879459	0	0
DepthKnown_A	408007305	407875075	0	0
RvalidKnown_A	408007305	407875075	0	0
WreadyKnown_A	408007305	407875075	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	13879459	0	0
T1	252241	4080	0	0
T2	364151	134818	0	0
T3	15479	47	0	0
T4	359769	23050	0	0
T5	919395	19897	0	0
T6	15692	750	0	0
T7	451307	3374	0	0
T8	5151	457	0	0
T9	14311	1795	0	0
T10	27433	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	407875075	0	0
T1	252241	252232	0	0
T2	364151	364142	0	0
T3	15479	15383	0	0
T4	359769	359705	0	0
T5	919395	919321	0	0
T6	15692	15599	0	0
T7	451307	451248	0	0
T8	5151	5055	0	0
T9	14311	14253	0	0
T10	27433	27379	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	407875075	0	0
T1	252241	252232	0	0
T2	364151	364142	0	0
T3	15479	15383	0	0
T4	359769	359705	0	0
T5	919395	919321	0	0
T6	15692	15599	0	0
T7	451307	451248	0	0
T8	5151	5055	0	0
T9	14311	14253	0	0
T10	27433	27379	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408007305	407875075	0	0
T1	252241	252232	0	0
T2	364151	364142	0	0
T3	15479	15383	0	0
T4	359769	359705	0	0
T5	919395	919321	0	0
T6	15692	15599	0	0
T7	451307	451248	0	0
T8	5151	5055	0	0
T9	14311	14253	0	0
T10	27433	27379	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0