Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.05	100.00	85.19			100.00	75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
90.97	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	652477808	527620603	0	0
CheckNGreaterZero_A	2718	2718	0	0
GntImpliesReady_A	652477808	3149699	0	0
GntImpliesValid_A	652477808	3149699	0	0
GrantKnown_A	652477808	527620603	0	0
IdxKnown_A	652477808	527620603	0	0
IndexIsCorrect_A	652477808	3149699	0	0
LockArbDecision_A	652477808	0	0	0
NoReadyValidNoGrant_A	652477808	0	0	0
ReadyAndValidImplyGrant_A	652477808	3149699	0	0
ReqAndReadyImplyGrant_A	652477808	3149699	0	0
ReqImpliesValid_A	652477808	3149699	0	0
ReqStaysHighUntilGranted0_M	652477808	0	0	0
RoundRobin_A	652477808	0	0	906
ValidKnown_A	652477808	527620603	0	0
gen_data_port_assertion.DataFlow_A	652477808	3149699	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652477808	527620603	0	0
T1	750559	748357	0	0
T2	1792575	1071598	0	0
T3	23743	19515	0	0
T4	591275	472945	0	0
T5	2618641	1762294	0	0
T6	40412	27959	0	0
T7	595823	523506	0	0
T8	5751	5119	0	0
T9	71825	42293	0	0
T10	189917	108621	0	0
T11	25424	25424	0	0
T22	0	144576	0	0
T23	0	103936	0	0
T26	0	108848	0	0
T27	0	109256	0	0
T31	0	120696	0	0
T32	0	2480	0	0
T33	0	36488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2718	2718	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652477808	3149699	0	0
T1	750559	7572	0	0
T2	1792575	12880	0	0
T3	23743	832	0	0
T4	591275	6516	0	0
T5	2618641	20416	0	0
T6	40412	832	0	0
T7	595823	940	0	0
T8	5751	832	0	0
T9	71825	832	0	0
T10	189917	832	0	0
T11	25424	0	0	0
T12	0	140	0	0
T14	0	7870	0	0
T15	0	5557	0	0
T22	0	4479	0	0
T23	0	6634	0	0
T24	0	396	0	0
T27	0	3522	0	0
T31	0	5182	0	0
T32	0	107	0	0
T42	0	188	0	0
T43	0	2	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652477808	3149699	0	0
T1	750559	7572	0	0
T2	1792575	12880	0	0
T3	23743	832	0	0
T4	591275	6516	0	0
T5	2618641	20416	0	0
T6	40412	832	0	0
T7	595823	940	0	0
T8	5751	832	0	0
T9	71825	832	0	0
T10	189917	832	0	0
T11	25424	0	0	0
T12	0	140	0	0
T14	0	7870	0	0
T15	0	5557	0	0
T22	0	4479	0	0
T23	0	6634	0	0
T24	0	396	0	0
T27	0	3522	0	0
T31	0	5182	0	0
T32	0	107	0	0
T42	0	188	0	0
T43	0	2	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652477808	527620603	0	0
T1	750559	748357	0	0
T2	1792575	1071598	0	0
T3	23743	19515	0	0
T4	591275	472945	0	0
T5	2618641	1762294	0	0
T6	40412	27959	0	0
T7	595823	523506	0	0
T8	5751	5119	0	0
T9	71825	42293	0	0
T10	189917	108621	0	0
T11	25424	25424	0	0
T22	0	144576	0	0
T23	0	103936	0	0
T26	0	108848	0	0
T27	0	109256	0	0
T31	0	120696	0	0
T32	0	2480	0	0
T33	0	36488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652477808	527620603	0	0
T1	750559	748357	0	0
T2	1792575	1071598	0	0
T3	23743	19515	0	0
T4	591275	472945	0	0
T5	2618641	1762294	0	0
T6	40412	27959	0	0
T7	595823	523506	0	0
T8	5751	5119	0	0
T9	71825	42293	0	0
T10	189917	108621	0	0
T11	25424	25424	0	0
T22	0	144576	0	0
T23	0	103936	0	0
T26	0	108848	0	0
T27	0	109256	0	0
T31	0	120696	0	0
T32	0	2480	0	0
T33	0	36488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652477808	3149699	0	0
T1	750559	7572	0	0
T2	1792575	12880	0	0
T3	23743	832	0	0
T4	591275	6516	0	0
T5	2618641	20416	0	0
T6	40412	832	0	0
T7	595823	940	0	0
T8	5751	832	0	0
T9	71825	832	0	0
T10	189917	832	0	0
T11	25424	0	0	0
T12	0	140	0	0
T14	0	7870	0	0
T15	0	5557	0	0
T22	0	4479	0	0
T23	0	6634	0	0
T24	0	396	0	0
T27	0	3522	0	0
T31	0	5182	0	0
T32	0	107	0	0
T42	0	188	0	0
T43	0	2	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652477808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652477808	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652477808	3149699	0	0
T1	750559	7572	0	0
T2	1792575	12880	0	0
T3	23743	832	0	0
T4	591275	6516	0	0
T5	2618641	20416	0	0
T6	40412	832	0	0
T7	595823	940	0	0
T8	5751	832	0	0
T9	71825	832	0	0
T10	189917	832	0	0
T11	25424	0	0	0
T12	0	140	0	0
T14	0	7870	0	0
T15	0	5557	0	0
T22	0	4479	0	0
T23	0	6634	0	0
T24	0	396	0	0
T27	0	3522	0	0
T31	0	5182	0	0
T32	0	107	0	0
T42	0	188	0	0
T43	0	2	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652477808	3149699	0	0
T1	750559	7572	0	0
T2	1792575	12880	0	0
T3	23743	832	0	0
T4	591275	6516	0	0
T5	2618641	20416	0	0
T6	40412	832	0	0
T7	595823	940	0	0
T8	5751	832	0	0
T9	71825	832	0	0
T10	189917	832	0	0
T11	25424	0	0	0
T12	0	140	0	0
T14	0	7870	0	0
T15	0	5557	0	0
T22	0	4479	0	0
T23	0	6634	0	0
T24	0	396	0	0
T27	0	3522	0	0
T31	0	5182	0	0
T32	0	107	0	0
T42	0	188	0	0
T43	0	2	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652477808	3149699	0	0
T1	750559	7572	0	0
T2	1792575	12880	0	0
T3	23743	832	0	0
T4	591275	6516	0	0
T5	2618641	20416	0	0
T6	40412	832	0	0
T7	595823	940	0	0
T8	5751	832	0	0
T9	71825	832	0	0
T10	189917	832	0	0
T11	25424	0	0	0
T12	0	140	0	0
T14	0	7870	0	0
T15	0	5557	0	0
T22	0	4479	0	0
T23	0	6634	0	0
T24	0	396	0	0
T27	0	3522	0	0
T31	0	5182	0	0
T32	0	107	0	0
T42	0	188	0	0
T43	0	2	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	652477808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652477808	0	0	906

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652477808	527620603	0	0
T1	750559	748357	0	0
T2	1792575	1071598	0	0
T3	23743	19515	0	0
T4	591275	472945	0	0
T5	2618641	1762294	0	0
T6	40412	27959	0	0
T7	595823	523506	0	0
T8	5751	5119	0	0
T9	71825	42293	0	0
T10	189917	108621	0	0
T11	25424	25424	0	0
T22	0	144576	0	0
T23	0	103936	0	0
T26	0	108848	0	0
T27	0	109256	0	0
T31	0	120696	0	0
T32	0	2480	0	0
T33	0	36488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652477808	3149699	0	0
T1	750559	7572	0	0
T2	1792575	12880	0	0
T3	23743	832	0	0
T4	591275	6516	0	0
T5	2618641	20416	0	0
T6	40412	832	0	0
T7	595823	940	0	0
T8	5751	832	0	0
T9	71825	832	0	0
T10	189917	832	0	0
T11	25424	0	0	0
T12	0	140	0	0
T14	0	7870	0	0
T15	0	5557	0	0
T22	0	4479	0	0
T23	0	6634	0	0
T24	0	396	0	0
T27	0	3522	0	0
T31	0	5182	0	0
T32	0	107	0	0
T42	0	188	0	0
T43	0	2	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	123569230	27341336	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	123569230	603839	0	0
GntImpliesValid_A	123569230	603839	0	0
GrantKnown_A	123569230	27341336	0	0
IdxKnown_A	123569230	27341336	0	0
IndexIsCorrect_A	123569230	603839	0	0
LockArbDecision_A	123569230	0	0	0
NoReadyValidNoGrant_A	123569230	0	0	0
ReadyAndValidImplyGrant_A	123569230	603839	0	0
ReqAndReadyImplyGrant_A	123569230	603839	0	0
ReqImpliesValid_A	123569230	603839	0	0
ReqStaysHighUntilGranted0_M	123569230	0	0	0
RoundRobin_A	123569230	0	0	0
ValidKnown_A	123569230	27341336	0	0
gen_data_port_assertion.DataFlow_A	123569230	603839	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	27341336	0	0
T2	714212	50352	0	0
T3	4132	0	0	0
T4	115753	113240	0	0
T5	849623	193296	0	0
T6	12360	0	0	0
T7	72258	0	0	0
T8	300	0	0	0
T9	28757	0	0	0
T10	81242	0	0	0
T11	25424	0	0	0
T22	0	144576	0	0
T23	0	103936	0	0
T26	0	108848	0	0
T27	0	109256	0	0
T31	0	120696	0	0
T32	0	2480	0	0
T33	0	36488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	603839	0	0
T2	714212	2170	0	0
T3	4132	0	0	0
T4	115753	4532	0	0
T5	849623	5237	0	0
T6	12360	0	0	0
T7	72258	0	0	0
T8	300	0	0	0
T9	28757	0	0	0
T10	81242	0	0	0
T11	25424	0	0	0
T14	0	853	0	0
T22	0	4479	0	0
T23	0	4112	0	0
T27	0	3522	0	0
T31	0	5182	0	0
T32	0	107	0	0
T42	0	188	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	603839	0	0
T2	714212	2170	0	0
T3	4132	0	0	0
T4	115753	4532	0	0
T5	849623	5237	0	0
T6	12360	0	0	0
T7	72258	0	0	0
T8	300	0	0	0
T9	28757	0	0	0
T10	81242	0	0	0
T11	25424	0	0	0
T14	0	853	0	0
T22	0	4479	0	0
T23	0	4112	0	0
T27	0	3522	0	0
T31	0	5182	0	0
T32	0	107	0	0
T42	0	188	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	27341336	0	0
T2	714212	50352	0	0
T3	4132	0	0	0
T4	115753	113240	0	0
T5	849623	193296	0	0
T6	12360	0	0	0
T7	72258	0	0	0
T8	300	0	0	0
T9	28757	0	0	0
T10	81242	0	0	0
T11	25424	0	0	0
T22	0	144576	0	0
T23	0	103936	0	0
T26	0	108848	0	0
T27	0	109256	0	0
T31	0	120696	0	0
T32	0	2480	0	0
T33	0	36488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	27341336	0	0
T2	714212	50352	0	0
T3	4132	0	0	0
T4	115753	113240	0	0
T5	849623	193296	0	0
T6	12360	0	0	0
T7	72258	0	0	0
T8	300	0	0	0
T9	28757	0	0	0
T10	81242	0	0	0
T11	25424	0	0	0
T22	0	144576	0	0
T23	0	103936	0	0
T26	0	108848	0	0
T27	0	109256	0	0
T31	0	120696	0	0
T32	0	2480	0	0
T33	0	36488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	603839	0	0
T2	714212	2170	0	0
T3	4132	0	0	0
T4	115753	4532	0	0
T5	849623	5237	0	0
T6	12360	0	0	0
T7	72258	0	0	0
T8	300	0	0	0
T9	28757	0	0	0
T10	81242	0	0	0
T11	25424	0	0	0
T14	0	853	0	0
T22	0	4479	0	0
T23	0	4112	0	0
T27	0	3522	0	0
T31	0	5182	0	0
T32	0	107	0	0
T42	0	188	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	603839	0	0
T2	714212	2170	0	0
T3	4132	0	0	0
T4	115753	4532	0	0
T5	849623	5237	0	0
T6	12360	0	0	0
T7	72258	0	0	0
T8	300	0	0	0
T9	28757	0	0	0
T10	81242	0	0	0
T11	25424	0	0	0
T14	0	853	0	0
T22	0	4479	0	0
T23	0	4112	0	0
T27	0	3522	0	0
T31	0	5182	0	0
T32	0	107	0	0
T42	0	188	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	603839	0	0
T2	714212	2170	0	0
T3	4132	0	0	0
T4	115753	4532	0	0
T5	849623	5237	0	0
T6	12360	0	0	0
T7	72258	0	0	0
T8	300	0	0	0
T9	28757	0	0	0
T10	81242	0	0	0
T11	25424	0	0	0
T14	0	853	0	0
T22	0	4479	0	0
T23	0	4112	0	0
T27	0	3522	0	0
T31	0	5182	0	0
T32	0	107	0	0
T42	0	188	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	603839	0	0
T2	714212	2170	0	0
T3	4132	0	0	0
T4	115753	4532	0	0
T5	849623	5237	0	0
T6	12360	0	0	0
T7	72258	0	0	0
T8	300	0	0	0
T9	28757	0	0	0
T10	81242	0	0	0
T11	25424	0	0	0
T14	0	853	0	0
T22	0	4479	0	0
T23	0	4112	0	0
T27	0	3522	0	0
T31	0	5182	0	0
T32	0	107	0	0
T42	0	188	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	27341336	0	0
T2	714212	50352	0	0
T3	4132	0	0	0
T4	115753	113240	0	0
T5	849623	193296	0	0
T6	12360	0	0	0
T7	72258	0	0	0
T8	300	0	0	0
T9	28757	0	0	0
T10	81242	0	0	0
T11	25424	0	0	0
T22	0	144576	0	0
T23	0	103936	0	0
T26	0	108848	0	0
T27	0	109256	0	0
T31	0	120696	0	0
T32	0	2480	0	0
T33	0	36488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	603839	0	0
T2	714212	2170	0	0
T3	4132	0	0	0
T4	115753	4532	0	0
T5	849623	5237	0	0
T6	12360	0	0	0
T7	72258	0	0	0
T8	300	0	0	0
T9	28757	0	0	0
T10	81242	0	0	0
T11	25424	0	0	0
T14	0	853	0	0
T22	0	4479	0	0
T23	0	4112	0	0
T27	0	3522	0	0
T31	0	5182	0	0
T32	0	107	0	0
T42	0	188	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	123569230	95024142	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	123569230	629811	0	0
GntImpliesValid_A	123569230	629811	0	0
GrantKnown_A	123569230	95024142	0	0
IdxKnown_A	123569230	95024142	0	0
IndexIsCorrect_A	123569230	629811	0	0
LockArbDecision_A	123569230	0	0	0
NoReadyValidNoGrant_A	123569230	0	0	0
ReadyAndValidImplyGrant_A	123569230	629811	0	0
ReqAndReadyImplyGrant_A	123569230	629811	0	0
ReqImpliesValid_A	123569230	629811	0	0
ReqStaysHighUntilGranted0_M	123569230	0	0	0
RoundRobin_A	123569230	0	0	0
ValidKnown_A	123569230	95024142	0	0
gen_data_port_assertion.DataFlow_A	123569230	629811	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	95024142	0	0
T1	498318	496125	0	0
T2	714212	657104	0	0
T3	4132	4132	0	0
T4	115753	0	0	0
T5	849623	649677	0	0
T6	12360	12360	0	0
T7	72258	72258	0	0
T8	300	64	0	0
T9	28757	28040	0	0
T10	81242	81242	0	0
T11	0	25424	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	629811	0	0
T1	498318	777	0	0
T2	714212	369	0	0
T3	4132	0	0	0
T4	115753	0	0	0
T5	849623	5848	0	0
T6	12360	0	0	0
T7	72258	82	0	0
T8	300	0	0	0
T9	28757	0	0	0
T10	81242	0	0	0
T12	0	140	0	0
T14	0	7017	0	0
T15	0	5557	0	0
T23	0	2522	0	0
T24	0	396	0	0
T43	0	2	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	629811	0	0
T1	498318	777	0	0
T2	714212	369	0	0
T3	4132	0	0	0
T4	115753	0	0	0
T5	849623	5848	0	0
T6	12360	0	0	0
T7	72258	82	0	0
T8	300	0	0	0
T9	28757	0	0	0
T10	81242	0	0	0
T12	0	140	0	0
T14	0	7017	0	0
T15	0	5557	0	0
T23	0	2522	0	0
T24	0	396	0	0
T43	0	2	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	95024142	0	0
T1	498318	496125	0	0
T2	714212	657104	0	0
T3	4132	4132	0	0
T4	115753	0	0	0
T5	849623	649677	0	0
T6	12360	12360	0	0
T7	72258	72258	0	0
T8	300	64	0	0
T9	28757	28040	0	0
T10	81242	81242	0	0
T11	0	25424	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	95024142	0	0
T1	498318	496125	0	0
T2	714212	657104	0	0
T3	4132	4132	0	0
T4	115753	0	0	0
T5	849623	649677	0	0
T6	12360	12360	0	0
T7	72258	72258	0	0
T8	300	64	0	0
T9	28757	28040	0	0
T10	81242	81242	0	0
T11	0	25424	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	629811	0	0
T1	498318	777	0	0
T2	714212	369	0	0
T3	4132	0	0	0
T4	115753	0	0	0
T5	849623	5848	0	0
T6	12360	0	0	0
T7	72258	82	0	0
T8	300	0	0	0
T9	28757	0	0	0
T10	81242	0	0	0
T12	0	140	0	0
T14	0	7017	0	0
T15	0	5557	0	0
T23	0	2522	0	0
T24	0	396	0	0
T43	0	2	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	629811	0	0
T1	498318	777	0	0
T2	714212	369	0	0
T3	4132	0	0	0
T4	115753	0	0	0
T5	849623	5848	0	0
T6	12360	0	0	0
T7	72258	82	0	0
T8	300	0	0	0
T9	28757	0	0	0
T10	81242	0	0	0
T12	0	140	0	0
T14	0	7017	0	0
T15	0	5557	0	0
T23	0	2522	0	0
T24	0	396	0	0
T43	0	2	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	629811	0	0
T1	498318	777	0	0
T2	714212	369	0	0
T3	4132	0	0	0
T4	115753	0	0	0
T5	849623	5848	0	0
T6	12360	0	0	0
T7	72258	82	0	0
T8	300	0	0	0
T9	28757	0	0	0
T10	81242	0	0	0
T12	0	140	0	0
T14	0	7017	0	0
T15	0	5557	0	0
T23	0	2522	0	0
T24	0	396	0	0
T43	0	2	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	629811	0	0
T1	498318	777	0	0
T2	714212	369	0	0
T3	4132	0	0	0
T4	115753	0	0	0
T5	849623	5848	0	0
T6	12360	0	0	0
T7	72258	82	0	0
T8	300	0	0	0
T9	28757	0	0	0
T10	81242	0	0	0
T12	0	140	0	0
T14	0	7017	0	0
T15	0	5557	0	0
T23	0	2522	0	0
T24	0	396	0	0
T43	0	2	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	95024142	0	0
T1	498318	496125	0	0
T2	714212	657104	0	0
T3	4132	4132	0	0
T4	115753	0	0	0
T5	849623	649677	0	0
T6	12360	12360	0	0
T7	72258	72258	0	0
T8	300	64	0	0
T9	28757	28040	0	0
T10	81242	81242	0	0
T11	0	25424	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123569230	629811	0	0
T1	498318	777	0	0
T2	714212	369	0	0
T3	4132	0	0	0
T4	115753	0	0	0
T5	849623	5848	0	0
T6	12360	0	0	0
T7	72258	82	0	0
T8	300	0	0	0
T9	28757	0	0	0
T10	81242	0	0	0
T12	0	140	0	0
T14	0	7017	0	0
T15	0	5557	0	0
T23	0	2522	0	0
T24	0	396	0	0
T43	0	2	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405339348	405255125	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	405339348	1916049	0	0
GntImpliesValid_A	405339348	1916049	0	0
GrantKnown_A	405339348	405255125	0	0
IdxKnown_A	405339348	405255125	0	0
IndexIsCorrect_A	405339348	1916049	0	0
LockArbDecision_A	405339348	0	0	0
NoReadyValidNoGrant_A	405339348	0	0	0
ReadyAndValidImplyGrant_A	405339348	1916049	0	0
ReqAndReadyImplyGrant_A	405339348	1916049	0	0
ReqImpliesValid_A	405339348	1916049	0	0
ReqStaysHighUntilGranted0_M	405339348	0	0	0
RoundRobin_A	405339348	0	0	906
ValidKnown_A	405339348	405255125	0	0
gen_data_port_assertion.DataFlow_A	405339348	1916049	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405339348	405255125	0	0
T1	252241	252232	0	0
T2	364151	364142	0	0
T3	15479	15383	0	0
T4	359769	359705	0	0
T5	919395	919321	0	0
T6	15692	15599	0	0
T7	451307	451248	0	0
T8	5151	5055	0	0
T9	14311	14253	0	0
T10	27433	27379	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405339348	1916049	0	0
T1	252241	6795	0	0
T2	364151	10341	0	0
T3	15479	832	0	0
T4	359769	1984	0	0
T5	919395	9331	0	0
T6	15692	832	0	0
T7	451307	858	0	0
T8	5151	832	0	0
T9	14311	832	0	0
T10	27433	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405339348	1916049	0	0
T1	252241	6795	0	0
T2	364151	10341	0	0
T3	15479	832	0	0
T4	359769	1984	0	0
T5	919395	9331	0	0
T6	15692	832	0	0
T7	451307	858	0	0
T8	5151	832	0	0
T9	14311	832	0	0
T10	27433	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405339348	405255125	0	0
T1	252241	252232	0	0
T2	364151	364142	0	0
T3	15479	15383	0	0
T4	359769	359705	0	0
T5	919395	919321	0	0
T6	15692	15599	0	0
T7	451307	451248	0	0
T8	5151	5055	0	0
T9	14311	14253	0	0
T10	27433	27379	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405339348	405255125	0	0
T1	252241	252232	0	0
T2	364151	364142	0	0
T3	15479	15383	0	0
T4	359769	359705	0	0
T5	919395	919321	0	0
T6	15692	15599	0	0
T7	451307	451248	0	0
T8	5151	5055	0	0
T9	14311	14253	0	0
T10	27433	27379	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405339348	1916049	0	0
T1	252241	6795	0	0
T2	364151	10341	0	0
T3	15479	832	0	0
T4	359769	1984	0	0
T5	919395	9331	0	0
T6	15692	832	0	0
T7	451307	858	0	0
T8	5151	832	0	0
T9	14311	832	0	0
T10	27433	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405339348	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405339348	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405339348	1916049	0	0
T1	252241	6795	0	0
T2	364151	10341	0	0
T3	15479	832	0	0
T4	359769	1984	0	0
T5	919395	9331	0	0
T6	15692	832	0	0
T7	451307	858	0	0
T8	5151	832	0	0
T9	14311	832	0	0
T10	27433	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405339348	1916049	0	0
T1	252241	6795	0	0
T2	364151	10341	0	0
T3	15479	832	0	0
T4	359769	1984	0	0
T5	919395	9331	0	0
T6	15692	832	0	0
T7	451307	858	0	0
T8	5151	832	0	0
T9	14311	832	0	0
T10	27433	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405339348	1916049	0	0
T1	252241	6795	0	0
T2	364151	10341	0	0
T3	15479	832	0	0
T4	359769	1984	0	0
T5	919395	9331	0	0
T6	15692	832	0	0
T7	451307	858	0	0
T8	5151	832	0	0
T9	14311	832	0	0
T10	27433	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405339348	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405339348	0	0	906

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405339348	405255125	0	0
T1	252241	252232	0	0
T2	364151	364142	0	0
T3	15479	15383	0	0
T4	359769	359705	0	0
T5	919395	919321	0	0
T6	15692	15599	0	0
T7	451307	451248	0	0
T8	5151	5055	0	0
T9	14311	14253	0	0
T10	27433	27379	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405339348	1916049	0	0
T1	252241	6795	0	0
T2	364151	10341	0	0
T3	15479	832	0	0
T4	359769	1984	0	0
T5	919395	9331	0	0
T6	15692	832	0	0
T7	451307	858	0	0
T8	5151	832	0	0
T9	14311	832	0	0
T10	27433	832	0	0