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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.01 98.38 93.98 98.62 89.36 97.19 95.31 99.25


Total test records in report: 1081
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T147 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2535319451 Jun 25 05:09:50 PM PDT 24 Jun 25 05:10:17 PM PDT 24 1107452329 ps
T107 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1465939595 Jun 25 05:09:46 PM PDT 24 Jun 25 05:09:48 PM PDT 24 64148990 ps
T1008 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1099241708 Jun 25 05:09:48 PM PDT 24 Jun 25 05:09:51 PM PDT 24 114264622 ps
T1009 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.106980924 Jun 25 05:09:52 PM PDT 24 Jun 25 05:10:01 PM PDT 24 334072982 ps
T1010 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3133265668 Jun 25 05:09:30 PM PDT 24 Jun 25 05:09:34 PM PDT 24 19582053 ps
T1011 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1280761455 Jun 25 05:09:18 PM PDT 24 Jun 25 05:09:22 PM PDT 24 116490047 ps
T152 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2943802165 Jun 25 05:09:29 PM PDT 24 Jun 25 05:09:47 PM PDT 24 672695330 ps
T1012 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2516013596 Jun 25 05:09:17 PM PDT 24 Jun 25 05:09:18 PM PDT 24 21220847 ps
T1013 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1510078684 Jun 25 05:09:53 PM PDT 24 Jun 25 05:09:55 PM PDT 24 46345893 ps
T1014 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2440838309 Jun 25 05:09:27 PM PDT 24 Jun 25 05:09:32 PM PDT 24 174291470 ps
T1015 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3458443953 Jun 25 05:09:48 PM PDT 24 Jun 25 05:09:53 PM PDT 24 105216412 ps
T1016 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2364483848 Jun 25 05:09:41 PM PDT 24 Jun 25 05:09:59 PM PDT 24 1109725542 ps
T1017 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.875129115 Jun 25 05:09:30 PM PDT 24 Jun 25 05:09:33 PM PDT 24 26617132 ps
T1018 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.208643445 Jun 25 05:09:25 PM PDT 24 Jun 25 05:09:29 PM PDT 24 252288670 ps
T1019 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.874500079 Jun 25 05:09:36 PM PDT 24 Jun 25 05:09:38 PM PDT 24 212123364 ps
T1020 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2844329316 Jun 25 05:09:28 PM PDT 24 Jun 25 05:09:53 PM PDT 24 1245297316 ps
T1021 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1716871806 Jun 25 05:09:28 PM PDT 24 Jun 25 05:09:32 PM PDT 24 306701545 ps
T1022 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2325719779 Jun 25 05:09:39 PM PDT 24 Jun 25 05:09:45 PM PDT 24 759045928 ps
T1023 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.642522967 Jun 25 05:09:57 PM PDT 24 Jun 25 05:10:01 PM PDT 24 19765573 ps
T108 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1385162066 Jun 25 05:09:41 PM PDT 24 Jun 25 05:09:44 PM PDT 24 253810934 ps
T1024 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1756675046 Jun 25 05:09:28 PM PDT 24 Jun 25 05:09:54 PM PDT 24 1864605482 ps
T1025 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.122567629 Jun 25 05:09:28 PM PDT 24 Jun 25 05:09:31 PM PDT 24 347769108 ps
T1026 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.739382831 Jun 25 05:09:56 PM PDT 24 Jun 25 05:10:00 PM PDT 24 120801108 ps
T153 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.616793213 Jun 25 05:09:45 PM PDT 24 Jun 25 05:09:59 PM PDT 24 2430754564 ps
T1027 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1489585565 Jun 25 05:09:29 PM PDT 24 Jun 25 05:09:53 PM PDT 24 796423589 ps
T1028 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1776926045 Jun 25 05:09:19 PM PDT 24 Jun 25 05:09:47 PM PDT 24 5016500474 ps
T1029 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3771767665 Jun 25 05:09:55 PM PDT 24 Jun 25 05:09:59 PM PDT 24 28973964 ps
T1030 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.280136384 Jun 25 05:09:30 PM PDT 24 Jun 25 05:09:36 PM PDT 24 58812969 ps
T151 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3850442436 Jun 25 05:09:37 PM PDT 24 Jun 25 05:10:02 PM PDT 24 3974023032 ps
T1031 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3837815459 Jun 25 05:09:50 PM PDT 24 Jun 25 05:09:56 PM PDT 24 134685322 ps
T1032 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2592170589 Jun 25 05:09:57 PM PDT 24 Jun 25 05:10:02 PM PDT 24 50867472 ps
T1033 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.401421624 Jun 25 05:09:27 PM PDT 24 Jun 25 05:09:29 PM PDT 24 47219527 ps
T1034 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2045799518 Jun 25 05:09:33 PM PDT 24 Jun 25 05:09:59 PM PDT 24 2512303003 ps
T1035 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2746337960 Jun 25 05:09:39 PM PDT 24 Jun 25 05:09:44 PM PDT 24 110857054 ps
T150 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3752216635 Jun 25 05:09:52 PM PDT 24 Jun 25 05:10:17 PM PDT 24 3119366484 ps
T1036 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2168772418 Jun 25 05:09:38 PM PDT 24 Jun 25 05:09:42 PM PDT 24 62772768 ps
T1037 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.374376086 Jun 25 05:09:29 PM PDT 24 Jun 25 05:09:39 PM PDT 24 607854180 ps
T1038 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.814958028 Jun 25 05:09:54 PM PDT 24 Jun 25 05:09:56 PM PDT 24 39539705 ps
T1039 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1528184531 Jun 25 05:09:39 PM PDT 24 Jun 25 05:09:44 PM PDT 24 323056169 ps
T1040 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1758666054 Jun 25 05:09:48 PM PDT 24 Jun 25 05:09:50 PM PDT 24 159490377 ps
T1041 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2856247214 Jun 25 05:09:37 PM PDT 24 Jun 25 05:10:02 PM PDT 24 2204554004 ps
T1042 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2244438278 Jun 25 05:09:55 PM PDT 24 Jun 25 05:09:59 PM PDT 24 19435004 ps
T1043 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.379074837 Jun 25 05:09:29 PM PDT 24 Jun 25 05:09:33 PM PDT 24 207301807 ps
T1044 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3683637969 Jun 25 05:09:55 PM PDT 24 Jun 25 05:09:57 PM PDT 24 14471071 ps
T1045 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4242219955 Jun 25 05:09:58 PM PDT 24 Jun 25 05:10:02 PM PDT 24 40171533 ps
T1046 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2370176727 Jun 25 05:09:55 PM PDT 24 Jun 25 05:09:58 PM PDT 24 14543823 ps
T1047 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3125400695 Jun 25 05:09:37 PM PDT 24 Jun 25 05:09:41 PM PDT 24 114067680 ps
T1048 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3656166500 Jun 25 05:09:49 PM PDT 24 Jun 25 05:09:56 PM PDT 24 786761795 ps
T1049 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.912187448 Jun 25 05:09:29 PM PDT 24 Jun 25 05:09:35 PM PDT 24 132318421 ps
T1050 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3523643535 Jun 25 05:09:29 PM PDT 24 Jun 25 05:09:39 PM PDT 24 2337222670 ps
T1051 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3964030349 Jun 25 05:09:58 PM PDT 24 Jun 25 05:10:02 PM PDT 24 23719765 ps
T1052 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3092471290 Jun 25 05:09:20 PM PDT 24 Jun 25 05:09:36 PM PDT 24 722178940 ps
T1053 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1000677685 Jun 25 05:09:56 PM PDT 24 Jun 25 05:10:01 PM PDT 24 12812520 ps
T1054 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.21343099 Jun 25 05:09:37 PM PDT 24 Jun 25 05:09:39 PM PDT 24 15763977 ps
T1055 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1591000645 Jun 25 05:09:29 PM PDT 24 Jun 25 05:09:58 PM PDT 24 1824843141 ps
T1056 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.768621309 Jun 25 05:09:33 PM PDT 24 Jun 25 05:09:36 PM PDT 24 191719644 ps
T1057 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.672310358 Jun 25 05:09:50 PM PDT 24 Jun 25 05:09:52 PM PDT 24 50749023 ps
T1058 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1988948062 Jun 25 05:09:28 PM PDT 24 Jun 25 05:09:31 PM PDT 24 91946740 ps
T1059 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3097406356 Jun 25 05:09:36 PM PDT 24 Jun 25 05:09:40 PM PDT 24 173001448 ps
T1060 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.939963546 Jun 25 05:09:30 PM PDT 24 Jun 25 05:09:34 PM PDT 24 164849173 ps
T1061 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.537007000 Jun 25 05:09:55 PM PDT 24 Jun 25 05:10:00 PM PDT 24 14722882 ps
T1062 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2900802696 Jun 25 05:09:19 PM PDT 24 Jun 25 05:09:23 PM PDT 24 206561277 ps
T1063 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2804092617 Jun 25 05:09:27 PM PDT 24 Jun 25 05:09:51 PM PDT 24 1033378768 ps
T1064 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3590135140 Jun 25 05:09:29 PM PDT 24 Jun 25 05:09:35 PM PDT 24 1261816666 ps
T1065 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.980874166 Jun 25 05:09:30 PM PDT 24 Jun 25 05:09:40 PM PDT 24 306303070 ps
T1066 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3219019259 Jun 25 05:09:59 PM PDT 24 Jun 25 05:10:03 PM PDT 24 36995356 ps
T1067 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1987793443 Jun 25 05:09:19 PM PDT 24 Jun 25 05:09:22 PM PDT 24 15057870 ps
T1068 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1253622874 Jun 25 05:09:45 PM PDT 24 Jun 25 05:09:49 PM PDT 24 446811152 ps
T1069 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2881720936 Jun 25 05:09:47 PM PDT 24 Jun 25 05:09:49 PM PDT 24 44934359 ps
T1070 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3263270321 Jun 25 05:09:52 PM PDT 24 Jun 25 05:09:54 PM PDT 24 11227321 ps
T1071 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.4005264827 Jun 25 05:09:18 PM PDT 24 Jun 25 05:09:20 PM PDT 24 21495084 ps
T1072 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.28884724 Jun 25 05:09:53 PM PDT 24 Jun 25 05:09:57 PM PDT 24 167997907 ps
T1073 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1707296784 Jun 25 05:09:30 PM PDT 24 Jun 25 05:09:48 PM PDT 24 3036493002 ps
T1074 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2605341074 Jun 25 05:09:38 PM PDT 24 Jun 25 05:09:48 PM PDT 24 392399203 ps
T1075 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2154786966 Jun 25 05:09:29 PM PDT 24 Jun 25 05:09:33 PM PDT 24 154162838 ps
T1076 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3175647540 Jun 25 05:09:38 PM PDT 24 Jun 25 05:09:40 PM PDT 24 45618631 ps
T1077 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1325515736 Jun 25 05:09:37 PM PDT 24 Jun 25 05:09:41 PM PDT 24 97765779 ps
T1078 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3591388214 Jun 25 05:09:54 PM PDT 24 Jun 25 05:10:00 PM PDT 24 52681852 ps
T1079 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4199832914 Jun 25 05:09:28 PM PDT 24 Jun 25 05:09:31 PM PDT 24 52404652 ps
T1080 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2222512387 Jun 25 05:09:38 PM PDT 24 Jun 25 05:09:43 PM PDT 24 38372865 ps
T1081 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3923904748 Jun 25 05:09:56 PM PDT 24 Jun 25 05:10:00 PM PDT 24 23057452 ps

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2109996263
Short name T2
Test name
Test status
Simulation time 37933636701 ps
CPU time 332.74 seconds
Started Jun 25 06:56:42 PM PDT 24
Finished Jun 25 07:02:16 PM PDT 24
Peak memory 250168 kb
Host smart-3f26b8f7-b5d3-45ac-baf8-9f3bd8b6fc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109996263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2109996263
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.228426036
Short name T5
Test name
Test status
Simulation time 9193976422 ps
CPU time 159.84 seconds
Started Jun 25 06:55:52 PM PDT 24
Finished Jun 25 06:58:33 PM PDT 24
Peak memory 251352 kb
Host smart-3f6b0c08-0a2e-4a9c-a912-878f606a887b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228426036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.228426036
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.117774350
Short name T19
Test name
Test status
Simulation time 8459103793 ps
CPU time 130.37 seconds
Started Jun 25 06:55:30 PM PDT 24
Finished Jun 25 06:57:41 PM PDT 24
Peak memory 264904 kb
Host smart-2f8f9aca-23fb-4645-99e5-356f347927ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117774350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.117774350
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1655475602
Short name T78
Test name
Test status
Simulation time 5824336235 ps
CPU time 24.6 seconds
Started Jun 25 05:09:31 PM PDT 24
Finished Jun 25 05:09:58 PM PDT 24
Peak memory 214748 kb
Host smart-cc37e4b4-cd7a-4779-8952-131f94c057e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655475602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1655475602
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.321387678
Short name T60
Test name
Test status
Simulation time 47119861934 ps
CPU time 538.28 seconds
Started Jun 25 06:55:31 PM PDT 24
Finished Jun 25 07:04:30 PM PDT 24
Peak memory 274560 kb
Host smart-7a62ae7b-6e83-4e79-a10b-07608d7285f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321387678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.321387678
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1251814604
Short name T56
Test name
Test status
Simulation time 15476996 ps
CPU time 0.72 seconds
Started Jun 25 06:53:38 PM PDT 24
Finished Jun 25 06:53:40 PM PDT 24
Peak memory 216900 kb
Host smart-2e215a58-ff6e-44b1-950e-efa523ada08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251814604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1251814604
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3421517104
Short name T127
Test name
Test status
Simulation time 79677404013 ps
CPU time 567.22 seconds
Started Jun 25 06:55:02 PM PDT 24
Finished Jun 25 07:04:30 PM PDT 24
Peak memory 269504 kb
Host smart-a938affa-31b6-4ca2-9a75-18c9b7b5cef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421517104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3421517104
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2721663242
Short name T41
Test name
Test status
Simulation time 53886139550 ps
CPU time 67.62 seconds
Started Jun 25 06:58:24 PM PDT 24
Finished Jun 25 06:59:33 PM PDT 24
Peak memory 232324 kb
Host smart-8190b632-6d8a-4292-8ca3-57043e415402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721663242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2721663242
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.4085614592
Short name T44
Test name
Test status
Simulation time 22728906115 ps
CPU time 171.07 seconds
Started Jun 25 06:54:05 PM PDT 24
Finished Jun 25 06:56:57 PM PDT 24
Peak memory 267688 kb
Host smart-6023baac-f988-4eda-a50d-22ddc5bdc29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085614592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.4085614592
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3796065030
Short name T61
Test name
Test status
Simulation time 81200145277 ps
CPU time 763.21 seconds
Started Jun 25 06:57:54 PM PDT 24
Finished Jun 25 07:10:39 PM PDT 24
Peak memory 271428 kb
Host smart-c2c22775-2d57-4c36-8a48-0d497058a86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796065030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3796065030
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2037015338
Short name T82
Test name
Test status
Simulation time 53542177 ps
CPU time 3.32 seconds
Started Jun 25 05:09:19 PM PDT 24
Finished Jun 25 05:09:25 PM PDT 24
Peak memory 215068 kb
Host smart-b11536e8-3e82-413a-94a9-7b7f918bd1d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037015338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
037015338
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2340007095
Short name T117
Test name
Test status
Simulation time 567436212 ps
CPU time 11.43 seconds
Started Jun 25 06:56:21 PM PDT 24
Finished Jun 25 06:56:33 PM PDT 24
Peak memory 233616 kb
Host smart-e9ad70d6-3190-4181-b930-82a2944f3f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340007095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2340007095
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3657945694
Short name T21
Test name
Test status
Simulation time 731394342 ps
CPU time 1.12 seconds
Started Jun 25 06:53:53 PM PDT 24
Finished Jun 25 06:53:55 PM PDT 24
Peak memory 237100 kb
Host smart-e499738e-0db8-4906-891e-137952748508
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657945694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3657945694
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3554318184
Short name T168
Test name
Test status
Simulation time 76129897130 ps
CPU time 600.74 seconds
Started Jun 25 06:56:48 PM PDT 24
Finished Jun 25 07:06:50 PM PDT 24
Peak memory 269472 kb
Host smart-f8bfaadb-b197-4832-9cf3-8b5dbad14c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554318184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3554318184
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1841059513
Short name T62
Test name
Test status
Simulation time 83741535084 ps
CPU time 421.25 seconds
Started Jun 25 06:53:53 PM PDT 24
Finished Jun 25 07:00:55 PM PDT 24
Peak memory 274792 kb
Host smart-441f3e12-03db-47b9-b506-c69e2dc29407
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841059513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1841059513
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3090000998
Short name T64
Test name
Test status
Simulation time 106897464 ps
CPU time 1.19 seconds
Started Jun 25 05:09:21 PM PDT 24
Finished Jun 25 05:09:24 PM PDT 24
Peak memory 206856 kb
Host smart-c028f357-1e2e-4e45-90ac-ec223ae304a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090000998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3090000998
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1541827736
Short name T20
Test name
Test status
Simulation time 87894064761 ps
CPU time 151.79 seconds
Started Jun 25 06:56:28 PM PDT 24
Finished Jun 25 06:59:00 PM PDT 24
Peak memory 264412 kb
Host smart-c2b72d3d-ae86-4d4b-8863-db1e3533f112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541827736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1541827736
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1917199458
Short name T171
Test name
Test status
Simulation time 59038749526 ps
CPU time 180.49 seconds
Started Jun 25 06:54:34 PM PDT 24
Finished Jun 25 06:57:35 PM PDT 24
Peak memory 274752 kb
Host smart-5d3cb3d9-a5ea-4cf7-b8fd-0e5b051844be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917199458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1917199458
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3124673959
Short name T299
Test name
Test status
Simulation time 2028285122 ps
CPU time 24.63 seconds
Started Jun 25 06:55:50 PM PDT 24
Finished Jun 25 06:56:16 PM PDT 24
Peak memory 217260 kb
Host smart-9443a024-a5d7-4c16-9999-232bacdfbd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124673959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3124673959
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3996695774
Short name T36
Test name
Test status
Simulation time 475786630777 ps
CPU time 1125.45 seconds
Started Jun 25 06:59:13 PM PDT 24
Finished Jun 25 07:17:59 PM PDT 24
Peak memory 286440 kb
Host smart-21c01a3a-f828-4645-bc1b-fc4088f0fb91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996695774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3996695774
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.411493582
Short name T190
Test name
Test status
Simulation time 523356069583 ps
CPU time 421.66 seconds
Started Jun 25 06:59:03 PM PDT 24
Finished Jun 25 07:06:06 PM PDT 24
Peak memory 250236 kb
Host smart-22127812-d992-430b-9454-4614e0440e05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411493582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.411493582
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1488532784
Short name T273
Test name
Test status
Simulation time 136553931141 ps
CPU time 272.79 seconds
Started Jun 25 06:57:15 PM PDT 24
Finished Jun 25 07:01:49 PM PDT 24
Peak memory 266384 kb
Host smart-655c6d41-c9cc-44f4-9631-07903f3e6513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488532784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1488532784
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2502986788
Short name T173
Test name
Test status
Simulation time 117694359160 ps
CPU time 623.18 seconds
Started Jun 25 06:57:14 PM PDT 24
Finished Jun 25 07:07:38 PM PDT 24
Peak memory 274764 kb
Host smart-35ed3e36-8c40-40dd-90fd-612c03eeaf5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502986788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2502986788
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3488152372
Short name T201
Test name
Test status
Simulation time 41126565981 ps
CPU time 362.63 seconds
Started Jun 25 06:57:53 PM PDT 24
Finished Jun 25 07:03:57 PM PDT 24
Peak memory 250204 kb
Host smart-b10159c4-a6d4-4340-99e5-d112be1de913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488152372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3488152372
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2221321453
Short name T195
Test name
Test status
Simulation time 39807275599 ps
CPU time 397.73 seconds
Started Jun 25 06:58:11 PM PDT 24
Finished Jun 25 07:04:50 PM PDT 24
Peak memory 256872 kb
Host smart-a7827081-497f-4bba-8932-b64a6fb7f910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221321453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2221321453
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2637702500
Short name T178
Test name
Test status
Simulation time 173777803709 ps
CPU time 396.9 seconds
Started Jun 25 06:58:32 PM PDT 24
Finished Jun 25 07:05:10 PM PDT 24
Peak memory 256928 kb
Host smart-71d09546-2f42-4f0c-8b5f-54ab2c9885f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637702500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2637702500
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.334010326
Short name T381
Test name
Test status
Simulation time 46307435 ps
CPU time 0.78 seconds
Started Jun 25 06:55:09 PM PDT 24
Finished Jun 25 06:55:11 PM PDT 24
Peak memory 206064 kb
Host smart-33dac0fc-7aca-42f0-88f3-12a9c9f351f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334010326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.334010326
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4046576081
Short name T85
Test name
Test status
Simulation time 201340361 ps
CPU time 5 seconds
Started Jun 25 05:09:31 PM PDT 24
Finished Jun 25 05:09:39 PM PDT 24
Peak memory 215084 kb
Host smart-91fc8318-4ad0-4a14-9397-3ec2bed34b3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046576081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.4
046576081
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.616793213
Short name T153
Test name
Test status
Simulation time 2430754564 ps
CPU time 12.48 seconds
Started Jun 25 05:09:45 PM PDT 24
Finished Jun 25 05:09:59 PM PDT 24
Peak memory 215544 kb
Host smart-9b85a51c-37ce-47db-8ddf-0f1bed0b25dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616793213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.616793213
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2790672373
Short name T182
Test name
Test status
Simulation time 5945211171 ps
CPU time 51.04 seconds
Started Jun 25 06:56:58 PM PDT 24
Finished Jun 25 06:57:50 PM PDT 24
Peak memory 258184 kb
Host smart-c483192d-0959-4433-8cf5-68703605f9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790672373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2790672373
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3036247826
Short name T12
Test name
Test status
Simulation time 15773465544 ps
CPU time 112.39 seconds
Started Jun 25 06:57:38 PM PDT 24
Finished Jun 25 06:59:31 PM PDT 24
Peak memory 250104 kb
Host smart-62071a73-342b-4c33-bd19-35ebb0d11b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036247826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3036247826
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1583563429
Short name T251
Test name
Test status
Simulation time 5269827876 ps
CPU time 76.46 seconds
Started Jun 25 06:55:03 PM PDT 24
Finished Jun 25 06:56:21 PM PDT 24
Peak memory 252220 kb
Host smart-378a9834-1bf5-40f1-8b83-8b4501c44c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583563429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1583563429
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2132376050
Short name T270
Test name
Test status
Simulation time 427450531150 ps
CPU time 312.83 seconds
Started Jun 25 06:57:16 PM PDT 24
Finished Jun 25 07:02:30 PM PDT 24
Peak memory 263200 kb
Host smart-f009df16-311a-4dc4-94f4-3a18efb76b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132376050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2132376050
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3369754786
Short name T286
Test name
Test status
Simulation time 2988285172 ps
CPU time 48.16 seconds
Started Jun 25 06:58:32 PM PDT 24
Finished Jun 25 06:59:21 PM PDT 24
Peak memory 235016 kb
Host smart-01e9407c-8853-4fb8-afee-651cd8cde735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369754786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3369754786
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.667994473
Short name T18
Test name
Test status
Simulation time 89274356014 ps
CPU time 225.81 seconds
Started Jun 25 06:55:30 PM PDT 24
Finished Jun 25 06:59:17 PM PDT 24
Peak memory 274748 kb
Host smart-02504491-4100-47fa-8bbc-d7fa29ab30f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667994473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.667994473
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3127154151
Short name T27
Test name
Test status
Simulation time 4983898809 ps
CPU time 20.36 seconds
Started Jun 25 06:55:38 PM PDT 24
Finished Jun 25 06:55:59 PM PDT 24
Peak memory 217404 kb
Host smart-eb4bf10f-1328-444b-9ed1-26e7c9165770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127154151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3127154151
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.429506028
Short name T249
Test name
Test status
Simulation time 18816767074 ps
CPU time 200.65 seconds
Started Jun 25 06:55:59 PM PDT 24
Finished Jun 25 06:59:20 PM PDT 24
Peak memory 267324 kb
Host smart-596bc97d-c206-4539-9483-ee64f84a38e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429506028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.429506028
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2605222671
Short name T71
Test name
Test status
Simulation time 17612056195 ps
CPU time 20 seconds
Started Jun 25 06:57:20 PM PDT 24
Finished Jun 25 06:57:41 PM PDT 24
Peak memory 225460 kb
Host smart-87218d38-b1b3-47a2-bb78-a4d38b1b749f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605222671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2605222671
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1850554060
Short name T15
Test name
Test status
Simulation time 4305614546 ps
CPU time 68.53 seconds
Started Jun 25 06:54:33 PM PDT 24
Finished Jun 25 06:55:42 PM PDT 24
Peak memory 256612 kb
Host smart-4a33aeeb-791f-4c98-b206-7aa7bd73f83e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850554060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1850554060
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3752216635
Short name T150
Test name
Test status
Simulation time 3119366484 ps
CPU time 22.82 seconds
Started Jun 25 05:09:52 PM PDT 24
Finished Jun 25 05:10:17 PM PDT 24
Peak memory 214996 kb
Host smart-61628d9b-bd2e-4877-adb5-aafe678f2ed8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752216635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3752216635
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3551977880
Short name T280
Test name
Test status
Simulation time 34328277784 ps
CPU time 363.19 seconds
Started Jun 25 06:55:14 PM PDT 24
Finished Jun 25 07:01:18 PM PDT 24
Peak memory 264252 kb
Host smart-487861bf-6af3-4ccf-ba3e-e1c811a01747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551977880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3551977880
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1249946338
Short name T37
Test name
Test status
Simulation time 308156750694 ps
CPU time 713.88 seconds
Started Jun 25 06:55:31 PM PDT 24
Finished Jun 25 07:07:26 PM PDT 24
Peak memory 269484 kb
Host smart-01b2ba6d-1739-41c2-8de6-9af702089646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249946338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1249946338
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.80864403
Short name T155
Test name
Test status
Simulation time 61217881560 ps
CPU time 141.94 seconds
Started Jun 25 06:55:32 PM PDT 24
Finished Jun 25 06:57:55 PM PDT 24
Peak memory 257172 kb
Host smart-94df77b6-7c2b-40c7-bba7-f1d62fc53098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80864403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.80864403
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1201393567
Short name T956
Test name
Test status
Simulation time 2406090616 ps
CPU time 8.98 seconds
Started Jun 25 06:55:37 PM PDT 24
Finished Jun 25 06:55:47 PM PDT 24
Peak memory 233728 kb
Host smart-2cd436f0-963a-4b45-ab2f-a9803a52c726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201393567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1201393567
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2493157722
Short name T279
Test name
Test status
Simulation time 51206037798 ps
CPU time 487.49 seconds
Started Jun 25 06:56:24 PM PDT 24
Finished Jun 25 07:04:34 PM PDT 24
Peak memory 266360 kb
Host smart-16948d0a-50ec-43c0-b8b5-4a01b167dcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493157722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2493157722
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1582121256
Short name T202
Test name
Test status
Simulation time 9824012807 ps
CPU time 135.58 seconds
Started Jun 25 06:56:42 PM PDT 24
Finished Jun 25 06:58:59 PM PDT 24
Peak memory 264412 kb
Host smart-b8cea5de-b851-44f0-8540-3d3a155db689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582121256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1582121256
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2838939361
Short name T88
Test name
Test status
Simulation time 305671760 ps
CPU time 3.71 seconds
Started Jun 25 05:09:36 PM PDT 24
Finished Jun 25 05:09:41 PM PDT 24
Peak memory 215072 kb
Host smart-138172c8-e3fd-4d41-8bfb-2a74634e9582
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838939361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2838939361
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3553665538
Short name T70
Test name
Test status
Simulation time 529701013 ps
CPU time 7.07 seconds
Started Jun 25 06:53:53 PM PDT 24
Finished Jun 25 06:54:01 PM PDT 24
Peak memory 233648 kb
Host smart-d8078ef4-151d-4cce-9e1f-390188a256e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553665538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3553665538
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2861796374
Short name T39
Test name
Test status
Simulation time 1277337015 ps
CPU time 11.91 seconds
Started Jun 25 06:55:02 PM PDT 24
Finished Jun 25 06:55:16 PM PDT 24
Peak memory 223504 kb
Host smart-9d0167e8-13ac-4b27-969f-ec66869922f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2861796374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2861796374
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2802523511
Short name T47
Test name
Test status
Simulation time 7844048034 ps
CPU time 22.17 seconds
Started Jun 25 06:54:42 PM PDT 24
Finished Jun 25 06:55:05 PM PDT 24
Peak memory 233736 kb
Host smart-f70d7252-39ce-4e42-876b-a0004f8ef553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802523511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2802523511
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3092471290
Short name T1052
Test name
Test status
Simulation time 722178940 ps
CPU time 13.46 seconds
Started Jun 25 05:09:20 PM PDT 24
Finished Jun 25 05:09:36 PM PDT 24
Peak memory 214908 kb
Host smart-8f8b1fba-82b1-49ce-a2e1-56d7c660118f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092471290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3092471290
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1776926045
Short name T1028
Test name
Test status
Simulation time 5016500474 ps
CPU time 26.26 seconds
Started Jun 25 05:09:19 PM PDT 24
Finished Jun 25 05:09:47 PM PDT 24
Peak memory 206696 kb
Host smart-49070134-75eb-4708-8271-147cdf2b40ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776926045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1776926045
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2900802696
Short name T1062
Test name
Test status
Simulation time 206561277 ps
CPU time 1.68 seconds
Started Jun 25 05:09:19 PM PDT 24
Finished Jun 25 05:09:23 PM PDT 24
Peak memory 214952 kb
Host smart-564886a6-c73a-4867-8de7-f4f01072a51b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900802696 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2900802696
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1280761455
Short name T1011
Test name
Test status
Simulation time 116490047 ps
CPU time 2.8 seconds
Started Jun 25 05:09:18 PM PDT 24
Finished Jun 25 05:09:22 PM PDT 24
Peak memory 214908 kb
Host smart-fcf139e7-5faf-4d25-bae3-88d2d017a002
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280761455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
280761455
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.4005264827
Short name T1071
Test name
Test status
Simulation time 21495084 ps
CPU time 0.73 seconds
Started Jun 25 05:09:18 PM PDT 24
Finished Jun 25 05:09:20 PM PDT 24
Peak memory 203504 kb
Host smart-4a0577bf-b603-4440-82e6-b6aa26818b5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005264827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.4
005264827
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2237828672
Short name T104
Test name
Test status
Simulation time 18780160 ps
CPU time 1.25 seconds
Started Jun 25 05:09:19 PM PDT 24
Finished Jun 25 05:09:22 PM PDT 24
Peak memory 214776 kb
Host smart-b81007c8-9d2c-4815-8262-855ce9fdd6a3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237828672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2237828672
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2516013596
Short name T1012
Test name
Test status
Simulation time 21220847 ps
CPU time 0.67 seconds
Started Jun 25 05:09:17 PM PDT 24
Finished Jun 25 05:09:18 PM PDT 24
Peak memory 203428 kb
Host smart-91a4dbe1-d815-4464-826d-35f23e113dea
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516013596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2516013596
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3435003704
Short name T977
Test name
Test status
Simulation time 43745783 ps
CPU time 2.63 seconds
Started Jun 25 05:09:17 PM PDT 24
Finished Jun 25 05:09:20 PM PDT 24
Peak memory 214860 kb
Host smart-ca0cb56a-dc76-4a99-975b-2e33d983ba39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435003704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3435003704
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2542563925
Short name T79
Test name
Test status
Simulation time 199995654 ps
CPU time 6.05 seconds
Started Jun 25 05:09:18 PM PDT 24
Finished Jun 25 05:09:25 PM PDT 24
Peak memory 214788 kb
Host smart-cf5c10b2-99a1-4425-b61e-df0e9a68738a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542563925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2542563925
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3523643535
Short name T1050
Test name
Test status
Simulation time 2337222670 ps
CPU time 8.52 seconds
Started Jun 25 05:09:29 PM PDT 24
Finished Jun 25 05:09:39 PM PDT 24
Peak memory 214892 kb
Host smart-d2c154c8-92e7-4785-9814-2ac34725d174
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523643535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3523643535
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2844329316
Short name T1020
Test name
Test status
Simulation time 1245297316 ps
CPU time 22.99 seconds
Started Jun 25 05:09:28 PM PDT 24
Finished Jun 25 05:09:53 PM PDT 24
Peak memory 206648 kb
Host smart-d24b761a-a9f8-451a-9fe2-08a601ef1b65
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844329316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2844329316
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3695998657
Short name T65
Test name
Test status
Simulation time 78092851 ps
CPU time 1.32 seconds
Started Jun 25 05:09:30 PM PDT 24
Finished Jun 25 05:09:34 PM PDT 24
Peak memory 206688 kb
Host smart-0a009917-34f6-47ff-98cf-878beaef5616
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695998657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3695998657
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.208643445
Short name T1018
Test name
Test status
Simulation time 252288670 ps
CPU time 2.54 seconds
Started Jun 25 05:09:25 PM PDT 24
Finished Jun 25 05:09:29 PM PDT 24
Peak memory 216692 kb
Host smart-b428a6ff-6841-4782-afa0-c857bbf1e9b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208643445 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.208643445
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1815457996
Short name T95
Test name
Test status
Simulation time 151728860 ps
CPU time 2.25 seconds
Started Jun 25 05:09:27 PM PDT 24
Finished Jun 25 05:09:30 PM PDT 24
Peak memory 206636 kb
Host smart-bb60a7fb-cf71-4494-81e3-c8c8f79c9366
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815457996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
815457996
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1987793443
Short name T1067
Test name
Test status
Simulation time 15057870 ps
CPU time 0.77 seconds
Started Jun 25 05:09:19 PM PDT 24
Finished Jun 25 05:09:22 PM PDT 24
Peak memory 203816 kb
Host smart-0fbf0205-b348-4fb1-9b00-ee9886eff241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987793443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
987793443
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1355564052
Short name T106
Test name
Test status
Simulation time 181969467 ps
CPU time 1.74 seconds
Started Jun 25 05:09:28 PM PDT 24
Finished Jun 25 05:09:31 PM PDT 24
Peak memory 214800 kb
Host smart-bb6a84d9-96e5-420f-8399-c1fdbf29d6cf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355564052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1355564052
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4165549066
Short name T979
Test name
Test status
Simulation time 17874952 ps
CPU time 0.68 seconds
Started Jun 25 05:09:21 PM PDT 24
Finished Jun 25 05:09:24 PM PDT 24
Peak memory 203568 kb
Host smart-aa2c5947-afee-4d67-bee0-6816725e0f8b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165549066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.4165549066
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.280136384
Short name T1030
Test name
Test status
Simulation time 58812969 ps
CPU time 3.66 seconds
Started Jun 25 05:09:30 PM PDT 24
Finished Jun 25 05:09:36 PM PDT 24
Peak memory 214868 kb
Host smart-febb79a4-299b-4f1c-a7a6-b1f6f76e4c5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280136384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.280136384
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3703891400
Short name T992
Test name
Test status
Simulation time 200947632 ps
CPU time 1.58 seconds
Started Jun 25 05:09:18 PM PDT 24
Finished Jun 25 05:09:22 PM PDT 24
Peak memory 215040 kb
Host smart-d43a92d9-029a-4636-a71a-ff7b44397b2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703891400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
703891400
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3396920900
Short name T91
Test name
Test status
Simulation time 107829048 ps
CPU time 6.33 seconds
Started Jun 25 05:09:19 PM PDT 24
Finished Jun 25 05:09:27 PM PDT 24
Peak memory 214912 kb
Host smart-476af3ec-b780-423b-b039-738e7e3ba47d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396920900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3396920900
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2170347264
Short name T982
Test name
Test status
Simulation time 240365585 ps
CPU time 4.08 seconds
Started Jun 25 05:09:37 PM PDT 24
Finished Jun 25 05:09:43 PM PDT 24
Peak memory 216848 kb
Host smart-9c64d478-ec96-46a4-b6fa-13eca06dd7c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170347264 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2170347264
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2547611868
Short name T102
Test name
Test status
Simulation time 62770949 ps
CPU time 2.07 seconds
Started Jun 25 05:09:39 PM PDT 24
Finished Jun 25 05:09:43 PM PDT 24
Peak memory 214856 kb
Host smart-12b8b6ad-3f3f-40eb-a7ed-b7ecd96129b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547611868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2547611868
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.21343099
Short name T1054
Test name
Test status
Simulation time 15763977 ps
CPU time 0.74 seconds
Started Jun 25 05:09:37 PM PDT 24
Finished Jun 25 05:09:39 PM PDT 24
Peak memory 203508 kb
Host smart-0e948213-e7ab-45a7-b970-edb287fee7b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21343099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.21343099
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2325719779
Short name T1022
Test name
Test status
Simulation time 759045928 ps
CPU time 4.26 seconds
Started Jun 25 05:09:39 PM PDT 24
Finished Jun 25 05:09:45 PM PDT 24
Peak memory 214884 kb
Host smart-20e6531b-a24e-46db-8477-f10d653551a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325719779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2325719779
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2996870340
Short name T83
Test name
Test status
Simulation time 44468255 ps
CPU time 2.56 seconds
Started Jun 25 05:09:40 PM PDT 24
Finished Jun 25 05:09:44 PM PDT 24
Peak memory 215008 kb
Host smart-c86507ec-8596-4eed-a774-4337fd63a3fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996870340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2996870340
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2364483848
Short name T1016
Test name
Test status
Simulation time 1109725542 ps
CPU time 17.29 seconds
Started Jun 25 05:09:41 PM PDT 24
Finished Jun 25 05:09:59 PM PDT 24
Peak memory 214796 kb
Host smart-90cc1060-3202-4bc2-9095-064af2b0fd04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364483848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2364483848
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2222512387
Short name T1080
Test name
Test status
Simulation time 38372865 ps
CPU time 2.67 seconds
Started Jun 25 05:09:38 PM PDT 24
Finished Jun 25 05:09:43 PM PDT 24
Peak memory 216212 kb
Host smart-c925cddd-9397-4cf9-9de0-7c5915543056
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222512387 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2222512387
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3550366242
Short name T101
Test name
Test status
Simulation time 34029810 ps
CPU time 1.93 seconds
Started Jun 25 05:09:38 PM PDT 24
Finished Jun 25 05:09:42 PM PDT 24
Peak memory 214876 kb
Host smart-e4a72f6d-c5b0-432c-bfaa-95f4f1ac145d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550366242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3550366242
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.404242335
Short name T983
Test name
Test status
Simulation time 14933276 ps
CPU time 0.76 seconds
Started Jun 25 05:09:40 PM PDT 24
Finished Jun 25 05:09:43 PM PDT 24
Peak memory 203324 kb
Host smart-fe4aa3c1-3b85-41ac-978f-20eb1081f34f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404242335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.404242335
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3565663666
Short name T122
Test name
Test status
Simulation time 366646500 ps
CPU time 1.87 seconds
Started Jun 25 05:09:38 PM PDT 24
Finished Jun 25 05:09:42 PM PDT 24
Peak memory 206660 kb
Host smart-960b8b5d-f04c-4733-8688-7bec2dd922e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565663666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3565663666
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1140940180
Short name T53
Test name
Test status
Simulation time 391220263 ps
CPU time 11.95 seconds
Started Jun 25 05:09:38 PM PDT 24
Finished Jun 25 05:09:52 PM PDT 24
Peak memory 214760 kb
Host smart-43e515fc-7b44-4f57-b714-8e663bdc0671
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140940180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1140940180
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4172437158
Short name T971
Test name
Test status
Simulation time 372336978 ps
CPU time 3.98 seconds
Started Jun 25 05:09:37 PM PDT 24
Finished Jun 25 05:09:43 PM PDT 24
Peak memory 217312 kb
Host smart-2f869d64-1dfb-4837-bcb5-b76959309d73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172437158 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.4172437158
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3125400695
Short name T1047
Test name
Test status
Simulation time 114067680 ps
CPU time 2.04 seconds
Started Jun 25 05:09:37 PM PDT 24
Finished Jun 25 05:09:41 PM PDT 24
Peak memory 214936 kb
Host smart-5cae638d-8daf-4753-a8ef-2ec3e15fd377
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125400695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3125400695
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2936219306
Short name T965
Test name
Test status
Simulation time 25313785 ps
CPU time 0.75 seconds
Started Jun 25 05:09:36 PM PDT 24
Finished Jun 25 05:09:38 PM PDT 24
Peak memory 203524 kb
Host smart-9db3d3b9-8f61-46fa-9933-b943163b4c99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936219306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2936219306
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3850186289
Short name T111
Test name
Test status
Simulation time 67393051 ps
CPU time 3.8 seconds
Started Jun 25 05:09:37 PM PDT 24
Finished Jun 25 05:09:43 PM PDT 24
Peak memory 214792 kb
Host smart-1e84b88d-8edb-4089-bd48-fe4748395eac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850186289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3850186289
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.943253905
Short name T87
Test name
Test status
Simulation time 139182591 ps
CPU time 4 seconds
Started Jun 25 05:09:40 PM PDT 24
Finished Jun 25 05:09:46 PM PDT 24
Peak memory 215108 kb
Host smart-d4a27f15-1cb0-474f-b588-cdcc8ceb5dfa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943253905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.943253905
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2605341074
Short name T1074
Test name
Test status
Simulation time 392399203 ps
CPU time 7.9 seconds
Started Jun 25 05:09:38 PM PDT 24
Finished Jun 25 05:09:48 PM PDT 24
Peak memory 214804 kb
Host smart-34bb90eb-27f2-4740-9933-f71779790126
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605341074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2605341074
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.345862800
Short name T974
Test name
Test status
Simulation time 308123182 ps
CPU time 3.09 seconds
Started Jun 25 05:09:37 PM PDT 24
Finished Jun 25 05:09:41 PM PDT 24
Peak memory 217088 kb
Host smart-aafab9b6-99a6-4f7e-8f0a-79d13402bda2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345862800 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.345862800
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1791176679
Short name T97
Test name
Test status
Simulation time 70916271 ps
CPU time 1.37 seconds
Started Jun 25 05:09:38 PM PDT 24
Finished Jun 25 05:09:41 PM PDT 24
Peak memory 206708 kb
Host smart-3ba8a8dc-769e-4e89-95fc-22b2b2d9b307
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791176679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1791176679
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1153362390
Short name T986
Test name
Test status
Simulation time 113583830 ps
CPU time 0.69 seconds
Started Jun 25 05:09:39 PM PDT 24
Finished Jun 25 05:09:41 PM PDT 24
Peak memory 203720 kb
Host smart-6acab025-dfaa-4dcd-8133-8770e0638795
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153362390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1153362390
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1677712786
Short name T1003
Test name
Test status
Simulation time 232103843 ps
CPU time 4.16 seconds
Started Jun 25 05:09:37 PM PDT 24
Finished Jun 25 05:09:42 PM PDT 24
Peak memory 215216 kb
Host smart-59692d65-f8d5-488c-8420-043625dbebf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677712786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1677712786
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.981876647
Short name T1006
Test name
Test status
Simulation time 125893104 ps
CPU time 4.33 seconds
Started Jun 25 05:09:37 PM PDT 24
Finished Jun 25 05:09:43 PM PDT 24
Peak memory 215080 kb
Host smart-1cb91def-21ec-43ad-b6ed-03fec5594412
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981876647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.981876647
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.890241308
Short name T123
Test name
Test status
Simulation time 2254965207 ps
CPU time 8.59 seconds
Started Jun 25 05:09:36 PM PDT 24
Finished Jun 25 05:09:46 PM PDT 24
Peak memory 215076 kb
Host smart-7f2d6db1-ea6f-4d8c-b2ed-0068e8cbac4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890241308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.890241308
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1291142424
Short name T978
Test name
Test status
Simulation time 64254254 ps
CPU time 4.15 seconds
Started Jun 25 05:09:46 PM PDT 24
Finished Jun 25 05:09:51 PM PDT 24
Peak memory 216788 kb
Host smart-279ea020-6545-44e0-acc3-755036bdbd03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291142424 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1291142424
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4072592840
Short name T100
Test name
Test status
Simulation time 194792666 ps
CPU time 2.84 seconds
Started Jun 25 05:09:46 PM PDT 24
Finished Jun 25 05:09:50 PM PDT 24
Peak memory 214844 kb
Host smart-5141de52-91db-450d-87e0-bcabe7af8a78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072592840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
4072592840
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.672310358
Short name T1057
Test name
Test status
Simulation time 50749023 ps
CPU time 0.77 seconds
Started Jun 25 05:09:50 PM PDT 24
Finished Jun 25 05:09:52 PM PDT 24
Peak memory 203420 kb
Host smart-2d760ec8-26a7-4b8e-913c-dc8eb81bcbec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672310358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.672310358
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.920857071
Short name T980
Test name
Test status
Simulation time 379240656 ps
CPU time 2.86 seconds
Started Jun 25 05:09:52 PM PDT 24
Finished Jun 25 05:09:57 PM PDT 24
Peak memory 214892 kb
Host smart-453edd6c-5fb5-45e9-a19d-914dbcc0db74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920857071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.920857071
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2080436794
Short name T55
Test name
Test status
Simulation time 204644244 ps
CPU time 2.14 seconds
Started Jun 25 05:09:46 PM PDT 24
Finished Jun 25 05:09:49 PM PDT 24
Peak memory 215040 kb
Host smart-4749b2a2-eaf9-4e40-aa89-1807c7a75f32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080436794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2080436794
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1786881446
Short name T124
Test name
Test status
Simulation time 13840668392 ps
CPU time 16.1 seconds
Started Jun 25 05:09:46 PM PDT 24
Finished Jun 25 05:10:04 PM PDT 24
Peak memory 214972 kb
Host smart-3339e820-3d49-4a77-81f5-977acba0bf0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786881446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1786881446
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.4294252540
Short name T94
Test name
Test status
Simulation time 913861383 ps
CPU time 1.82 seconds
Started Jun 25 05:09:46 PM PDT 24
Finished Jun 25 05:09:49 PM PDT 24
Peak memory 214896 kb
Host smart-225348fe-28da-4f1b-b5b6-51ad57774435
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294252540 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.4294252540
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.28884724
Short name T1072
Test name
Test status
Simulation time 167997907 ps
CPU time 2.2 seconds
Started Jun 25 05:09:53 PM PDT 24
Finished Jun 25 05:09:57 PM PDT 24
Peak memory 214912 kb
Host smart-06bb6330-78bd-4e2e-8575-d93a758311da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28884724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.28884724
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1832692447
Short name T968
Test name
Test status
Simulation time 32115246 ps
CPU time 0.68 seconds
Started Jun 25 05:09:46 PM PDT 24
Finished Jun 25 05:09:48 PM PDT 24
Peak memory 203504 kb
Host smart-4a84d711-8f70-4d23-baeb-88ec1d1a8aa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832692447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1832692447
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3799144547
Short name T1000
Test name
Test status
Simulation time 115527239 ps
CPU time 3.73 seconds
Started Jun 25 05:09:46 PM PDT 24
Finished Jun 25 05:09:50 PM PDT 24
Peak memory 214868 kb
Host smart-24e7ed33-7718-4d37-9b8d-99e0ea927fb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799144547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3799144547
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3656166500
Short name T1048
Test name
Test status
Simulation time 786761795 ps
CPU time 5.68 seconds
Started Jun 25 05:09:49 PM PDT 24
Finished Jun 25 05:09:56 PM PDT 24
Peak memory 214956 kb
Host smart-92979be2-528f-441b-965d-7e8f3ae70c71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656166500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3656166500
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2549798099
Short name T148
Test name
Test status
Simulation time 1175132453 ps
CPU time 19.32 seconds
Started Jun 25 05:09:45 PM PDT 24
Finished Jun 25 05:10:06 PM PDT 24
Peak memory 214860 kb
Host smart-3a9aca8b-9ef7-42b3-b19e-fd1cfa125662
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549798099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2549798099
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3837815459
Short name T1031
Test name
Test status
Simulation time 134685322 ps
CPU time 3.78 seconds
Started Jun 25 05:09:50 PM PDT 24
Finished Jun 25 05:09:56 PM PDT 24
Peak memory 216996 kb
Host smart-5eea10fe-5fa2-43d4-9804-aff0fc0e8def
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837815459 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3837815459
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1099241708
Short name T1008
Test name
Test status
Simulation time 114264622 ps
CPU time 2.67 seconds
Started Jun 25 05:09:48 PM PDT 24
Finished Jun 25 05:09:51 PM PDT 24
Peak memory 214912 kb
Host smart-013f6609-5312-4b34-9de4-af462045ae50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099241708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1099241708
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4077398158
Short name T996
Test name
Test status
Simulation time 11189619 ps
CPU time 0.79 seconds
Started Jun 25 05:09:48 PM PDT 24
Finished Jun 25 05:09:50 PM PDT 24
Peak memory 203836 kb
Host smart-0c637a0b-0b4b-4217-bd47-fddb90bec7fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077398158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
4077398158
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3010516
Short name T993
Test name
Test status
Simulation time 298531385 ps
CPU time 2.01 seconds
Started Jun 25 05:09:50 PM PDT 24
Finished Jun 25 05:09:54 PM PDT 24
Peak memory 206616 kb
Host smart-c01b407f-56b7-4a20-ab66-f22d64e296c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi
_device_same_csr_outstanding.3010516
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2969098966
Short name T77
Test name
Test status
Simulation time 150487229 ps
CPU time 4.02 seconds
Started Jun 25 05:09:46 PM PDT 24
Finished Jun 25 05:09:51 PM PDT 24
Peak memory 215068 kb
Host smart-d2bfee9f-08f3-4581-8fce-49c043c5de23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969098966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2969098966
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3294797634
Short name T1004
Test name
Test status
Simulation time 227327052 ps
CPU time 4.19 seconds
Started Jun 25 05:09:50 PM PDT 24
Finished Jun 25 05:09:56 PM PDT 24
Peak memory 216652 kb
Host smart-62a118cd-4b61-468b-b8b8-0b3b585e38d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294797634 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3294797634
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.589630417
Short name T103
Test name
Test status
Simulation time 68112497 ps
CPU time 2 seconds
Started Jun 25 05:09:45 PM PDT 24
Finished Jun 25 05:09:48 PM PDT 24
Peak memory 214880 kb
Host smart-6f6f0f33-97a9-48d6-812c-8fb6b71d3959
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589630417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.589630417
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1758666054
Short name T1040
Test name
Test status
Simulation time 159490377 ps
CPU time 0.75 seconds
Started Jun 25 05:09:48 PM PDT 24
Finished Jun 25 05:09:50 PM PDT 24
Peak memory 203732 kb
Host smart-89aaf144-308d-4e8f-ac2b-3aa86fab5348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758666054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1758666054
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3523605188
Short name T1005
Test name
Test status
Simulation time 47434179 ps
CPU time 1.7 seconds
Started Jun 25 05:09:52 PM PDT 24
Finished Jun 25 05:09:56 PM PDT 24
Peak memory 214904 kb
Host smart-0f20b0fd-b59c-49d9-b7ce-0ad4dfeecad3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523605188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3523605188
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3458443953
Short name T1015
Test name
Test status
Simulation time 105216412 ps
CPU time 3.21 seconds
Started Jun 25 05:09:48 PM PDT 24
Finished Jun 25 05:09:53 PM PDT 24
Peak memory 216088 kb
Host smart-96a08a74-0dd1-4354-8068-6e790391cd03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458443953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3458443953
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2535319451
Short name T147
Test name
Test status
Simulation time 1107452329 ps
CPU time 24.7 seconds
Started Jun 25 05:09:50 PM PDT 24
Finished Jun 25 05:10:17 PM PDT 24
Peak memory 215064 kb
Host smart-15592c19-1280-4cb3-8599-4f5092c4c629
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535319451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2535319451
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.805154304
Short name T90
Test name
Test status
Simulation time 158060996 ps
CPU time 3.61 seconds
Started Jun 25 05:09:54 PM PDT 24
Finished Jun 25 05:10:00 PM PDT 24
Peak memory 217192 kb
Host smart-f4197004-4c16-41b1-9de3-67cca099d4f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805154304 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.805154304
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1448419013
Short name T96
Test name
Test status
Simulation time 115105148 ps
CPU time 2.84 seconds
Started Jun 25 05:09:53 PM PDT 24
Finished Jun 25 05:09:57 PM PDT 24
Peak memory 214940 kb
Host smart-7180106b-4690-4a4f-bc2e-bd800db79f96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448419013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1448419013
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3263270321
Short name T1070
Test name
Test status
Simulation time 11227321 ps
CPU time 0.73 seconds
Started Jun 25 05:09:52 PM PDT 24
Finished Jun 25 05:09:54 PM PDT 24
Peak memory 203524 kb
Host smart-df14269d-acc2-49c3-a988-700e7a6facf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263270321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3263270321
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4039054523
Short name T984
Test name
Test status
Simulation time 536130794 ps
CPU time 1.59 seconds
Started Jun 25 05:09:53 PM PDT 24
Finished Jun 25 05:09:56 PM PDT 24
Peak memory 214864 kb
Host smart-23284c08-74d5-49bf-9472-929be23f3a99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039054523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.4039054523
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3591388214
Short name T1078
Test name
Test status
Simulation time 52681852 ps
CPU time 3.41 seconds
Started Jun 25 05:09:54 PM PDT 24
Finished Jun 25 05:10:00 PM PDT 24
Peak memory 216124 kb
Host smart-96e12ff7-eb15-4674-a25d-dc14451fffcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591388214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3591388214
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2469826327
Short name T92
Test name
Test status
Simulation time 86759918 ps
CPU time 1.8 seconds
Started Jun 25 05:09:49 PM PDT 24
Finished Jun 25 05:09:52 PM PDT 24
Peak memory 216012 kb
Host smart-f9abbcb9-6da6-4c31-ad79-9a2dba9193b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469826327 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2469826327
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1465939595
Short name T107
Test name
Test status
Simulation time 64148990 ps
CPU time 1.21 seconds
Started Jun 25 05:09:46 PM PDT 24
Finished Jun 25 05:09:48 PM PDT 24
Peak memory 214928 kb
Host smart-67b895b4-f1b6-4c71-9866-f2a06c184b8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465939595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1465939595
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1510078684
Short name T1013
Test name
Test status
Simulation time 46345893 ps
CPU time 0.68 seconds
Started Jun 25 05:09:53 PM PDT 24
Finished Jun 25 05:09:55 PM PDT 24
Peak memory 203512 kb
Host smart-57dced2b-bbab-4e16-a8cf-e1a6a310d14e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510078684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1510078684
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1253622874
Short name T1068
Test name
Test status
Simulation time 446811152 ps
CPU time 3.26 seconds
Started Jun 25 05:09:45 PM PDT 24
Finished Jun 25 05:09:49 PM PDT 24
Peak memory 214884 kb
Host smart-5876dc8e-f9fa-4b0b-858d-02d008eedad6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253622874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1253622874
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4071236299
Short name T54
Test name
Test status
Simulation time 51208147 ps
CPU time 3.03 seconds
Started Jun 25 05:09:47 PM PDT 24
Finished Jun 25 05:09:51 PM PDT 24
Peak memory 215076 kb
Host smart-4191318a-87da-42ff-a562-b5d298944459
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071236299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
4071236299
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.106980924
Short name T1009
Test name
Test status
Simulation time 334072982 ps
CPU time 7.45 seconds
Started Jun 25 05:09:52 PM PDT 24
Finished Jun 25 05:10:01 PM PDT 24
Peak memory 214916 kb
Host smart-13165850-ab1e-484d-a5c6-33eb13c8e347
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106980924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.106980924
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1707296784
Short name T1073
Test name
Test status
Simulation time 3036493002 ps
CPU time 15.2 seconds
Started Jun 25 05:09:30 PM PDT 24
Finished Jun 25 05:09:48 PM PDT 24
Peak memory 214988 kb
Host smart-9958b794-e31d-4fa6-b56e-2e1eb445adab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707296784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1707296784
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1756675046
Short name T1024
Test name
Test status
Simulation time 1864605482 ps
CPU time 24.15 seconds
Started Jun 25 05:09:28 PM PDT 24
Finished Jun 25 05:09:54 PM PDT 24
Peak memory 206732 kb
Host smart-7ceb7216-3184-436d-bbf4-377df9f12f19
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756675046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1756675046
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2652342191
Short name T63
Test name
Test status
Simulation time 18824809 ps
CPU time 1.14 seconds
Started Jun 25 05:09:30 PM PDT 24
Finished Jun 25 05:09:34 PM PDT 24
Peak memory 206708 kb
Host smart-df84f9f5-43b2-4261-a557-456d135cdbf4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652342191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2652342191
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1469321401
Short name T1001
Test name
Test status
Simulation time 304450807 ps
CPU time 1.64 seconds
Started Jun 25 05:09:29 PM PDT 24
Finished Jun 25 05:09:32 PM PDT 24
Peak memory 214848 kb
Host smart-8674828c-9722-4db4-979f-5ea6017d7bee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469321401 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1469321401
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4177065323
Short name T112
Test name
Test status
Simulation time 67762321 ps
CPU time 1.97 seconds
Started Jun 25 05:09:26 PM PDT 24
Finished Jun 25 05:09:29 PM PDT 24
Peak memory 214784 kb
Host smart-6aa757cb-8145-4488-ad97-b355f3a4ac6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177065323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.4
177065323
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2389878511
Short name T994
Test name
Test status
Simulation time 15471081 ps
CPU time 0.74 seconds
Started Jun 25 05:09:27 PM PDT 24
Finished Jun 25 05:09:28 PM PDT 24
Peak memory 203716 kb
Host smart-a5eefa68-e455-4320-8ab8-03b49f801529
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389878511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
389878511
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2154786966
Short name T1075
Test name
Test status
Simulation time 154162838 ps
CPU time 1.82 seconds
Started Jun 25 05:09:29 PM PDT 24
Finished Jun 25 05:09:33 PM PDT 24
Peak memory 214936 kb
Host smart-f3477a21-d62a-4c0f-8507-c3e4931afad6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154786966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2154786966
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.875129115
Short name T1017
Test name
Test status
Simulation time 26617132 ps
CPU time 0.66 seconds
Started Jun 25 05:09:30 PM PDT 24
Finished Jun 25 05:09:33 PM PDT 24
Peak memory 203736 kb
Host smart-810aa24f-81a5-424d-8c43-9d90fc012fe6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875129115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.875129115
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1029493043
Short name T967
Test name
Test status
Simulation time 264862159 ps
CPU time 1.88 seconds
Started Jun 25 05:09:26 PM PDT 24
Finished Jun 25 05:09:29 PM PDT 24
Peak memory 214872 kb
Host smart-89430132-7462-4475-8ef4-fdbb39825a9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029493043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1029493043
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.122567629
Short name T1025
Test name
Test status
Simulation time 347769108 ps
CPU time 2.47 seconds
Started Jun 25 05:09:28 PM PDT 24
Finished Jun 25 05:09:31 PM PDT 24
Peak memory 216144 kb
Host smart-c5911ec4-145a-4bdd-9241-6f141b9b9885
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122567629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.122567629
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2881720936
Short name T1069
Test name
Test status
Simulation time 44934359 ps
CPU time 0.75 seconds
Started Jun 25 05:09:47 PM PDT 24
Finished Jun 25 05:09:49 PM PDT 24
Peak memory 203816 kb
Host smart-b384aafa-3351-460e-b3a6-59747a7fea96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881720936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2881720936
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1947804586
Short name T966
Test name
Test status
Simulation time 30197058 ps
CPU time 0.78 seconds
Started Jun 25 05:09:55 PM PDT 24
Finished Jun 25 05:09:57 PM PDT 24
Peak memory 203416 kb
Host smart-ad3c3ab6-5faf-4a74-9a54-3a0b45f742cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947804586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1947804586
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4072056360
Short name T959
Test name
Test status
Simulation time 11558022 ps
CPU time 0.71 seconds
Started Jun 25 05:09:57 PM PDT 24
Finished Jun 25 05:10:02 PM PDT 24
Peak memory 203504 kb
Host smart-f1a8d557-2e60-49a0-aed9-e59369e4848e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072056360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
4072056360
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3923904748
Short name T1081
Test name
Test status
Simulation time 23057452 ps
CPU time 0.69 seconds
Started Jun 25 05:09:56 PM PDT 24
Finished Jun 25 05:10:00 PM PDT 24
Peak memory 203828 kb
Host smart-65406caa-481c-4cb4-a9b8-bf3278a283dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923904748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3923904748
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2370176727
Short name T1046
Test name
Test status
Simulation time 14543823 ps
CPU time 0.72 seconds
Started Jun 25 05:09:55 PM PDT 24
Finished Jun 25 05:09:58 PM PDT 24
Peak memory 203364 kb
Host smart-288ca49b-0e59-49fa-a0ba-6f05698b50c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370176727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2370176727
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.537007000
Short name T1061
Test name
Test status
Simulation time 14722882 ps
CPU time 0.77 seconds
Started Jun 25 05:09:55 PM PDT 24
Finished Jun 25 05:10:00 PM PDT 24
Peak memory 203708 kb
Host smart-3b5687a5-a685-41fb-96c3-b8b08a4a92f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537007000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.537007000
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2095958778
Short name T969
Test name
Test status
Simulation time 55622587 ps
CPU time 0.79 seconds
Started Jun 25 05:09:56 PM PDT 24
Finished Jun 25 05:10:00 PM PDT 24
Peak memory 203396 kb
Host smart-4fd50ab8-ea6f-4782-8c6d-0b894ab066bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095958778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2095958778
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.739382831
Short name T1026
Test name
Test status
Simulation time 120801108 ps
CPU time 0.79 seconds
Started Jun 25 05:09:56 PM PDT 24
Finished Jun 25 05:10:00 PM PDT 24
Peak memory 203532 kb
Host smart-6b322364-cb2a-4c6a-833d-55ed657d1f4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739382831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.739382831
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4242219955
Short name T1045
Test name
Test status
Simulation time 40171533 ps
CPU time 0.77 seconds
Started Jun 25 05:09:58 PM PDT 24
Finished Jun 25 05:10:02 PM PDT 24
Peak memory 203828 kb
Host smart-0c1e4d94-0895-4588-b004-d25dbc952ddc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242219955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
4242219955
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3711436334
Short name T990
Test name
Test status
Simulation time 22234672 ps
CPU time 0.77 seconds
Started Jun 25 05:09:55 PM PDT 24
Finished Jun 25 05:09:59 PM PDT 24
Peak memory 203504 kb
Host smart-7b312386-4889-4be9-ab89-4141957d1d13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711436334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3711436334
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.374376086
Short name T1037
Test name
Test status
Simulation time 607854180 ps
CPU time 7.88 seconds
Started Jun 25 05:09:29 PM PDT 24
Finished Jun 25 05:09:39 PM PDT 24
Peak memory 206708 kb
Host smart-71dc487f-3adf-4b1d-b363-4c65df35012e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374376086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.374376086
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1591000645
Short name T1055
Test name
Test status
Simulation time 1824843141 ps
CPU time 26.23 seconds
Started Jun 25 05:09:29 PM PDT 24
Finished Jun 25 05:09:58 PM PDT 24
Peak memory 206676 kb
Host smart-7179f891-b412-4b54-8024-c302b0d226f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591000645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1591000645
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.401421624
Short name T1033
Test name
Test status
Simulation time 47219527 ps
CPU time 1.43 seconds
Started Jun 25 05:09:27 PM PDT 24
Finished Jun 25 05:09:29 PM PDT 24
Peak memory 206664 kb
Host smart-acabfaee-cebc-46ed-b4b7-9239530adf01
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401421624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.401421624
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2197705824
Short name T999
Test name
Test status
Simulation time 54067421 ps
CPU time 3.9 seconds
Started Jun 25 05:09:31 PM PDT 24
Finished Jun 25 05:09:38 PM PDT 24
Peak memory 217916 kb
Host smart-ca0aeb68-6591-4c07-88db-8a0bab9bd589
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197705824 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2197705824
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1012715124
Short name T105
Test name
Test status
Simulation time 64088543 ps
CPU time 2.19 seconds
Started Jun 25 05:09:29 PM PDT 24
Finished Jun 25 05:09:33 PM PDT 24
Peak memory 214832 kb
Host smart-c912c5d8-c86a-4b74-a6c3-7dd8a8981507
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012715124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
012715124
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3133265668
Short name T1010
Test name
Test status
Simulation time 19582053 ps
CPU time 0.74 seconds
Started Jun 25 05:09:30 PM PDT 24
Finished Jun 25 05:09:34 PM PDT 24
Peak memory 203832 kb
Host smart-2c5ccb34-5f59-4b49-81f9-96c31b838a97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133265668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
133265668
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3022009182
Short name T99
Test name
Test status
Simulation time 84950973 ps
CPU time 1.77 seconds
Started Jun 25 05:09:32 PM PDT 24
Finished Jun 25 05:09:36 PM PDT 24
Peak memory 214940 kb
Host smart-1c870290-06e2-4ddf-b9ef-8ee0b2de0494
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022009182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3022009182
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2954446763
Short name T973
Test name
Test status
Simulation time 11807589 ps
CPU time 0.7 seconds
Started Jun 25 05:09:27 PM PDT 24
Finished Jun 25 05:09:29 PM PDT 24
Peak memory 203400 kb
Host smart-91a9278e-0715-4c46-94f6-890f1b9c8e1a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954446763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2954446763
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.865491098
Short name T972
Test name
Test status
Simulation time 410027570 ps
CPU time 3.11 seconds
Started Jun 25 05:09:31 PM PDT 24
Finished Jun 25 05:09:37 PM PDT 24
Peak memory 214900 kb
Host smart-60116776-59b6-48d3-b4c4-0e359c7a3a33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865491098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.865491098
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3995282566
Short name T84
Test name
Test status
Simulation time 290695237 ps
CPU time 3.63 seconds
Started Jun 25 05:09:28 PM PDT 24
Finished Jun 25 05:09:33 PM PDT 24
Peak memory 214940 kb
Host smart-40d9104f-2571-46a0-bb61-832b076c9c19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995282566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
995282566
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.14445017
Short name T93
Test name
Test status
Simulation time 751669663 ps
CPU time 15.73 seconds
Started Jun 25 05:09:32 PM PDT 24
Finished Jun 25 05:09:50 PM PDT 24
Peak memory 215504 kb
Host smart-8cbe1cee-0075-4cda-a485-c594d543d7b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14445017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_t
l_intg_err.14445017
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.899246045
Short name T989
Test name
Test status
Simulation time 74441680 ps
CPU time 0.74 seconds
Started Jun 25 05:09:56 PM PDT 24
Finished Jun 25 05:10:01 PM PDT 24
Peak memory 203832 kb
Host smart-c69a64e0-5711-4a9f-8cc3-c567624d9515
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899246045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.899246045
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1714986026
Short name T988
Test name
Test status
Simulation time 26011152 ps
CPU time 0.76 seconds
Started Jun 25 05:09:55 PM PDT 24
Finished Jun 25 05:09:58 PM PDT 24
Peak memory 203716 kb
Host smart-7d985512-22f3-4a51-813e-bf3c42ae402a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714986026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1714986026
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3389640819
Short name T975
Test name
Test status
Simulation time 134943836 ps
CPU time 0.73 seconds
Started Jun 25 05:09:56 PM PDT 24
Finished Jun 25 05:10:01 PM PDT 24
Peak memory 203428 kb
Host smart-4fb39a25-7b66-4392-879f-b45bbb737c1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389640819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3389640819
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.221408832
Short name T987
Test name
Test status
Simulation time 22984753 ps
CPU time 0.77 seconds
Started Jun 25 05:09:57 PM PDT 24
Finished Jun 25 05:10:01 PM PDT 24
Peak memory 203524 kb
Host smart-77dff849-fde9-4b74-a8da-9ff01e11e3b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221408832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.221408832
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2617551344
Short name T997
Test name
Test status
Simulation time 42751351 ps
CPU time 0.73 seconds
Started Jun 25 05:09:55 PM PDT 24
Finished Jun 25 05:10:00 PM PDT 24
Peak memory 203668 kb
Host smart-03869586-8488-44e6-9a31-864535373429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617551344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2617551344
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1668958236
Short name T961
Test name
Test status
Simulation time 24727120 ps
CPU time 0.77 seconds
Started Jun 25 05:09:57 PM PDT 24
Finished Jun 25 05:10:02 PM PDT 24
Peak memory 203524 kb
Host smart-ca6836bb-fea4-4623-886a-60db0ee958da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668958236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1668958236
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.384488333
Short name T995
Test name
Test status
Simulation time 64972086 ps
CPU time 0.71 seconds
Started Jun 25 05:09:56 PM PDT 24
Finished Jun 25 05:10:00 PM PDT 24
Peak memory 203520 kb
Host smart-8687571d-18e4-40f9-b182-5baea37901b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384488333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.384488333
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3683637969
Short name T1044
Test name
Test status
Simulation time 14471071 ps
CPU time 0.71 seconds
Started Jun 25 05:09:55 PM PDT 24
Finished Jun 25 05:09:57 PM PDT 24
Peak memory 203508 kb
Host smart-3b8382ee-b0d2-4a4f-9ae6-0862e37d56a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683637969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3683637969
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.517655999
Short name T998
Test name
Test status
Simulation time 16878188 ps
CPU time 0.76 seconds
Started Jun 25 05:09:56 PM PDT 24
Finished Jun 25 05:10:00 PM PDT 24
Peak memory 203808 kb
Host smart-f5c452e1-b0cb-4af3-a219-81c4789d3938
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517655999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.517655999
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1000677685
Short name T1053
Test name
Test status
Simulation time 12812520 ps
CPU time 0.72 seconds
Started Jun 25 05:09:56 PM PDT 24
Finished Jun 25 05:10:01 PM PDT 24
Peak memory 203736 kb
Host smart-117c7af2-7351-4935-bd8e-59d5c1d30a60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000677685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1000677685
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.980874166
Short name T1065
Test name
Test status
Simulation time 306303070 ps
CPU time 7.97 seconds
Started Jun 25 05:09:30 PM PDT 24
Finished Jun 25 05:09:40 PM PDT 24
Peak memory 206728 kb
Host smart-a9d8e308-2a48-431e-b5a7-68cef940ff02
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980874166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.980874166
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2045799518
Short name T1034
Test name
Test status
Simulation time 2512303003 ps
CPU time 23.91 seconds
Started Jun 25 05:09:33 PM PDT 24
Finished Jun 25 05:09:59 PM PDT 24
Peak memory 206744 kb
Host smart-98e4fe5f-dcb2-4cd1-9548-8bcc176703f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045799518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2045799518
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.768621309
Short name T1056
Test name
Test status
Simulation time 191719644 ps
CPU time 1.47 seconds
Started Jun 25 05:09:33 PM PDT 24
Finished Jun 25 05:09:36 PM PDT 24
Peak memory 206752 kb
Host smart-ef809ff6-3099-4148-940e-1207e5d8e2f9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768621309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.768621309
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4199832914
Short name T1079
Test name
Test status
Simulation time 52404652 ps
CPU time 1.75 seconds
Started Jun 25 05:09:28 PM PDT 24
Finished Jun 25 05:09:31 PM PDT 24
Peak memory 214972 kb
Host smart-13455ea6-49d3-4bb6-8b76-e6eba170844a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199832914 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.4199832914
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2819229615
Short name T113
Test name
Test status
Simulation time 21383913 ps
CPU time 1.27 seconds
Started Jun 25 05:09:28 PM PDT 24
Finished Jun 25 05:09:31 PM PDT 24
Peak memory 214888 kb
Host smart-07809085-7b10-4683-a483-52df08a6f621
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819229615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
819229615
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1505677892
Short name T960
Test name
Test status
Simulation time 28854807 ps
CPU time 0.78 seconds
Started Jun 25 05:09:29 PM PDT 24
Finished Jun 25 05:09:32 PM PDT 24
Peak memory 203736 kb
Host smart-37496c9e-60cd-4e6f-ad4c-9b5c1e476a25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505677892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
505677892
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.379074837
Short name T1043
Test name
Test status
Simulation time 207301807 ps
CPU time 2.15 seconds
Started Jun 25 05:09:29 PM PDT 24
Finished Jun 25 05:09:33 PM PDT 24
Peak memory 214936 kb
Host smart-6333cb95-4725-42f9-89ec-9f7338f8704e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379074837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.379074837
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1768620943
Short name T970
Test name
Test status
Simulation time 11478261 ps
CPU time 0.66 seconds
Started Jun 25 05:09:33 PM PDT 24
Finished Jun 25 05:09:36 PM PDT 24
Peak memory 203388 kb
Host smart-1b6e0f0f-a9d9-44da-b9ae-c47d69165e82
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768620943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1768620943
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3590135140
Short name T1064
Test name
Test status
Simulation time 1261816666 ps
CPU time 3.92 seconds
Started Jun 25 05:09:29 PM PDT 24
Finished Jun 25 05:09:35 PM PDT 24
Peak memory 215220 kb
Host smart-9c9ed0af-43db-4c54-8e28-ef02fb4bc513
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590135140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3590135140
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2148990044
Short name T86
Test name
Test status
Simulation time 103859863 ps
CPU time 3.63 seconds
Started Jun 25 05:09:28 PM PDT 24
Finished Jun 25 05:09:33 PM PDT 24
Peak memory 216032 kb
Host smart-4dcfef05-4384-4b18-8780-890c60a0f60c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148990044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
148990044
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2804092617
Short name T1063
Test name
Test status
Simulation time 1033378768 ps
CPU time 23.53 seconds
Started Jun 25 05:09:27 PM PDT 24
Finished Jun 25 05:09:51 PM PDT 24
Peak memory 215780 kb
Host smart-3d80e21e-f24f-4ba6-85a4-1d2fb7a08acf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804092617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2804092617
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.642522967
Short name T1023
Test name
Test status
Simulation time 19765573 ps
CPU time 0.72 seconds
Started Jun 25 05:09:57 PM PDT 24
Finished Jun 25 05:10:01 PM PDT 24
Peak memory 203516 kb
Host smart-fb0be936-e4ef-44c5-b167-e57d8034469c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642522967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.642522967
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2592170589
Short name T1032
Test name
Test status
Simulation time 50867472 ps
CPU time 0.77 seconds
Started Jun 25 05:09:57 PM PDT 24
Finished Jun 25 05:10:02 PM PDT 24
Peak memory 203416 kb
Host smart-40f36629-c493-4e45-8d1d-55e40a87edb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592170589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2592170589
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2244438278
Short name T1042
Test name
Test status
Simulation time 19435004 ps
CPU time 0.76 seconds
Started Jun 25 05:09:55 PM PDT 24
Finished Jun 25 05:09:59 PM PDT 24
Peak memory 203412 kb
Host smart-a7727787-d337-41bb-b314-4f2411bc0b18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244438278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2244438278
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3071025371
Short name T962
Test name
Test status
Simulation time 18107089 ps
CPU time 0.76 seconds
Started Jun 25 05:09:56 PM PDT 24
Finished Jun 25 05:10:01 PM PDT 24
Peak memory 203508 kb
Host smart-45fb6489-76e1-49ce-a107-6338856c3910
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071025371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3071025371
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3219019259
Short name T1066
Test name
Test status
Simulation time 36995356 ps
CPU time 0.76 seconds
Started Jun 25 05:09:59 PM PDT 24
Finished Jun 25 05:10:03 PM PDT 24
Peak memory 203500 kb
Host smart-4015f535-745d-47e3-b73c-5ba1efc3436c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219019259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3219019259
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3771767665
Short name T1029
Test name
Test status
Simulation time 28973964 ps
CPU time 0.77 seconds
Started Jun 25 05:09:55 PM PDT 24
Finished Jun 25 05:09:59 PM PDT 24
Peak memory 203816 kb
Host smart-05a51fc7-81e1-4ac9-8ea5-30b5ff56e74a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771767665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3771767665
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.814958028
Short name T1038
Test name
Test status
Simulation time 39539705 ps
CPU time 0.76 seconds
Started Jun 25 05:09:54 PM PDT 24
Finished Jun 25 05:09:56 PM PDT 24
Peak memory 203492 kb
Host smart-6a07c2f9-783d-405c-94d7-827ecb4bd9f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814958028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.814958028
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3964030349
Short name T1051
Test name
Test status
Simulation time 23719765 ps
CPU time 0.78 seconds
Started Jun 25 05:09:58 PM PDT 24
Finished Jun 25 05:10:02 PM PDT 24
Peak memory 203508 kb
Host smart-9c79ec25-ceb1-4142-b868-4dd9fbbffacb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964030349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3964030349
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.205492402
Short name T991
Test name
Test status
Simulation time 22491431 ps
CPU time 0.77 seconds
Started Jun 25 05:09:54 PM PDT 24
Finished Jun 25 05:09:56 PM PDT 24
Peak memory 203836 kb
Host smart-b0e386c0-db4f-408c-b17a-b5e0b57346cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205492402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.205492402
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.839271379
Short name T964
Test name
Test status
Simulation time 14798712 ps
CPU time 0.78 seconds
Started Jun 25 05:09:54 PM PDT 24
Finished Jun 25 05:09:56 PM PDT 24
Peak memory 203504 kb
Host smart-da18c00f-37e3-4b05-9ead-e8a1ae21af8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839271379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.839271379
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.912187448
Short name T1049
Test name
Test status
Simulation time 132318421 ps
CPU time 3.75 seconds
Started Jun 25 05:09:29 PM PDT 24
Finished Jun 25 05:09:35 PM PDT 24
Peak memory 217828 kb
Host smart-738b3b49-d3a3-4cdb-9d12-ed03d549c6c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912187448 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.912187448
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1716871806
Short name T1021
Test name
Test status
Simulation time 306701545 ps
CPU time 2.39 seconds
Started Jun 25 05:09:28 PM PDT 24
Finished Jun 25 05:09:32 PM PDT 24
Peak memory 214912 kb
Host smart-36b04da4-1a57-4483-adee-a18b36aefe0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716871806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
716871806
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.197196303
Short name T981
Test name
Test status
Simulation time 20005752 ps
CPU time 0.8 seconds
Started Jun 25 05:09:31 PM PDT 24
Finished Jun 25 05:09:34 PM PDT 24
Peak memory 203524 kb
Host smart-b42b91f3-1cd2-46ca-9657-3ab45e7c7777
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197196303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.197196303
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.939963546
Short name T1060
Test name
Test status
Simulation time 164849173 ps
CPU time 1.75 seconds
Started Jun 25 05:09:30 PM PDT 24
Finished Jun 25 05:09:34 PM PDT 24
Peak memory 215120 kb
Host smart-defcdf67-aa0e-44fe-81c1-02cd6d236899
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939963546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.939963546
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1988948062
Short name T1058
Test name
Test status
Simulation time 91946740 ps
CPU time 1.41 seconds
Started Jun 25 05:09:28 PM PDT 24
Finished Jun 25 05:09:31 PM PDT 24
Peak memory 215112 kb
Host smart-ea5745f5-a1bd-419d-bd83-780bfe84e64f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988948062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
988948062
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1489585565
Short name T1027
Test name
Test status
Simulation time 796423589 ps
CPU time 21.76 seconds
Started Jun 25 05:09:29 PM PDT 24
Finished Jun 25 05:09:53 PM PDT 24
Peak memory 215348 kb
Host smart-e6f0d495-fada-4a89-b207-06fc83646f15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489585565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1489585565
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1475284767
Short name T125
Test name
Test status
Simulation time 1138843966 ps
CPU time 4.02 seconds
Started Jun 25 05:09:31 PM PDT 24
Finished Jun 25 05:09:38 PM PDT 24
Peak memory 217380 kb
Host smart-6e358d44-145b-497e-b6c3-8d6c09db98dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475284767 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1475284767
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4264111791
Short name T98
Test name
Test status
Simulation time 132988815 ps
CPU time 1.34 seconds
Started Jun 25 05:09:25 PM PDT 24
Finished Jun 25 05:09:28 PM PDT 24
Peak memory 206736 kb
Host smart-88715267-a790-4d3f-88dc-aee036c85f65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264111791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.4
264111791
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.134404887
Short name T976
Test name
Test status
Simulation time 19263654 ps
CPU time 0.74 seconds
Started Jun 25 05:09:30 PM PDT 24
Finished Jun 25 05:09:32 PM PDT 24
Peak memory 203660 kb
Host smart-727ff4cd-022b-49bd-bb95-6211694d25b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134404887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.134404887
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2440838309
Short name T1014
Test name
Test status
Simulation time 174291470 ps
CPU time 3.19 seconds
Started Jun 25 05:09:27 PM PDT 24
Finished Jun 25 05:09:32 PM PDT 24
Peak memory 214908 kb
Host smart-a77ab3ce-de7b-4f19-8b68-53b08c326e1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440838309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2440838309
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2943802165
Short name T152
Test name
Test status
Simulation time 672695330 ps
CPU time 15.67 seconds
Started Jun 25 05:09:29 PM PDT 24
Finished Jun 25 05:09:47 PM PDT 24
Peak memory 214912 kb
Host smart-02f10ada-2a9c-402b-98ad-001ba7fd1b8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943802165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2943802165
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2746337960
Short name T1035
Test name
Test status
Simulation time 110857054 ps
CPU time 3.79 seconds
Started Jun 25 05:09:39 PM PDT 24
Finished Jun 25 05:09:44 PM PDT 24
Peak memory 217144 kb
Host smart-a3580ef6-088a-4f2c-9e88-9649658642ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746337960 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2746337960
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.874500079
Short name T1019
Test name
Test status
Simulation time 212123364 ps
CPU time 1.39 seconds
Started Jun 25 05:09:36 PM PDT 24
Finished Jun 25 05:09:38 PM PDT 24
Peak memory 206652 kb
Host smart-027857db-3a21-4de0-bf5b-435244704951
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874500079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.874500079
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1979575233
Short name T963
Test name
Test status
Simulation time 22823217 ps
CPU time 0.74 seconds
Started Jun 25 05:09:37 PM PDT 24
Finished Jun 25 05:09:40 PM PDT 24
Peak memory 203528 kb
Host smart-4239cce4-0558-4209-95d2-987ce3f4e255
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979575233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
979575233
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.815848053
Short name T985
Test name
Test status
Simulation time 63523230 ps
CPU time 3.92 seconds
Started Jun 25 05:09:39 PM PDT 24
Finished Jun 25 05:09:44 PM PDT 24
Peak memory 214880 kb
Host smart-8a4e2328-9ef4-483c-ba71-3c1b0a1fdaf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815848053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.815848053
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3663305213
Short name T81
Test name
Test status
Simulation time 121515988 ps
CPU time 2.16 seconds
Started Jun 25 05:09:28 PM PDT 24
Finished Jun 25 05:09:31 PM PDT 24
Peak memory 215204 kb
Host smart-19deca3b-6400-4520-bd94-2e5697cbce0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663305213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
663305213
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2892975724
Short name T149
Test name
Test status
Simulation time 390090035 ps
CPU time 8.68 seconds
Started Jun 25 05:09:41 PM PDT 24
Finished Jun 25 05:09:51 PM PDT 24
Peak memory 214760 kb
Host smart-4fa6f25e-9b76-417f-8a39-7a0229baaca8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892975724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2892975724
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.274020027
Short name T126
Test name
Test status
Simulation time 319085102 ps
CPU time 3.84 seconds
Started Jun 25 05:09:37 PM PDT 24
Finished Jun 25 05:09:42 PM PDT 24
Peak memory 216732 kb
Host smart-d4f9c9cd-1da9-4e4f-960f-8e0f282cd9bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274020027 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.274020027
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1385162066
Short name T108
Test name
Test status
Simulation time 253810934 ps
CPU time 2.11 seconds
Started Jun 25 05:09:41 PM PDT 24
Finished Jun 25 05:09:44 PM PDT 24
Peak memory 206684 kb
Host smart-0ac4aa91-6730-4c16-892f-010b71170cdb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385162066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
385162066
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.84316344
Short name T1002
Test name
Test status
Simulation time 14768265 ps
CPU time 0.76 seconds
Started Jun 25 05:09:38 PM PDT 24
Finished Jun 25 05:09:41 PM PDT 24
Peak memory 203460 kb
Host smart-ef14b59e-91c1-405d-b06a-6a317fa8e70f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84316344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.84316344
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1528184531
Short name T1039
Test name
Test status
Simulation time 323056169 ps
CPU time 3 seconds
Started Jun 25 05:09:39 PM PDT 24
Finished Jun 25 05:09:44 PM PDT 24
Peak memory 214820 kb
Host smart-e8d24015-b298-4bc0-9b7c-cb0baf0b77ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528184531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1528184531
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3405235270
Short name T89
Test name
Test status
Simulation time 206359812 ps
CPU time 1.98 seconds
Started Jun 25 05:09:39 PM PDT 24
Finished Jun 25 05:09:43 PM PDT 24
Peak memory 215108 kb
Host smart-3a43b424-5106-4e3a-9d6d-f227c15a91fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405235270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
405235270
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3850442436
Short name T151
Test name
Test status
Simulation time 3974023032 ps
CPU time 22.7 seconds
Started Jun 25 05:09:37 PM PDT 24
Finished Jun 25 05:10:02 PM PDT 24
Peak memory 214932 kb
Host smart-ac155e9b-c487-49ee-891c-180c51b98941
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850442436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3850442436
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3097406356
Short name T1059
Test name
Test status
Simulation time 173001448 ps
CPU time 3.04 seconds
Started Jun 25 05:09:36 PM PDT 24
Finished Jun 25 05:09:40 PM PDT 24
Peak memory 217212 kb
Host smart-f959447a-9ddb-45db-b2e8-c416d8adfbbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097406356 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3097406356
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1325515736
Short name T1077
Test name
Test status
Simulation time 97765779 ps
CPU time 2.43 seconds
Started Jun 25 05:09:37 PM PDT 24
Finished Jun 25 05:09:41 PM PDT 24
Peak memory 214912 kb
Host smart-77c13b19-fa3b-4a57-a158-339e4680ad36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325515736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
325515736
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3175647540
Short name T1076
Test name
Test status
Simulation time 45618631 ps
CPU time 0.77 seconds
Started Jun 25 05:09:38 PM PDT 24
Finished Jun 25 05:09:40 PM PDT 24
Peak memory 203496 kb
Host smart-61cc8126-6d1d-468d-904e-e361b98a666e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175647540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
175647540
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1538129091
Short name T1007
Test name
Test status
Simulation time 45218254 ps
CPU time 2.9 seconds
Started Jun 25 05:09:39 PM PDT 24
Finished Jun 25 05:09:44 PM PDT 24
Peak memory 215400 kb
Host smart-7eef7e9f-a0a0-4476-874d-70b98abae995
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538129091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1538129091
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2168772418
Short name T1036
Test name
Test status
Simulation time 62772768 ps
CPU time 2.14 seconds
Started Jun 25 05:09:38 PM PDT 24
Finished Jun 25 05:09:42 PM PDT 24
Peak memory 214988 kb
Host smart-17cb6189-47fe-4f4e-8f2f-9d2b3c5d9550
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168772418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
168772418
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2856247214
Short name T1041
Test name
Test status
Simulation time 2204554004 ps
CPU time 22.82 seconds
Started Jun 25 05:09:37 PM PDT 24
Finished Jun 25 05:10:02 PM PDT 24
Peak memory 215356 kb
Host smart-702ff91c-6ec1-4eb3-9bcd-af2350fb6b2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856247214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2856247214
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1577639594
Short name T832
Test name
Test status
Simulation time 45207501 ps
CPU time 0.72 seconds
Started Jun 25 06:53:46 PM PDT 24
Finished Jun 25 06:53:48 PM PDT 24
Peak memory 205756 kb
Host smart-6c2f837c-8b04-42e4-875d-6994bfc83467
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577639594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
577639594
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1427509285
Short name T764
Test name
Test status
Simulation time 669676833 ps
CPU time 2.4 seconds
Started Jun 25 06:53:46 PM PDT 24
Finished Jun 25 06:53:49 PM PDT 24
Peak memory 225376 kb
Host smart-82631fcf-7187-43e1-bfa8-2e14f82a9138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427509285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1427509285
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.154697198
Short name T48
Test name
Test status
Simulation time 33622710 ps
CPU time 0.78 seconds
Started Jun 25 06:53:38 PM PDT 24
Finished Jun 25 06:53:39 PM PDT 24
Peak memory 207376 kb
Host smart-02fed7a6-2cb5-4df4-9761-7da818f726e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154697198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.154697198
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1057407059
Short name T625
Test name
Test status
Simulation time 35411146772 ps
CPU time 79.54 seconds
Started Jun 25 06:53:46 PM PDT 24
Finished Jun 25 06:55:06 PM PDT 24
Peak memory 251216 kb
Host smart-0bb5db84-4888-4489-a7ba-ee4b9d8269fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057407059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1057407059
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3947391793
Short name T600
Test name
Test status
Simulation time 5146426753 ps
CPU time 62.78 seconds
Started Jun 25 06:53:45 PM PDT 24
Finished Jun 25 06:54:48 PM PDT 24
Peak memory 264232 kb
Host smart-67f428ac-5344-48cd-a04b-b936c6f44ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947391793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3947391793
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.983970075
Short name T830
Test name
Test status
Simulation time 73888922223 ps
CPU time 143.26 seconds
Started Jun 25 06:53:47 PM PDT 24
Finished Jun 25 06:56:11 PM PDT 24
Peak memory 252476 kb
Host smart-0ccf2aae-3340-42da-83e8-56a71cd9ab13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983970075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
983970075
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1251486120
Short name T529
Test name
Test status
Simulation time 467599363 ps
CPU time 4.1 seconds
Started Jun 25 06:53:46 PM PDT 24
Finished Jun 25 06:53:52 PM PDT 24
Peak memory 233632 kb
Host smart-d972680e-d51d-4910-a1d7-4c212e931705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251486120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1251486120
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2830263056
Short name T581
Test name
Test status
Simulation time 348048818 ps
CPU time 2.2 seconds
Started Jun 25 06:53:39 PM PDT 24
Finished Jun 25 06:53:43 PM PDT 24
Peak memory 223876 kb
Host smart-33c3574b-db85-45f1-aca0-bea63e5a7b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830263056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2830263056
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3703506617
Short name T337
Test name
Test status
Simulation time 975316164 ps
CPU time 10.11 seconds
Started Jun 25 06:53:48 PM PDT 24
Finished Jun 25 06:53:59 PM PDT 24
Peak memory 225420 kb
Host smart-2a7cc992-aff3-4de2-901d-3d6c807f42d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703506617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3703506617
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3511051370
Short name T206
Test name
Test status
Simulation time 135458371 ps
CPU time 2.92 seconds
Started Jun 25 06:53:38 PM PDT 24
Finished Jun 25 06:53:41 PM PDT 24
Peak memory 233608 kb
Host smart-909ac9b2-8db7-4246-b392-994827c5ebe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511051370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3511051370
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.616487635
Short name T790
Test name
Test status
Simulation time 40294455 ps
CPU time 2.2 seconds
Started Jun 25 06:53:38 PM PDT 24
Finished Jun 25 06:53:41 PM PDT 24
Peak memory 225364 kb
Host smart-b87adfa7-01c9-46ce-b57d-5a22d7f8bb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616487635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.616487635
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3955582723
Short name T695
Test name
Test status
Simulation time 256475524 ps
CPU time 3.8 seconds
Started Jun 25 06:53:47 PM PDT 24
Finished Jun 25 06:53:52 PM PDT 24
Peak memory 224028 kb
Host smart-f4e50818-3e84-4f45-9166-d7ddc77b7a5d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3955582723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3955582723
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2335021505
Short name T59
Test name
Test status
Simulation time 412170404 ps
CPU time 1.23 seconds
Started Jun 25 06:53:47 PM PDT 24
Finished Jun 25 06:53:50 PM PDT 24
Peak memory 237584 kb
Host smart-f6fe13a0-ce79-43b4-9139-8931c595d88f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335021505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2335021505
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3522387643
Short name T132
Test name
Test status
Simulation time 71374573 ps
CPU time 1.2 seconds
Started Jun 25 06:53:47 PM PDT 24
Finished Jun 25 06:53:49 PM PDT 24
Peak memory 208676 kb
Host smart-0d59688e-abdd-425c-9cf7-5f3261369e21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522387643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3522387643
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1047802610
Short name T776
Test name
Test status
Simulation time 9158367999 ps
CPU time 19.4 seconds
Started Jun 25 06:53:39 PM PDT 24
Finished Jun 25 06:54:00 PM PDT 24
Peak memory 220956 kb
Host smart-8aff0f31-ca46-4179-82fc-e184fbf6edc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047802610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1047802610
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.4135873491
Short name T637
Test name
Test status
Simulation time 2997188889 ps
CPU time 5.87 seconds
Started Jun 25 06:53:40 PM PDT 24
Finished Jun 25 06:53:47 PM PDT 24
Peak memory 217212 kb
Host smart-e3d07e33-3b89-49f9-b48a-ebb6d4fc3bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135873491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.4135873491
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.4054843618
Short name T32
Test name
Test status
Simulation time 108538520 ps
CPU time 1.27 seconds
Started Jun 25 06:53:37 PM PDT 24
Finished Jun 25 06:53:39 PM PDT 24
Peak memory 208928 kb
Host smart-ee80c43f-8b1d-4984-8f18-251130959107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054843618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.4054843618
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1608552461
Short name T457
Test name
Test status
Simulation time 30756835 ps
CPU time 0.83 seconds
Started Jun 25 06:53:40 PM PDT 24
Finished Jun 25 06:53:42 PM PDT 24
Peak memory 206712 kb
Host smart-648e2d3c-0b71-4263-bca9-654e51cf85e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608552461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1608552461
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.4140851246
Short name T7
Test name
Test status
Simulation time 9026175730 ps
CPU time 17.19 seconds
Started Jun 25 06:53:47 PM PDT 24
Finished Jun 25 06:54:05 PM PDT 24
Peak memory 233672 kb
Host smart-8e5d00ce-c628-47c4-aa74-b443540f0c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140851246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.4140851246
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1720029337
Short name T469
Test name
Test status
Simulation time 14480842 ps
CPU time 0.72 seconds
Started Jun 25 06:53:51 PM PDT 24
Finished Jun 25 06:53:53 PM PDT 24
Peak memory 206244 kb
Host smart-bfc1c87d-fc68-471f-a666-68f7b0a2ad95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720029337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
720029337
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.101822773
Short name T235
Test name
Test status
Simulation time 38398423 ps
CPU time 2.29 seconds
Started Jun 25 06:53:54 PM PDT 24
Finished Jun 25 06:53:57 PM PDT 24
Peak memory 225388 kb
Host smart-9c2c6a6c-142f-46e2-8c74-d6e723db0565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101822773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.101822773
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1475350652
Short name T472
Test name
Test status
Simulation time 16864268 ps
CPU time 0.77 seconds
Started Jun 25 06:53:46 PM PDT 24
Finished Jun 25 06:53:47 PM PDT 24
Peak memory 206396 kb
Host smart-ade051c3-d38c-49ff-b4af-fed129f632cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475350652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1475350652
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2190165273
Short name T802
Test name
Test status
Simulation time 453862222316 ps
CPU time 312.25 seconds
Started Jun 25 06:53:53 PM PDT 24
Finished Jun 25 06:59:06 PM PDT 24
Peak memory 256928 kb
Host smart-be312fe4-b8c5-4df7-a640-abaef86f90b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190165273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2190165273
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1509781069
Short name T388
Test name
Test status
Simulation time 14266621867 ps
CPU time 103.66 seconds
Started Jun 25 06:53:52 PM PDT 24
Finished Jun 25 06:55:36 PM PDT 24
Peak memory 250424 kb
Host smart-3033e0ca-e33c-4a8d-b333-2b106450e095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509781069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1509781069
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1500571401
Short name T258
Test name
Test status
Simulation time 16955985261 ps
CPU time 174.08 seconds
Started Jun 25 06:53:53 PM PDT 24
Finished Jun 25 06:56:48 PM PDT 24
Peak memory 250160 kb
Host smart-f7df8582-a8c0-476c-8c5d-b4e521d219ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500571401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1500571401
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.739454565
Short name T408
Test name
Test status
Simulation time 1619446739 ps
CPU time 3.31 seconds
Started Jun 25 06:53:52 PM PDT 24
Finished Jun 25 06:53:56 PM PDT 24
Peak memory 225424 kb
Host smart-5fd2f1b8-e943-4d40-9314-7323c5ccd60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739454565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.739454565
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.272944858
Short name T770
Test name
Test status
Simulation time 330915495 ps
CPU time 6.94 seconds
Started Jun 25 06:53:54 PM PDT 24
Finished Jun 25 06:54:02 PM PDT 24
Peak memory 233608 kb
Host smart-69395c51-016d-4459-9860-c1467b243fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272944858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.272944858
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.4162308670
Short name T671
Test name
Test status
Simulation time 32158854 ps
CPU time 2.57 seconds
Started Jun 25 06:53:54 PM PDT 24
Finished Jun 25 06:53:58 PM PDT 24
Peak memory 233496 kb
Host smart-920f5565-f383-43e3-bb06-144cd6af331e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162308670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.4162308670
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.4197525120
Short name T907
Test name
Test status
Simulation time 10157653732 ps
CPU time 8.2 seconds
Started Jun 25 06:53:47 PM PDT 24
Finished Jun 25 06:53:56 PM PDT 24
Peak memory 233748 kb
Host smart-64fa220b-cf92-43a8-8682-daf011e2832e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197525120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4197525120
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1532491525
Short name T404
Test name
Test status
Simulation time 1479323818 ps
CPU time 10.2 seconds
Started Jun 25 06:53:53 PM PDT 24
Finished Jun 25 06:54:04 PM PDT 24
Peak memory 220312 kb
Host smart-12cfda40-8125-49d2-8c2a-467fbdb05639
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1532491525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1532491525
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1352225369
Short name T510
Test name
Test status
Simulation time 18718776 ps
CPU time 0.75 seconds
Started Jun 25 06:53:45 PM PDT 24
Finished Jun 25 06:53:47 PM PDT 24
Peak memory 206528 kb
Host smart-6339c725-25a5-4afe-ad64-3ca9ee100d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352225369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1352225369
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1406491445
Short name T905
Test name
Test status
Simulation time 4055536563 ps
CPU time 6.26 seconds
Started Jun 25 06:53:47 PM PDT 24
Finished Jun 25 06:53:54 PM PDT 24
Peak memory 217196 kb
Host smart-6bd5b06f-8ec0-4c62-b22c-ecf71a4edcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406491445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1406491445
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.235166776
Short name T638
Test name
Test status
Simulation time 12994810 ps
CPU time 0.68 seconds
Started Jun 25 06:53:49 PM PDT 24
Finished Jun 25 06:53:50 PM PDT 24
Peak memory 206428 kb
Host smart-5f403d81-7112-4281-9180-8f244a3d07dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235166776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.235166776
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3108929984
Short name T689
Test name
Test status
Simulation time 100170831 ps
CPU time 0.85 seconds
Started Jun 25 06:53:48 PM PDT 24
Finished Jun 25 06:53:50 PM PDT 24
Peak memory 206740 kb
Host smart-c9ef0628-8996-43a8-8991-75a7db7031ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108929984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3108929984
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2125389751
Short name T38
Test name
Test status
Simulation time 448594034 ps
CPU time 2.7 seconds
Started Jun 25 06:53:55 PM PDT 24
Finished Jun 25 06:53:59 PM PDT 24
Peak memory 225288 kb
Host smart-e0a500c4-8ff9-468a-af29-a622ac8f65e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125389751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2125389751
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3487292494
Short name T456
Test name
Test status
Simulation time 400295580 ps
CPU time 7.24 seconds
Started Jun 25 06:55:02 PM PDT 24
Finished Jun 25 06:55:11 PM PDT 24
Peak memory 233616 kb
Host smart-abfc29ae-01f5-4a17-ba68-23b183559da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487292494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3487292494
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.656079041
Short name T882
Test name
Test status
Simulation time 39657021 ps
CPU time 0.84 seconds
Started Jun 25 06:54:53 PM PDT 24
Finished Jun 25 06:54:55 PM PDT 24
Peak memory 207424 kb
Host smart-65e18e3b-ce8e-4d20-b789-1161946300ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656079041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.656079041
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1196826655
Short name T527
Test name
Test status
Simulation time 3353186477 ps
CPU time 38.11 seconds
Started Jun 25 06:55:01 PM PDT 24
Finished Jun 25 06:55:40 PM PDT 24
Peak memory 250164 kb
Host smart-785c6c7f-ca6d-4db7-8281-22d891507c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196826655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1196826655
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3240937942
Short name T186
Test name
Test status
Simulation time 49947280681 ps
CPU time 117.5 seconds
Started Jun 25 06:55:02 PM PDT 24
Finished Jun 25 06:57:01 PM PDT 24
Peak memory 240348 kb
Host smart-d0c4d0a5-abc9-4cd2-a91a-c1f409fbbec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240937942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3240937942
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.413874117
Short name T290
Test name
Test status
Simulation time 16661500127 ps
CPU time 42.37 seconds
Started Jun 25 06:55:03 PM PDT 24
Finished Jun 25 06:55:47 PM PDT 24
Peak memory 233688 kb
Host smart-eb85b63b-c593-48b5-bcc5-189f4e43850a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413874117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.413874117
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3738450132
Short name T410
Test name
Test status
Simulation time 31308544 ps
CPU time 2.07 seconds
Started Jun 25 06:55:01 PM PDT 24
Finished Jun 25 06:55:05 PM PDT 24
Peak memory 224028 kb
Host smart-3debd7b1-aba1-4839-96c8-b4373e1bcb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738450132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3738450132
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.480115551
Short name T909
Test name
Test status
Simulation time 6081399940 ps
CPU time 6.26 seconds
Started Jun 25 06:55:01 PM PDT 24
Finished Jun 25 06:55:08 PM PDT 24
Peak memory 233784 kb
Host smart-34c433fd-3264-45a0-a2ec-624d4f025ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480115551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.480115551
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2908622336
Short name T284
Test name
Test status
Simulation time 1437972433 ps
CPU time 11.37 seconds
Started Jun 25 06:55:01 PM PDT 24
Finished Jun 25 06:55:13 PM PDT 24
Peak memory 241572 kb
Host smart-257b4de9-3287-4874-9bd3-51225f8fda36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908622336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2908622336
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.67155827
Short name T821
Test name
Test status
Simulation time 521402535 ps
CPU time 4.35 seconds
Started Jun 25 06:55:01 PM PDT 24
Finished Jun 25 06:55:06 PM PDT 24
Peak memory 225404 kb
Host smart-4fb3409d-6177-4488-947e-1c6c06d05484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67155827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.67155827
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2270743437
Short name T66
Test name
Test status
Simulation time 1584615215 ps
CPU time 9.12 seconds
Started Jun 25 06:55:01 PM PDT 24
Finished Jun 25 06:55:11 PM PDT 24
Peak memory 220548 kb
Host smart-3ceeb802-c242-4e07-b8d0-fedccc49d1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270743437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2270743437
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1258607088
Short name T845
Test name
Test status
Simulation time 2449914168 ps
CPU time 10.5 seconds
Started Jun 25 06:55:01 PM PDT 24
Finished Jun 25 06:55:13 PM PDT 24
Peak memory 217180 kb
Host smart-60e33010-ac25-465e-a5c4-b8b31f768a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258607088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1258607088
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2637732436
Short name T403
Test name
Test status
Simulation time 83283638 ps
CPU time 1.59 seconds
Started Jun 25 06:55:04 PM PDT 24
Finished Jun 25 06:55:06 PM PDT 24
Peak memory 217152 kb
Host smart-dc635fa1-f6de-4ce9-9b0f-bcadf7ed5d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637732436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2637732436
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3046669279
Short name T819
Test name
Test status
Simulation time 105286495 ps
CPU time 0.82 seconds
Started Jun 25 06:55:02 PM PDT 24
Finished Jun 25 06:55:05 PM PDT 24
Peak memory 206728 kb
Host smart-01af4e65-d6f4-425b-a640-23270922d866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046669279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3046669279
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2511871901
Short name T211
Test name
Test status
Simulation time 1522452797 ps
CPU time 7.37 seconds
Started Jun 25 06:55:01 PM PDT 24
Finished Jun 25 06:55:10 PM PDT 24
Peak memory 237756 kb
Host smart-c350dc9f-be30-47c6-a841-260058ef5443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511871901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2511871901
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.33458967
Short name T51
Test name
Test status
Simulation time 13683060 ps
CPU time 0.71 seconds
Started Jun 25 06:55:07 PM PDT 24
Finished Jun 25 06:55:09 PM PDT 24
Peak memory 205680 kb
Host smart-99ef4d5c-db41-41b8-a88b-fed604d61a9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33458967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.33458967
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.633605565
Short name T345
Test name
Test status
Simulation time 3875373025 ps
CPU time 10.65 seconds
Started Jun 25 06:55:08 PM PDT 24
Finished Jun 25 06:55:19 PM PDT 24
Peak memory 225532 kb
Host smart-8effbd7e-bbd1-4358-b8c8-7498b3bd849f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633605565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.633605565
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.4089586971
Short name T557
Test name
Test status
Simulation time 61393805 ps
CPU time 0.78 seconds
Started Jun 25 06:55:08 PM PDT 24
Finished Jun 25 06:55:10 PM PDT 24
Peak memory 207728 kb
Host smart-02c26bad-df97-4638-b9a7-39cebb9accb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089586971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.4089586971
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1417976591
Short name T666
Test name
Test status
Simulation time 8205462695 ps
CPU time 36.19 seconds
Started Jun 25 06:55:09 PM PDT 24
Finished Jun 25 06:55:47 PM PDT 24
Peak memory 250152 kb
Host smart-be2f3f91-39ab-4730-8ce0-3cc97946df11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417976591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1417976591
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3842592483
Short name T142
Test name
Test status
Simulation time 53940111933 ps
CPU time 73.31 seconds
Started Jun 25 06:55:08 PM PDT 24
Finished Jun 25 06:56:23 PM PDT 24
Peak memory 252624 kb
Host smart-259a1f17-863c-49bf-8593-7615bd22450e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842592483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3842592483
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.820932900
Short name T407
Test name
Test status
Simulation time 220876179661 ps
CPU time 412.39 seconds
Started Jun 25 06:55:09 PM PDT 24
Finished Jun 25 07:02:02 PM PDT 24
Peak memory 256996 kb
Host smart-eaa2582c-979b-48e9-ae07-85260f8d69e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820932900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.820932900
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.4213072936
Short name T427
Test name
Test status
Simulation time 364912834 ps
CPU time 4.61 seconds
Started Jun 25 06:55:10 PM PDT 24
Finished Jun 25 06:55:15 PM PDT 24
Peak memory 237444 kb
Host smart-2a388914-dedb-4b94-943a-cebf52769da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213072936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.4213072936
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3602798139
Short name T859
Test name
Test status
Simulation time 5100062912 ps
CPU time 11.89 seconds
Started Jun 25 06:55:07 PM PDT 24
Finished Jun 25 06:55:20 PM PDT 24
Peak memory 225496 kb
Host smart-90c35642-ae52-4b57-83d0-44470a701ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602798139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3602798139
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.120362677
Short name T261
Test name
Test status
Simulation time 1316277255 ps
CPU time 22.91 seconds
Started Jun 25 06:55:09 PM PDT 24
Finished Jun 25 06:55:33 PM PDT 24
Peak memory 225396 kb
Host smart-da476ebd-6ea5-456b-81d2-11f66b14b2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120362677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.120362677
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3130033942
Short name T890
Test name
Test status
Simulation time 870930397 ps
CPU time 4.21 seconds
Started Jun 25 06:55:10 PM PDT 24
Finished Jun 25 06:55:15 PM PDT 24
Peak memory 225408 kb
Host smart-aad94cf7-cd14-4aa1-bd85-7bbe8eb93a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130033942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3130033942
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2309614487
Short name T818
Test name
Test status
Simulation time 2828184007 ps
CPU time 14.35 seconds
Started Jun 25 06:55:11 PM PDT 24
Finished Jun 25 06:55:26 PM PDT 24
Peak memory 232684 kb
Host smart-d6bdcf85-8097-4029-85bc-3c878d2a39c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309614487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2309614487
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2036650135
Short name T811
Test name
Test status
Simulation time 5152906826 ps
CPU time 14.48 seconds
Started Jun 25 06:55:08 PM PDT 24
Finished Jun 25 06:55:23 PM PDT 24
Peak memory 224172 kb
Host smart-de01957b-f29f-49d4-a5cd-a94b6a92b6a6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2036650135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2036650135
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.940700694
Short name T854
Test name
Test status
Simulation time 39064729 ps
CPU time 0.95 seconds
Started Jun 25 06:55:08 PM PDT 24
Finished Jun 25 06:55:10 PM PDT 24
Peak memory 208280 kb
Host smart-30e52e86-8d57-4d49-b6da-27fc14f3553d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940700694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.940700694
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.495607792
Short name T904
Test name
Test status
Simulation time 18081261647 ps
CPU time 23.03 seconds
Started Jun 25 06:55:11 PM PDT 24
Finished Jun 25 06:55:35 PM PDT 24
Peak memory 216304 kb
Host smart-3e9d2486-ecab-4eb9-ab0b-63b8aaffd36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495607792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.495607792
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1327167371
Short name T577
Test name
Test status
Simulation time 2341719557 ps
CPU time 6.29 seconds
Started Jun 25 06:55:08 PM PDT 24
Finished Jun 25 06:55:16 PM PDT 24
Peak memory 217148 kb
Host smart-5d9f95d9-b9ad-469a-a271-93a32f24a322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327167371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1327167371
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3297894888
Short name T748
Test name
Test status
Simulation time 14315792 ps
CPU time 0.79 seconds
Started Jun 25 06:55:08 PM PDT 24
Finished Jun 25 06:55:10 PM PDT 24
Peak memory 206724 kb
Host smart-7f56ad6b-5826-4c84-ab3a-3bb1a9cdfd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297894888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3297894888
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.4283061444
Short name T630
Test name
Test status
Simulation time 376469008 ps
CPU time 0.8 seconds
Started Jun 25 06:55:09 PM PDT 24
Finished Jun 25 06:55:11 PM PDT 24
Peak memory 206696 kb
Host smart-26db1d99-ebdc-4b81-a2bd-f254d4c327cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283061444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.4283061444
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1741507786
Short name T386
Test name
Test status
Simulation time 517035121 ps
CPU time 7.82 seconds
Started Jun 25 06:55:09 PM PDT 24
Finished Jun 25 06:55:18 PM PDT 24
Peak memory 225388 kb
Host smart-a7a7ab53-fef2-49ec-940a-be3765aa5d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741507786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1741507786
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2921788289
Short name T535
Test name
Test status
Simulation time 46688958 ps
CPU time 0.73 seconds
Started Jun 25 06:55:25 PM PDT 24
Finished Jun 25 06:55:27 PM PDT 24
Peak memory 206284 kb
Host smart-d5dfad14-6cd6-4060-a3f7-32ca6ec1ebc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921788289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2921788289
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.4251959408
Short name T229
Test name
Test status
Simulation time 30787985 ps
CPU time 2.12 seconds
Started Jun 25 06:55:17 PM PDT 24
Finished Jun 25 06:55:21 PM PDT 24
Peak memory 225452 kb
Host smart-1efc4182-0713-41ff-9678-f927830df15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251959408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.4251959408
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2438012003
Short name T565
Test name
Test status
Simulation time 16023864 ps
CPU time 0.79 seconds
Started Jun 25 06:55:18 PM PDT 24
Finished Jun 25 06:55:20 PM PDT 24
Peak memory 207752 kb
Host smart-86939d8f-d0ba-496d-a4d2-0686baf462c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438012003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2438012003
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3645403742
Short name T183
Test name
Test status
Simulation time 3926607325 ps
CPU time 29.71 seconds
Started Jun 25 06:55:17 PM PDT 24
Finished Jun 25 06:55:48 PM PDT 24
Peak memory 235416 kb
Host smart-8104efc0-03d4-4158-a3b6-693a25ea962d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645403742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3645403742
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2618415924
Short name T829
Test name
Test status
Simulation time 1588122206 ps
CPU time 29.42 seconds
Started Jun 25 06:55:15 PM PDT 24
Finished Jun 25 06:55:46 PM PDT 24
Peak memory 251556 kb
Host smart-699e13f1-ee2e-4496-a077-1bb2d745a61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618415924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2618415924
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2247274190
Short name T463
Test name
Test status
Simulation time 46456922 ps
CPU time 2.83 seconds
Started Jun 25 06:55:16 PM PDT 24
Finished Jun 25 06:55:20 PM PDT 24
Peak memory 229612 kb
Host smart-9213766f-53b0-47b0-90d5-7b9e0461d899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247274190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2247274190
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2488936845
Short name T188
Test name
Test status
Simulation time 361278178 ps
CPU time 3.1 seconds
Started Jun 25 06:55:16 PM PDT 24
Finished Jun 25 06:55:20 PM PDT 24
Peak memory 225416 kb
Host smart-e1b6fe8f-c3a9-470e-93ea-009e5a02e791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488936845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2488936845
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2172715257
Short name T627
Test name
Test status
Simulation time 126819440 ps
CPU time 2.59 seconds
Started Jun 25 06:55:16 PM PDT 24
Finished Jun 25 06:55:20 PM PDT 24
Peak memory 233364 kb
Host smart-928a2145-0d49-446f-94e6-28e91d6f7bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172715257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2172715257
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1087238669
Short name T411
Test name
Test status
Simulation time 1228028866 ps
CPU time 3.89 seconds
Started Jun 25 06:55:14 PM PDT 24
Finished Jun 25 06:55:19 PM PDT 24
Peak memory 225364 kb
Host smart-bda5de43-df42-400e-8889-b9c4db955a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087238669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1087238669
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2525573356
Short name T654
Test name
Test status
Simulation time 544526906 ps
CPU time 3.95 seconds
Started Jun 25 06:55:15 PM PDT 24
Finished Jun 25 06:55:21 PM PDT 24
Peak memory 225444 kb
Host smart-7f28ef5c-f28a-4b73-9980-8f3a413397df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525573356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2525573356
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.624475182
Short name T536
Test name
Test status
Simulation time 1177493939 ps
CPU time 6.83 seconds
Started Jun 25 06:55:17 PM PDT 24
Finished Jun 25 06:55:25 PM PDT 24
Peak memory 219788 kb
Host smart-52df6a4e-969d-4a11-b4e2-e0b38c504966
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=624475182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.624475182
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1283754239
Short name T281
Test name
Test status
Simulation time 5839600913 ps
CPU time 58.91 seconds
Started Jun 25 06:55:16 PM PDT 24
Finished Jun 25 06:56:17 PM PDT 24
Peak memory 258544 kb
Host smart-61f8d9e9-3d83-43a9-bf0f-8d7abf7c90b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283754239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1283754239
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1798622798
Short name T943
Test name
Test status
Simulation time 280770161 ps
CPU time 4.95 seconds
Started Jun 25 06:55:15 PM PDT 24
Finished Jun 25 06:55:22 PM PDT 24
Peak memory 217372 kb
Host smart-194c41c5-3731-430e-99f9-55227dd7c2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798622798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1798622798
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1672489277
Short name T639
Test name
Test status
Simulation time 3288170878 ps
CPU time 5.34 seconds
Started Jun 25 06:55:14 PM PDT 24
Finished Jun 25 06:55:20 PM PDT 24
Peak memory 217212 kb
Host smart-3ac905f2-f5c8-4a53-858b-1072e9f65035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672489277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1672489277
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1690138228
Short name T355
Test name
Test status
Simulation time 137916494 ps
CPU time 2.69 seconds
Started Jun 25 06:55:15 PM PDT 24
Finished Jun 25 06:55:19 PM PDT 24
Peak memory 217072 kb
Host smart-bcec9b08-f972-4550-b733-8d6ca4fcf62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690138228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1690138228
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.622171828
Short name T827
Test name
Test status
Simulation time 130674617 ps
CPU time 0.87 seconds
Started Jun 25 06:55:17 PM PDT 24
Finished Jun 25 06:55:19 PM PDT 24
Peak memory 206812 kb
Host smart-a95f138a-13f1-474a-b1a5-488cb28427b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622171828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.622171828
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3603867478
Short name T795
Test name
Test status
Simulation time 2840261401 ps
CPU time 12.26 seconds
Started Jun 25 06:55:15 PM PDT 24
Finished Jun 25 06:55:29 PM PDT 24
Peak memory 225524 kb
Host smart-78a183aa-746b-4201-ba60-1921b16fe48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603867478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3603867478
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2168485596
Short name T373
Test name
Test status
Simulation time 17131328 ps
CPU time 0.78 seconds
Started Jun 25 06:55:32 PM PDT 24
Finished Jun 25 06:55:34 PM PDT 24
Peak memory 206332 kb
Host smart-d6f33954-f36c-469c-ab44-ceec9fba6129
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168485596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2168485596
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2049269486
Short name T352
Test name
Test status
Simulation time 85509287 ps
CPU time 3.24 seconds
Started Jun 25 06:55:23 PM PDT 24
Finished Jun 25 06:55:27 PM PDT 24
Peak memory 233548 kb
Host smart-487a4c2c-77aa-41af-bd11-9eb03f90b4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049269486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2049269486
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.4194464182
Short name T307
Test name
Test status
Simulation time 27587437 ps
CPU time 0.81 seconds
Started Jun 25 06:55:23 PM PDT 24
Finished Jun 25 06:55:25 PM PDT 24
Peak memory 207416 kb
Host smart-c8d17b73-5c32-4033-abb9-d438827f0339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194464182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.4194464182
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2367329336
Short name T241
Test name
Test status
Simulation time 13088360014 ps
CPU time 46.64 seconds
Started Jun 25 06:55:22 PM PDT 24
Finished Jun 25 06:56:09 PM PDT 24
Peak memory 240800 kb
Host smart-2bf075e0-242a-44de-906d-b34683fcbeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367329336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2367329336
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3135881681
Short name T787
Test name
Test status
Simulation time 2079525494 ps
CPU time 44.63 seconds
Started Jun 25 06:55:32 PM PDT 24
Finished Jun 25 06:56:18 PM PDT 24
Peak memory 257512 kb
Host smart-6211c1ee-34b9-431a-9336-f6140f9f3983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135881681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3135881681
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.371584522
Short name T711
Test name
Test status
Simulation time 605334836 ps
CPU time 6.44 seconds
Started Jun 25 06:55:23 PM PDT 24
Finished Jun 25 06:55:31 PM PDT 24
Peak memory 237796 kb
Host smart-09e9afa2-c373-4665-8fd6-26aa19b4bfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371584522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.371584522
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1065555765
Short name T184
Test name
Test status
Simulation time 643366206 ps
CPU time 5.61 seconds
Started Jun 25 06:55:25 PM PDT 24
Finished Jun 25 06:55:32 PM PDT 24
Peak memory 233568 kb
Host smart-5aa3931f-41e0-406f-82fe-fae5012d97c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065555765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1065555765
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3770484458
Short name T242
Test name
Test status
Simulation time 3045727132 ps
CPU time 18.81 seconds
Started Jun 25 06:55:24 PM PDT 24
Finished Jun 25 06:55:43 PM PDT 24
Peak memory 257464 kb
Host smart-a742870e-af58-499a-b3ed-3bfde6c3640b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770484458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3770484458
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.584402036
Short name T810
Test name
Test status
Simulation time 20222788117 ps
CPU time 16.07 seconds
Started Jun 25 06:55:25 PM PDT 24
Finished Jun 25 06:55:42 PM PDT 24
Peak memory 233692 kb
Host smart-da1711b9-7fb9-46ef-b33b-4ad4a7b0308d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584402036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.584402036
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2848246314
Short name T121
Test name
Test status
Simulation time 3632549340 ps
CPU time 11.35 seconds
Started Jun 25 06:55:25 PM PDT 24
Finished Jun 25 06:55:37 PM PDT 24
Peak memory 233776 kb
Host smart-4d01d173-dd94-44b9-8a02-5e7755b5ff36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848246314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2848246314
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.873528384
Short name T458
Test name
Test status
Simulation time 823266677 ps
CPU time 4.53 seconds
Started Jun 25 06:55:22 PM PDT 24
Finished Jun 25 06:55:28 PM PDT 24
Peak memory 223532 kb
Host smart-22f7ac38-e29c-466f-999c-e4207892218d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=873528384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.873528384
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1473966356
Short name T295
Test name
Test status
Simulation time 32013242627 ps
CPU time 42.63 seconds
Started Jun 25 06:55:23 PM PDT 24
Finished Jun 25 06:56:06 PM PDT 24
Peak memory 217472 kb
Host smart-660075fd-b5cc-4d2f-96e4-e19e3b9b76db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473966356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1473966356
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1537408398
Short name T361
Test name
Test status
Simulation time 658048937 ps
CPU time 1.35 seconds
Started Jun 25 06:55:22 PM PDT 24
Finished Jun 25 06:55:24 PM PDT 24
Peak memory 208708 kb
Host smart-aa0529f1-2e80-46de-a699-8c072f710b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537408398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1537408398
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1555521190
Short name T893
Test name
Test status
Simulation time 92972641 ps
CPU time 0.99 seconds
Started Jun 25 06:55:23 PM PDT 24
Finished Jun 25 06:55:24 PM PDT 24
Peak memory 208116 kb
Host smart-2fc276d8-ee73-4a4a-a055-476df86b755c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555521190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1555521190
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2002167292
Short name T722
Test name
Test status
Simulation time 766419232 ps
CPU time 0.99 seconds
Started Jun 25 06:55:24 PM PDT 24
Finished Jun 25 06:55:26 PM PDT 24
Peak memory 206716 kb
Host smart-e98e8024-d21a-41f8-b089-8e8a3cdd437f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002167292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2002167292
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2003695052
Short name T507
Test name
Test status
Simulation time 17395550457 ps
CPU time 15.68 seconds
Started Jun 25 06:55:24 PM PDT 24
Finished Jun 25 06:55:41 PM PDT 24
Peak memory 241480 kb
Host smart-65098244-f915-4052-bb8d-bc3b3ce3c1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003695052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2003695052
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1978548090
Short name T661
Test name
Test status
Simulation time 35140721 ps
CPU time 0.71 seconds
Started Jun 25 06:55:38 PM PDT 24
Finished Jun 25 06:55:40 PM PDT 24
Peak memory 205780 kb
Host smart-a61e6070-a49d-424e-8507-8d192d913497
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978548090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1978548090
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3425331389
Short name T269
Test name
Test status
Simulation time 407044988 ps
CPU time 2.51 seconds
Started Jun 25 06:55:31 PM PDT 24
Finished Jun 25 06:55:35 PM PDT 24
Peak memory 225348 kb
Host smart-c0332292-2770-4b4f-8115-5fab02954a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425331389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3425331389
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1256248193
Short name T692
Test name
Test status
Simulation time 81776590 ps
CPU time 0.78 seconds
Started Jun 25 06:55:30 PM PDT 24
Finished Jun 25 06:55:31 PM PDT 24
Peak memory 207736 kb
Host smart-b5b9c415-404e-404f-8d62-677983371cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256248193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1256248193
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.365706283
Short name T794
Test name
Test status
Simulation time 249837692697 ps
CPU time 304.49 seconds
Started Jun 25 06:55:31 PM PDT 24
Finished Jun 25 07:00:36 PM PDT 24
Peak memory 258360 kb
Host smart-fb7e7e74-2b45-4c43-95cf-d2d19ad19337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365706283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.365706283
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1439516472
Short name T556
Test name
Test status
Simulation time 329561080 ps
CPU time 7.96 seconds
Started Jun 25 06:55:30 PM PDT 24
Finished Jun 25 06:55:39 PM PDT 24
Peak memory 234220 kb
Host smart-b98fc4a7-0540-4753-a4dd-b5b9b3088be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439516472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1439516472
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.4283037008
Short name T782
Test name
Test status
Simulation time 139585717 ps
CPU time 2.48 seconds
Started Jun 25 06:55:30 PM PDT 24
Finished Jun 25 06:55:34 PM PDT 24
Peak memory 233504 kb
Host smart-1d04e472-2189-4c3e-9755-00ac934dbc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283037008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.4283037008
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2773473610
Short name T877
Test name
Test status
Simulation time 766033349 ps
CPU time 9.36 seconds
Started Jun 25 06:55:32 PM PDT 24
Finished Jun 25 06:55:42 PM PDT 24
Peak memory 233608 kb
Host smart-14d6fd77-e989-4f2e-996d-4b163e6790e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773473610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2773473610
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3988208734
Short name T886
Test name
Test status
Simulation time 1505124597 ps
CPU time 5.63 seconds
Started Jun 25 06:55:32 PM PDT 24
Finished Jun 25 06:55:38 PM PDT 24
Peak memory 233608 kb
Host smart-12f27ff9-9b65-45ec-9520-995bc07bb418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988208734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3988208734
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3341392732
Short name T741
Test name
Test status
Simulation time 2364655634 ps
CPU time 8.17 seconds
Started Jun 25 06:55:32 PM PDT 24
Finished Jun 25 06:55:41 PM PDT 24
Peak memory 233768 kb
Host smart-8198d5e5-2d9f-4fae-89bc-641fb62e153b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341392732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3341392732
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2832479173
Short name T362
Test name
Test status
Simulation time 399842664 ps
CPU time 5.28 seconds
Started Jun 25 06:55:32 PM PDT 24
Finished Jun 25 06:55:39 PM PDT 24
Peak memory 223584 kb
Host smart-1ac79143-ee42-4b63-b669-e5b27b81d8d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2832479173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2832479173
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2260656304
Short name T296
Test name
Test status
Simulation time 73462064836 ps
CPU time 49.77 seconds
Started Jun 25 06:55:32 PM PDT 24
Finished Jun 25 06:56:23 PM PDT 24
Peak memory 217304 kb
Host smart-e8d99eec-7aba-4cec-8698-bee447d9f937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260656304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2260656304
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1135527569
Short name T555
Test name
Test status
Simulation time 972365351 ps
CPU time 7.15 seconds
Started Jun 25 06:55:31 PM PDT 24
Finished Jun 25 06:55:39 PM PDT 24
Peak memory 217020 kb
Host smart-cd8a5ea1-4a20-448c-99bc-88fa2d18d2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135527569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1135527569
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.226620761
Short name T392
Test name
Test status
Simulation time 219565934 ps
CPU time 7.91 seconds
Started Jun 25 06:55:32 PM PDT 24
Finished Jun 25 06:55:41 PM PDT 24
Peak memory 217112 kb
Host smart-63f6cff9-82db-4d80-8dff-d285d5933fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226620761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.226620761
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2079697733
Short name T538
Test name
Test status
Simulation time 49645345 ps
CPU time 0.9 seconds
Started Jun 25 06:55:31 PM PDT 24
Finished Jun 25 06:55:33 PM PDT 24
Peak memory 206716 kb
Host smart-34ddc7c3-ac7e-44e6-8db3-d542909abc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079697733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2079697733
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.490249805
Short name T349
Test name
Test status
Simulation time 49849779 ps
CPU time 2.32 seconds
Started Jun 25 06:55:33 PM PDT 24
Finished Jun 25 06:55:36 PM PDT 24
Peak memory 233296 kb
Host smart-bbb3999f-8ee1-4458-b089-4d048c6e95cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490249805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.490249805
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3344972490
Short name T604
Test name
Test status
Simulation time 32221435 ps
CPU time 0.73 seconds
Started Jun 25 06:55:45 PM PDT 24
Finished Jun 25 06:55:47 PM PDT 24
Peak memory 206648 kb
Host smart-8deb4a52-97ab-4c40-8d81-1239c9f43e6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344972490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3344972490
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1723282877
Short name T774
Test name
Test status
Simulation time 223325261 ps
CPU time 3.84 seconds
Started Jun 25 06:55:40 PM PDT 24
Finished Jun 25 06:55:45 PM PDT 24
Peak memory 233592 kb
Host smart-eefd0fbc-5a71-4b50-95b3-be6c9b07bbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723282877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1723282877
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2846420373
Short name T523
Test name
Test status
Simulation time 46141280 ps
CPU time 0.81 seconds
Started Jun 25 06:55:40 PM PDT 24
Finished Jun 25 06:55:42 PM PDT 24
Peak memory 207424 kb
Host smart-ef3163e5-f3c7-4d9b-9911-a1cadc90016d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846420373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2846420373
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2264029244
Short name T176
Test name
Test status
Simulation time 194116660023 ps
CPU time 133.44 seconds
Started Jun 25 06:55:42 PM PDT 24
Finished Jun 25 06:57:56 PM PDT 24
Peak memory 253196 kb
Host smart-2ef1f79c-72c1-4083-b399-a27753e294f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264029244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2264029244
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1457037565
Short name T260
Test name
Test status
Simulation time 197566002417 ps
CPU time 445.66 seconds
Started Jun 25 06:55:40 PM PDT 24
Finished Jun 25 07:03:06 PM PDT 24
Peak memory 257176 kb
Host smart-270fa51e-a467-4d64-be4b-fb89d33c1be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457037565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1457037565
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1426172711
Short name T928
Test name
Test status
Simulation time 34044002978 ps
CPU time 132.42 seconds
Started Jun 25 06:55:39 PM PDT 24
Finished Jun 25 06:57:52 PM PDT 24
Peak memory 241952 kb
Host smart-64984b22-130a-4c52-87d6-b607e271f66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426172711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1426172711
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2171092821
Short name T574
Test name
Test status
Simulation time 12784703222 ps
CPU time 20.14 seconds
Started Jun 25 06:55:39 PM PDT 24
Finished Jun 25 06:56:00 PM PDT 24
Peak memory 237260 kb
Host smart-fb6595ae-ca97-4a5a-9de9-c238934e9362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171092821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2171092821
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2323840358
Short name T194
Test name
Test status
Simulation time 10263895850 ps
CPU time 25.24 seconds
Started Jun 25 06:55:39 PM PDT 24
Finished Jun 25 06:56:05 PM PDT 24
Peak memory 233716 kb
Host smart-a47e8356-4c64-48f0-9e91-be224e394e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323840358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2323840358
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.635667692
Short name T663
Test name
Test status
Simulation time 37309759 ps
CPU time 2.78 seconds
Started Jun 25 06:55:39 PM PDT 24
Finished Jun 25 06:55:43 PM PDT 24
Peak memory 233660 kb
Host smart-5780a78e-13e6-4bdc-ad90-91a719495912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635667692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.635667692
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.579965810
Short name T583
Test name
Test status
Simulation time 80439995 ps
CPU time 2.71 seconds
Started Jun 25 06:55:38 PM PDT 24
Finished Jun 25 06:55:42 PM PDT 24
Peak memory 233600 kb
Host smart-49825d70-b656-4076-ac9e-33b1985ae24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579965810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.579965810
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2213338634
Short name T115
Test name
Test status
Simulation time 1060366903 ps
CPU time 5.01 seconds
Started Jun 25 06:55:39 PM PDT 24
Finished Jun 25 06:55:45 PM PDT 24
Peak memory 221248 kb
Host smart-da4bf10c-b06a-47d1-b752-d630d2f0f514
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2213338634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2213338634
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3175770031
Short name T773
Test name
Test status
Simulation time 96987506004 ps
CPU time 263.12 seconds
Started Jun 25 06:55:44 PM PDT 24
Finished Jun 25 07:00:08 PM PDT 24
Peak memory 266804 kb
Host smart-783839de-c2f4-4753-b126-07a492b0c794
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175770031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3175770031
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.137296218
Short name T387
Test name
Test status
Simulation time 1917133317 ps
CPU time 3.29 seconds
Started Jun 25 06:55:39 PM PDT 24
Finished Jun 25 06:55:43 PM PDT 24
Peak memory 217140 kb
Host smart-9712621e-4d87-4373-ac1b-fbb3ca8d24bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137296218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.137296218
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.779184306
Short name T931
Test name
Test status
Simulation time 54083577 ps
CPU time 0.86 seconds
Started Jun 25 06:55:37 PM PDT 24
Finished Jun 25 06:55:39 PM PDT 24
Peak memory 207300 kb
Host smart-ec6f1ffc-fdd5-410e-8473-a1b78904be1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779184306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.779184306
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3913880853
Short name T700
Test name
Test status
Simulation time 29713881 ps
CPU time 0.8 seconds
Started Jun 25 06:55:42 PM PDT 24
Finished Jun 25 06:55:43 PM PDT 24
Peak memory 206516 kb
Host smart-58659c5c-d341-48c8-aca6-2b9761e98832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913880853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3913880853
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1436453061
Short name T731
Test name
Test status
Simulation time 820392503 ps
CPU time 7.15 seconds
Started Jun 25 06:55:37 PM PDT 24
Finished Jun 25 06:55:44 PM PDT 24
Peak memory 233568 kb
Host smart-4ed335cd-f9ad-48ca-8ffb-78443ae4ce90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436453061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1436453061
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3904888755
Short name T332
Test name
Test status
Simulation time 111115768 ps
CPU time 0.71 seconds
Started Jun 25 06:55:51 PM PDT 24
Finished Jun 25 06:55:52 PM PDT 24
Peak memory 205772 kb
Host smart-b73e252e-3c0e-4ce1-931d-ebc9779af0f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904888755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3904888755
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1919514353
Short name T888
Test name
Test status
Simulation time 1587975969 ps
CPU time 14.08 seconds
Started Jun 25 06:55:49 PM PDT 24
Finished Jun 25 06:56:04 PM PDT 24
Peak memory 225568 kb
Host smart-988268e7-f0eb-4363-8a8b-5f3583372b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919514353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1919514353
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1635097802
Short name T139
Test name
Test status
Simulation time 71789117 ps
CPU time 0.79 seconds
Started Jun 25 06:55:43 PM PDT 24
Finished Jun 25 06:55:44 PM PDT 24
Peak memory 207420 kb
Host smart-6c7b74c4-50d3-410f-a2e3-6d52537b007d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635097802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1635097802
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1042957556
Short name T651
Test name
Test status
Simulation time 13881909949 ps
CPU time 103.66 seconds
Started Jun 25 06:55:49 PM PDT 24
Finished Jun 25 06:57:33 PM PDT 24
Peak memory 240432 kb
Host smart-de299020-4aa8-4f63-8762-dac456fce1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042957556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1042957556
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2636927717
Short name T382
Test name
Test status
Simulation time 18974175820 ps
CPU time 40.05 seconds
Started Jun 25 06:55:44 PM PDT 24
Finished Jun 25 06:56:25 PM PDT 24
Peak memory 249308 kb
Host smart-a832b478-f081-4bc9-aedd-3f8c639be3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636927717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2636927717
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1417184230
Short name T552
Test name
Test status
Simulation time 782914618 ps
CPU time 14.2 seconds
Started Jun 25 06:55:51 PM PDT 24
Finished Jun 25 06:56:06 PM PDT 24
Peak memory 225440 kb
Host smart-172225ba-bf04-4fad-9b71-d6d9eb7b82ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417184230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1417184230
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3112882682
Short name T367
Test name
Test status
Simulation time 914560286 ps
CPU time 10.47 seconds
Started Jun 25 06:55:49 PM PDT 24
Finished Jun 25 06:56:00 PM PDT 24
Peak memory 237776 kb
Host smart-a584bdfa-8477-418d-aaf2-816948fcabf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112882682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3112882682
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.263914908
Short name T317
Test name
Test status
Simulation time 168068598 ps
CPU time 2.27 seconds
Started Jun 25 06:55:44 PM PDT 24
Finished Jun 25 06:55:47 PM PDT 24
Peak memory 219324 kb
Host smart-3aec8c5c-7fa8-4b55-b76b-9d2610652665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263914908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.263914908
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3561135990
Short name T940
Test name
Test status
Simulation time 10524405322 ps
CPU time 84.75 seconds
Started Jun 25 06:55:44 PM PDT 24
Finished Jun 25 06:57:10 PM PDT 24
Peak memory 233636 kb
Host smart-bdb70136-636a-4426-8156-683d0017ffe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561135990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3561135990
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2378352700
Short name T878
Test name
Test status
Simulation time 2949633567 ps
CPU time 6.83 seconds
Started Jun 25 06:55:44 PM PDT 24
Finished Jun 25 06:55:52 PM PDT 24
Peak memory 233772 kb
Host smart-98e7085f-081a-4c27-8439-3b004502443e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378352700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2378352700
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2646487592
Short name T232
Test name
Test status
Simulation time 3183106385 ps
CPU time 6.38 seconds
Started Jun 25 06:55:41 PM PDT 24
Finished Jun 25 06:55:48 PM PDT 24
Peak memory 233756 kb
Host smart-edf8c40e-c422-4334-b05c-b9596f9c5dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646487592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2646487592
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3785886446
Short name T801
Test name
Test status
Simulation time 7287609932 ps
CPU time 13.46 seconds
Started Jun 25 06:55:44 PM PDT 24
Finished Jun 25 06:55:59 PM PDT 24
Peak memory 223708 kb
Host smart-478a9086-307f-47fc-82bc-283bc4e75613
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3785886446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3785886446
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.4710226
Short name T130
Test name
Test status
Simulation time 1728432997 ps
CPU time 6.57 seconds
Started Jun 25 06:55:57 PM PDT 24
Finished Jun 25 06:56:04 PM PDT 24
Peak memory 218560 kb
Host smart-2e13bf00-32dd-4728-94dc-c0e2f05bbb3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4710226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress_
all.4710226
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1247250414
Short name T438
Test name
Test status
Simulation time 312665608 ps
CPU time 2.62 seconds
Started Jun 25 06:55:43 PM PDT 24
Finished Jun 25 06:55:46 PM PDT 24
Peak memory 217060 kb
Host smart-56bd0c7e-7782-48c5-9b66-fbea14a2a785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247250414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1247250414
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.4204467233
Short name T371
Test name
Test status
Simulation time 4854226763 ps
CPU time 8.54 seconds
Started Jun 25 06:55:44 PM PDT 24
Finished Jun 25 06:55:54 PM PDT 24
Peak memory 217152 kb
Host smart-87789afc-8422-4cb3-945a-2fc263f9ae2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204467233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.4204467233
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1814620246
Short name T42
Test name
Test status
Simulation time 1425014772 ps
CPU time 3.65 seconds
Started Jun 25 06:55:44 PM PDT 24
Finished Jun 25 06:55:49 PM PDT 24
Peak memory 217064 kb
Host smart-e4835ac0-51de-4ee8-b91d-532c3bf92f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814620246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1814620246
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.4049493163
Short name T479
Test name
Test status
Simulation time 41459935 ps
CPU time 0.84 seconds
Started Jun 25 06:55:44 PM PDT 24
Finished Jun 25 06:55:46 PM PDT 24
Peak memory 206708 kb
Host smart-3d23c3cd-3ab9-4f97-a23f-0efa92248ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049493163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.4049493163
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3818841934
Short name T716
Test name
Test status
Simulation time 3470139598 ps
CPU time 13.28 seconds
Started Jun 25 06:55:44 PM PDT 24
Finished Jun 25 06:55:58 PM PDT 24
Peak memory 233756 kb
Host smart-687539fc-54af-4920-804f-679fe608b101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818841934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3818841934
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3357253866
Short name T948
Test name
Test status
Simulation time 25047555 ps
CPU time 0.75 seconds
Started Jun 25 06:55:58 PM PDT 24
Finished Jun 25 06:56:00 PM PDT 24
Peak memory 206300 kb
Host smart-27355e24-d919-455c-a0cd-a459f87ec65b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357253866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3357253866
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1944218186
Short name T575
Test name
Test status
Simulation time 77838196 ps
CPU time 2.13 seconds
Started Jun 25 06:55:51 PM PDT 24
Finished Jun 25 06:55:55 PM PDT 24
Peak memory 225344 kb
Host smart-034e1cac-3190-4dc4-a01d-7ca8603c7cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944218186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1944218186
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1408750930
Short name T525
Test name
Test status
Simulation time 28356336 ps
CPU time 0.79 seconds
Started Jun 25 06:55:50 PM PDT 24
Finished Jun 25 06:55:51 PM PDT 24
Peak memory 207364 kb
Host smart-1f586e75-87b8-467e-9521-462657c083f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408750930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1408750930
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3859198889
Short name T396
Test name
Test status
Simulation time 5193761146 ps
CPU time 72.2 seconds
Started Jun 25 06:55:54 PM PDT 24
Finished Jun 25 06:57:07 PM PDT 24
Peak memory 250492 kb
Host smart-91659a3a-c26f-4b51-bb75-70005b8105e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859198889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3859198889
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.4093093463
Short name T216
Test name
Test status
Simulation time 3281668673 ps
CPU time 31.76 seconds
Started Jun 25 06:55:51 PM PDT 24
Finished Jun 25 06:56:24 PM PDT 24
Peak memory 233744 kb
Host smart-4e737609-77f1-47bf-828b-2a8ef2da1811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093093463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.4093093463
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3858587944
Short name T530
Test name
Test status
Simulation time 171334088 ps
CPU time 5.49 seconds
Started Jun 25 06:55:59 PM PDT 24
Finished Jun 25 06:56:06 PM PDT 24
Peak memory 241828 kb
Host smart-81010e6c-b9e0-4829-9111-7318116c9615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858587944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3858587944
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2334045367
Short name T749
Test name
Test status
Simulation time 2254711744 ps
CPU time 26.48 seconds
Started Jun 25 06:55:50 PM PDT 24
Finished Jun 25 06:56:17 PM PDT 24
Peak memory 225492 kb
Host smart-11678512-852a-44fd-954e-bea23a3cbdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334045367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2334045367
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.545033447
Short name T228
Test name
Test status
Simulation time 1073865470 ps
CPU time 13.06 seconds
Started Jun 25 06:55:52 PM PDT 24
Finished Jun 25 06:56:06 PM PDT 24
Peak memory 241600 kb
Host smart-2194e8d7-1c06-4b95-a7e0-2f703ed1ca05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545033447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.545033447
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.71380316
Short name T10
Test name
Test status
Simulation time 1097392262 ps
CPU time 7.15 seconds
Started Jun 25 06:55:56 PM PDT 24
Finished Jun 25 06:56:03 PM PDT 24
Peak memory 233552 kb
Host smart-63a88c92-954a-41d0-bdca-5d5405e74447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71380316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.71380316
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2243472028
Short name T266
Test name
Test status
Simulation time 47865536442 ps
CPU time 31.72 seconds
Started Jun 25 06:55:51 PM PDT 24
Finished Jun 25 06:56:24 PM PDT 24
Peak memory 241816 kb
Host smart-a7a9ce73-425f-41e6-b928-75cbfc19fd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243472028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2243472028
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2577502599
Short name T513
Test name
Test status
Simulation time 455078750 ps
CPU time 3.72 seconds
Started Jun 25 06:55:53 PM PDT 24
Finished Jun 25 06:55:57 PM PDT 24
Peak memory 224060 kb
Host smart-6240b7d7-262c-4ad8-8715-1c10e7cc5dd3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2577502599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2577502599
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3836403338
Short name T354
Test name
Test status
Simulation time 200008092 ps
CPU time 1.14 seconds
Started Jun 25 06:55:52 PM PDT 24
Finished Jun 25 06:55:54 PM PDT 24
Peak memory 208052 kb
Host smart-f431f5e1-08b6-44c4-bf56-7bb5221b64ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836403338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3836403338
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.663303745
Short name T26
Test name
Test status
Simulation time 1692679673 ps
CPU time 9.39 seconds
Started Jun 25 06:55:51 PM PDT 24
Finished Jun 25 06:56:02 PM PDT 24
Peak memory 216976 kb
Host smart-0b4dc662-2da8-4eb2-a0b7-f60d44f87c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663303745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.663303745
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.922380152
Short name T338
Test name
Test status
Simulation time 113999586 ps
CPU time 0.86 seconds
Started Jun 25 06:55:51 PM PDT 24
Finished Jun 25 06:55:53 PM PDT 24
Peak memory 208640 kb
Host smart-946490bc-3620-4242-88d0-c5359648c83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922380152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.922380152
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.211179092
Short name T318
Test name
Test status
Simulation time 42766161 ps
CPU time 0.78 seconds
Started Jun 25 06:55:50 PM PDT 24
Finished Jun 25 06:55:52 PM PDT 24
Peak memory 206708 kb
Host smart-eba77221-5fa1-4dcf-be03-6e9e1d197068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211179092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.211179092
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1046719591
Short name T923
Test name
Test status
Simulation time 121003750 ps
CPU time 2.56 seconds
Started Jun 25 06:55:51 PM PDT 24
Finished Jun 25 06:55:55 PM PDT 24
Peak memory 225136 kb
Host smart-e8c3eb6a-1ea3-473e-a98d-c9caea665559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046719591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1046719591
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.271840129
Short name T737
Test name
Test status
Simulation time 33216343 ps
CPU time 0.73 seconds
Started Jun 25 06:55:58 PM PDT 24
Finished Jun 25 06:55:59 PM PDT 24
Peak memory 206600 kb
Host smart-847c1a93-9817-4837-b149-50adce9e1b7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271840129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.271840129
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.4089839244
Short name T374
Test name
Test status
Simulation time 112621041 ps
CPU time 2.76 seconds
Started Jun 25 06:55:58 PM PDT 24
Finished Jun 25 06:56:02 PM PDT 24
Peak memory 233356 kb
Host smart-69610b57-348d-43ac-90ac-5c17d7a90210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089839244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.4089839244
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3278429908
Short name T138
Test name
Test status
Simulation time 20362870 ps
CPU time 0.8 seconds
Started Jun 25 06:55:57 PM PDT 24
Finished Jun 25 06:55:59 PM PDT 24
Peak memory 207720 kb
Host smart-3d02220d-11f4-49c1-801a-ea14d6a52862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278429908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3278429908
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.485700384
Short name T375
Test name
Test status
Simulation time 5294128693 ps
CPU time 20.33 seconds
Started Jun 25 06:55:59 PM PDT 24
Finished Jun 25 06:56:20 PM PDT 24
Peak memory 236424 kb
Host smart-6c631b58-2197-4704-9acd-f8af49c55389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485700384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.485700384
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3763899319
Short name T758
Test name
Test status
Simulation time 1701686724 ps
CPU time 18.06 seconds
Started Jun 25 06:55:58 PM PDT 24
Finished Jun 25 06:56:17 PM PDT 24
Peak memory 218400 kb
Host smart-83a096f2-5042-41b2-948d-a0c49b263ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763899319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3763899319
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3007270504
Short name T292
Test name
Test status
Simulation time 10753275891 ps
CPU time 16.34 seconds
Started Jun 25 06:56:01 PM PDT 24
Finished Jun 25 06:56:18 PM PDT 24
Peak memory 241920 kb
Host smart-d536b6a0-3b44-4ecd-b0d5-80966d74567a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007270504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3007270504
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3082501014
Short name T733
Test name
Test status
Simulation time 108719377 ps
CPU time 2.16 seconds
Started Jun 25 06:56:02 PM PDT 24
Finished Jun 25 06:56:05 PM PDT 24
Peak memory 223816 kb
Host smart-dce6b705-4767-489b-a11e-0aa19dfaa251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082501014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3082501014
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.405264008
Short name T843
Test name
Test status
Simulation time 41697454358 ps
CPU time 123.57 seconds
Started Jun 25 06:55:58 PM PDT 24
Finished Jun 25 06:58:03 PM PDT 24
Peak memory 239276 kb
Host smart-0d8d24cc-07e0-4144-926b-3f6c0c7be235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405264008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.405264008
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.4045632799
Short name T812
Test name
Test status
Simulation time 501285349 ps
CPU time 5.65 seconds
Started Jun 25 06:55:59 PM PDT 24
Finished Jun 25 06:56:06 PM PDT 24
Peak memory 225420 kb
Host smart-34a7d9aa-b30b-4cf7-b872-571409d1945f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045632799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.4045632799
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.4146983650
Short name T221
Test name
Test status
Simulation time 4195526014 ps
CPU time 14.07 seconds
Started Jun 25 06:56:00 PM PDT 24
Finished Jun 25 06:56:15 PM PDT 24
Peak memory 241528 kb
Host smart-b0925196-79f3-483b-9d17-0736491808a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146983650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.4146983650
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1930774907
Short name T6
Test name
Test status
Simulation time 1207188595 ps
CPU time 5.1 seconds
Started Jun 25 06:56:02 PM PDT 24
Finished Jun 25 06:56:08 PM PDT 24
Peak memory 223968 kb
Host smart-bdcfb0aa-dfb0-4ab0-ba22-f05b67cec9a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1930774907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1930774907
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.640652877
Short name T14
Test name
Test status
Simulation time 22120057837 ps
CPU time 214.69 seconds
Started Jun 25 06:55:59 PM PDT 24
Finished Jun 25 06:59:35 PM PDT 24
Peak memory 258388 kb
Host smart-06672976-69e1-4b63-aaca-341b6cedb1c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640652877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.640652877
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.68636422
Short name T423
Test name
Test status
Simulation time 14322747 ps
CPU time 0.74 seconds
Started Jun 25 06:55:59 PM PDT 24
Finished Jun 25 06:56:00 PM PDT 24
Peak memory 206472 kb
Host smart-3ab57bc9-ccd2-4c1a-84f2-1e5787c1b38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68636422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.68636422
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.494685852
Short name T415
Test name
Test status
Simulation time 704515043 ps
CPU time 5.35 seconds
Started Jun 25 06:56:00 PM PDT 24
Finished Jun 25 06:56:06 PM PDT 24
Peak memory 217208 kb
Host smart-8b3226ca-f1ea-4a46-8e41-94e11761b27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494685852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.494685852
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2685860123
Short name T329
Test name
Test status
Simulation time 111247640 ps
CPU time 0.9 seconds
Started Jun 25 06:55:58 PM PDT 24
Finished Jun 25 06:55:59 PM PDT 24
Peak memory 207756 kb
Host smart-a1b48b62-0fdd-4989-9f0f-a7ead1563f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685860123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2685860123
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1802167486
Short name T488
Test name
Test status
Simulation time 122975342 ps
CPU time 0.88 seconds
Started Jun 25 06:55:59 PM PDT 24
Finished Jun 25 06:56:01 PM PDT 24
Peak memory 206704 kb
Host smart-6e287304-84d0-4a4a-bbf5-fa1be572bc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802167486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1802167486
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2458046996
Short name T263
Test name
Test status
Simulation time 1738195729 ps
CPU time 8.21 seconds
Started Jun 25 06:55:59 PM PDT 24
Finished Jun 25 06:56:08 PM PDT 24
Peak memory 233660 kb
Host smart-ec1b151e-f4ea-405d-9dda-a69d55efc0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458046996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2458046996
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2873756165
Short name T847
Test name
Test status
Simulation time 50483540 ps
CPU time 0.7 seconds
Started Jun 25 06:56:07 PM PDT 24
Finished Jun 25 06:56:09 PM PDT 24
Peak memory 205780 kb
Host smart-7d78c2c5-c618-4e5e-9184-42f146cd3150
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873756165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2873756165
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.4229798612
Short name T268
Test name
Test status
Simulation time 1616859212 ps
CPU time 7.01 seconds
Started Jun 25 06:56:02 PM PDT 24
Finished Jun 25 06:56:10 PM PDT 24
Peak memory 233600 kb
Host smart-b095cde5-aa06-4aed-9708-e91732143e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229798612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.4229798612
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1950383845
Short name T647
Test name
Test status
Simulation time 29433799 ps
CPU time 0.74 seconds
Started Jun 25 06:55:58 PM PDT 24
Finished Jun 25 06:55:59 PM PDT 24
Peak memory 206428 kb
Host smart-94aeea00-b0a2-43cd-9e7b-f41300ab785e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950383845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1950383845
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1843686260
Short name T664
Test name
Test status
Simulation time 7867140376 ps
CPU time 63.08 seconds
Started Jun 25 06:56:03 PM PDT 24
Finished Jun 25 06:57:07 PM PDT 24
Peak memory 239708 kb
Host smart-99b77c86-f3cf-4a7a-8efc-f987eb571fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843686260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1843686260
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.937330823
Short name T933
Test name
Test status
Simulation time 12037018663 ps
CPU time 49.09 seconds
Started Jun 25 06:56:03 PM PDT 24
Finished Jun 25 06:56:53 PM PDT 24
Peak memory 250180 kb
Host smart-d63bd091-2da9-48ef-a628-0d60f2a61e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937330823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.937330823
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.817778582
Short name T398
Test name
Test status
Simulation time 24791496333 ps
CPU time 13.35 seconds
Started Jun 25 06:56:04 PM PDT 24
Finished Jun 25 06:56:18 PM PDT 24
Peak memory 220400 kb
Host smart-09814e37-f2a9-47ae-98f9-39278b182777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817778582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.817778582
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.876595943
Short name T140
Test name
Test status
Simulation time 104435524 ps
CPU time 3.16 seconds
Started Jun 25 06:56:03 PM PDT 24
Finished Jun 25 06:56:07 PM PDT 24
Peak memory 225376 kb
Host smart-b59e4f78-26e3-4ccb-8e99-3b2f28695e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876595943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.876595943
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2218195151
Short name T633
Test name
Test status
Simulation time 4767389747 ps
CPU time 11.25 seconds
Started Jun 25 06:56:07 PM PDT 24
Finished Jun 25 06:56:19 PM PDT 24
Peak memory 225500 kb
Host smart-e7ce90c1-226a-4587-ad2b-37c1727ca105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218195151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2218195151
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1687811554
Short name T515
Test name
Test status
Simulation time 127334355 ps
CPU time 2.75 seconds
Started Jun 25 06:56:05 PM PDT 24
Finished Jun 25 06:56:09 PM PDT 24
Peak memory 225376 kb
Host smart-f4e59ebd-0c33-4cac-be3d-bd8b92dbf394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687811554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1687811554
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2366286721
Short name T254
Test name
Test status
Simulation time 11050960067 ps
CPU time 10.62 seconds
Started Jun 25 06:56:08 PM PDT 24
Finished Jun 25 06:56:20 PM PDT 24
Peak memory 233956 kb
Host smart-ba98a8fb-c37c-44f5-99d1-6f9cedf8fad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366286721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2366286721
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2445223880
Short name T136
Test name
Test status
Simulation time 107254552 ps
CPU time 2.29 seconds
Started Jun 25 06:56:04 PM PDT 24
Finished Jun 25 06:56:07 PM PDT 24
Peak memory 233384 kb
Host smart-94797711-18b2-4cc7-8f79-71486a41a409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445223880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2445223880
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1630693483
Short name T691
Test name
Test status
Simulation time 3844730641 ps
CPU time 6.67 seconds
Started Jun 25 06:56:02 PM PDT 24
Finished Jun 25 06:56:10 PM PDT 24
Peak memory 220908 kb
Host smart-4a66d7e8-b5ab-41f3-94b7-338ea6c97c25
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1630693483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1630693483
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2962571443
Short name T585
Test name
Test status
Simulation time 49605943657 ps
CPU time 507.71 seconds
Started Jun 25 06:56:09 PM PDT 24
Finished Jun 25 07:04:39 PM PDT 24
Peak memory 291188 kb
Host smart-7ca81daa-d46c-460d-8319-139407c73c8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962571443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2962571443
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2093018333
Short name T920
Test name
Test status
Simulation time 37106987 ps
CPU time 0.75 seconds
Started Jun 25 06:56:03 PM PDT 24
Finished Jun 25 06:56:04 PM PDT 24
Peak memory 206512 kb
Host smart-74170459-3366-4eca-9498-5d4d7c15cab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093018333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2093018333
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3449689445
Short name T688
Test name
Test status
Simulation time 843421012 ps
CPU time 3.21 seconds
Started Jun 25 06:56:01 PM PDT 24
Finished Jun 25 06:56:06 PM PDT 24
Peak memory 208688 kb
Host smart-960b7a8f-a18a-4a9a-bb43-155839d562c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449689445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3449689445
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1231322220
Short name T544
Test name
Test status
Simulation time 261765652 ps
CPU time 2.75 seconds
Started Jun 25 06:56:08 PM PDT 24
Finished Jun 25 06:56:12 PM PDT 24
Peak memory 217284 kb
Host smart-f8843051-cb11-4c06-895e-97fc1d267bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231322220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1231322220
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3857325172
Short name T309
Test name
Test status
Simulation time 86517008 ps
CPU time 0.96 seconds
Started Jun 25 06:56:06 PM PDT 24
Finished Jun 25 06:56:08 PM PDT 24
Peak memory 206708 kb
Host smart-6bdaf0ec-1454-4d92-a71a-4cb73d3e8fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857325172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3857325172
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3205358849
Short name T925
Test name
Test status
Simulation time 9172589773 ps
CPU time 30.7 seconds
Started Jun 25 06:56:05 PM PDT 24
Finished Jun 25 06:56:37 PM PDT 24
Peak memory 225536 kb
Host smart-edcbd72d-87ad-4b9c-9a3a-3420654fbdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205358849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3205358849
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.4167790059
Short name T659
Test name
Test status
Simulation time 11795852 ps
CPU time 0.73 seconds
Started Jun 25 06:54:00 PM PDT 24
Finished Jun 25 06:54:03 PM PDT 24
Peak memory 206660 kb
Host smart-c41fbbb1-7c26-46e4-b0f7-e9e0f15f155b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167790059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.4
167790059
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.4225437229
Short name T541
Test name
Test status
Simulation time 679630183 ps
CPU time 5.56 seconds
Started Jun 25 06:53:59 PM PDT 24
Finished Jun 25 06:54:06 PM PDT 24
Peak memory 233624 kb
Host smart-9d512a0c-02ea-4b8b-8076-ca6be15563af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225437229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.4225437229
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.542499587
Short name T428
Test name
Test status
Simulation time 17370536 ps
CPU time 0.78 seconds
Started Jun 25 06:53:59 PM PDT 24
Finished Jun 25 06:54:02 PM PDT 24
Peak memory 206392 kb
Host smart-0f9cfc84-66e6-4d41-9a48-ce90a315d437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542499587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.542499587
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2092787836
Short name T369
Test name
Test status
Simulation time 36717810 ps
CPU time 0.78 seconds
Started Jun 25 06:54:00 PM PDT 24
Finished Jun 25 06:54:03 PM PDT 24
Peak memory 216788 kb
Host smart-80df3469-60ed-4770-8787-076844db0219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092787836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2092787836
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.437510498
Short name T246
Test name
Test status
Simulation time 39270691605 ps
CPU time 310.08 seconds
Started Jun 25 06:54:00 PM PDT 24
Finished Jun 25 06:59:13 PM PDT 24
Peak memory 258236 kb
Host smart-170c99ab-933a-4870-8df4-f9e20a8bc1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437510498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.437510498
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.659628376
Short name T649
Test name
Test status
Simulation time 34540703596 ps
CPU time 165.46 seconds
Started Jun 25 06:53:58 PM PDT 24
Finished Jun 25 06:56:45 PM PDT 24
Peak memory 250120 kb
Host smart-625e6095-dfde-4281-b649-c79d3df3b08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659628376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
659628376
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3163259458
Short name T289
Test name
Test status
Simulation time 2031421067 ps
CPU time 14.53 seconds
Started Jun 25 06:53:59 PM PDT 24
Finished Jun 25 06:54:15 PM PDT 24
Peak memory 241788 kb
Host smart-d921b6a0-c1ae-4afb-a511-f13424e627f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163259458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3163259458
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.949167587
Short name T913
Test name
Test status
Simulation time 30525978 ps
CPU time 2.89 seconds
Started Jun 25 06:53:58 PM PDT 24
Finished Jun 25 06:54:03 PM PDT 24
Peak memory 233364 kb
Host smart-cbf4e266-ba3a-4d78-81c0-61305fabe5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949167587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.949167587
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.259636563
Short name T814
Test name
Test status
Simulation time 462058207 ps
CPU time 2.56 seconds
Started Jun 25 06:53:59 PM PDT 24
Finished Jun 25 06:54:03 PM PDT 24
Peak memory 225356 kb
Host smart-c9d0acde-c647-4067-92ae-b2ed398ed786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259636563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.259636563
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3566769765
Short name T806
Test name
Test status
Simulation time 119440007 ps
CPU time 2.6 seconds
Started Jun 25 06:54:00 PM PDT 24
Finished Jun 25 06:54:05 PM PDT 24
Peak memory 225384 kb
Host smart-07dc41e8-c996-4c8c-b4a4-c045306e50bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566769765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3566769765
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.113770088
Short name T851
Test name
Test status
Simulation time 912233837 ps
CPU time 3.08 seconds
Started Jun 25 06:53:59 PM PDT 24
Finished Jun 25 06:54:04 PM PDT 24
Peak memory 225400 kb
Host smart-10a5546e-d672-4ed2-91a5-39ef0d5a1aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113770088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.113770088
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3303552600
Short name T120
Test name
Test status
Simulation time 5827579462 ps
CPU time 11.23 seconds
Started Jun 25 06:53:59 PM PDT 24
Finished Jun 25 06:54:12 PM PDT 24
Peak memory 221536 kb
Host smart-a6291557-d4b9-4793-9bb9-03550f199975
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3303552600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3303552600
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2101202383
Short name T13
Test name
Test status
Simulation time 153016496 ps
CPU time 1.01 seconds
Started Jun 25 06:54:00 PM PDT 24
Finished Jun 25 06:54:03 PM PDT 24
Peak memory 237112 kb
Host smart-6bbe3811-eb6a-4bae-9562-9a48fb245662
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101202383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2101202383
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.520432767
Short name T276
Test name
Test status
Simulation time 183541906466 ps
CPU time 567.38 seconds
Started Jun 25 06:54:00 PM PDT 24
Finished Jun 25 07:03:30 PM PDT 24
Peak memory 290016 kb
Host smart-7f423b56-b39a-4360-a34c-ad45cd712975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520432767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.520432767
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3814926747
Short name T736
Test name
Test status
Simulation time 3401185542 ps
CPU time 6.16 seconds
Started Jun 25 06:53:59 PM PDT 24
Finished Jun 25 06:54:07 PM PDT 24
Peak memory 220244 kb
Host smart-556d5412-1e82-413b-8c53-2d03a736b7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814926747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3814926747
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.324901128
Short name T448
Test name
Test status
Simulation time 6178663377 ps
CPU time 4.31 seconds
Started Jun 25 06:53:59 PM PDT 24
Finished Jun 25 06:54:06 PM PDT 24
Peak memory 217220 kb
Host smart-062df001-792f-415e-9d6c-4a893f41a4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324901128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.324901128
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3986692587
Short name T679
Test name
Test status
Simulation time 989795455 ps
CPU time 2.84 seconds
Started Jun 25 06:54:00 PM PDT 24
Finished Jun 25 06:54:06 PM PDT 24
Peak memory 217240 kb
Host smart-e2caa424-3500-4ced-86d1-cab7af4eacbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986692587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3986692587
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1672913939
Short name T389
Test name
Test status
Simulation time 20289451 ps
CPU time 0.78 seconds
Started Jun 25 06:53:58 PM PDT 24
Finished Jun 25 06:54:01 PM PDT 24
Peak memory 206728 kb
Host smart-5c0f5738-2b5b-4f2f-aacf-9e6478e8e376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672913939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1672913939
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3390832902
Short name T222
Test name
Test status
Simulation time 29109152510 ps
CPU time 17.38 seconds
Started Jun 25 06:53:59 PM PDT 24
Finished Jun 25 06:54:19 PM PDT 24
Peak memory 239120 kb
Host smart-52989282-c23b-4863-8619-bfbb68054496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390832902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3390832902
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3911870456
Short name T673
Test name
Test status
Simulation time 37064496 ps
CPU time 0.74 seconds
Started Jun 25 06:56:15 PM PDT 24
Finished Jun 25 06:56:16 PM PDT 24
Peak memory 206352 kb
Host smart-0a8f13b3-13ba-4142-8d01-714ee8386da7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911870456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3911870456
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1907712086
Short name T586
Test name
Test status
Simulation time 293721959 ps
CPU time 2.67 seconds
Started Jun 25 06:56:09 PM PDT 24
Finished Jun 25 06:56:13 PM PDT 24
Peak memory 233612 kb
Host smart-c7bc20b3-bf93-4917-b425-edfa5f0b4cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907712086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1907712086
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.4115941161
Short name T900
Test name
Test status
Simulation time 116788392 ps
CPU time 0.74 seconds
Started Jun 25 06:56:10 PM PDT 24
Finished Jun 25 06:56:12 PM PDT 24
Peak memory 207412 kb
Host smart-d7d8450f-8a56-48b5-91a3-e2c38b3a634a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115941161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.4115941161
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3485017672
Short name T430
Test name
Test status
Simulation time 31703665997 ps
CPU time 128.96 seconds
Started Jun 25 06:56:13 PM PDT 24
Finished Jun 25 06:58:23 PM PDT 24
Peak memory 250128 kb
Host smart-b33e1ae2-2613-4c20-922b-339b0f3b5734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485017672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3485017672
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2747051446
Short name T205
Test name
Test status
Simulation time 194479948543 ps
CPU time 733.79 seconds
Started Jun 25 06:56:17 PM PDT 24
Finished Jun 25 07:08:31 PM PDT 24
Peak memory 268788 kb
Host smart-7ab3aba1-7fdb-4094-8a42-4630776c234a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747051446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2747051446
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2838096517
Short name T166
Test name
Test status
Simulation time 19530967506 ps
CPU time 100.26 seconds
Started Jun 25 06:56:15 PM PDT 24
Finished Jun 25 06:57:56 PM PDT 24
Peak memory 250208 kb
Host smart-465b60b5-4168-499d-8aef-a9be48d58181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838096517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2838096517
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.4208028696
Short name T864
Test name
Test status
Simulation time 939204085 ps
CPU time 9.62 seconds
Started Jun 25 06:56:11 PM PDT 24
Finished Jun 25 06:56:22 PM PDT 24
Peak memory 235112 kb
Host smart-3229f2cc-431d-4dec-ba55-a7b51b42d450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208028696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.4208028696
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3549004489
Short name T934
Test name
Test status
Simulation time 421933930 ps
CPU time 7.16 seconds
Started Jun 25 06:56:09 PM PDT 24
Finished Jun 25 06:56:18 PM PDT 24
Peak memory 225460 kb
Host smart-b79b18ec-606a-4f46-a2fc-27c4408e8683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549004489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3549004489
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3464487015
Short name T238
Test name
Test status
Simulation time 134893305 ps
CPU time 6.33 seconds
Started Jun 25 06:56:12 PM PDT 24
Finished Jun 25 06:56:19 PM PDT 24
Peak memory 233652 kb
Host smart-06e28fd1-172e-4544-8450-d92658a22b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464487015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3464487015
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2170173567
Short name T796
Test name
Test status
Simulation time 157234248 ps
CPU time 3.52 seconds
Started Jun 25 06:56:10 PM PDT 24
Finished Jun 25 06:56:15 PM PDT 24
Peak memory 233608 kb
Host smart-1512ea28-a8d6-4dcb-8d78-f4ca4646d981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170173567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2170173567
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1102334874
Short name T521
Test name
Test status
Simulation time 1383202678 ps
CPU time 7.97 seconds
Started Jun 25 06:56:09 PM PDT 24
Finished Jun 25 06:56:18 PM PDT 24
Peak memory 241160 kb
Host smart-6d750d7a-e278-407d-98c8-1ecb699a7891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102334874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1102334874
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2905496148
Short name T703
Test name
Test status
Simulation time 516778219 ps
CPU time 3.52 seconds
Started Jun 25 06:56:13 PM PDT 24
Finished Jun 25 06:56:17 PM PDT 24
Peak memory 220276 kb
Host smart-e3c27d25-5ebe-4a68-98d3-e55609fe0dbf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2905496148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2905496148
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2941700850
Short name T282
Test name
Test status
Simulation time 25045287065 ps
CPU time 197.13 seconds
Started Jun 25 06:56:16 PM PDT 24
Finished Jun 25 06:59:34 PM PDT 24
Peak memory 258156 kb
Host smart-add2227b-7096-4bf1-884f-7fbe921ecbe1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941700850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2941700850
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1078675816
Short name T334
Test name
Test status
Simulation time 4239624134 ps
CPU time 17.08 seconds
Started Jun 25 06:56:09 PM PDT 24
Finished Jun 25 06:56:27 PM PDT 24
Peak memory 217436 kb
Host smart-677dfa2a-9d99-4979-84d6-4c53b6da9516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078675816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1078675816
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2478746275
Short name T573
Test name
Test status
Simulation time 461037414 ps
CPU time 2.45 seconds
Started Jun 25 06:56:08 PM PDT 24
Finished Jun 25 06:56:12 PM PDT 24
Peak memory 217072 kb
Host smart-dbf50ddc-7aa4-458f-aa00-4941ed7e2565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478746275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2478746275
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.383438701
Short name T297
Test name
Test status
Simulation time 102126072 ps
CPU time 1.35 seconds
Started Jun 25 06:56:09 PM PDT 24
Finished Jun 25 06:56:12 PM PDT 24
Peak memory 208688 kb
Host smart-65d8aab5-c2d1-4d58-9f7a-709b451d2c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383438701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.383438701
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2207294527
Short name T526
Test name
Test status
Simulation time 180175856 ps
CPU time 0.91 seconds
Started Jun 25 06:56:10 PM PDT 24
Finished Jun 25 06:56:13 PM PDT 24
Peak memory 206716 kb
Host smart-67fc6baa-d2d6-4a1f-8a77-705f92b5e0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207294527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2207294527
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3649213432
Short name T918
Test name
Test status
Simulation time 611812332 ps
CPU time 3.8 seconds
Started Jun 25 06:56:09 PM PDT 24
Finished Jun 25 06:56:14 PM PDT 24
Peak memory 233608 kb
Host smart-ea8abc4d-1380-4cba-9816-81e6d4254178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649213432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3649213432
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2161237370
Short name T547
Test name
Test status
Simulation time 22713640 ps
CPU time 0.71 seconds
Started Jun 25 06:56:23 PM PDT 24
Finished Jun 25 06:56:25 PM PDT 24
Peak memory 206308 kb
Host smart-bef4794f-c24b-4266-b929-ee6a41609243
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161237370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2161237370
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1259262048
Short name T73
Test name
Test status
Simulation time 790703942 ps
CPU time 4 seconds
Started Jun 25 06:56:23 PM PDT 24
Finished Jun 25 06:56:28 PM PDT 24
Peak memory 225388 kb
Host smart-47535e5f-1c28-45ed-a0ca-982e1838eb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259262048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1259262048
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.4068480999
Short name T343
Test name
Test status
Simulation time 18111427 ps
CPU time 0.73 seconds
Started Jun 25 06:56:14 PM PDT 24
Finished Jun 25 06:56:16 PM PDT 24
Peak memory 206412 kb
Host smart-b41de35c-73ee-42b0-a0ce-e02f2b4f9640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068480999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.4068480999
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.4116879225
Short name T146
Test name
Test status
Simulation time 3083187277 ps
CPU time 54.97 seconds
Started Jun 25 06:56:24 PM PDT 24
Finished Jun 25 06:57:21 PM PDT 24
Peak memory 252492 kb
Host smart-be882689-b1aa-42e1-8452-2d9bd3c17195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116879225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.4116879225
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2884930730
Short name T726
Test name
Test status
Simulation time 141389351137 ps
CPU time 324.33 seconds
Started Jun 25 06:56:21 PM PDT 24
Finished Jun 25 07:01:46 PM PDT 24
Peak memory 252668 kb
Host smart-a5b6aedd-4182-473c-b83c-131190a54607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884930730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2884930730
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2730144649
Short name T46
Test name
Test status
Simulation time 46263801012 ps
CPU time 147.71 seconds
Started Jun 25 06:56:24 PM PDT 24
Finished Jun 25 06:58:53 PM PDT 24
Peak memory 250204 kb
Host smart-7fb02056-5f23-4cc7-988f-6d39954d75c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730144649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2730144649
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1257208657
Short name T701
Test name
Test status
Simulation time 107489001 ps
CPU time 2.84 seconds
Started Jun 25 06:56:22 PM PDT 24
Finished Jun 25 06:56:25 PM PDT 24
Peak memory 225404 kb
Host smart-46b8f5ec-a6fa-4044-9795-beb9fa8fef5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257208657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1257208657
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3618165311
Short name T889
Test name
Test status
Simulation time 1236313251 ps
CPU time 13.44 seconds
Started Jun 25 06:56:22 PM PDT 24
Finished Jun 25 06:56:37 PM PDT 24
Peak memory 225464 kb
Host smart-1ec90f91-fe8c-473f-9a4b-72e6fcb2bdd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618165311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3618165311
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1146084963
Short name T932
Test name
Test status
Simulation time 242906292 ps
CPU time 6.05 seconds
Started Jun 25 06:56:22 PM PDT 24
Finished Jun 25 06:56:29 PM PDT 24
Peak memory 233636 kb
Host smart-9293aa80-f4f7-486d-957a-242da5b1b502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146084963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1146084963
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1108884710
Short name T45
Test name
Test status
Simulation time 1422915016 ps
CPU time 3.64 seconds
Started Jun 25 06:56:14 PM PDT 24
Finished Jun 25 06:56:18 PM PDT 24
Peak memory 233612 kb
Host smart-d673de76-f429-4cc6-951e-399f5d348f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108884710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1108884710
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.199474196
Short name T566
Test name
Test status
Simulation time 23527417202 ps
CPU time 17.54 seconds
Started Jun 25 06:56:16 PM PDT 24
Finished Jun 25 06:56:34 PM PDT 24
Peak memory 225500 kb
Host smart-10c28b1e-140f-4be2-afba-e2bfd7066dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199474196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.199474196
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.369452331
Short name T119
Test name
Test status
Simulation time 319228465 ps
CPU time 3.7 seconds
Started Jun 25 06:56:24 PM PDT 24
Finished Jun 25 06:56:29 PM PDT 24
Peak memory 220864 kb
Host smart-70d9ea9b-1919-4063-a511-9fea83bed606
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=369452331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.369452331
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2175682941
Short name T955
Test name
Test status
Simulation time 87963367076 ps
CPU time 216.33 seconds
Started Jun 25 06:56:22 PM PDT 24
Finished Jun 25 06:59:59 PM PDT 24
Peak memory 246628 kb
Host smart-dcb202bf-f88f-4897-a973-7437a62b7f63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175682941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2175682941
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3572100122
Short name T564
Test name
Test status
Simulation time 833306960 ps
CPU time 13.7 seconds
Started Jun 25 06:56:15 PM PDT 24
Finished Jun 25 06:56:29 PM PDT 24
Peak memory 217544 kb
Host smart-0feeb86c-1520-4f10-a28a-bf13d85d31b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572100122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3572100122
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2447248373
Short name T452
Test name
Test status
Simulation time 2381603674 ps
CPU time 4.37 seconds
Started Jun 25 06:56:15 PM PDT 24
Finished Jun 25 06:56:20 PM PDT 24
Peak memory 217216 kb
Host smart-34e94be3-cc6e-4514-8652-6543ac5a1462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447248373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2447248373
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1752042010
Short name T350
Test name
Test status
Simulation time 12905770 ps
CPU time 0.72 seconds
Started Jun 25 06:56:14 PM PDT 24
Finished Jun 25 06:56:15 PM PDT 24
Peak memory 206316 kb
Host smart-fdc95507-047f-46c4-9639-cb6644a67139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752042010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1752042010
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2298129530
Short name T676
Test name
Test status
Simulation time 160685930 ps
CPU time 0.76 seconds
Started Jun 25 06:56:17 PM PDT 24
Finished Jun 25 06:56:18 PM PDT 24
Peak memory 206612 kb
Host smart-96000698-04fa-4a40-a018-d5dc6c5df1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298129530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2298129530
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.421477602
Short name T768
Test name
Test status
Simulation time 12674970755 ps
CPU time 9.65 seconds
Started Jun 25 06:56:22 PM PDT 24
Finished Jun 25 06:56:32 PM PDT 24
Peak memory 237408 kb
Host smart-94aae618-3d9e-4bae-bcb8-d4b82555f64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421477602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.421477602
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3001848889
Short name T738
Test name
Test status
Simulation time 42813266 ps
CPU time 0.71 seconds
Started Jun 25 06:56:29 PM PDT 24
Finished Jun 25 06:56:31 PM PDT 24
Peak memory 205748 kb
Host smart-a69fb575-2b10-4af0-bde6-d4cfed629f64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001848889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3001848889
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.684003195
Short name T744
Test name
Test status
Simulation time 406907851 ps
CPU time 5.28 seconds
Started Jun 25 06:56:22 PM PDT 24
Finished Jun 25 06:56:28 PM PDT 24
Peak memory 233568 kb
Host smart-5d9867c9-8509-4856-ad70-304225135517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684003195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.684003195
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.58371637
Short name T460
Test name
Test status
Simulation time 22271394 ps
CPU time 0.8 seconds
Started Jun 25 06:56:22 PM PDT 24
Finished Jun 25 06:56:24 PM PDT 24
Peak memory 207716 kb
Host smart-b409bf6b-4635-4274-a2b3-5b1591ccba40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58371637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.58371637
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1279218250
Short name T501
Test name
Test status
Simulation time 39490986221 ps
CPU time 101.1 seconds
Started Jun 25 06:56:24 PM PDT 24
Finished Jun 25 06:58:07 PM PDT 24
Peak memory 250076 kb
Host smart-46c22cf8-4fad-4abb-b2fb-09031c8d9fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279218250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1279218250
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1380391041
Short name T31
Test name
Test status
Simulation time 56264064647 ps
CPU time 38.28 seconds
Started Jun 25 06:56:25 PM PDT 24
Finished Jun 25 06:57:05 PM PDT 24
Peak memory 225508 kb
Host smart-a7fd0255-fae7-4568-b9a4-63854c2a8889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380391041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1380391041
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2555012795
Short name T809
Test name
Test status
Simulation time 496604691 ps
CPU time 7.5 seconds
Started Jun 25 06:56:24 PM PDT 24
Finished Jun 25 06:56:33 PM PDT 24
Peak memory 225324 kb
Host smart-098e32ac-64d0-444d-8d97-c823c11ce461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555012795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2555012795
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.73420696
Short name T420
Test name
Test status
Simulation time 16273646235 ps
CPU time 173.13 seconds
Started Jun 25 06:56:25 PM PDT 24
Finished Jun 25 06:59:19 PM PDT 24
Peak memory 233668 kb
Host smart-dbf4d9ca-dd76-4c3c-83a7-5994c8719bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73420696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.73420696
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.4251621955
Short name T937
Test name
Test status
Simulation time 3842305936 ps
CPU time 15.73 seconds
Started Jun 25 06:56:23 PM PDT 24
Finished Jun 25 06:56:41 PM PDT 24
Peak memory 241744 kb
Host smart-e4918656-166e-4d62-9dee-6f41c1eb751a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251621955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.4251621955
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2845111689
Short name T401
Test name
Test status
Simulation time 1475544836 ps
CPU time 10.75 seconds
Started Jun 25 06:56:23 PM PDT 24
Finished Jun 25 06:56:34 PM PDT 24
Peak memory 233612 kb
Host smart-e45a0ebe-a592-4e42-b335-0b73ab517304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845111689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2845111689
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2785856203
Short name T881
Test name
Test status
Simulation time 249133857 ps
CPU time 3.36 seconds
Started Jun 25 06:56:24 PM PDT 24
Finished Jun 25 06:56:29 PM PDT 24
Peak memory 223500 kb
Host smart-7c5cc9ef-17b5-4358-b093-e315f0cbb7a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2785856203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2785856203
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4131354136
Short name T301
Test name
Test status
Simulation time 5422249256 ps
CPU time 36.9 seconds
Started Jun 25 06:56:23 PM PDT 24
Finished Jun 25 06:57:01 PM PDT 24
Peak memory 217168 kb
Host smart-0ecab3de-ba0e-41a0-b736-f504354dccca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131354136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4131354136
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2153892628
Short name T822
Test name
Test status
Simulation time 3858024457 ps
CPU time 10.91 seconds
Started Jun 25 06:56:22 PM PDT 24
Finished Jun 25 06:56:33 PM PDT 24
Peak memory 217224 kb
Host smart-fad2d570-e723-417a-8b66-305a971c0a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153892628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2153892628
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3531120089
Short name T25
Test name
Test status
Simulation time 13846185 ps
CPU time 0.69 seconds
Started Jun 25 06:56:23 PM PDT 24
Finished Jun 25 06:56:25 PM PDT 24
Peak memory 206476 kb
Host smart-0a61cdba-ba46-49fa-bb60-3f22a599e60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531120089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3531120089
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1207095428
Short name T724
Test name
Test status
Simulation time 105247998 ps
CPU time 0.82 seconds
Started Jun 25 06:56:23 PM PDT 24
Finished Jun 25 06:56:24 PM PDT 24
Peak memory 206708 kb
Host smart-13654d1d-7290-44cf-879b-e11d60a21549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207095428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1207095428
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1074120862
Short name T683
Test name
Test status
Simulation time 1564480222 ps
CPU time 3.21 seconds
Started Jun 25 06:56:24 PM PDT 24
Finished Jun 25 06:56:29 PM PDT 24
Peak memory 225388 kb
Host smart-f17e7466-2a88-4309-8792-7147223c04f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074120862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1074120862
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1298927776
Short name T580
Test name
Test status
Simulation time 21043458 ps
CPU time 0.73 seconds
Started Jun 25 06:56:36 PM PDT 24
Finished Jun 25 06:56:38 PM PDT 24
Peak memory 206656 kb
Host smart-80635257-15a8-4cfd-a73b-faff9e0bdd26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298927776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1298927776
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2364173833
Short name T756
Test name
Test status
Simulation time 1372756505 ps
CPU time 2.61 seconds
Started Jun 25 06:56:29 PM PDT 24
Finished Jun 25 06:56:33 PM PDT 24
Peak memory 225380 kb
Host smart-212c31ca-3e7f-449b-b8cc-661625e11c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364173833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2364173833
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3421928228
Short name T316
Test name
Test status
Simulation time 55256649 ps
CPU time 0.77 seconds
Started Jun 25 06:56:33 PM PDT 24
Finished Jun 25 06:56:35 PM PDT 24
Peak memory 206392 kb
Host smart-e4d0ee02-59b7-40f5-9a9a-a1b441337766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421928228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3421928228
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2897687591
Short name T743
Test name
Test status
Simulation time 2017134425 ps
CPU time 19.5 seconds
Started Jun 25 06:56:37 PM PDT 24
Finished Jun 25 06:56:58 PM PDT 24
Peak memory 225412 kb
Host smart-fc226fc0-d1ea-4c73-80de-a773d361b4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897687591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2897687591
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3777409008
Short name T584
Test name
Test status
Simulation time 61849318929 ps
CPU time 27.45 seconds
Started Jun 25 06:56:35 PM PDT 24
Finished Jun 25 06:57:04 PM PDT 24
Peak memory 250136 kb
Host smart-38417914-373e-4e68-9876-47fe98533935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777409008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3777409008
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2933959280
Short name T619
Test name
Test status
Simulation time 40652751915 ps
CPU time 135.73 seconds
Started Jun 25 06:56:36 PM PDT 24
Finished Jun 25 06:58:52 PM PDT 24
Peak memory 241968 kb
Host smart-2718809b-d3f1-4e07-9f21-a07d1f7b263f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933959280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2933959280
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2664432206
Short name T118
Test name
Test status
Simulation time 5773364715 ps
CPU time 16.07 seconds
Started Jun 25 06:56:33 PM PDT 24
Finished Jun 25 06:56:50 PM PDT 24
Peak memory 225496 kb
Host smart-778bf886-a982-4182-8e47-a4ddeb7cf479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664432206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2664432206
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2442215801
Short name T887
Test name
Test status
Simulation time 1244481734 ps
CPU time 17.63 seconds
Started Jun 25 06:56:30 PM PDT 24
Finished Jun 25 06:56:49 PM PDT 24
Peak memory 233632 kb
Host smart-1a7eecd5-f43a-4621-b9e8-46a8ace184c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442215801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2442215801
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2382076597
Short name T348
Test name
Test status
Simulation time 2671173994 ps
CPU time 9.18 seconds
Started Jun 25 06:56:32 PM PDT 24
Finished Jun 25 06:56:43 PM PDT 24
Peak memory 233716 kb
Host smart-61b37a50-65a9-4dd2-82cc-d6b327725f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382076597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2382076597
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1681853244
Short name T250
Test name
Test status
Simulation time 1382974047 ps
CPU time 8.17 seconds
Started Jun 25 06:56:28 PM PDT 24
Finished Jun 25 06:56:38 PM PDT 24
Peak memory 240724 kb
Host smart-8d898806-7839-4e61-8fc6-d98cc8c6420e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681853244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1681853244
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.628573923
Short name T930
Test name
Test status
Simulation time 2003782414 ps
CPU time 7.46 seconds
Started Jun 25 06:56:31 PM PDT 24
Finished Jun 25 06:56:40 PM PDT 24
Peak memory 233608 kb
Host smart-e7f99bde-f8b9-4cf3-9540-01eec18d942e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628573923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.628573923
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.789591166
Short name T594
Test name
Test status
Simulation time 767307583 ps
CPU time 10.89 seconds
Started Jun 25 06:56:35 PM PDT 24
Finished Jun 25 06:56:47 PM PDT 24
Peak memory 221356 kb
Host smart-414ef21f-fd32-4095-b571-65bdfd140203
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=789591166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.789591166
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.378577801
Short name T879
Test name
Test status
Simulation time 2073381670 ps
CPU time 25.94 seconds
Started Jun 25 06:56:29 PM PDT 24
Finished Jun 25 06:56:56 PM PDT 24
Peak memory 217084 kb
Host smart-ea1cfbb8-9991-48ff-a16c-e01a26389a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378577801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.378577801
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1682173780
Short name T33
Test name
Test status
Simulation time 1661349147 ps
CPU time 6.98 seconds
Started Jun 25 06:56:29 PM PDT 24
Finished Jun 25 06:56:37 PM PDT 24
Peak memory 217128 kb
Host smart-713b9fa4-943d-405f-a8dc-8e5333e3758b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682173780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1682173780
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.290901720
Short name T901
Test name
Test status
Simulation time 62856774 ps
CPU time 1.09 seconds
Started Jun 25 06:56:31 PM PDT 24
Finished Jun 25 06:56:33 PM PDT 24
Peak memory 208212 kb
Host smart-cf25e2ee-75d9-410d-9f56-f7bf36b50100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290901720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.290901720
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3658992029
Short name T539
Test name
Test status
Simulation time 43180152 ps
CPU time 0.88 seconds
Started Jun 25 06:56:30 PM PDT 24
Finished Jun 25 06:56:32 PM PDT 24
Peak memory 206752 kb
Host smart-3cd3474c-3170-4dec-8499-e49f892d4fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658992029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3658992029
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2100108328
Short name T502
Test name
Test status
Simulation time 43433793 ps
CPU time 2.27 seconds
Started Jun 25 06:56:29 PM PDT 24
Finished Jun 25 06:56:33 PM PDT 24
Peak memory 224744 kb
Host smart-abe35efe-5b56-40b5-a9a3-ddeebeb28878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100108328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2100108328
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2936860671
Short name T646
Test name
Test status
Simulation time 18913523 ps
CPU time 0.73 seconds
Started Jun 25 06:56:41 PM PDT 24
Finished Jun 25 06:56:43 PM PDT 24
Peak memory 206636 kb
Host smart-9669b986-4022-4a91-8501-f0d5f25d1373
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936860671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2936860671
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3633082000
Short name T72
Test name
Test status
Simulation time 3580386358 ps
CPU time 8.73 seconds
Started Jun 25 06:56:41 PM PDT 24
Finished Jun 25 06:56:51 PM PDT 24
Peak memory 225516 kb
Host smart-1cc0649a-08d0-4169-bd0f-2f3be1f3a5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633082000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3633082000
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3173187325
Short name T314
Test name
Test status
Simulation time 49844453 ps
CPU time 0.76 seconds
Started Jun 25 06:56:36 PM PDT 24
Finished Jun 25 06:56:38 PM PDT 24
Peak memory 206712 kb
Host smart-1a6574fb-6ad7-4c92-9725-99ceb39770f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173187325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3173187325
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2154153317
Short name T181
Test name
Test status
Simulation time 198380629645 ps
CPU time 360.02 seconds
Started Jun 25 06:56:42 PM PDT 24
Finished Jun 25 07:02:44 PM PDT 24
Peak memory 266496 kb
Host smart-33e1f096-f4cd-4938-a4ed-09e94a31ae1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154153317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2154153317
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1525890569
Short name T771
Test name
Test status
Simulation time 31951768931 ps
CPU time 56.75 seconds
Started Jun 25 06:56:43 PM PDT 24
Finished Jun 25 06:57:41 PM PDT 24
Peak memory 225584 kb
Host smart-0b20ac05-809c-4387-9168-59e07edce28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525890569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1525890569
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1399391584
Short name T291
Test name
Test status
Simulation time 5355435563 ps
CPU time 25.05 seconds
Started Jun 25 06:56:41 PM PDT 24
Finished Jun 25 06:57:07 PM PDT 24
Peak memory 237832 kb
Host smart-2b0349fd-2b5d-41f9-b597-42383856eee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399391584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1399391584
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1771629814
Short name T528
Test name
Test status
Simulation time 117879060 ps
CPU time 3.15 seconds
Started Jun 25 06:56:35 PM PDT 24
Finished Jun 25 06:56:39 PM PDT 24
Peak memory 225408 kb
Host smart-be1d3ab3-66ae-4c63-a9f2-163f589e540c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771629814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1771629814
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3204103142
Short name T437
Test name
Test status
Simulation time 4069083462 ps
CPU time 38.82 seconds
Started Jun 25 06:56:37 PM PDT 24
Finished Jun 25 06:57:17 PM PDT 24
Peak memory 225588 kb
Host smart-ae546151-e2b9-4206-90cf-ef3166ff20dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204103142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3204103142
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3463578606
Short name T285
Test name
Test status
Simulation time 3389452745 ps
CPU time 9.94 seconds
Started Jun 25 06:56:35 PM PDT 24
Finished Jun 25 06:56:45 PM PDT 24
Peak memory 241812 kb
Host smart-10ee3806-54a6-4792-b06a-1952fb9c021d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463578606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3463578606
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.170924451
Short name T593
Test name
Test status
Simulation time 1115727230 ps
CPU time 6.58 seconds
Started Jun 25 06:56:36 PM PDT 24
Finished Jun 25 06:56:44 PM PDT 24
Peak memory 225320 kb
Host smart-6bc494a3-53a6-446c-9e41-ee4cc3397247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170924451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.170924451
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3034609746
Short name T503
Test name
Test status
Simulation time 6857504739 ps
CPU time 15.81 seconds
Started Jun 25 06:56:42 PM PDT 24
Finished Jun 25 06:57:00 PM PDT 24
Peak memory 224164 kb
Host smart-88009b23-4437-4551-b2b3-16507bbbcee9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3034609746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3034609746
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.709605237
Short name T769
Test name
Test status
Simulation time 78469434782 ps
CPU time 271.81 seconds
Started Jun 25 06:56:41 PM PDT 24
Finished Jun 25 07:01:13 PM PDT 24
Peak memory 271468 kb
Host smart-e58311a0-fbaf-4558-bfb3-141e200c8d62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709605237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.709605237
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2114463233
Short name T543
Test name
Test status
Simulation time 11272721275 ps
CPU time 19.44 seconds
Started Jun 25 06:56:42 PM PDT 24
Finished Jun 25 06:57:03 PM PDT 24
Peak memory 216604 kb
Host smart-823a1f31-266f-47c2-8453-2765147e1e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114463233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2114463233
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.460653497
Short name T303
Test name
Test status
Simulation time 6489315913 ps
CPU time 9.44 seconds
Started Jun 25 06:56:41 PM PDT 24
Finished Jun 25 06:56:52 PM PDT 24
Peak memory 217252 kb
Host smart-b545031f-70ba-45dd-b14b-c86966463959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460653497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.460653497
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.139917474
Short name T545
Test name
Test status
Simulation time 51859930 ps
CPU time 1.47 seconds
Started Jun 25 06:56:36 PM PDT 24
Finished Jun 25 06:56:39 PM PDT 24
Peak memory 217208 kb
Host smart-9a4a118e-0197-4843-bc62-b9bf306e3bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139917474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.139917474
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1198551390
Short name T840
Test name
Test status
Simulation time 17773154 ps
CPU time 0.74 seconds
Started Jun 25 06:56:36 PM PDT 24
Finished Jun 25 06:56:38 PM PDT 24
Peak memory 206724 kb
Host smart-edc76d01-50d5-4756-b3fd-21152dfe6bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198551390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1198551390
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.454506211
Short name T945
Test name
Test status
Simulation time 2502071334 ps
CPU time 2.75 seconds
Started Jun 25 06:56:42 PM PDT 24
Finished Jun 25 06:56:47 PM PDT 24
Peak memory 225516 kb
Host smart-83d12d54-af14-40b9-aa0c-67e23a4815fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454506211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.454506211
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1859903428
Short name T440
Test name
Test status
Simulation time 47444171 ps
CPU time 0.76 seconds
Started Jun 25 06:56:48 PM PDT 24
Finished Jun 25 06:56:50 PM PDT 24
Peak memory 206628 kb
Host smart-cd41ab29-aaa6-4985-ab81-ccb8489c2752
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859903428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1859903428
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.792085439
Short name T224
Test name
Test status
Simulation time 112399913 ps
CPU time 2.64 seconds
Started Jun 25 06:56:42 PM PDT 24
Finished Jun 25 06:56:46 PM PDT 24
Peak memory 225428 kb
Host smart-4cb19750-c290-4102-9d1d-12566a61b116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792085439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.792085439
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1565568998
Short name T762
Test name
Test status
Simulation time 112303031 ps
CPU time 0.76 seconds
Started Jun 25 06:56:44 PM PDT 24
Finished Jun 25 06:56:45 PM PDT 24
Peak memory 206376 kb
Host smart-06126633-460f-4d29-9e48-557196e071b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565568998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1565568998
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3252043005
Short name T865
Test name
Test status
Simulation time 48116839 ps
CPU time 0.81 seconds
Started Jun 25 06:56:49 PM PDT 24
Finished Jun 25 06:56:51 PM PDT 24
Peak memory 217024 kb
Host smart-7fd3123e-3638-457d-877e-ce47239469a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252043005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3252043005
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.963695225
Short name T274
Test name
Test status
Simulation time 7450647172 ps
CPU time 151.36 seconds
Started Jun 25 06:56:48 PM PDT 24
Finished Jun 25 06:59:21 PM PDT 24
Peak memory 266364 kb
Host smart-22f414b6-22f9-42fb-a915-e87dc8166b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963695225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.963695225
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3559088501
Short name T451
Test name
Test status
Simulation time 137340841 ps
CPU time 3.69 seconds
Started Jun 25 06:56:41 PM PDT 24
Finished Jun 25 06:56:46 PM PDT 24
Peak memory 225424 kb
Host smart-49e52b7c-4524-436b-990c-0ca90b974542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559088501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3559088501
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2928550845
Short name T635
Test name
Test status
Simulation time 474445853 ps
CPU time 7.2 seconds
Started Jun 25 06:56:40 PM PDT 24
Finished Jun 25 06:56:48 PM PDT 24
Peak memory 225288 kb
Host smart-39c02364-611d-465f-aa7e-7a1167e9e93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928550845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2928550845
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.4119858160
Short name T912
Test name
Test status
Simulation time 20355746201 ps
CPU time 31.98 seconds
Started Jun 25 06:56:43 PM PDT 24
Finished Jun 25 06:57:16 PM PDT 24
Peak memory 225504 kb
Host smart-b34fa6d9-b31b-4432-a7db-566e755c78e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119858160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.4119858160
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.578845251
Short name T705
Test name
Test status
Simulation time 31222963292 ps
CPU time 11.26 seconds
Started Jun 25 06:56:42 PM PDT 24
Finished Jun 25 06:56:55 PM PDT 24
Peak memory 237836 kb
Host smart-7ba629cf-dece-4a53-8156-5160d2b4f766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578845251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.578845251
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.392883299
Short name T880
Test name
Test status
Simulation time 21812905868 ps
CPU time 17.63 seconds
Started Jun 25 06:56:42 PM PDT 24
Finished Jun 25 06:57:02 PM PDT 24
Peak memory 225556 kb
Host smart-0af30d6a-11f0-4b8a-a56e-d694cd9ef7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392883299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.392883299
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3908867250
Short name T462
Test name
Test status
Simulation time 3684360102 ps
CPU time 7.68 seconds
Started Jun 25 06:56:41 PM PDT 24
Finished Jun 25 06:56:50 PM PDT 24
Peak memory 220412 kb
Host smart-ac6c5348-749e-465e-b0e9-cd3da35bac91
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3908867250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3908867250
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1644039026
Short name T578
Test name
Test status
Simulation time 48568220 ps
CPU time 1.05 seconds
Started Jun 25 06:56:50 PM PDT 24
Finished Jun 25 06:56:53 PM PDT 24
Peak memory 207976 kb
Host smart-c1812c7f-ca39-4453-90ed-88a96377b940
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644039026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1644039026
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.4053177929
Short name T380
Test name
Test status
Simulation time 1926457378 ps
CPU time 7.95 seconds
Started Jun 25 06:56:42 PM PDT 24
Finished Jun 25 06:56:51 PM PDT 24
Peak memory 217064 kb
Host smart-6211b7cf-a05d-49a0-ac5a-8ae3df50bd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053177929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.4053177929
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.305805994
Short name T685
Test name
Test status
Simulation time 223869839 ps
CPU time 1.95 seconds
Started Jun 25 06:56:42 PM PDT 24
Finished Jun 25 06:56:45 PM PDT 24
Peak memory 208688 kb
Host smart-834c731d-a6d0-4b91-bd4b-a167f300f101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305805994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.305805994
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.174183396
Short name T628
Test name
Test status
Simulation time 28389929 ps
CPU time 0.76 seconds
Started Jun 25 06:56:41 PM PDT 24
Finished Jun 25 06:56:43 PM PDT 24
Peak memory 206716 kb
Host smart-69ebaa48-a2fa-472a-a1dc-a2a54fc4c776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174183396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.174183396
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.279223190
Short name T582
Test name
Test status
Simulation time 176314822 ps
CPU time 0.9 seconds
Started Jun 25 06:56:42 PM PDT 24
Finished Jun 25 06:56:45 PM PDT 24
Peak memory 206704 kb
Host smart-6a39b187-133f-42e3-91f2-3516ae00b48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279223190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.279223190
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3250865487
Short name T708
Test name
Test status
Simulation time 350993644 ps
CPU time 3.31 seconds
Started Jun 25 06:56:43 PM PDT 24
Finished Jun 25 06:56:47 PM PDT 24
Peak memory 233700 kb
Host smart-71d13da8-2e17-4a9a-8aba-4f96a55167ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250865487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3250865487
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1752283635
Short name T861
Test name
Test status
Simulation time 13760094 ps
CPU time 0.75 seconds
Started Jun 25 06:56:55 PM PDT 24
Finished Jun 25 06:56:57 PM PDT 24
Peak memory 206664 kb
Host smart-6c0b54b1-2233-4918-9aee-057919f04ea1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752283635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1752283635
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3403942803
Short name T911
Test name
Test status
Simulation time 87866122 ps
CPU time 3.37 seconds
Started Jun 25 06:56:49 PM PDT 24
Finished Jun 25 06:56:54 PM PDT 24
Peak memory 233592 kb
Host smart-12bb60b9-056e-47de-8223-8fca750f239d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403942803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3403942803
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1048643317
Short name T590
Test name
Test status
Simulation time 16418548 ps
CPU time 0.82 seconds
Started Jun 25 06:56:49 PM PDT 24
Finished Jun 25 06:56:51 PM PDT 24
Peak memory 207424 kb
Host smart-e0464969-f9a7-4bff-9718-8fd35c8f740c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048643317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1048643317
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2813739715
Short name T24
Test name
Test status
Simulation time 150083540479 ps
CPU time 279.08 seconds
Started Jun 25 06:56:55 PM PDT 24
Finished Jun 25 07:01:35 PM PDT 24
Peak memory 250152 kb
Host smart-39491511-038c-47db-a0f2-6ca8be32294e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813739715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2813739715
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.981360348
Short name T277
Test name
Test status
Simulation time 6431035669 ps
CPU time 95.58 seconds
Started Jun 25 06:56:56 PM PDT 24
Finished Jun 25 06:58:33 PM PDT 24
Peak memory 251204 kb
Host smart-09f01107-78c0-486b-9c37-34a3371d2265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981360348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.981360348
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.106150411
Short name T910
Test name
Test status
Simulation time 877351692 ps
CPU time 20.66 seconds
Started Jun 25 06:56:50 PM PDT 24
Finished Jun 25 06:57:13 PM PDT 24
Peak memory 233640 kb
Host smart-3abddeb3-10c8-44ca-963d-bc6475ebb48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106150411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.106150411
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.309693591
Short name T747
Test name
Test status
Simulation time 851497394 ps
CPU time 4.35 seconds
Started Jun 25 06:56:48 PM PDT 24
Finished Jun 25 06:56:54 PM PDT 24
Peak memory 233720 kb
Host smart-d0659d89-5955-4e07-9530-e4cd4c26f912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309693591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.309693591
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.4180441638
Short name T435
Test name
Test status
Simulation time 29854927563 ps
CPU time 16.6 seconds
Started Jun 25 06:56:48 PM PDT 24
Finished Jun 25 06:57:05 PM PDT 24
Peak memory 233736 kb
Host smart-f89e8db5-bb83-4812-992c-bd052a70d2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180441638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.4180441638
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.548139494
Short name T253
Test name
Test status
Simulation time 4504678711 ps
CPU time 15.87 seconds
Started Jun 25 06:56:50 PM PDT 24
Finished Jun 25 06:57:07 PM PDT 24
Peak memory 233716 kb
Host smart-34280d61-8689-4c52-9ac8-2aa529520d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548139494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.548139494
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.852699250
Short name T347
Test name
Test status
Simulation time 1177416818 ps
CPU time 4.34 seconds
Started Jun 25 06:56:50 PM PDT 24
Finished Jun 25 06:56:56 PM PDT 24
Peak memory 225444 kb
Host smart-cc08eff9-b8c8-4956-81f5-a2e05e7791a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852699250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.852699250
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1401971593
Short name T721
Test name
Test status
Simulation time 1121466960 ps
CPU time 13.97 seconds
Started Jun 25 06:56:48 PM PDT 24
Finished Jun 25 06:57:03 PM PDT 24
Peak memory 221628 kb
Host smart-96c9b4a4-4c14-448f-b39c-3c5f54c3bff3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1401971593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1401971593
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3918188205
Short name T185
Test name
Test status
Simulation time 49933145130 ps
CPU time 378.89 seconds
Started Jun 25 06:56:54 PM PDT 24
Finished Jun 25 07:03:13 PM PDT 24
Peak memory 254296 kb
Host smart-ae118a66-7fc1-4b81-b376-7b33421c7d3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918188205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3918188205
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3264413749
Short name T884
Test name
Test status
Simulation time 743670635 ps
CPU time 13.35 seconds
Started Jun 25 06:56:49 PM PDT 24
Finished Jun 25 06:57:03 PM PDT 24
Peak memory 217076 kb
Host smart-e7634ae7-c9f2-4616-8ebb-5675d3c3155e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264413749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3264413749
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.4111566174
Short name T610
Test name
Test status
Simulation time 1321450661 ps
CPU time 2.29 seconds
Started Jun 25 06:56:48 PM PDT 24
Finished Jun 25 06:56:51 PM PDT 24
Peak memory 208552 kb
Host smart-ec39e90c-4e29-42a0-9e2f-835a294c7836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111566174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.4111566174
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.336093295
Short name T785
Test name
Test status
Simulation time 286622982 ps
CPU time 2.08 seconds
Started Jun 25 06:56:50 PM PDT 24
Finished Jun 25 06:56:53 PM PDT 24
Peak memory 217116 kb
Host smart-c90dd189-61e4-4322-945f-5a603e52b4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336093295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.336093295
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1568939349
Short name T572
Test name
Test status
Simulation time 380490318 ps
CPU time 0.98 seconds
Started Jun 25 06:56:49 PM PDT 24
Finished Jun 25 06:56:51 PM PDT 24
Peak memory 206700 kb
Host smart-9de41c33-6598-479f-a495-895225201a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568939349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1568939349
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1210212427
Short name T917
Test name
Test status
Simulation time 1812648572 ps
CPU time 6.92 seconds
Started Jun 25 06:56:52 PM PDT 24
Finished Jun 25 06:56:59 PM PDT 24
Peak memory 225400 kb
Host smart-66ad1eda-119d-4f49-adba-6f74c7c81244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210212427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1210212427
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2864320518
Short name T494
Test name
Test status
Simulation time 60695146 ps
CPU time 0.7 seconds
Started Jun 25 06:56:56 PM PDT 24
Finished Jun 25 06:56:58 PM PDT 24
Peak memory 205760 kb
Host smart-ff42e964-ea99-4bbf-9352-7b87730d8d42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864320518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2864320518
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2082452159
Short name T217
Test name
Test status
Simulation time 327224109 ps
CPU time 3.51 seconds
Started Jun 25 06:56:57 PM PDT 24
Finished Jun 25 06:57:01 PM PDT 24
Peak memory 225384 kb
Host smart-f677a029-7b96-4a07-a896-780a3de634e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082452159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2082452159
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1488917808
Short name T944
Test name
Test status
Simulation time 27667811 ps
CPU time 0.78 seconds
Started Jun 25 06:56:55 PM PDT 24
Finished Jun 25 06:56:57 PM PDT 24
Peak memory 207448 kb
Host smart-9565979f-cbfe-4a55-9083-80d8ecd1c4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488917808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1488917808
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1577438528
Short name T239
Test name
Test status
Simulation time 147200102133 ps
CPU time 486.53 seconds
Started Jun 25 06:56:58 PM PDT 24
Finished Jun 25 07:05:05 PM PDT 24
Peak memory 255396 kb
Host smart-5af7859d-52d4-49a5-8513-55544c591b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577438528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1577438528
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.4284937824
Short name T640
Test name
Test status
Simulation time 3374714643 ps
CPU time 29.7 seconds
Started Jun 25 06:56:53 PM PDT 24
Finished Jun 25 06:57:23 PM PDT 24
Peak memory 250124 kb
Host smart-a91c0989-8a7b-47e7-b8c3-e88364afbd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284937824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.4284937824
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1045501505
Short name T110
Test name
Test status
Simulation time 3214890495 ps
CPU time 72.89 seconds
Started Jun 25 06:56:59 PM PDT 24
Finished Jun 25 06:58:12 PM PDT 24
Peak memory 266516 kb
Host smart-d02e4704-2043-4658-821f-ef6d4fcae86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045501505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1045501505
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2139914992
Short name T614
Test name
Test status
Simulation time 208881590 ps
CPU time 5.25 seconds
Started Jun 25 06:56:55 PM PDT 24
Finished Jun 25 06:57:01 PM PDT 24
Peak memory 233640 kb
Host smart-df632743-59f0-4df4-9524-62e842070eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139914992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2139914992
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1898979283
Short name T214
Test name
Test status
Simulation time 119918216 ps
CPU time 3.69 seconds
Started Jun 25 06:56:56 PM PDT 24
Finished Jun 25 06:57:01 PM PDT 24
Peak memory 233628 kb
Host smart-759ae8de-513e-4949-8d25-b1fca5ded424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898979283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1898979283
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1835827275
Short name T213
Test name
Test status
Simulation time 19382326076 ps
CPU time 44.18 seconds
Started Jun 25 06:56:55 PM PDT 24
Finished Jun 25 06:57:41 PM PDT 24
Peak memory 225508 kb
Host smart-c23f7f0b-7d66-49e3-9264-52bfae4e91e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835827275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1835827275
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3226430826
Short name T873
Test name
Test status
Simulation time 1151113291 ps
CPU time 5.67 seconds
Started Jun 25 06:56:56 PM PDT 24
Finished Jun 25 06:57:04 PM PDT 24
Peak memory 241700 kb
Host smart-26748695-c3a7-43ed-8a8d-8b35b3690c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226430826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3226430826
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2343046938
Short name T370
Test name
Test status
Simulation time 1905012296 ps
CPU time 3.79 seconds
Started Jun 25 06:56:55 PM PDT 24
Finished Jun 25 06:57:00 PM PDT 24
Peak memory 233624 kb
Host smart-4cf2df5d-0a53-4a1d-b8bc-17d47d4b8a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343046938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2343046938
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1443327962
Short name T344
Test name
Test status
Simulation time 8675424916 ps
CPU time 13.63 seconds
Started Jun 25 06:56:54 PM PDT 24
Finished Jun 25 06:57:08 PM PDT 24
Peak memory 224188 kb
Host smart-f3d58ce2-ab67-4061-b2c8-8fdf87b341bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1443327962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1443327962
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1172551976
Short name T855
Test name
Test status
Simulation time 1972245922 ps
CPU time 11.82 seconds
Started Jun 25 06:56:55 PM PDT 24
Finished Jun 25 06:57:08 PM PDT 24
Peak memory 225464 kb
Host smart-b3868d82-655e-40f7-ab16-96003284cb00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172551976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1172551976
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.337486788
Short name T433
Test name
Test status
Simulation time 3325563534 ps
CPU time 24.5 seconds
Started Jun 25 06:56:55 PM PDT 24
Finished Jun 25 06:57:21 PM PDT 24
Peak memory 217252 kb
Host smart-b4f0fea8-e3a0-431a-b184-aae98663464d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337486788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.337486788
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2455433527
Short name T331
Test name
Test status
Simulation time 43205519 ps
CPU time 0.72 seconds
Started Jun 25 06:56:56 PM PDT 24
Finished Jun 25 06:56:58 PM PDT 24
Peak memory 206520 kb
Host smart-e60c393f-dcb7-481d-a013-fa0dc335b5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455433527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2455433527
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1467642524
Short name T568
Test name
Test status
Simulation time 143131992 ps
CPU time 2.95 seconds
Started Jun 25 06:56:54 PM PDT 24
Finished Jun 25 06:56:57 PM PDT 24
Peak memory 217064 kb
Host smart-b5648fc2-a034-416b-9022-7b9700a1f137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467642524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1467642524
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3360156190
Short name T825
Test name
Test status
Simulation time 37796504 ps
CPU time 0.7 seconds
Started Jun 25 06:56:55 PM PDT 24
Finished Jun 25 06:56:57 PM PDT 24
Peak memory 206448 kb
Host smart-5675cdd7-d2fa-4652-952f-4e6e4a84f53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360156190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3360156190
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3533306613
Short name T835
Test name
Test status
Simulation time 131058855 ps
CPU time 2.67 seconds
Started Jun 25 06:56:56 PM PDT 24
Finished Jun 25 06:57:00 PM PDT 24
Peak memory 233348 kb
Host smart-950fe296-d452-4adc-ab39-52102fac572d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533306613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3533306613
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2653046237
Short name T720
Test name
Test status
Simulation time 38154610 ps
CPU time 0.76 seconds
Started Jun 25 06:57:01 PM PDT 24
Finished Jun 25 06:57:03 PM PDT 24
Peak memory 205784 kb
Host smart-6a0c633e-9b2a-4690-8d58-89f91831e1c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653046237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2653046237
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2793330198
Short name T519
Test name
Test status
Simulation time 28638291747 ps
CPU time 19.27 seconds
Started Jun 25 06:57:01 PM PDT 24
Finished Jun 25 06:57:21 PM PDT 24
Peak memory 225544 kb
Host smart-e7fefad1-7064-423c-9d58-9eb0e0775612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793330198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2793330198
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3140312614
Short name T466
Test name
Test status
Simulation time 21446474 ps
CPU time 0.78 seconds
Started Jun 25 06:56:55 PM PDT 24
Finished Jun 25 06:56:57 PM PDT 24
Peak memory 207412 kb
Host smart-646e0bcc-a9bb-4bbf-8d77-dceb64227089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140312614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3140312614
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.651427350
Short name T413
Test name
Test status
Simulation time 7457462589 ps
CPU time 82.99 seconds
Started Jun 25 06:57:02 PM PDT 24
Finished Jun 25 06:58:26 PM PDT 24
Peak memory 251228 kb
Host smart-fb7de0f6-6f2e-46d4-9e78-66f7ea1aa5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651427350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.651427350
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.706322497
Short name T813
Test name
Test status
Simulation time 33987886521 ps
CPU time 148.12 seconds
Started Jun 25 06:57:00 PM PDT 24
Finished Jun 25 06:59:29 PM PDT 24
Peak memory 251204 kb
Host smart-7b4ea31c-5730-43ef-920e-333ac51daf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706322497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.706322497
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3982916229
Short name T275
Test name
Test status
Simulation time 57347653789 ps
CPU time 310.18 seconds
Started Jun 25 06:57:01 PM PDT 24
Finished Jun 25 07:02:13 PM PDT 24
Peak memory 255176 kb
Host smart-d4d31028-7c73-4541-b643-5d4d4f62e8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982916229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3982916229
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3015156953
Short name T484
Test name
Test status
Simulation time 437006242 ps
CPU time 10.12 seconds
Started Jun 25 06:57:00 PM PDT 24
Finished Jun 25 06:57:10 PM PDT 24
Peak memory 241820 kb
Host smart-4d53f970-ed12-418a-baf5-910c23acd86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015156953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3015156953
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.586600434
Short name T340
Test name
Test status
Simulation time 450907393 ps
CPU time 6.07 seconds
Started Jun 25 06:57:01 PM PDT 24
Finished Jun 25 06:57:08 PM PDT 24
Peak memory 225388 kb
Host smart-21e0b336-65a5-42e6-8fe0-7241f410e391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586600434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.586600434
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.162832104
Short name T778
Test name
Test status
Simulation time 2824898296 ps
CPU time 14.99 seconds
Started Jun 25 06:57:02 PM PDT 24
Finished Jun 25 06:57:18 PM PDT 24
Peak memory 239940 kb
Host smart-c59b4d30-051c-4780-86b6-6699f2600e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162832104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.162832104
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1457295158
Short name T444
Test name
Test status
Simulation time 14878246507 ps
CPU time 25.91 seconds
Started Jun 25 06:57:00 PM PDT 24
Finished Jun 25 06:57:27 PM PDT 24
Peak memory 233736 kb
Host smart-9b1b2049-7fbc-48b1-b5f3-f19e01d810d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457295158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1457295158
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2956696054
Short name T745
Test name
Test status
Simulation time 1425565186 ps
CPU time 2.44 seconds
Started Jun 25 06:57:01 PM PDT 24
Finished Jun 25 06:57:05 PM PDT 24
Peak memory 224044 kb
Host smart-3ff76e61-68fb-41a3-89a3-01a61898a25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956696054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2956696054
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2318336052
Short name T559
Test name
Test status
Simulation time 3730831463 ps
CPU time 6.85 seconds
Started Jun 25 06:57:01 PM PDT 24
Finished Jun 25 06:57:09 PM PDT 24
Peak memory 223704 kb
Host smart-6328630f-36aa-4318-88c3-fbb8c6a41ce7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2318336052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2318336052
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.640111788
Short name T875
Test name
Test status
Simulation time 793657212 ps
CPU time 1.06 seconds
Started Jun 25 06:57:00 PM PDT 24
Finished Jun 25 06:57:02 PM PDT 24
Peak memory 207908 kb
Host smart-b04045c9-a64d-4abc-845e-527eec64b805
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640111788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.640111788
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.553384390
Short name T406
Test name
Test status
Simulation time 31800097250 ps
CPU time 17.53 seconds
Started Jun 25 06:56:56 PM PDT 24
Finished Jun 25 06:57:15 PM PDT 24
Peak memory 218528 kb
Host smart-efe4887d-666c-4663-94f9-c3b8dcfb4ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553384390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.553384390
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.523326678
Short name T658
Test name
Test status
Simulation time 438128216 ps
CPU time 2.79 seconds
Started Jun 25 06:56:55 PM PDT 24
Finished Jun 25 06:57:00 PM PDT 24
Peak memory 217144 kb
Host smart-15593012-584b-4c81-b622-a480043501e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523326678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.523326678
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.217494625
Short name T655
Test name
Test status
Simulation time 723112005 ps
CPU time 3.59 seconds
Started Jun 25 06:57:00 PM PDT 24
Finished Jun 25 06:57:05 PM PDT 24
Peak memory 217116 kb
Host smart-bdeadbcc-2b25-4962-be05-e5483dba0540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217494625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.217494625
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.4029085519
Short name T739
Test name
Test status
Simulation time 70551837 ps
CPU time 0.92 seconds
Started Jun 25 06:56:54 PM PDT 24
Finished Jun 25 06:56:56 PM PDT 24
Peak memory 206752 kb
Host smart-4b05ac1a-8804-4c87-ab15-7cbf21e6417b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029085519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.4029085519
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2916460332
Short name T454
Test name
Test status
Simulation time 7384813194 ps
CPU time 11.55 seconds
Started Jun 25 06:57:02 PM PDT 24
Finished Jun 25 06:57:15 PM PDT 24
Peak memory 233768 kb
Host smart-70d1d5b5-5e67-46cc-ac64-1605c6dbf20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916460332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2916460332
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.719928531
Short name T602
Test name
Test status
Simulation time 16080304 ps
CPU time 0.76 seconds
Started Jun 25 06:57:16 PM PDT 24
Finished Jun 25 06:57:18 PM PDT 24
Peak memory 206332 kb
Host smart-bdcd307e-4455-4e60-9a2f-2964a00af2ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719928531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.719928531
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2883984526
Short name T351
Test name
Test status
Simulation time 100559314 ps
CPU time 3.16 seconds
Started Jun 25 06:57:07 PM PDT 24
Finished Jun 25 06:57:12 PM PDT 24
Peak memory 233624 kb
Host smart-a376931a-9785-4e9d-b7ad-d222ecafdfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883984526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2883984526
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.276161166
Short name T781
Test name
Test status
Simulation time 79324981 ps
CPU time 0.87 seconds
Started Jun 25 06:57:02 PM PDT 24
Finished Jun 25 06:57:04 PM PDT 24
Peak memory 207728 kb
Host smart-476dc64c-2dc6-4c6e-93ed-19d65583e8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276161166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.276161166
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1790418762
Short name T626
Test name
Test status
Simulation time 1604162182 ps
CPU time 33.13 seconds
Started Jun 25 06:57:16 PM PDT 24
Finished Jun 25 06:57:51 PM PDT 24
Peak memory 253884 kb
Host smart-b62f68a9-dbb2-452b-8e59-337bee1d7309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790418762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1790418762
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1193740228
Short name T839
Test name
Test status
Simulation time 8664889967 ps
CPU time 83.95 seconds
Started Jun 25 06:57:15 PM PDT 24
Finished Jun 25 06:58:40 PM PDT 24
Peak memory 250188 kb
Host smart-eb88578e-d107-45d9-8245-1a1d8c5fa5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193740228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1193740228
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.94347216
Short name T682
Test name
Test status
Simulation time 164592575 ps
CPU time 3.24 seconds
Started Jun 25 06:57:08 PM PDT 24
Finished Jun 25 06:57:13 PM PDT 24
Peak memory 225440 kb
Host smart-0c46b69d-128f-479f-916a-64b8d958c399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94347216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.94347216
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3811424480
Short name T656
Test name
Test status
Simulation time 692260901 ps
CPU time 7.45 seconds
Started Jun 25 06:57:10 PM PDT 24
Finished Jun 25 06:57:18 PM PDT 24
Peak memory 233632 kb
Host smart-083119fe-d029-4d42-87a1-4e4a96fdaf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811424480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3811424480
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.803320752
Short name T788
Test name
Test status
Simulation time 3708333779 ps
CPU time 18.4 seconds
Started Jun 25 06:57:09 PM PDT 24
Finished Jun 25 06:57:28 PM PDT 24
Peak memory 225552 kb
Host smart-14530e40-b0c6-48fd-b6cd-40453b6a7a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803320752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.803320752
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1114726607
Short name T312
Test name
Test status
Simulation time 235443602 ps
CPU time 2.17 seconds
Started Jun 25 06:57:08 PM PDT 24
Finished Jun 25 06:57:12 PM PDT 24
Peak memory 224656 kb
Host smart-01e2f03f-a988-41d4-85f0-c05503397700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114726607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1114726607
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2712084051
Short name T192
Test name
Test status
Simulation time 884762635 ps
CPU time 6.32 seconds
Started Jun 25 06:57:08 PM PDT 24
Finished Jun 25 06:57:16 PM PDT 24
Peak memory 233620 kb
Host smart-1c653d0f-e938-40a8-9e14-a481e6611daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712084051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2712084051
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.889650939
Short name T418
Test name
Test status
Simulation time 2477411227 ps
CPU time 8.39 seconds
Started Jun 25 06:57:09 PM PDT 24
Finished Jun 25 06:57:18 PM PDT 24
Peak memory 224180 kb
Host smart-8112db12-e088-4c2e-9592-071cc08f9595
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=889650939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.889650939
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3771051350
Short name T791
Test name
Test status
Simulation time 30307044 ps
CPU time 0.75 seconds
Started Jun 25 06:57:08 PM PDT 24
Finished Jun 25 06:57:11 PM PDT 24
Peak memory 206464 kb
Host smart-a71ddb82-f33b-4f99-8d80-3b4c8d928e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771051350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3771051350
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.684292762
Short name T899
Test name
Test status
Simulation time 163660119 ps
CPU time 1.58 seconds
Started Jun 25 06:57:08 PM PDT 24
Finished Jun 25 06:57:11 PM PDT 24
Peak memory 208676 kb
Host smart-db36ab06-b66d-487e-9455-fc2e6b1ec6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684292762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.684292762
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3253759111
Short name T322
Test name
Test status
Simulation time 172478814 ps
CPU time 2.89 seconds
Started Jun 25 06:57:08 PM PDT 24
Finished Jun 25 06:57:13 PM PDT 24
Peak memory 217096 kb
Host smart-b889acdf-2378-443f-aa0c-717716e33bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253759111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3253759111
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1919834099
Short name T135
Test name
Test status
Simulation time 77443092 ps
CPU time 0.88 seconds
Started Jun 25 06:57:07 PM PDT 24
Finished Jun 25 06:57:10 PM PDT 24
Peak memory 206664 kb
Host smart-a75ed510-46bf-4c90-a201-a39cec6c0095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919834099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1919834099
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3941660032
Short name T164
Test name
Test status
Simulation time 3114658838 ps
CPU time 13.99 seconds
Started Jun 25 06:57:07 PM PDT 24
Finished Jun 25 06:57:23 PM PDT 24
Peak memory 233612 kb
Host smart-1917c49a-70b9-4926-a429-703eba16eda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941660032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3941660032
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.994138341
Short name T446
Test name
Test status
Simulation time 17559697 ps
CPU time 0.77 seconds
Started Jun 25 06:54:14 PM PDT 24
Finished Jun 25 06:54:17 PM PDT 24
Peak memory 206300 kb
Host smart-4ef27a76-ecf9-41d4-bdcf-8b0f91b4204b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994138341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.994138341
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3796101184
Short name T537
Test name
Test status
Simulation time 78705742 ps
CPU time 2.48 seconds
Started Jun 25 06:54:09 PM PDT 24
Finished Jun 25 06:54:12 PM PDT 24
Peak memory 225304 kb
Host smart-63c35865-9331-47ac-b55e-2f7ff5cc5d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796101184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3796101184
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.4234658801
Short name T686
Test name
Test status
Simulation time 64709279 ps
CPU time 0.77 seconds
Started Jun 25 06:53:59 PM PDT 24
Finished Jun 25 06:54:03 PM PDT 24
Peak memory 207408 kb
Host smart-99ac2176-423d-4f20-b5c1-d1730a55d510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234658801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.4234658801
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.4280836918
Short name T828
Test name
Test status
Simulation time 11416526061 ps
CPU time 84.94 seconds
Started Jun 25 06:54:06 PM PDT 24
Finished Jun 25 06:55:33 PM PDT 24
Peak memory 241584 kb
Host smart-202392dc-7e4c-4984-ba8c-da5287d80cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280836918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.4280836918
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3400293812
Short name T68
Test name
Test status
Simulation time 14945592995 ps
CPU time 74.3 seconds
Started Jun 25 06:54:06 PM PDT 24
Finished Jun 25 06:55:22 PM PDT 24
Peak memory 240312 kb
Host smart-fa850aa3-2745-47b3-892b-d51d1b3489b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400293812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3400293812
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1565914666
Short name T798
Test name
Test status
Simulation time 9483249483 ps
CPU time 54.94 seconds
Started Jun 25 06:54:06 PM PDT 24
Finished Jun 25 06:55:02 PM PDT 24
Peak memory 253292 kb
Host smart-bdfc2bf2-24c8-4ac1-99be-84ac9d4ed399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565914666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1565914666
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1133620982
Short name T569
Test name
Test status
Simulation time 9259133239 ps
CPU time 16.54 seconds
Started Jun 25 06:54:07 PM PDT 24
Finished Jun 25 06:54:25 PM PDT 24
Peak memory 233760 kb
Host smart-8669d81d-0494-46a9-9133-c530e4f6f443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133620982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1133620982
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1216363909
Short name T191
Test name
Test status
Simulation time 1094523068 ps
CPU time 20.89 seconds
Started Jun 25 06:54:05 PM PDT 24
Finished Jun 25 06:54:27 PM PDT 24
Peak memory 233632 kb
Host smart-d209f286-da0f-4a8b-8ec2-292410ccdd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216363909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1216363909
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.832505846
Short name T395
Test name
Test status
Simulation time 2452731001 ps
CPU time 7.28 seconds
Started Jun 25 06:54:06 PM PDT 24
Finished Jun 25 06:54:15 PM PDT 24
Peak memory 233716 kb
Host smart-d93d5da5-1956-46e4-bcba-cb56c1f28fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832505846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
832505846
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.4093161563
Short name T534
Test name
Test status
Simulation time 4009730663 ps
CPU time 14.28 seconds
Started Jun 25 06:54:08 PM PDT 24
Finished Jun 25 06:54:24 PM PDT 24
Peak memory 233656 kb
Host smart-c6173729-fbd8-4316-b1b5-0ff239868def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093161563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.4093161563
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1910565945
Short name T837
Test name
Test status
Simulation time 453621547 ps
CPU time 4.99 seconds
Started Jun 25 06:54:06 PM PDT 24
Finished Jun 25 06:54:11 PM PDT 24
Peak memory 219668 kb
Host smart-031ca232-5bbb-4dac-8479-6f1363844b19
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1910565945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1910565945
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2836449340
Short name T58
Test name
Test status
Simulation time 60507372 ps
CPU time 1.12 seconds
Started Jun 25 06:54:05 PM PDT 24
Finished Jun 25 06:54:07 PM PDT 24
Peak memory 236036 kb
Host smart-88e280e1-9567-4813-9409-3350c381fd1e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836449340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2836449340
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.999985918
Short name T162
Test name
Test status
Simulation time 378150912738 ps
CPU time 800.15 seconds
Started Jun 25 06:54:07 PM PDT 24
Finished Jun 25 07:07:28 PM PDT 24
Peak memory 286644 kb
Host smart-f8ecbf02-8f28-440d-bd46-c7fc48478436
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999985918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.999985918
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2048529358
Short name T306
Test name
Test status
Simulation time 33570024 ps
CPU time 0.74 seconds
Started Jun 25 06:53:58 PM PDT 24
Finished Jun 25 06:54:00 PM PDT 24
Peak memory 206536 kb
Host smart-9bae0368-67f5-48cd-9c22-356e252fa348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048529358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2048529358
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.865682493
Short name T612
Test name
Test status
Simulation time 943600543 ps
CPU time 6.38 seconds
Started Jun 25 06:54:02 PM PDT 24
Finished Jun 25 06:54:11 PM PDT 24
Peak memory 217076 kb
Host smart-48d752ce-0637-4f0f-99a0-4d7df26124b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865682493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.865682493
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2748063909
Short name T434
Test name
Test status
Simulation time 683259038 ps
CPU time 0.96 seconds
Started Jun 25 06:54:07 PM PDT 24
Finished Jun 25 06:54:10 PM PDT 24
Peak memory 207648 kb
Host smart-2e801076-a873-45d4-be9f-079d48e73f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748063909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2748063909
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2154272444
Short name T426
Test name
Test status
Simulation time 177270780 ps
CPU time 0.88 seconds
Started Jun 25 06:54:06 PM PDT 24
Finished Jun 25 06:54:09 PM PDT 24
Peak memory 206704 kb
Host smart-b91988f0-30d0-4090-9a18-e72afeb9872a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154272444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2154272444
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.480810067
Short name T816
Test name
Test status
Simulation time 685400049 ps
CPU time 6.59 seconds
Started Jun 25 06:54:08 PM PDT 24
Finished Jun 25 06:54:16 PM PDT 24
Peak memory 233580 kb
Host smart-2e4ce1a0-59c3-4120-b470-576e9a632070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480810067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.480810067
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3634549138
Short name T669
Test name
Test status
Simulation time 13345293 ps
CPU time 0.73 seconds
Started Jun 25 06:57:17 PM PDT 24
Finished Jun 25 06:57:19 PM PDT 24
Peak memory 206372 kb
Host smart-c67e8288-d5d9-4d4b-b278-9d6c42f9cdae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634549138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3634549138
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1695244488
Short name T702
Test name
Test status
Simulation time 1579184235 ps
CPU time 7.08 seconds
Started Jun 25 06:57:16 PM PDT 24
Finished Jun 25 06:57:25 PM PDT 24
Peak memory 225344 kb
Host smart-3a1b395b-306a-4c56-9f81-4174374ce918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695244488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1695244488
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1290311194
Short name T393
Test name
Test status
Simulation time 40514139 ps
CPU time 0.78 seconds
Started Jun 25 06:57:15 PM PDT 24
Finished Jun 25 06:57:17 PM PDT 24
Peak memory 206716 kb
Host smart-c12befb0-f413-4d8c-b17e-bde0bbaa7cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290311194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1290311194
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.4014858778
Short name T562
Test name
Test status
Simulation time 148604430 ps
CPU time 0.76 seconds
Started Jun 25 06:57:15 PM PDT 24
Finished Jun 25 06:57:18 PM PDT 24
Peak memory 216780 kb
Host smart-7db448fd-1a68-4870-bc78-3862983b1354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014858778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.4014858778
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.42418220
Short name T826
Test name
Test status
Simulation time 13756197311 ps
CPU time 35.72 seconds
Started Jun 25 06:57:17 PM PDT 24
Finished Jun 25 06:57:54 PM PDT 24
Peak memory 238588 kb
Host smart-157874a7-3bc8-4644-8959-3a28e7dbc0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42418220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.42418220
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.4220406758
Short name T554
Test name
Test status
Simulation time 6999264680 ps
CPU time 36.64 seconds
Started Jun 25 06:57:15 PM PDT 24
Finished Jun 25 06:57:53 PM PDT 24
Peak memory 250084 kb
Host smart-3720ae20-fcc7-43ee-9579-228a02c35c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220406758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.4220406758
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.4145783693
Short name T28
Test name
Test status
Simulation time 1103202895 ps
CPU time 8.97 seconds
Started Jun 25 06:57:15 PM PDT 24
Finished Jun 25 06:57:25 PM PDT 24
Peak memory 233592 kb
Host smart-3828a0a8-3b84-4e52-bcf6-7fa644472532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145783693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.4145783693
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3402665053
Short name T394
Test name
Test status
Simulation time 934043611 ps
CPU time 11.02 seconds
Started Jun 25 06:57:18 PM PDT 24
Finished Jun 25 06:57:30 PM PDT 24
Peak memory 233620 kb
Host smart-0972843e-6d51-426a-a638-942d277b1fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402665053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3402665053
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2654479099
Short name T622
Test name
Test status
Simulation time 1216817806 ps
CPU time 8.07 seconds
Started Jun 25 06:57:15 PM PDT 24
Finished Jun 25 06:57:25 PM PDT 24
Peak memory 225376 kb
Host smart-7ea57464-2f19-4019-9916-04f42643163c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654479099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2654479099
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1715764707
Short name T603
Test name
Test status
Simulation time 4184114431 ps
CPU time 6.54 seconds
Started Jun 25 06:57:15 PM PDT 24
Finished Jun 25 06:57:23 PM PDT 24
Peak memory 233724 kb
Host smart-43a95372-8a2c-4254-b3a1-0c93e11b4ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715764707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1715764707
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3927574662
Short name T441
Test name
Test status
Simulation time 679190856 ps
CPU time 7.71 seconds
Started Jun 25 06:57:17 PM PDT 24
Finished Jun 25 06:57:26 PM PDT 24
Peak memory 221348 kb
Host smart-a0aaa871-78a3-487e-91b3-bf94585dd8f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3927574662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3927574662
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.581552440
Short name T16
Test name
Test status
Simulation time 6757711234 ps
CPU time 75.19 seconds
Started Jun 25 06:57:15 PM PDT 24
Finished Jun 25 06:58:32 PM PDT 24
Peak memory 253028 kb
Host smart-2ff98ed6-17e6-459d-bc80-4918d527549b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581552440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.581552440
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.528955037
Short name T641
Test name
Test status
Simulation time 6255571572 ps
CPU time 16.35 seconds
Started Jun 25 06:57:16 PM PDT 24
Finished Jun 25 06:57:34 PM PDT 24
Peak memory 217300 kb
Host smart-42cbb843-c83e-4b1e-8710-c46d67255ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528955037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.528955037
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2022581578
Short name T313
Test name
Test status
Simulation time 785033210 ps
CPU time 4.16 seconds
Started Jun 25 06:57:14 PM PDT 24
Finished Jun 25 06:57:19 PM PDT 24
Peak memory 217000 kb
Host smart-4d86f4ab-6111-4416-ab06-b5bca9a5883b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022581578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2022581578
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.4178979151
Short name T657
Test name
Test status
Simulation time 110219712 ps
CPU time 1.57 seconds
Started Jun 25 06:57:18 PM PDT 24
Finished Jun 25 06:57:21 PM PDT 24
Peak memory 217112 kb
Host smart-7151d232-9114-458a-8a86-24efa35d06ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178979151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.4178979151
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1106367193
Short name T497
Test name
Test status
Simulation time 407675862 ps
CPU time 1.07 seconds
Started Jun 25 06:57:17 PM PDT 24
Finished Jun 25 06:57:19 PM PDT 24
Peak memory 206956 kb
Host smart-211506f8-a2d3-4314-91a1-0a4590972df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106367193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1106367193
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.912294697
Short name T898
Test name
Test status
Simulation time 276050965 ps
CPU time 4.34 seconds
Started Jun 25 06:57:18 PM PDT 24
Finished Jun 25 06:57:23 PM PDT 24
Peak memory 225400 kb
Host smart-f3062869-a5f8-4b55-8c8b-ada1e67a14d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912294697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.912294697
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2562733991
Short name T746
Test name
Test status
Simulation time 59584378 ps
CPU time 0.79 seconds
Started Jun 25 06:57:22 PM PDT 24
Finished Jun 25 06:57:24 PM PDT 24
Peak memory 206668 kb
Host smart-4259e2ac-d205-4f6c-ba05-3dc9563199e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562733991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2562733991
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.4281563945
Short name T308
Test name
Test status
Simulation time 53223241 ps
CPU time 0.81 seconds
Started Jun 25 06:57:15 PM PDT 24
Finished Jun 25 06:57:17 PM PDT 24
Peak memory 207728 kb
Host smart-b2dba151-4236-406c-8682-5edf048429c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281563945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.4281563945
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3436965496
Short name T335
Test name
Test status
Simulation time 29890473 ps
CPU time 0.78 seconds
Started Jun 25 06:57:22 PM PDT 24
Finished Jun 25 06:57:24 PM PDT 24
Peak memory 216772 kb
Host smart-c07581d8-3720-483e-b8b6-81b4b7b1be2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436965496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3436965496
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.4023449630
Short name T436
Test name
Test status
Simulation time 6205303083 ps
CPU time 19.8 seconds
Started Jun 25 06:57:22 PM PDT 24
Finished Jun 25 06:57:42 PM PDT 24
Peak memory 254092 kb
Host smart-f040655c-8e90-4663-b2be-864dc8915eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023449630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.4023449630
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3514893662
Short name T391
Test name
Test status
Simulation time 2992199375 ps
CPU time 9.66 seconds
Started Jun 25 06:57:22 PM PDT 24
Finished Jun 25 06:57:33 PM PDT 24
Peak memory 238436 kb
Host smart-8d037243-7ea0-4f04-9268-be19de814fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514893662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3514893662
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2725570989
Short name T542
Test name
Test status
Simulation time 7638799964 ps
CPU time 28.05 seconds
Started Jun 25 06:57:22 PM PDT 24
Finished Jun 25 06:57:52 PM PDT 24
Peak memory 239908 kb
Host smart-6418e940-8de3-47bc-bc49-1078beb9a6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725570989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2725570989
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1869812899
Short name T486
Test name
Test status
Simulation time 182525308 ps
CPU time 2.99 seconds
Started Jun 25 06:57:23 PM PDT 24
Finished Jun 25 06:57:27 PM PDT 24
Peak memory 233624 kb
Host smart-6b93b4f0-32a4-45db-a2ad-5b59e0873e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869812899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1869812899
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1286059982
Short name T750
Test name
Test status
Simulation time 4750898957 ps
CPU time 25.57 seconds
Started Jun 25 06:57:21 PM PDT 24
Finished Jun 25 06:57:48 PM PDT 24
Peak memory 225596 kb
Host smart-4de4be5e-bdfb-4e02-9e6b-25cf64476dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286059982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1286059982
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1361124839
Short name T852
Test name
Test status
Simulation time 5583150838 ps
CPU time 18.88 seconds
Started Jun 25 06:57:23 PM PDT 24
Finished Jun 25 06:57:43 PM PDT 24
Peak memory 241776 kb
Host smart-1ed2e963-aded-4c3b-a95d-179e728f5074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361124839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1361124839
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3104935232
Short name T815
Test name
Test status
Simulation time 10525170285 ps
CPU time 7.94 seconds
Started Jun 25 06:57:22 PM PDT 24
Finished Jun 25 06:57:30 PM PDT 24
Peak memory 225496 kb
Host smart-253ae5b4-f810-45c9-b59d-db337e83abd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104935232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3104935232
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2454668223
Short name T820
Test name
Test status
Simulation time 1397527311 ps
CPU time 15.34 seconds
Started Jun 25 06:57:22 PM PDT 24
Finished Jun 25 06:57:39 PM PDT 24
Peak memory 223576 kb
Host smart-332637ba-54b6-410c-81f2-9e303bcfedb0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2454668223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2454668223
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2124370739
Short name T109
Test name
Test status
Simulation time 29651726370 ps
CPU time 333.44 seconds
Started Jun 25 06:57:21 PM PDT 24
Finished Jun 25 07:02:55 PM PDT 24
Peak memory 252836 kb
Host smart-d5580888-62f6-4aed-a849-1c73f0a03151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124370739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2124370739
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3750680988
Short name T872
Test name
Test status
Simulation time 35345819799 ps
CPU time 42.63 seconds
Started Jun 25 06:57:21 PM PDT 24
Finished Jun 25 06:58:04 PM PDT 24
Peak memory 217464 kb
Host smart-51260762-bc67-4fef-9042-72da97ced5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750680988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3750680988
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.324254319
Short name T950
Test name
Test status
Simulation time 1229443785 ps
CPU time 2.34 seconds
Started Jun 25 06:57:15 PM PDT 24
Finished Jun 25 06:57:18 PM PDT 24
Peak memory 217076 kb
Host smart-5222b2d7-478d-4dab-9337-04f0f188158f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324254319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.324254319
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2622737808
Short name T300
Test name
Test status
Simulation time 62017851 ps
CPU time 1.36 seconds
Started Jun 25 06:57:22 PM PDT 24
Finished Jun 25 06:57:24 PM PDT 24
Peak memory 217128 kb
Host smart-3e22c49a-bb29-4d80-be34-937db00c3f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622737808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2622737808
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2033336287
Short name T949
Test name
Test status
Simulation time 28463079 ps
CPU time 0.87 seconds
Started Jun 25 06:57:23 PM PDT 24
Finished Jun 25 06:57:25 PM PDT 24
Peak memory 206700 kb
Host smart-45e7c727-dcf8-4004-b5e5-5421f6d288c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033336287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2033336287
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1717880207
Short name T204
Test name
Test status
Simulation time 5159399954 ps
CPU time 11.64 seconds
Started Jun 25 06:57:21 PM PDT 24
Finished Jun 25 06:57:33 PM PDT 24
Peak memory 225504 kb
Host smart-0d1cb096-bcce-4647-b0d1-9ddd80a3d481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717880207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1717880207
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1047982827
Short name T670
Test name
Test status
Simulation time 45984400 ps
CPU time 0.75 seconds
Started Jun 25 06:57:28 PM PDT 24
Finished Jun 25 06:57:31 PM PDT 24
Peak memory 205752 kb
Host smart-bffc2a0f-4a0a-44de-b41b-5fc51aa71cb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047982827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1047982827
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2236951685
Short name T777
Test name
Test status
Simulation time 384559270 ps
CPU time 6.68 seconds
Started Jun 25 06:57:28 PM PDT 24
Finished Jun 25 06:57:35 PM PDT 24
Peak memory 225388 kb
Host smart-e5180463-577a-47fd-9475-b30484b8ae18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236951685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2236951685
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.4058561511
Short name T636
Test name
Test status
Simulation time 37085705 ps
CPU time 0.74 seconds
Started Jun 25 06:57:22 PM PDT 24
Finished Jun 25 06:57:24 PM PDT 24
Peak memory 206732 kb
Host smart-07db3d82-b258-4958-bf18-a322dcaa1da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058561511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.4058561511
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2131488776
Short name T800
Test name
Test status
Simulation time 1852553933 ps
CPU time 17.62 seconds
Started Jun 25 06:57:30 PM PDT 24
Finished Jun 25 06:57:49 PM PDT 24
Peak memory 241780 kb
Host smart-e72cbc60-d812-4c7b-8445-cf379f12522e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131488776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2131488776
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1338453421
Short name T358
Test name
Test status
Simulation time 2527273034 ps
CPU time 4.48 seconds
Started Jun 25 06:57:29 PM PDT 24
Finished Jun 25 06:57:34 PM PDT 24
Peak memory 224056 kb
Host smart-1d2bda1e-c3c8-4b2d-b548-1834d7e57448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338453421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1338453421
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1368366659
Short name T532
Test name
Test status
Simulation time 18327569745 ps
CPU time 112.8 seconds
Started Jun 25 06:57:27 PM PDT 24
Finished Jun 25 06:59:20 PM PDT 24
Peak memory 252196 kb
Host smart-4c93dce5-ae84-4a23-a0d5-4ff76921fde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368366659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1368366659
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.859222120
Short name T817
Test name
Test status
Simulation time 5343670377 ps
CPU time 13.29 seconds
Started Jun 25 06:57:30 PM PDT 24
Finished Jun 25 06:57:44 PM PDT 24
Peak memory 241948 kb
Host smart-f80e9958-c21d-42d9-be59-e3a7b0d8ef41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859222120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.859222120
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3730860700
Short name T304
Test name
Test status
Simulation time 187568507 ps
CPU time 2.51 seconds
Started Jun 25 06:57:28 PM PDT 24
Finished Jun 25 06:57:31 PM PDT 24
Peak memory 233312 kb
Host smart-e5e1b104-dbc8-4747-9a1d-28770e297661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730860700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3730860700
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2688845048
Short name T696
Test name
Test status
Simulation time 321623441 ps
CPU time 2.53 seconds
Started Jun 25 06:57:30 PM PDT 24
Finished Jun 25 06:57:34 PM PDT 24
Peak memory 224900 kb
Host smart-add18f46-ee41-4d22-8b4e-8e8a0195353c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688845048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2688845048
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.214106600
Short name T723
Test name
Test status
Simulation time 1341187376 ps
CPU time 9.69 seconds
Started Jun 25 06:57:29 PM PDT 24
Finished Jun 25 06:57:40 PM PDT 24
Peak memory 225360 kb
Host smart-9c57ca3d-acbe-4fab-81b0-8ae723711cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214106600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.214106600
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3874347266
Short name T952
Test name
Test status
Simulation time 3896223829 ps
CPU time 14.14 seconds
Started Jun 25 06:57:28 PM PDT 24
Finished Jun 25 06:57:43 PM PDT 24
Peak memory 225648 kb
Host smart-23d1a331-e3f6-4a36-9dcb-5783196faca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874347266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3874347266
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.711741475
Short name T378
Test name
Test status
Simulation time 6839039231 ps
CPU time 12.88 seconds
Started Jun 25 06:57:28 PM PDT 24
Finished Jun 25 06:57:42 PM PDT 24
Peak memory 221552 kb
Host smart-641fea5f-3dd4-4462-9f1f-0e8ad0c1bcf2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=711741475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.711741475
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1475172027
Short name T131
Test name
Test status
Simulation time 79062523 ps
CPU time 0.97 seconds
Started Jun 25 06:57:28 PM PDT 24
Finished Jun 25 06:57:31 PM PDT 24
Peak memory 207540 kb
Host smart-4ccd4584-1db7-4ee5-8bed-499e73a05252
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475172027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1475172027
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1662882183
Short name T377
Test name
Test status
Simulation time 1926642898 ps
CPU time 15.97 seconds
Started Jun 25 06:57:29 PM PDT 24
Finished Jun 25 06:57:46 PM PDT 24
Peak memory 217168 kb
Host smart-57b0fc9d-6827-4d13-b8a8-2265b8294629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662882183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1662882183
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.4142021542
Short name T591
Test name
Test status
Simulation time 390751739 ps
CPU time 1.78 seconds
Started Jun 25 06:57:28 PM PDT 24
Finished Jun 25 06:57:30 PM PDT 24
Peak memory 208676 kb
Host smart-e75b7759-64a4-43fd-9783-3334ef8d95ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142021542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.4142021542
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3026487114
Short name T548
Test name
Test status
Simulation time 256770116 ps
CPU time 2.41 seconds
Started Jun 25 06:57:27 PM PDT 24
Finished Jun 25 06:57:31 PM PDT 24
Peak memory 217112 kb
Host smart-d13f5ba8-0161-451a-ace2-40130d960b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026487114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3026487114
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2014872132
Short name T341
Test name
Test status
Simulation time 260333846 ps
CPU time 0.89 seconds
Started Jun 25 06:57:29 PM PDT 24
Finished Jun 25 06:57:31 PM PDT 24
Peak memory 206736 kb
Host smart-de451f73-2096-49d6-8588-403b41e9cbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014872132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2014872132
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2591759993
Short name T834
Test name
Test status
Simulation time 323782943 ps
CPU time 3.08 seconds
Started Jun 25 06:57:29 PM PDT 24
Finished Jun 25 06:57:33 PM PDT 24
Peak memory 225444 kb
Host smart-1bedcac8-166e-42d0-b208-9c93bce4cffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591759993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2591759993
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2062361809
Short name T650
Test name
Test status
Simulation time 12127212 ps
CPU time 0.71 seconds
Started Jun 25 06:57:38 PM PDT 24
Finished Jun 25 06:57:39 PM PDT 24
Peak memory 206312 kb
Host smart-b5cbf83c-9569-4d7a-afd5-a2162eb99988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062361809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2062361809
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.484328055
Short name T8
Test name
Test status
Simulation time 112004058 ps
CPU time 2.58 seconds
Started Jun 25 06:57:36 PM PDT 24
Finished Jun 25 06:57:39 PM PDT 24
Peak memory 233632 kb
Host smart-084105bc-357e-4479-ba6d-9cd09987a2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484328055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.484328055
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2783845675
Short name T511
Test name
Test status
Simulation time 13887364 ps
CPU time 0.79 seconds
Started Jun 25 06:57:37 PM PDT 24
Finished Jun 25 06:57:39 PM PDT 24
Peak memory 206376 kb
Host smart-3bed49ca-b3d3-4250-8492-d0a2babd0a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783845675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2783845675
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3643774166
Short name T193
Test name
Test status
Simulation time 73612662670 ps
CPU time 94.36 seconds
Started Jun 25 06:57:35 PM PDT 24
Finished Jun 25 06:59:10 PM PDT 24
Peak memory 239852 kb
Host smart-4865eb38-a4dd-451b-a3a7-3a450bb889bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643774166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3643774166
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2286758203
Short name T424
Test name
Test status
Simulation time 13069786561 ps
CPU time 106.8 seconds
Started Jun 25 06:57:36 PM PDT 24
Finished Jun 25 06:59:24 PM PDT 24
Peak memory 241940 kb
Host smart-5039ef6f-0ca2-43bd-999f-374b4660b58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286758203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2286758203
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3379496188
Short name T516
Test name
Test status
Simulation time 2148837588 ps
CPU time 13.34 seconds
Started Jun 25 06:57:36 PM PDT 24
Finished Jun 25 06:57:51 PM PDT 24
Peak memory 241936 kb
Host smart-0b597b3e-8595-47b0-a6bc-003d8e2df1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379496188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3379496188
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.69464354
Short name T76
Test name
Test status
Simulation time 171702152 ps
CPU time 4.47 seconds
Started Jun 25 06:57:34 PM PDT 24
Finished Jun 25 06:57:40 PM PDT 24
Peak memory 233592 kb
Host smart-54c3a507-3017-4ecd-805c-8b64086d2f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69464354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.69464354
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.480961316
Short name T489
Test name
Test status
Simulation time 6693500559 ps
CPU time 57.82 seconds
Started Jun 25 06:57:37 PM PDT 24
Finished Jun 25 06:58:36 PM PDT 24
Peak memory 241576 kb
Host smart-c3460f50-b237-4c7e-8427-bb902c24afe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480961316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.480961316
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1759508803
Short name T180
Test name
Test status
Simulation time 543400369 ps
CPU time 8.73 seconds
Started Jun 25 06:57:35 PM PDT 24
Finished Jun 25 06:57:45 PM PDT 24
Peak memory 240056 kb
Host smart-022d89c3-49ce-4610-bec5-00ba607d7487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759508803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1759508803
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.890640347
Short name T75
Test name
Test status
Simulation time 759727986 ps
CPU time 4.27 seconds
Started Jun 25 06:57:38 PM PDT 24
Finished Jun 25 06:57:43 PM PDT 24
Peak memory 219640 kb
Host smart-e58d5db7-a1da-41ec-bddf-c8ae12b26d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890640347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.890640347
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3906300559
Short name T929
Test name
Test status
Simulation time 721329593 ps
CPU time 8.15 seconds
Started Jun 25 06:57:37 PM PDT 24
Finished Jun 25 06:57:46 PM PDT 24
Peak memory 223240 kb
Host smart-df7b904b-5042-40c1-afcf-c786a5bd482a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3906300559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3906300559
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3205578183
Short name T617
Test name
Test status
Simulation time 53159307081 ps
CPU time 73.29 seconds
Started Jun 25 06:57:35 PM PDT 24
Finished Jun 25 06:58:50 PM PDT 24
Peak memory 250228 kb
Host smart-0956ba71-11f0-4592-b15e-c69765c45acb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205578183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3205578183
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1790451496
Short name T752
Test name
Test status
Simulation time 27300047915 ps
CPU time 26.91 seconds
Started Jun 25 06:57:36 PM PDT 24
Finished Jun 25 06:58:04 PM PDT 24
Peak memory 217176 kb
Host smart-b634c79e-1f41-4216-9d75-53e1e4b77c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790451496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1790451496
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.792426288
Short name T476
Test name
Test status
Simulation time 807109281 ps
CPU time 2.91 seconds
Started Jun 25 06:57:37 PM PDT 24
Finished Jun 25 06:57:41 PM PDT 24
Peak memory 217116 kb
Host smart-57965397-0ae8-4dc2-b452-bc71cf8b34e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792426288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.792426288
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1803185583
Short name T792
Test name
Test status
Simulation time 187858358 ps
CPU time 2.12 seconds
Started Jun 25 06:57:35 PM PDT 24
Finished Jun 25 06:57:38 PM PDT 24
Peak memory 208880 kb
Host smart-49a6f012-a8f6-484c-bf9e-77baddec8c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803185583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1803185583
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.497707641
Short name T450
Test name
Test status
Simulation time 47827534 ps
CPU time 0.84 seconds
Started Jun 25 06:57:35 PM PDT 24
Finished Jun 25 06:57:37 PM PDT 24
Peak memory 206728 kb
Host smart-510cd845-242d-4c25-b2d7-ae73b414a4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497707641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.497707641
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1187323927
Short name T159
Test name
Test status
Simulation time 24466455304 ps
CPU time 19.93 seconds
Started Jun 25 06:57:35 PM PDT 24
Finished Jun 25 06:57:56 PM PDT 24
Peak memory 233724 kb
Host smart-97147461-de04-4274-8a41-d170dbe319dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187323927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1187323927
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.4101260331
Short name T618
Test name
Test status
Simulation time 38865679 ps
CPU time 0.72 seconds
Started Jun 25 06:57:47 PM PDT 24
Finished Jun 25 06:57:49 PM PDT 24
Peak memory 206324 kb
Host smart-fdbe0bae-9eba-4db6-8406-d9ab92735f8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101260331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
4101260331
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3503250609
Short name T570
Test name
Test status
Simulation time 698589301 ps
CPU time 6.92 seconds
Started Jun 25 06:57:43 PM PDT 24
Finished Jun 25 06:57:51 PM PDT 24
Peak memory 233548 kb
Host smart-3891bac9-1b61-41d3-a63e-1f2908cf4fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503250609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3503250609
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2880365543
Short name T831
Test name
Test status
Simulation time 17454596 ps
CPU time 0.81 seconds
Started Jun 25 06:57:37 PM PDT 24
Finished Jun 25 06:57:39 PM PDT 24
Peak memory 207508 kb
Host smart-d66fb94b-a2d7-4dbb-b523-d31b9de4d53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880365543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2880365543
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1761705169
Short name T914
Test name
Test status
Simulation time 26947495203 ps
CPU time 52.53 seconds
Started Jun 25 06:57:41 PM PDT 24
Finished Jun 25 06:58:35 PM PDT 24
Peak memory 255628 kb
Host smart-f0dcfe99-4442-45d8-a412-6c1748518faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761705169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1761705169
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3013199746
Short name T553
Test name
Test status
Simulation time 4079179904 ps
CPU time 40.66 seconds
Started Jun 25 06:57:41 PM PDT 24
Finished Jun 25 06:58:23 PM PDT 24
Peak memory 225580 kb
Host smart-af30d20a-aec0-4f9d-84f0-abf08c004aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013199746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3013199746
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1263332135
Short name T767
Test name
Test status
Simulation time 4646989233 ps
CPU time 14.18 seconds
Started Jun 25 06:57:42 PM PDT 24
Finished Jun 25 06:57:57 PM PDT 24
Peak memory 220576 kb
Host smart-27b07f26-dfc5-488f-ae2e-092285ee9be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263332135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1263332135
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3225982286
Short name T693
Test name
Test status
Simulation time 2203379132 ps
CPU time 35.39 seconds
Started Jun 25 06:57:43 PM PDT 24
Finished Jun 25 06:58:19 PM PDT 24
Peak memory 233760 kb
Host smart-dc6fb49b-9684-4b13-aa36-92f8b5cdb5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225982286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3225982286
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3601275201
Short name T645
Test name
Test status
Simulation time 923503688 ps
CPU time 5 seconds
Started Jun 25 06:57:44 PM PDT 24
Finished Jun 25 06:57:50 PM PDT 24
Peak memory 233620 kb
Host smart-eb7da31a-526a-46b4-855c-7bd108559596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601275201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3601275201
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.672363391
Short name T163
Test name
Test status
Simulation time 28742518223 ps
CPU time 59.82 seconds
Started Jun 25 06:57:43 PM PDT 24
Finished Jun 25 06:58:44 PM PDT 24
Peak memory 233748 kb
Host smart-68fcbbd2-b487-441e-9ef7-6ccd1c93bfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672363391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.672363391
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.101296329
Short name T255
Test name
Test status
Simulation time 36176238662 ps
CPU time 13.53 seconds
Started Jun 25 06:57:44 PM PDT 24
Finished Jun 25 06:57:58 PM PDT 24
Peak memory 250024 kb
Host smart-88c5ac5e-bc28-4405-bd96-fe27595ebf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101296329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.101296329
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.759985270
Short name T902
Test name
Test status
Simulation time 1366979848 ps
CPU time 12.96 seconds
Started Jun 25 06:57:43 PM PDT 24
Finished Jun 25 06:57:57 PM PDT 24
Peak memory 240428 kb
Host smart-e13d76ec-1a82-423b-abc9-d1ab5e141b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759985270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.759985270
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.977433198
Short name T372
Test name
Test status
Simulation time 181046363 ps
CPU time 4.15 seconds
Started Jun 25 06:57:49 PM PDT 24
Finished Jun 25 06:57:56 PM PDT 24
Peak memory 224064 kb
Host smart-20b2bfe9-c4b9-45e2-9502-ba8880277490
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=977433198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.977433198
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.860799197
Short name T133
Test name
Test status
Simulation time 70662725633 ps
CPU time 255.28 seconds
Started Jun 25 06:57:42 PM PDT 24
Finished Jun 25 07:01:59 PM PDT 24
Peak memory 258100 kb
Host smart-a5174a6a-f491-4181-8b3a-77e3acb6d6ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860799197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.860799197
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.972067207
Short name T631
Test name
Test status
Simulation time 2483784948 ps
CPU time 7.81 seconds
Started Jun 25 06:57:35 PM PDT 24
Finished Jun 25 06:57:44 PM PDT 24
Peak memory 217376 kb
Host smart-af314440-a858-437a-a74a-570f5c33b23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972067207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.972067207
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2044177595
Short name T461
Test name
Test status
Simulation time 25908379680 ps
CPU time 15.07 seconds
Started Jun 25 06:57:36 PM PDT 24
Finished Jun 25 06:57:53 PM PDT 24
Peak memory 217332 kb
Host smart-5676fba3-73cc-4553-bd61-840e335d151a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044177595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2044177595
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.259458694
Short name T493
Test name
Test status
Simulation time 58450944 ps
CPU time 1.07 seconds
Started Jun 25 06:57:37 PM PDT 24
Finished Jun 25 06:57:39 PM PDT 24
Peak memory 208708 kb
Host smart-0de60dbe-55eb-4436-8fb1-a7627ee220fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259458694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.259458694
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.199186914
Short name T652
Test name
Test status
Simulation time 58031870 ps
CPU time 0.82 seconds
Started Jun 25 06:57:35 PM PDT 24
Finished Jun 25 06:57:37 PM PDT 24
Peak memory 206660 kb
Host smart-61968d28-4d22-4b43-810f-c3bf03065ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199186914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.199186914
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1279534485
Short name T409
Test name
Test status
Simulation time 1279150493 ps
CPU time 5.56 seconds
Started Jun 25 06:57:41 PM PDT 24
Finished Jun 25 06:57:48 PM PDT 24
Peak memory 225392 kb
Host smart-e2bf3494-8f9a-401f-b9bb-c13305f9cd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279534485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1279534485
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2425898388
Short name T323
Test name
Test status
Simulation time 21097793 ps
CPU time 0.74 seconds
Started Jun 25 06:57:49 PM PDT 24
Finished Jun 25 06:57:52 PM PDT 24
Peak memory 206320 kb
Host smart-3e9fea45-dd89-41f6-86c9-aa9b56a7efb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425898388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2425898388
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1681691246
Short name T560
Test name
Test status
Simulation time 163494222 ps
CPU time 2.95 seconds
Started Jun 25 06:57:42 PM PDT 24
Finished Jun 25 06:57:46 PM PDT 24
Peak memory 225404 kb
Host smart-e1ebb2a9-21cb-48a0-9e06-b5467228b377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681691246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1681691246
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3728897742
Short name T376
Test name
Test status
Simulation time 28681124 ps
CPU time 0.76 seconds
Started Jun 25 06:57:42 PM PDT 24
Finished Jun 25 06:57:44 PM PDT 24
Peak memory 207408 kb
Host smart-0cdfc7fe-f39a-492e-ab7c-0809d9d1e763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728897742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3728897742
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3099671800
Short name T629
Test name
Test status
Simulation time 7659462456 ps
CPU time 27.79 seconds
Started Jun 25 06:57:49 PM PDT 24
Finished Jun 25 06:58:19 PM PDT 24
Peak memory 250608 kb
Host smart-811f5757-daf4-4a5c-a770-6ada7d65468a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099671800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3099671800
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2063032213
Short name T175
Test name
Test status
Simulation time 25516066889 ps
CPU time 121.3 seconds
Started Jun 25 06:57:53 PM PDT 24
Finished Jun 25 06:59:56 PM PDT 24
Peak memory 266280 kb
Host smart-131bdaef-919c-49f3-8d02-655bce0495a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063032213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2063032213
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2221318776
Short name T35
Test name
Test status
Simulation time 19227529760 ps
CPU time 84.24 seconds
Started Jun 25 06:57:54 PM PDT 24
Finished Jun 25 06:59:20 PM PDT 24
Peak memory 257192 kb
Host smart-bd7ed9c0-e02b-4e1a-a430-04c57bdb7afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221318776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2221318776
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1581756350
Short name T475
Test name
Test status
Simulation time 66205784 ps
CPU time 2.77 seconds
Started Jun 25 06:57:45 PM PDT 24
Finished Jun 25 06:57:48 PM PDT 24
Peak memory 225324 kb
Host smart-fec6d524-142e-4b26-b5d1-bc57462cc372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581756350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1581756350
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1118191108
Short name T518
Test name
Test status
Simulation time 5466125057 ps
CPU time 10.98 seconds
Started Jun 25 06:57:44 PM PDT 24
Finished Jun 25 06:57:56 PM PDT 24
Peak memory 233736 kb
Host smart-8dba7f1e-b6c4-48a1-923c-f01bc29f3152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118191108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1118191108
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.4293223434
Short name T613
Test name
Test status
Simulation time 1569243018 ps
CPU time 8.81 seconds
Started Jun 25 06:57:42 PM PDT 24
Finished Jun 25 06:57:52 PM PDT 24
Peak memory 225416 kb
Host smart-c9a9c838-ce28-40b0-8540-83a07d7f49aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293223434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.4293223434
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.877281824
Short name T453
Test name
Test status
Simulation time 859998922 ps
CPU time 6.3 seconds
Started Jun 25 06:57:47 PM PDT 24
Finished Jun 25 06:57:54 PM PDT 24
Peak memory 225464 kb
Host smart-11a07d1b-3c57-4e48-88bb-bd3483d16f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877281824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.877281824
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3828680968
Short name T727
Test name
Test status
Simulation time 22890096976 ps
CPU time 14.62 seconds
Started Jun 25 06:57:44 PM PDT 24
Finished Jun 25 06:57:59 PM PDT 24
Peak memory 240148 kb
Host smart-391ce861-c748-427e-b4f3-1d82db225150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828680968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3828680968
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1221496186
Short name T779
Test name
Test status
Simulation time 363991359 ps
CPU time 4.16 seconds
Started Jun 25 06:57:47 PM PDT 24
Finished Jun 25 06:57:52 PM PDT 24
Peak memory 221312 kb
Host smart-3387b9ac-4cf6-4ff8-89e4-fd3dfc89542f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1221496186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1221496186
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3576034811
Short name T399
Test name
Test status
Simulation time 81265031 ps
CPU time 1.07 seconds
Started Jun 25 06:57:49 PM PDT 24
Finished Jun 25 06:57:53 PM PDT 24
Peak memory 207880 kb
Host smart-44e6f71f-9e7f-4718-bca2-387ec8267d40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576034811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3576034811
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1250713675
Short name T298
Test name
Test status
Simulation time 67721370511 ps
CPU time 31.17 seconds
Started Jun 25 06:57:42 PM PDT 24
Finished Jun 25 06:58:14 PM PDT 24
Peak memory 217180 kb
Host smart-15c9f8dd-3dae-4835-8ab7-710b42bf29e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250713675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1250713675
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2591908984
Short name T860
Test name
Test status
Simulation time 5793284560 ps
CPU time 17.15 seconds
Started Jun 25 06:57:41 PM PDT 24
Finished Jun 25 06:57:59 PM PDT 24
Peak memory 217108 kb
Host smart-7c10b725-326f-4ed8-bf19-b0ed90e20529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591908984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2591908984
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3878898434
Short name T478
Test name
Test status
Simulation time 34090084 ps
CPU time 0.71 seconds
Started Jun 25 06:57:40 PM PDT 24
Finished Jun 25 06:57:41 PM PDT 24
Peak memory 206480 kb
Host smart-30614174-6cfd-451b-8285-3a1cdab9c905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878898434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3878898434
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2072791680
Short name T698
Test name
Test status
Simulation time 17569004 ps
CPU time 0.72 seconds
Started Jun 25 06:57:45 PM PDT 24
Finished Jun 25 06:57:46 PM PDT 24
Peak memory 206704 kb
Host smart-c5b396cb-8d61-4cbd-a5ce-249cc4507782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072791680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2072791680
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.668156400
Short name T209
Test name
Test status
Simulation time 1238417153 ps
CPU time 4.9 seconds
Started Jun 25 06:57:41 PM PDT 24
Finished Jun 25 06:57:47 PM PDT 24
Peak memory 233584 kb
Host smart-05f8d0cf-2b16-45ac-9479-c0a0284892d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668156400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.668156400
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3991748734
Short name T509
Test name
Test status
Simulation time 20926219 ps
CPU time 0.74 seconds
Started Jun 25 06:57:54 PM PDT 24
Finished Jun 25 06:57:56 PM PDT 24
Peak memory 205748 kb
Host smart-20a88d43-bf74-4e4f-8ee5-8b167faf0241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991748734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3991748734
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.962079511
Short name T225
Test name
Test status
Simulation time 311947807 ps
CPU time 4.01 seconds
Started Jun 25 06:57:53 PM PDT 24
Finished Jun 25 06:57:58 PM PDT 24
Peak memory 233632 kb
Host smart-7cfd711b-4a13-4b45-b056-78d670ebcef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962079511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.962079511
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2022778774
Short name T857
Test name
Test status
Simulation time 61818578 ps
CPU time 0.8 seconds
Started Jun 25 06:57:50 PM PDT 24
Finished Jun 25 06:57:53 PM PDT 24
Peak memory 207404 kb
Host smart-dbce34bc-5676-4c61-8127-9b4a4b432832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022778774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2022778774
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.228160771
Short name T442
Test name
Test status
Simulation time 86320278768 ps
CPU time 191.62 seconds
Started Jun 25 06:57:49 PM PDT 24
Finished Jun 25 07:01:02 PM PDT 24
Peak memory 250072 kb
Host smart-ae813282-d218-4ecb-9ff2-e93f82a3205d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228160771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.228160771
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3965462976
Short name T197
Test name
Test status
Simulation time 162556918999 ps
CPU time 321.93 seconds
Started Jun 25 06:57:54 PM PDT 24
Finished Jun 25 07:03:18 PM PDT 24
Peak memory 258108 kb
Host smart-2253ecc4-3a2a-4c3d-bee3-de183df3f31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965462976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3965462976
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3513540904
Short name T742
Test name
Test status
Simulation time 3305036024 ps
CPU time 8.18 seconds
Started Jun 25 06:57:54 PM PDT 24
Finished Jun 25 06:58:03 PM PDT 24
Peak memory 237924 kb
Host smart-31220479-35d9-45c7-91c2-121c4e5332a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513540904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3513540904
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2840655026
Short name T678
Test name
Test status
Simulation time 1268921527 ps
CPU time 5.61 seconds
Started Jun 25 06:57:48 PM PDT 24
Finished Jun 25 06:57:55 PM PDT 24
Peak memory 233628 kb
Host smart-9193e4e7-8aa3-450b-b441-e34a3d5f34c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840655026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2840655026
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3842165190
Short name T220
Test name
Test status
Simulation time 8658984592 ps
CPU time 31.25 seconds
Started Jun 25 06:57:48 PM PDT 24
Finished Jun 25 06:58:21 PM PDT 24
Peak memory 233692 kb
Host smart-1a81bcfe-04e0-4db8-9cfa-f2ad9f28fdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842165190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3842165190
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3704805688
Short name T177
Test name
Test status
Simulation time 8983705271 ps
CPU time 15.49 seconds
Started Jun 25 06:57:54 PM PDT 24
Finished Jun 25 06:58:11 PM PDT 24
Peak memory 233744 kb
Host smart-9b12aef7-0ff9-4235-869a-15666cf49623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704805688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3704805688
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3634240634
Short name T784
Test name
Test status
Simulation time 28551502 ps
CPU time 2.19 seconds
Started Jun 25 06:57:48 PM PDT 24
Finished Jun 25 06:57:52 PM PDT 24
Peak memory 223708 kb
Host smart-55dad7c9-a5f1-4244-8e1f-6c9f88dd1484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634240634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3634240634
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3018231276
Short name T863
Test name
Test status
Simulation time 251503589 ps
CPU time 4.26 seconds
Started Jun 25 06:57:54 PM PDT 24
Finished Jun 25 06:57:59 PM PDT 24
Peak memory 223496 kb
Host smart-669aea58-eb13-47f2-9737-7773a8346b08
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3018231276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3018231276
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2691344053
Short name T283
Test name
Test status
Simulation time 104769200839 ps
CPU time 284.11 seconds
Started Jun 25 06:57:54 PM PDT 24
Finished Jun 25 07:02:40 PM PDT 24
Peak memory 266080 kb
Host smart-5605d6cc-fc4b-4ff7-a950-332eb67fb134
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691344053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2691344053
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2009819951
Short name T22
Test name
Test status
Simulation time 6745366844 ps
CPU time 29.2 seconds
Started Jun 25 06:57:49 PM PDT 24
Finished Jun 25 06:58:19 PM PDT 24
Peak memory 217200 kb
Host smart-e57e594a-e9c9-4f17-b3c8-ddb6d272e889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009819951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2009819951
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2905477594
Short name T869
Test name
Test status
Simulation time 1391400001 ps
CPU time 4.73 seconds
Started Jun 25 06:57:51 PM PDT 24
Finished Jun 25 06:57:57 PM PDT 24
Peak memory 217072 kb
Host smart-61d5fdbe-f206-423b-83f0-bb86dd303f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905477594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2905477594
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1043229806
Short name T858
Test name
Test status
Simulation time 850963235 ps
CPU time 2.51 seconds
Started Jun 25 06:57:50 PM PDT 24
Finished Jun 25 06:57:54 PM PDT 24
Peak memory 217116 kb
Host smart-aedc6727-44e2-4725-a2e0-f13d1cefb7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043229806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1043229806
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1658228795
Short name T780
Test name
Test status
Simulation time 87741426 ps
CPU time 0.95 seconds
Started Jun 25 06:57:51 PM PDT 24
Finished Jun 25 06:57:53 PM PDT 24
Peak memory 206708 kb
Host smart-79630b67-6dbc-45bd-a3bf-13025717d6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658228795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1658228795
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.4251197492
Short name T215
Test name
Test status
Simulation time 18116072918 ps
CPU time 13.57 seconds
Started Jun 25 06:57:49 PM PDT 24
Finished Jun 25 06:58:05 PM PDT 24
Peak memory 225480 kb
Host smart-a32d4722-1aad-49d1-aa75-164cfc14557d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251197492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.4251197492
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2179557965
Short name T947
Test name
Test status
Simulation time 49454159 ps
CPU time 0.73 seconds
Started Jun 25 06:58:04 PM PDT 24
Finished Jun 25 06:58:06 PM PDT 24
Peak memory 205748 kb
Host smart-ea77d055-878d-4928-ae16-3eb3b10af380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179557965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2179557965
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1070008475
Short name T379
Test name
Test status
Simulation time 2413541032 ps
CPU time 17.52 seconds
Started Jun 25 06:57:56 PM PDT 24
Finished Jun 25 06:58:15 PM PDT 24
Peak memory 233756 kb
Host smart-bbf8d60a-06fa-4a61-a817-7e52003cf357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070008475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1070008475
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2460731387
Short name T951
Test name
Test status
Simulation time 43346698 ps
CPU time 0.81 seconds
Started Jun 25 06:57:54 PM PDT 24
Finished Jun 25 06:57:56 PM PDT 24
Peak memory 207424 kb
Host smart-9b1d89ff-c64c-4207-8bf8-0ffda1ec9bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460731387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2460731387
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.50152094
Short name T144
Test name
Test status
Simulation time 58576865329 ps
CPU time 178.28 seconds
Started Jun 25 06:57:53 PM PDT 24
Finished Jun 25 07:00:52 PM PDT 24
Peak memory 256348 kb
Host smart-0ac2405e-cd37-4281-918c-36d2e4b6618c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50152094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.50152094
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3194441260
Short name T927
Test name
Test status
Simulation time 100663978304 ps
CPU time 234.02 seconds
Started Jun 25 06:58:03 PM PDT 24
Finished Jun 25 07:01:59 PM PDT 24
Peak memory 251180 kb
Host smart-c89abcde-3ce4-4be6-8446-967e4b8762ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194441260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3194441260
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2381505048
Short name T601
Test name
Test status
Simulation time 6711228857 ps
CPU time 27.88 seconds
Started Jun 25 06:57:55 PM PDT 24
Finished Jun 25 06:58:25 PM PDT 24
Peak memory 241776 kb
Host smart-648383cc-a66e-4af7-b9c3-acdace824622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381505048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2381505048
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3975845164
Short name T244
Test name
Test status
Simulation time 409906835 ps
CPU time 5.71 seconds
Started Jun 25 06:57:55 PM PDT 24
Finished Jun 25 06:58:02 PM PDT 24
Peak memory 225388 kb
Host smart-7699af42-d6f2-4629-b507-3feb8ae16599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975845164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3975845164
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2923047724
Short name T897
Test name
Test status
Simulation time 429371332 ps
CPU time 2.51 seconds
Started Jun 25 06:57:54 PM PDT 24
Finished Jun 25 06:57:58 PM PDT 24
Peak memory 225336 kb
Host smart-ca108da0-265d-4ed7-bfef-26b3582fa4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923047724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2923047724
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2412221939
Short name T517
Test name
Test status
Simulation time 300090538 ps
CPU time 3.12 seconds
Started Jun 25 06:57:55 PM PDT 24
Finished Jun 25 06:58:00 PM PDT 24
Peak memory 233584 kb
Host smart-2becd422-1512-4769-94dc-3bfe767c32bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412221939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2412221939
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3924721607
Short name T799
Test name
Test status
Simulation time 1316078390 ps
CPU time 3.28 seconds
Started Jun 25 06:57:56 PM PDT 24
Finished Jun 25 06:58:01 PM PDT 24
Peak memory 225276 kb
Host smart-57e50a86-146f-4d4c-9c50-6d2a6bb7cfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924721607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3924721607
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1537151188
Short name T842
Test name
Test status
Simulation time 143355446 ps
CPU time 4.11 seconds
Started Jun 25 06:57:53 PM PDT 24
Finished Jun 25 06:57:58 PM PDT 24
Peak memory 219688 kb
Host smart-8b1414b7-552c-4b23-a5dc-dc9eca39bc7e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1537151188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1537151188
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1142604422
Short name T853
Test name
Test status
Simulation time 200242003 ps
CPU time 1.12 seconds
Started Jun 25 06:58:02 PM PDT 24
Finished Jun 25 06:58:04 PM PDT 24
Peak memory 216112 kb
Host smart-379de625-d91f-4959-b33c-c1e42e060293
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142604422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1142604422
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2150114213
Short name T512
Test name
Test status
Simulation time 47980385773 ps
CPU time 24.28 seconds
Started Jun 25 06:57:58 PM PDT 24
Finished Jun 25 06:58:23 PM PDT 24
Peak memory 217208 kb
Host smart-8db6a3de-5553-4cd2-9234-3f0a42178d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150114213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2150114213
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1229683270
Short name T400
Test name
Test status
Simulation time 13379751523 ps
CPU time 12.96 seconds
Started Jun 25 06:57:57 PM PDT 24
Finished Jun 25 06:58:11 PM PDT 24
Peak memory 217216 kb
Host smart-54ca4d87-4ec8-4d7b-bdcd-b35efaec8578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229683270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1229683270
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.915167290
Short name T473
Test name
Test status
Simulation time 23416505 ps
CPU time 0.85 seconds
Started Jun 25 06:57:52 PM PDT 24
Finished Jun 25 06:57:54 PM PDT 24
Peak memory 208664 kb
Host smart-e0e0e944-6f01-4a3b-8439-954e096f7083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915167290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.915167290
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2243367900
Short name T533
Test name
Test status
Simulation time 10740661 ps
CPU time 0.71 seconds
Started Jun 25 06:57:53 PM PDT 24
Finished Jun 25 06:57:55 PM PDT 24
Peak memory 206436 kb
Host smart-857699d5-b3a4-49eb-9be5-ad8fbb6d9444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243367900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2243367900
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1908087356
Short name T158
Test name
Test status
Simulation time 1832035663 ps
CPU time 3.07 seconds
Started Jun 25 06:57:58 PM PDT 24
Finished Jun 25 06:58:02 PM PDT 24
Peak memory 225384 kb
Host smart-bc685ba2-5bc7-42eb-b762-501d33cd2dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908087356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1908087356
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2766931737
Short name T710
Test name
Test status
Simulation time 19623979 ps
CPU time 0.78 seconds
Started Jun 25 06:58:09 PM PDT 24
Finished Jun 25 06:58:10 PM PDT 24
Peak memory 205792 kb
Host smart-a439874d-bd9b-47c4-aa00-78a7af5e72e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766931737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2766931737
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2628799598
Short name T237
Test name
Test status
Simulation time 2610745495 ps
CPU time 4.13 seconds
Started Jun 25 06:58:03 PM PDT 24
Finished Jun 25 06:58:09 PM PDT 24
Peak memory 225496 kb
Host smart-bc303e04-43dd-462c-a510-81ee8a13e06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628799598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2628799598
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2452648976
Short name T849
Test name
Test status
Simulation time 31167770 ps
CPU time 0.81 seconds
Started Jun 25 06:58:03 PM PDT 24
Finished Jun 25 06:58:05 PM PDT 24
Peak memory 207436 kb
Host smart-5098da77-b90e-4251-98b3-da651751d0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452648976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2452648976
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1006306568
Short name T1
Test name
Test status
Simulation time 114656317874 ps
CPU time 197.19 seconds
Started Jun 25 06:58:02 PM PDT 24
Finished Jun 25 07:01:20 PM PDT 24
Peak memory 241940 kb
Host smart-f7537794-74b5-42c6-8d42-eed1dce9e224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006306568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1006306568
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2945065822
Short name T624
Test name
Test status
Simulation time 10833858867 ps
CPU time 134.59 seconds
Started Jun 25 06:58:10 PM PDT 24
Finished Jun 25 07:00:26 PM PDT 24
Peak memory 252356 kb
Host smart-cc4c882b-4557-4c0f-9ea2-df6e48289bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945065822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2945065822
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2703817786
Short name T706
Test name
Test status
Simulation time 94727775 ps
CPU time 2.64 seconds
Started Jun 25 06:58:04 PM PDT 24
Finished Jun 25 06:58:08 PM PDT 24
Peak memory 225420 kb
Host smart-068453db-8f90-4a4e-982d-315d7eb2b0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703817786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2703817786
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3850555883
Short name T160
Test name
Test status
Simulation time 5305953186 ps
CPU time 12.54 seconds
Started Jun 25 06:58:04 PM PDT 24
Finished Jun 25 06:58:18 PM PDT 24
Peak memory 233748 kb
Host smart-5fc20cc1-7a49-438e-89b0-9c993dd2c194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850555883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3850555883
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.528807411
Short name T514
Test name
Test status
Simulation time 499987345 ps
CPU time 9.19 seconds
Started Jun 25 06:58:11 PM PDT 24
Finished Jun 25 06:58:21 PM PDT 24
Peak memory 241048 kb
Host smart-0d08d426-1410-44ea-8756-c14c35dacb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528807411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.528807411
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1741070156
Short name T248
Test name
Test status
Simulation time 59921478574 ps
CPU time 16.86 seconds
Started Jun 25 06:58:04 PM PDT 24
Finished Jun 25 06:58:22 PM PDT 24
Peak memory 225556 kb
Host smart-eb12cbf5-bf03-47ca-aa7c-7acdc15904b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741070156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1741070156
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.4024381987
Short name T265
Test name
Test status
Simulation time 9612143804 ps
CPU time 7.77 seconds
Started Jun 25 06:58:03 PM PDT 24
Finished Jun 25 06:58:12 PM PDT 24
Peak memory 225488 kb
Host smart-35bbc6a7-1fc1-415d-bdb8-4b3b55c84e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024381987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.4024381987
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1950547823
Short name T116
Test name
Test status
Simulation time 545449217 ps
CPU time 3.98 seconds
Started Jun 25 06:58:02 PM PDT 24
Finished Jun 25 06:58:07 PM PDT 24
Peak memory 219972 kb
Host smart-3b7bfda0-c8f4-4f02-9942-3c818f6abd27
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1950547823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1950547823
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1110798967
Short name T862
Test name
Test status
Simulation time 26700418910 ps
CPU time 269.09 seconds
Started Jun 25 06:58:11 PM PDT 24
Finished Jun 25 07:02:41 PM PDT 24
Peak memory 263352 kb
Host smart-8b11fe1b-aaf1-4185-923c-5725619ad906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110798967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1110798967
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3625901245
Short name T783
Test name
Test status
Simulation time 8426745242 ps
CPU time 6.98 seconds
Started Jun 25 06:58:03 PM PDT 24
Finished Jun 25 06:58:12 PM PDT 24
Peak memory 217124 kb
Host smart-0f51c762-af58-46e4-9156-eaae58edbc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625901245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3625901245
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.425642715
Short name T549
Test name
Test status
Simulation time 2266313030 ps
CPU time 5.58 seconds
Started Jun 25 06:58:02 PM PDT 24
Finished Jun 25 06:58:09 PM PDT 24
Peak memory 217204 kb
Host smart-6142845f-4b25-46f4-942a-c5538817995b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425642715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.425642715
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2129445913
Short name T848
Test name
Test status
Simulation time 393842000 ps
CPU time 5.01 seconds
Started Jun 25 06:58:02 PM PDT 24
Finished Jun 25 06:58:09 PM PDT 24
Peak memory 217104 kb
Host smart-4029862e-a5f8-4381-807d-3b1798337360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129445913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2129445913
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3860061279
Short name T359
Test name
Test status
Simulation time 450078580 ps
CPU time 0.88 seconds
Started Jun 25 06:58:02 PM PDT 24
Finished Jun 25 06:58:04 PM PDT 24
Peak memory 207688 kb
Host smart-d32c3934-35fc-44ea-9a65-b69f125fd101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860061279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3860061279
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2837467716
Short name T824
Test name
Test status
Simulation time 54947835711 ps
CPU time 12.58 seconds
Started Jun 25 06:58:03 PM PDT 24
Finished Jun 25 06:58:17 PM PDT 24
Peak memory 237456 kb
Host smart-9dfb0b6b-2ea1-43e4-87a5-9977d79ec301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837467716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2837467716
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.32554704
Short name T508
Test name
Test status
Simulation time 61510608 ps
CPU time 0.78 seconds
Started Jun 25 06:58:16 PM PDT 24
Finished Jun 25 06:58:18 PM PDT 24
Peak memory 206328 kb
Host smart-08346452-a50a-4b57-8b27-a463659752bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32554704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.32554704
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.359044166
Short name T597
Test name
Test status
Simulation time 1513434717 ps
CPU time 8.24 seconds
Started Jun 25 06:58:10 PM PDT 24
Finished Jun 25 06:58:20 PM PDT 24
Peak memory 225392 kb
Host smart-e232cbb2-be2c-4270-8bfa-34221bb13783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359044166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.359044166
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1557867730
Short name T368
Test name
Test status
Simulation time 262292544 ps
CPU time 0.82 seconds
Started Jun 25 06:58:09 PM PDT 24
Finished Jun 25 06:58:11 PM PDT 24
Peak memory 207436 kb
Host smart-868e370a-10b2-4edf-808d-073a0100138e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557867730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1557867730
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3482870951
Short name T558
Test name
Test status
Simulation time 6117548384 ps
CPU time 49.36 seconds
Started Jun 25 06:58:10 PM PDT 24
Finished Jun 25 06:59:00 PM PDT 24
Peak memory 225500 kb
Host smart-b5199fe3-6a7e-4d67-88a6-033ef38c1bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482870951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3482870951
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1183759401
Short name T319
Test name
Test status
Simulation time 2814809667 ps
CPU time 9.54 seconds
Started Jun 25 06:58:16 PM PDT 24
Finished Jun 25 06:58:27 PM PDT 24
Peak memory 218660 kb
Host smart-9ad7233a-faba-49ae-b004-c0e494b0ae3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183759401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1183759401
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1407533512
Short name T145
Test name
Test status
Simulation time 8518223411 ps
CPU time 54.81 seconds
Started Jun 25 06:58:17 PM PDT 24
Finished Jun 25 06:59:13 PM PDT 24
Peak memory 255040 kb
Host smart-a34b8a98-95fa-4166-b649-9476054f7a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407533512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1407533512
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2594709373
Short name T3
Test name
Test status
Simulation time 162948712 ps
CPU time 3.47 seconds
Started Jun 25 06:58:10 PM PDT 24
Finished Jun 25 06:58:15 PM PDT 24
Peak memory 233620 kb
Host smart-5919e41e-a2f1-4c19-9248-01c6bfa8b10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594709373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2594709373
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1087289229
Short name T677
Test name
Test status
Simulation time 902899558 ps
CPU time 3.75 seconds
Started Jun 25 06:58:10 PM PDT 24
Finished Jun 25 06:58:14 PM PDT 24
Peak memory 233636 kb
Host smart-9d5a03a7-faf5-4e04-9216-525be0a350e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087289229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1087289229
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2941727861
Short name T906
Test name
Test status
Simulation time 6823309050 ps
CPU time 18.73 seconds
Started Jun 25 06:58:11 PM PDT 24
Finished Jun 25 06:58:31 PM PDT 24
Peak memory 233756 kb
Host smart-98b3ad79-3f5a-4acf-b322-cfd76309e44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941727861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2941727861
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1700045565
Short name T447
Test name
Test status
Simulation time 3447221383 ps
CPU time 12.6 seconds
Started Jun 25 06:58:10 PM PDT 24
Finished Jun 25 06:58:24 PM PDT 24
Peak memory 233724 kb
Host smart-7de29459-3237-468a-9718-a4eb125c1252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700045565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1700045565
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1043083560
Short name T471
Test name
Test status
Simulation time 87731653 ps
CPU time 2.98 seconds
Started Jun 25 06:58:10 PM PDT 24
Finished Jun 25 06:58:13 PM PDT 24
Peak memory 233576 kb
Host smart-15f59e8e-8d6c-4be7-acca-5b0b940eecc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043083560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1043083560
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.270298711
Short name T615
Test name
Test status
Simulation time 83864838 ps
CPU time 3.33 seconds
Started Jun 25 06:58:11 PM PDT 24
Finished Jun 25 06:58:15 PM PDT 24
Peak memory 223548 kb
Host smart-e708c486-5413-4ee2-b375-43d031b9a8b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=270298711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.270298711
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2132928863
Short name T697
Test name
Test status
Simulation time 12141935887 ps
CPU time 157.24 seconds
Started Jun 25 06:58:16 PM PDT 24
Finished Jun 25 07:00:54 PM PDT 24
Peak memory 267620 kb
Host smart-238fbf51-cb01-4833-a842-ebbdd1bba26a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132928863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2132928863
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3450981234
Short name T294
Test name
Test status
Simulation time 24221174335 ps
CPU time 28.5 seconds
Started Jun 25 06:58:10 PM PDT 24
Finished Jun 25 06:58:39 PM PDT 24
Peak memory 221180 kb
Host smart-29836b5c-1129-4dfe-8e3d-582afff93cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450981234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3450981234
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.237747421
Short name T757
Test name
Test status
Simulation time 522753147 ps
CPU time 1.92 seconds
Started Jun 25 06:58:10 PM PDT 24
Finished Jun 25 06:58:13 PM PDT 24
Peak memory 208688 kb
Host smart-fa63771f-6b90-4232-9fab-5c0a8d03410f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237747421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.237747421
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3965960710
Short name T729
Test name
Test status
Simulation time 163154587 ps
CPU time 1.46 seconds
Started Jun 25 06:58:11 PM PDT 24
Finished Jun 25 06:58:13 PM PDT 24
Peak memory 217084 kb
Host smart-5f5c211f-f6c6-450a-a410-6eb18a90f613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965960710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3965960710
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.945995896
Short name T414
Test name
Test status
Simulation time 36644206 ps
CPU time 0.72 seconds
Started Jun 25 06:58:10 PM PDT 24
Finished Jun 25 06:58:12 PM PDT 24
Peak memory 206712 kb
Host smart-41a47195-e12d-433d-bcd2-bedf4f9e6011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945995896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.945995896
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.766508142
Short name T179
Test name
Test status
Simulation time 810866912 ps
CPU time 10.05 seconds
Started Jun 25 06:58:09 PM PDT 24
Finished Jun 25 06:58:20 PM PDT 24
Peak memory 249520 kb
Host smart-f1240635-d8a8-46f2-a8e0-4e657291e85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766508142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.766508142
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3199619842
Short name T474
Test name
Test status
Simulation time 22292702 ps
CPU time 0.71 seconds
Started Jun 25 06:54:22 PM PDT 24
Finished Jun 25 06:54:23 PM PDT 24
Peak memory 206356 kb
Host smart-b64684d7-de4a-4562-873a-dd0589cf77c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199619842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
199619842
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2743491281
Short name T157
Test name
Test status
Simulation time 8014569495 ps
CPU time 13.51 seconds
Started Jun 25 06:54:17 PM PDT 24
Finished Jun 25 06:54:32 PM PDT 24
Peak memory 233744 kb
Host smart-c4f4d255-5058-48b2-884f-93a7a79848fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743491281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2743491281
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3146517703
Short name T766
Test name
Test status
Simulation time 16828767 ps
CPU time 0.79 seconds
Started Jun 25 06:54:15 PM PDT 24
Finished Jun 25 06:54:17 PM PDT 24
Peak memory 207408 kb
Host smart-5be18983-62f7-45a7-adf9-0d98e6b32d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146517703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3146517703
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3920073426
Short name T903
Test name
Test status
Simulation time 8461971041 ps
CPU time 54.07 seconds
Started Jun 25 06:54:17 PM PDT 24
Finished Jun 25 06:55:12 PM PDT 24
Peak memory 256588 kb
Host smart-0272c500-5a7b-40f2-b7b6-61704a5f91c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920073426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3920073426
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1967914181
Short name T589
Test name
Test status
Simulation time 13270398414 ps
CPU time 118.29 seconds
Started Jun 25 06:54:14 PM PDT 24
Finished Jun 25 06:56:14 PM PDT 24
Peak memory 250352 kb
Host smart-274ad77a-5581-4e7d-8411-07ea85d620e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967914181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1967914181
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1639258753
Short name T293
Test name
Test status
Simulation time 2387431881 ps
CPU time 43.34 seconds
Started Jun 25 06:54:20 PM PDT 24
Finished Jun 25 06:55:04 PM PDT 24
Peak memory 233820 kb
Host smart-51e8edba-ee27-479d-b66e-474fab2a24c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639258753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1639258753
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.322024847
Short name T11
Test name
Test status
Simulation time 2179386186 ps
CPU time 20.35 seconds
Started Jun 25 06:54:16 PM PDT 24
Finished Jun 25 06:54:37 PM PDT 24
Peak memory 233844 kb
Host smart-0e4279a1-67b5-4e67-8cef-03bd49de4bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322024847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.322024847
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1805395739
Short name T80
Test name
Test status
Simulation time 2568407181 ps
CPU time 19.73 seconds
Started Jun 25 06:54:15 PM PDT 24
Finished Jun 25 06:54:36 PM PDT 24
Peak memory 233740 kb
Host smart-896e703f-15fc-4c32-a8da-0db534ecb1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805395739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1805395739
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1394751791
Short name T326
Test name
Test status
Simulation time 619734264 ps
CPU time 3.51 seconds
Started Jun 25 06:54:14 PM PDT 24
Finished Jun 25 06:54:18 PM PDT 24
Peak memory 219624 kb
Host smart-6a93470d-c45b-477f-b952-a2313c678bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394751791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1394751791
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.96434666
Short name T506
Test name
Test status
Simulation time 384058554 ps
CPU time 4.79 seconds
Started Jun 25 06:54:15 PM PDT 24
Finished Jun 25 06:54:21 PM PDT 24
Peak memory 233456 kb
Host smart-d53ca2e7-1413-4538-b459-629897a216af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96434666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.96434666
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2761369136
Short name T165
Test name
Test status
Simulation time 567057789 ps
CPU time 6.22 seconds
Started Jun 25 06:54:14 PM PDT 24
Finished Jun 25 06:54:22 PM PDT 24
Peak memory 233636 kb
Host smart-ce3530b4-8761-49fe-be8c-b92508e73af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761369136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2761369136
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1402841983
Short name T383
Test name
Test status
Simulation time 377216099 ps
CPU time 3.27 seconds
Started Jun 25 06:54:16 PM PDT 24
Finished Jun 25 06:54:21 PM PDT 24
Peak memory 219776 kb
Host smart-c7e1d445-2706-4601-ba11-24ab8a977b5a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1402841983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1402841983
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.4132742349
Short name T57
Test name
Test status
Simulation time 83897895 ps
CPU time 1.04 seconds
Started Jun 25 06:54:22 PM PDT 24
Finished Jun 25 06:54:24 PM PDT 24
Peak memory 236456 kb
Host smart-652840de-bc90-4a8f-968e-96756a8b4939
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132742349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.4132742349
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.284259891
Short name T942
Test name
Test status
Simulation time 36095977 ps
CPU time 0.96 seconds
Started Jun 25 06:54:21 PM PDT 24
Finished Jun 25 06:54:23 PM PDT 24
Peak memory 207468 kb
Host smart-f153c49c-5f8a-4cae-b5e7-906b3b9642fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284259891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.284259891
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1097997515
Short name T302
Test name
Test status
Simulation time 7315769201 ps
CPU time 15.69 seconds
Started Jun 25 06:54:14 PM PDT 24
Finished Jun 25 06:54:31 PM PDT 24
Peak memory 217312 kb
Host smart-ee5a5ce3-45a8-4569-ac2f-e6a493a1748e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097997515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1097997515
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2908921163
Short name T327
Test name
Test status
Simulation time 7937279714 ps
CPU time 22.84 seconds
Started Jun 25 06:54:13 PM PDT 24
Finished Jun 25 06:54:37 PM PDT 24
Peak memory 217204 kb
Host smart-2d2a5aa4-3467-44c2-a754-e5abd02f280a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908921163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2908921163
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.715795567
Short name T137
Test name
Test status
Simulation time 45870731 ps
CPU time 1.16 seconds
Started Jun 25 06:54:15 PM PDT 24
Finished Jun 25 06:54:18 PM PDT 24
Peak memory 208576 kb
Host smart-81ecb204-52da-40e7-ba06-5f24593e326b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715795567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.715795567
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.341964544
Short name T320
Test name
Test status
Simulation time 69435793 ps
CPU time 0.9 seconds
Started Jun 25 06:54:17 PM PDT 24
Finished Jun 25 06:54:19 PM PDT 24
Peak memory 206720 kb
Host smart-1a347a8c-0918-4e01-8f59-7d69fe752ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341964544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.341964544
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.4049588608
Short name T524
Test name
Test status
Simulation time 3747889493 ps
CPU time 17.12 seconds
Started Jun 25 06:54:14 PM PDT 24
Finished Jun 25 06:54:33 PM PDT 24
Peak memory 249220 kb
Host smart-b696a452-dbcb-4a2d-8b0a-2883af296294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049588608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4049588608
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3420635775
Short name T844
Test name
Test status
Simulation time 12041526 ps
CPU time 0.69 seconds
Started Jun 25 06:58:23 PM PDT 24
Finished Jun 25 06:58:25 PM PDT 24
Peak memory 205764 kb
Host smart-fe2da0b1-70e1-4e65-af63-50576854dc99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420635775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3420635775
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1996982255
Short name T660
Test name
Test status
Simulation time 777954866 ps
CPU time 7.97 seconds
Started Jun 25 06:58:17 PM PDT 24
Finished Jun 25 06:58:26 PM PDT 24
Peak memory 225444 kb
Host smart-2e939b52-ccff-4b0f-8bd5-b9c939f04853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996982255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1996982255
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.4053617729
Short name T141
Test name
Test status
Simulation time 18168296 ps
CPU time 0.83 seconds
Started Jun 25 06:58:19 PM PDT 24
Finished Jun 25 06:58:21 PM PDT 24
Peak memory 206388 kb
Host smart-5338b876-058c-402c-84af-c5000d480ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053617729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.4053617729
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1964803504
Short name T218
Test name
Test status
Simulation time 46220136244 ps
CPU time 83.39 seconds
Started Jun 25 06:58:16 PM PDT 24
Finished Jun 25 06:59:40 PM PDT 24
Peak memory 260240 kb
Host smart-094587f0-5fdd-467e-b43c-bb614ceade01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964803504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1964803504
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.193127704
Short name T154
Test name
Test status
Simulation time 65904930121 ps
CPU time 203.64 seconds
Started Jun 25 06:58:25 PM PDT 24
Finished Jun 25 07:01:51 PM PDT 24
Peak memory 255408 kb
Host smart-8de3e5c7-5b9f-431b-9c52-96939ee7c222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193127704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.193127704
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1207525532
Short name T288
Test name
Test status
Simulation time 39229680882 ps
CPU time 55.1 seconds
Started Jun 25 06:58:18 PM PDT 24
Finished Jun 25 06:59:14 PM PDT 24
Peak memory 233688 kb
Host smart-ff3795de-e07f-4ab5-a8a8-096388eb8236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207525532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1207525532
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2913494584
Short name T833
Test name
Test status
Simulation time 260043924 ps
CPU time 2.56 seconds
Started Jun 25 06:58:18 PM PDT 24
Finished Jun 25 06:58:22 PM PDT 24
Peak memory 233648 kb
Host smart-5722a230-a115-4ca7-91bd-77947a591c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913494584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2913494584
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3462815368
Short name T579
Test name
Test status
Simulation time 3027096474 ps
CPU time 7.42 seconds
Started Jun 25 06:58:18 PM PDT 24
Finished Jun 25 06:58:27 PM PDT 24
Peak memory 225504 kb
Host smart-9a1946cd-240a-47cc-9cb1-f74a42feaec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462815368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3462815368
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.85845778
Short name T169
Test name
Test status
Simulation time 5788226309 ps
CPU time 15.96 seconds
Started Jun 25 06:58:18 PM PDT 24
Finished Jun 25 06:58:35 PM PDT 24
Peak memory 225520 kb
Host smart-a5784fce-4b19-4221-8955-c8895e1023d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85845778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.85845778
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.845792750
Short name T621
Test name
Test status
Simulation time 54811482 ps
CPU time 2.62 seconds
Started Jun 25 06:58:19 PM PDT 24
Finished Jun 25 06:58:23 PM PDT 24
Peak memory 233624 kb
Host smart-e4bb2981-284b-4564-85ac-0e9028b37ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845792750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.845792750
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3741297928
Short name T587
Test name
Test status
Simulation time 904304808 ps
CPU time 6.35 seconds
Started Jun 25 06:58:16 PM PDT 24
Finished Jun 25 06:58:23 PM PDT 24
Peak memory 224144 kb
Host smart-d098fab9-ed96-4e7e-9a48-3935b49b3713
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3741297928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3741297928
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3300193798
Short name T271
Test name
Test status
Simulation time 226433232061 ps
CPU time 502.59 seconds
Started Jun 25 06:58:25 PM PDT 24
Finished Jun 25 07:06:50 PM PDT 24
Peak memory 273728 kb
Host smart-96a188c9-712f-4071-be74-1a5256dcb8b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300193798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3300193798
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.941639044
Short name T561
Test name
Test status
Simulation time 50406116039 ps
CPU time 27.87 seconds
Started Jun 25 06:58:19 PM PDT 24
Finished Jun 25 06:58:48 PM PDT 24
Peak memory 217208 kb
Host smart-26165016-369f-4c1e-8d5b-c54c9bc3710d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941639044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.941639044
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3417867925
Short name T405
Test name
Test status
Simulation time 1708533967 ps
CPU time 6.81 seconds
Started Jun 25 06:58:17 PM PDT 24
Finished Jun 25 06:58:25 PM PDT 24
Peak memory 217280 kb
Host smart-aeee2b28-0c02-4a66-a7b7-5c75080727e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417867925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3417867925
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3410941856
Short name T668
Test name
Test status
Simulation time 30307724 ps
CPU time 0.71 seconds
Started Jun 25 06:58:17 PM PDT 24
Finished Jun 25 06:58:19 PM PDT 24
Peak memory 206508 kb
Host smart-5f0208e6-e4c0-42ed-8064-c7572645336d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410941856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3410941856
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3924277545
Short name T687
Test name
Test status
Simulation time 444236009 ps
CPU time 0.96 seconds
Started Jun 25 06:58:19 PM PDT 24
Finished Jun 25 06:58:21 PM PDT 24
Peak memory 206724 kb
Host smart-f7ec10ef-a43f-452e-b2b7-6c0f3cf70c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924277545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3924277545
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3186969555
Short name T915
Test name
Test status
Simulation time 5035430560 ps
CPU time 18.86 seconds
Started Jun 25 06:58:17 PM PDT 24
Finished Jun 25 06:58:37 PM PDT 24
Peak memory 236868 kb
Host smart-cefd3571-b5a9-4df1-b841-7be583af25d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186969555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3186969555
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3518253056
Short name T52
Test name
Test status
Simulation time 12024370 ps
CPU time 0.72 seconds
Started Jun 25 06:58:26 PM PDT 24
Finished Jun 25 06:58:28 PM PDT 24
Peak memory 206644 kb
Host smart-fff3a7a7-0e6e-4908-a108-3cd9493a0e60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518253056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3518253056
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1514620621
Short name T223
Test name
Test status
Simulation time 237174184 ps
CPU time 5.18 seconds
Started Jun 25 06:58:24 PM PDT 24
Finished Jun 25 06:58:30 PM PDT 24
Peak memory 225408 kb
Host smart-8dcaf2b4-6a40-44f9-a494-b701cd1a1572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514620621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1514620621
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2817593981
Short name T483
Test name
Test status
Simulation time 44962765 ps
CPU time 0.79 seconds
Started Jun 25 06:58:25 PM PDT 24
Finished Jun 25 06:58:27 PM PDT 24
Peak memory 207440 kb
Host smart-ab17ab1b-bb8e-4b3e-ab0c-7ffbcc2d1691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817593981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2817593981
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3065181139
Short name T505
Test name
Test status
Simulation time 39284575528 ps
CPU time 147.39 seconds
Started Jun 25 06:58:25 PM PDT 24
Finished Jun 25 07:00:54 PM PDT 24
Peak memory 254436 kb
Host smart-576cd4c4-e3f5-4143-b440-ba43ecfe6f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065181139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3065181139
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.605942454
Short name T467
Test name
Test status
Simulation time 59180494929 ps
CPU time 238.05 seconds
Started Jun 25 06:58:25 PM PDT 24
Finished Jun 25 07:02:25 PM PDT 24
Peak memory 255768 kb
Host smart-61b9374e-5457-4e47-8573-86ebb07a53f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605942454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.605942454
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2947800151
Short name T694
Test name
Test status
Simulation time 1704336933 ps
CPU time 12.27 seconds
Started Jun 25 06:58:24 PM PDT 24
Finished Jun 25 06:58:37 PM PDT 24
Peak memory 218420 kb
Host smart-f2ef4424-e2a5-46d1-b062-f6de57688483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947800151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2947800151
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2679168120
Short name T432
Test name
Test status
Simulation time 836600966 ps
CPU time 15.22 seconds
Started Jun 25 06:58:23 PM PDT 24
Finished Jun 25 06:58:39 PM PDT 24
Peak memory 225400 kb
Host smart-30e993bf-670e-472b-982f-6528d6734736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679168120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2679168120
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3903435941
Short name T550
Test name
Test status
Simulation time 1809591031 ps
CPU time 8.17 seconds
Started Jun 25 06:58:25 PM PDT 24
Finished Jun 25 06:58:34 PM PDT 24
Peak memory 233612 kb
Host smart-d2a597b3-9dd3-42e2-930c-9a56528407ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903435941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3903435941
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2016677411
Short name T938
Test name
Test status
Simulation time 7951144280 ps
CPU time 80.76 seconds
Started Jun 25 06:58:27 PM PDT 24
Finished Jun 25 06:59:49 PM PDT 24
Peak memory 233764 kb
Host smart-c5601b1f-2418-4773-8978-e50a5b705354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016677411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2016677411
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2381861628
Short name T712
Test name
Test status
Simulation time 4777999912 ps
CPU time 9.85 seconds
Started Jun 25 06:58:24 PM PDT 24
Finished Jun 25 06:58:35 PM PDT 24
Peak memory 225468 kb
Host smart-4a94e6e4-163e-4b42-961a-9a31613f7495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381861628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2381861628
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3344537488
Short name T804
Test name
Test status
Simulation time 5657906629 ps
CPU time 5.49 seconds
Started Jun 25 06:58:24 PM PDT 24
Finished Jun 25 06:58:31 PM PDT 24
Peak memory 225540 kb
Host smart-d5cfcf4a-4793-48f0-a4d7-703de8395720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344537488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3344537488
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2387579940
Short name T761
Test name
Test status
Simulation time 503340288 ps
CPU time 5.31 seconds
Started Jun 25 06:58:25 PM PDT 24
Finished Jun 25 06:58:32 PM PDT 24
Peak memory 224052 kb
Host smart-702aa08e-19d8-42c6-a5d7-f2cafa6003a7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2387579940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2387579940
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.584716517
Short name T256
Test name
Test status
Simulation time 9070171791 ps
CPU time 182.13 seconds
Started Jun 25 06:58:23 PM PDT 24
Finished Jun 25 07:01:26 PM PDT 24
Peak memory 279348 kb
Host smart-84fae63d-3330-4daa-98de-5bfd131c963d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584716517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.584716517
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.35951172
Short name T4
Test name
Test status
Simulation time 7195418848 ps
CPU time 27.06 seconds
Started Jun 25 06:58:25 PM PDT 24
Finished Jun 25 06:58:53 PM PDT 24
Peak memory 217188 kb
Host smart-9470a818-f203-4dd7-b324-8eb05239d042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35951172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.35951172
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2896872925
Short name T496
Test name
Test status
Simulation time 5144416298 ps
CPU time 4.97 seconds
Started Jun 25 06:58:26 PM PDT 24
Finished Jun 25 06:58:32 PM PDT 24
Peak memory 217256 kb
Host smart-19af445a-2b18-4c35-af5d-3f056a96d1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896872925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2896872925
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.4140646910
Short name T704
Test name
Test status
Simulation time 19137754 ps
CPU time 1.08 seconds
Started Jun 25 06:58:22 PM PDT 24
Finished Jun 25 06:58:24 PM PDT 24
Peak memory 208616 kb
Host smart-d78a52f7-6ddc-4487-94c5-00f7962d55cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140646910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.4140646910
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.363320422
Short name T885
Test name
Test status
Simulation time 40551611 ps
CPU time 0.92 seconds
Started Jun 25 06:58:24 PM PDT 24
Finished Jun 25 06:58:26 PM PDT 24
Peak memory 207264 kb
Host smart-8f9f27be-a5f5-4fc2-9e14-f21e46a6ecac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363320422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.363320422
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.162274445
Short name T29
Test name
Test status
Simulation time 8010194069 ps
CPU time 18.71 seconds
Started Jun 25 06:58:25 PM PDT 24
Finished Jun 25 06:58:45 PM PDT 24
Peak memory 240524 kb
Host smart-33d37056-e7ba-4b91-8b5b-4b23b72c7259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162274445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.162274445
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3728375729
Short name T397
Test name
Test status
Simulation time 15827202 ps
CPU time 0.77 seconds
Started Jun 25 06:58:33 PM PDT 24
Finished Jun 25 06:58:35 PM PDT 24
Peak memory 206660 kb
Host smart-1dac7b2a-d79f-418d-8ce3-ff42dda99593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728375729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3728375729
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3345419599
Short name T360
Test name
Test status
Simulation time 676857386 ps
CPU time 5.07 seconds
Started Jun 25 06:58:31 PM PDT 24
Finished Jun 25 06:58:37 PM PDT 24
Peak memory 225396 kb
Host smart-733687d2-7bb6-432a-9c37-99bd535cdf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345419599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3345419599
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3563692087
Short name T328
Test name
Test status
Simulation time 39306294 ps
CPU time 0.75 seconds
Started Jun 25 06:58:32 PM PDT 24
Finished Jun 25 06:58:34 PM PDT 24
Peak memory 206360 kb
Host smart-9cd5ec7e-7663-48ec-b639-39ace8a55588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563692087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3563692087
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1254568052
Short name T196
Test name
Test status
Simulation time 3839564052 ps
CPU time 67.13 seconds
Started Jun 25 06:58:33 PM PDT 24
Finished Jun 25 06:59:41 PM PDT 24
Peak memory 251420 kb
Host smart-50232ca0-e016-4113-8de9-fe38e8416f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254568052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1254568052
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.4038068031
Short name T728
Test name
Test status
Simulation time 3967500965 ps
CPU time 11.3 seconds
Started Jun 25 06:58:36 PM PDT 24
Finished Jun 25 06:58:48 PM PDT 24
Peak memory 218492 kb
Host smart-43704280-8049-4165-a70a-50dce44fea4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038068031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.4038068031
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_intercept.118236900
Short name T531
Test name
Test status
Simulation time 519355767 ps
CPU time 6.83 seconds
Started Jun 25 06:58:34 PM PDT 24
Finished Jun 25 06:58:42 PM PDT 24
Peak memory 225368 kb
Host smart-8c8784a5-6b2d-45e7-af5c-8951c2d3bd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118236900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.118236900
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3476972807
Short name T464
Test name
Test status
Simulation time 1257026736 ps
CPU time 17.73 seconds
Started Jun 25 06:58:36 PM PDT 24
Finished Jun 25 06:58:55 PM PDT 24
Peak memory 241528 kb
Host smart-685c1a9a-3c25-4a0f-b7d7-18134a4b8634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476972807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3476972807
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1457920635
Short name T793
Test name
Test status
Simulation time 764432862 ps
CPU time 8.4 seconds
Started Jun 25 06:58:34 PM PDT 24
Finished Jun 25 06:58:44 PM PDT 24
Peak memory 225372 kb
Host smart-efef23fa-ee8b-4e20-b1b7-a1b6b4e22cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457920635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1457920635
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.4143482941
Short name T763
Test name
Test status
Simulation time 126781841 ps
CPU time 3.82 seconds
Started Jun 25 06:58:32 PM PDT 24
Finished Jun 25 06:58:37 PM PDT 24
Peak memory 233600 kb
Host smart-2e55be2c-1ca6-4d07-b7cb-9ef8fa214600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143482941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.4143482941
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.154779954
Short name T653
Test name
Test status
Simulation time 8474961328 ps
CPU time 8.65 seconds
Started Jun 25 06:58:36 PM PDT 24
Finished Jun 25 06:58:46 PM PDT 24
Peak memory 223836 kb
Host smart-8fd6ca1e-bf6d-4695-8a18-702284bbc371
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=154779954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.154779954
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1811899470
Short name T730
Test name
Test status
Simulation time 107142932766 ps
CPU time 246.01 seconds
Started Jun 25 06:58:32 PM PDT 24
Finished Jun 25 07:02:39 PM PDT 24
Peak memory 266588 kb
Host smart-aa3cbf2b-7bd5-4495-ba67-8d82e0847b55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811899470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1811899470
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1692883445
Short name T870
Test name
Test status
Simulation time 2119412412 ps
CPU time 18.78 seconds
Started Jun 25 06:58:34 PM PDT 24
Finished Jun 25 06:58:54 PM PDT 24
Peak memory 218392 kb
Host smart-9bae490b-37c5-4901-98bd-bec9b2a67d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692883445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1692883445
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2543732157
Short name T325
Test name
Test status
Simulation time 10311929177 ps
CPU time 7.59 seconds
Started Jun 25 06:58:35 PM PDT 24
Finished Jun 25 06:58:43 PM PDT 24
Peak memory 217252 kb
Host smart-a53063be-6ad8-4358-9c00-513445adb1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543732157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2543732157
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2135592808
Short name T321
Test name
Test status
Simulation time 13483242 ps
CPU time 0.71 seconds
Started Jun 25 06:58:32 PM PDT 24
Finished Jun 25 06:58:34 PM PDT 24
Peak memory 206444 kb
Host smart-a1e4ee36-83c2-4d3d-8679-650fcd7b4d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135592808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2135592808
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1117088592
Short name T425
Test name
Test status
Simulation time 29872927 ps
CPU time 0.71 seconds
Started Jun 25 06:58:33 PM PDT 24
Finished Jun 25 06:58:35 PM PDT 24
Peak memory 206456 kb
Host smart-3eee6e39-41ee-4e63-87ac-76b26ae92838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117088592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1117088592
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.4113093242
Short name T954
Test name
Test status
Simulation time 793099913 ps
CPU time 3.89 seconds
Started Jun 25 06:58:31 PM PDT 24
Finished Jun 25 06:58:36 PM PDT 24
Peak memory 225392 kb
Host smart-7a714128-3c99-4638-8b1e-23c6d2d1016b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113093242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.4113093242
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2095075349
Short name T333
Test name
Test status
Simulation time 11448008 ps
CPU time 0.72 seconds
Started Jun 25 06:58:42 PM PDT 24
Finished Jun 25 06:58:44 PM PDT 24
Peak memory 206316 kb
Host smart-1bd2c4e4-1e4e-47b9-bbff-57d7f03bec79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095075349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2095075349
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1531869063
Short name T69
Test name
Test status
Simulation time 439203606 ps
CPU time 7.01 seconds
Started Jun 25 06:58:42 PM PDT 24
Finished Jun 25 06:58:50 PM PDT 24
Peak memory 233604 kb
Host smart-70be038b-e0df-43f8-a085-3d6eeb65362b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531869063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1531869063
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2172912228
Short name T419
Test name
Test status
Simulation time 86128647 ps
CPU time 0.78 seconds
Started Jun 25 06:58:32 PM PDT 24
Finished Jun 25 06:58:34 PM PDT 24
Peak memory 207420 kb
Host smart-a77ea903-c698-4ef5-b031-6cefaeccb1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172912228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2172912228
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2243538497
Short name T674
Test name
Test status
Simulation time 12111966477 ps
CPU time 51.43 seconds
Started Jun 25 06:58:42 PM PDT 24
Finished Jun 25 06:59:35 PM PDT 24
Peak memory 265948 kb
Host smart-eaff337f-038d-4a27-bbd4-cb741c15f14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243538497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2243538497
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1577775887
Short name T797
Test name
Test status
Simulation time 2344249150 ps
CPU time 58.81 seconds
Started Jun 25 06:58:40 PM PDT 24
Finished Jun 25 06:59:40 PM PDT 24
Peak memory 250172 kb
Host smart-0471f244-ee9f-4b44-8dbc-f8203747d421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577775887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1577775887
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2827663743
Short name T210
Test name
Test status
Simulation time 29865089120 ps
CPU time 312.87 seconds
Started Jun 25 06:58:40 PM PDT 24
Finished Jun 25 07:03:54 PM PDT 24
Peak memory 252680 kb
Host smart-0a576a01-10c0-4843-a153-c628bc2ed458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827663743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2827663743
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3917131962
Short name T357
Test name
Test status
Simulation time 302742894 ps
CPU time 4.03 seconds
Started Jun 25 06:58:38 PM PDT 24
Finished Jun 25 06:58:43 PM PDT 24
Peak memory 225364 kb
Host smart-8ce8571c-f823-48d3-9288-4d0a87b0a1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917131962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3917131962
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2586044354
Short name T30
Test name
Test status
Simulation time 375773449 ps
CPU time 5.04 seconds
Started Jun 25 06:58:36 PM PDT 24
Finished Jun 25 06:58:42 PM PDT 24
Peak memory 225172 kb
Host smart-92dc1cef-725b-4208-8d0b-d194355a103e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586044354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2586044354
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3463677697
Short name T520
Test name
Test status
Simulation time 3917432436 ps
CPU time 38.27 seconds
Started Jun 25 06:58:31 PM PDT 24
Finished Jun 25 06:59:10 PM PDT 24
Peak memory 233704 kb
Host smart-5ae35330-d6a0-4203-a455-82063d1d6f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463677697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3463677697
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.4279856056
Short name T247
Test name
Test status
Simulation time 427350261 ps
CPU time 2.33 seconds
Started Jun 25 06:58:33 PM PDT 24
Finished Jun 25 06:58:36 PM PDT 24
Peak memory 225516 kb
Host smart-115a43c8-c1aa-4370-9bf1-050d86d38fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279856056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.4279856056
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.866253418
Short name T231
Test name
Test status
Simulation time 258183108 ps
CPU time 2.84 seconds
Started Jun 25 06:58:32 PM PDT 24
Finished Jun 25 06:58:36 PM PDT 24
Peak memory 225324 kb
Host smart-f4d2cfc2-e1bb-489b-b11a-e71466082cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866253418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.866253418
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2182913949
Short name T339
Test name
Test status
Simulation time 493849293 ps
CPU time 3.8 seconds
Started Jun 25 06:58:42 PM PDT 24
Finished Jun 25 06:58:47 PM PDT 24
Peak memory 223860 kb
Host smart-9349e8e7-7f97-4493-8c85-db37b266c8e5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2182913949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2182913949
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1758446792
Short name T740
Test name
Test status
Simulation time 10510469984 ps
CPU time 120.99 seconds
Started Jun 25 06:58:39 PM PDT 24
Finished Jun 25 07:00:41 PM PDT 24
Peak memory 257420 kb
Host smart-b210d911-f301-4964-8a57-c9c18080f39d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758446792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1758446792
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.4252182853
Short name T699
Test name
Test status
Simulation time 14485200 ps
CPU time 0.75 seconds
Started Jun 25 06:58:32 PM PDT 24
Finished Jun 25 06:58:34 PM PDT 24
Peak memory 206872 kb
Host smart-9a3be645-2a42-40eb-b69c-9faf1fc2add6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252182853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.4252182853
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2232109430
Short name T713
Test name
Test status
Simulation time 7942082149 ps
CPU time 12.68 seconds
Started Jun 25 06:58:32 PM PDT 24
Finished Jun 25 06:58:46 PM PDT 24
Peak memory 217220 kb
Host smart-0ac16b52-804c-44a5-bd74-20c7b02d4733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232109430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2232109430
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2035351705
Short name T551
Test name
Test status
Simulation time 517103619 ps
CPU time 1.45 seconds
Started Jun 25 06:58:33 PM PDT 24
Finished Jun 25 06:58:36 PM PDT 24
Peak memory 217120 kb
Host smart-fb43a92c-89c2-49e8-8fad-133206d5b266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035351705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2035351705
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1951127419
Short name T412
Test name
Test status
Simulation time 35502943 ps
CPU time 0.75 seconds
Started Jun 25 06:58:33 PM PDT 24
Finished Jun 25 06:58:35 PM PDT 24
Peak memory 206672 kb
Host smart-ddf615a3-f564-4043-befd-41ad9d71dd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951127419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1951127419
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.749716542
Short name T680
Test name
Test status
Simulation time 1014833224 ps
CPU time 3.31 seconds
Started Jun 25 06:58:33 PM PDT 24
Finished Jun 25 06:58:37 PM PDT 24
Peak memory 225380 kb
Host smart-a2f1448a-a4bb-499c-8e6a-2f74fe3effbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749716542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.749716542
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.827517005
Short name T734
Test name
Test status
Simulation time 46642681 ps
CPU time 0.72 seconds
Started Jun 25 06:58:39 PM PDT 24
Finished Jun 25 06:58:41 PM PDT 24
Peak memory 206312 kb
Host smart-2b3ef9ee-3819-4ba5-b5e9-3a70a8fa34f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827517005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.827517005
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.870333987
Short name T226
Test name
Test status
Simulation time 1690542776 ps
CPU time 15.83 seconds
Started Jun 25 06:58:40 PM PDT 24
Finished Jun 25 06:58:58 PM PDT 24
Peak memory 225440 kb
Host smart-6a80c2fa-681c-420b-b346-badb8d799706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870333987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.870333987
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3989307821
Short name T491
Test name
Test status
Simulation time 53503138 ps
CPU time 0.8 seconds
Started Jun 25 06:58:40 PM PDT 24
Finished Jun 25 06:58:42 PM PDT 24
Peak memory 207436 kb
Host smart-6444c771-8092-4121-92d2-e9f640340e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989307821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3989307821
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3119331225
Short name T161
Test name
Test status
Simulation time 38839529450 ps
CPU time 123.49 seconds
Started Jun 25 06:58:40 PM PDT 24
Finished Jun 25 07:00:45 PM PDT 24
Peak memory 266420 kb
Host smart-ca0b25f8-faaa-4a9c-93c7-da0b0ab2917b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119331225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3119331225
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.4185352504
Short name T924
Test name
Test status
Simulation time 21342359983 ps
CPU time 101.44 seconds
Started Jun 25 06:58:39 PM PDT 24
Finished Jun 25 07:00:22 PM PDT 24
Peak memory 225588 kb
Host smart-0bdacdd0-d889-45b7-a9ba-4f46b42ae760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185352504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.4185352504
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2065023289
Short name T607
Test name
Test status
Simulation time 14726711414 ps
CPU time 48.62 seconds
Started Jun 25 06:58:43 PM PDT 24
Finished Jun 25 06:59:33 PM PDT 24
Peak memory 241856 kb
Host smart-77697937-8b86-4212-8771-d1d11140ae00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065023289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2065023289
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1707668669
Short name T498
Test name
Test status
Simulation time 75122032 ps
CPU time 2.98 seconds
Started Jun 25 06:58:40 PM PDT 24
Finished Jun 25 06:58:45 PM PDT 24
Peak memory 233608 kb
Host smart-bab90cbb-f9f2-496f-a5e8-a82aad45421b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707668669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1707668669
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3345780728
Short name T402
Test name
Test status
Simulation time 702540136 ps
CPU time 6.35 seconds
Started Jun 25 06:58:39 PM PDT 24
Finished Jun 25 06:58:46 PM PDT 24
Peak memory 225404 kb
Host smart-216f5b40-abd2-49f8-99de-faa0658080f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345780728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3345780728
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3609205818
Short name T922
Test name
Test status
Simulation time 889662298 ps
CPU time 4.87 seconds
Started Jun 25 06:58:40 PM PDT 24
Finished Jun 25 06:58:47 PM PDT 24
Peak memory 228944 kb
Host smart-0059a377-a090-408a-a8b5-b7a71c41abd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609205818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3609205818
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1338297157
Short name T170
Test name
Test status
Simulation time 5097408557 ps
CPU time 13.9 seconds
Started Jun 25 06:58:39 PM PDT 24
Finished Jun 25 06:58:55 PM PDT 24
Peak memory 241636 kb
Host smart-0960f070-4e24-41cf-bbde-c9ccf1d393d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338297157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1338297157
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2332280536
Short name T755
Test name
Test status
Simulation time 3959307617 ps
CPU time 8.12 seconds
Started Jun 25 06:58:38 PM PDT 24
Finished Jun 25 06:58:47 PM PDT 24
Peak memory 233728 kb
Host smart-29d8239f-4c80-4941-a3dc-94ee7fbd31ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332280536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2332280536
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1898135819
Short name T841
Test name
Test status
Simulation time 1886553866 ps
CPU time 8.31 seconds
Started Jun 25 06:58:39 PM PDT 24
Finished Jun 25 06:58:49 PM PDT 24
Peak memory 221568 kb
Host smart-09b8d09e-abff-4398-8e54-943913d4c75a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1898135819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1898135819
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1825914713
Short name T916
Test name
Test status
Simulation time 19004238484 ps
CPU time 133.03 seconds
Started Jun 25 06:58:40 PM PDT 24
Finished Jun 25 07:00:54 PM PDT 24
Peak memory 252944 kb
Host smart-48dc55e7-7b65-42ad-bae6-2542496066c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825914713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1825914713
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2557901288
Short name T662
Test name
Test status
Simulation time 1941978356 ps
CPU time 14.23 seconds
Started Jun 25 06:58:43 PM PDT 24
Finished Jun 25 06:58:58 PM PDT 24
Peak memory 217440 kb
Host smart-aaa8d9ab-47ae-4be3-8d03-d91d3034ad95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557901288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2557901288
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3736891505
Short name T311
Test name
Test status
Simulation time 1293560925 ps
CPU time 4.68 seconds
Started Jun 25 06:58:43 PM PDT 24
Finished Jun 25 06:58:49 PM PDT 24
Peak memory 217132 kb
Host smart-ce7fe2b1-6b92-47ce-b3c2-1046da256d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736891505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3736891505
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2087164023
Short name T786
Test name
Test status
Simulation time 25642353 ps
CPU time 0.99 seconds
Started Jun 25 06:58:40 PM PDT 24
Finished Jun 25 06:58:42 PM PDT 24
Peak memory 208168 kb
Host smart-8c66619b-4d20-4dc4-b087-35ee94f84451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087164023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2087164023
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.913511134
Short name T477
Test name
Test status
Simulation time 34839301 ps
CPU time 0.71 seconds
Started Jun 25 06:58:41 PM PDT 24
Finished Jun 25 06:58:43 PM PDT 24
Peak memory 206460 kb
Host smart-aa6f94c3-217f-42f2-9c7e-0a7ecb677878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913511134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.913511134
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.262839028
Short name T642
Test name
Test status
Simulation time 400891175 ps
CPU time 2.98 seconds
Started Jun 25 06:58:39 PM PDT 24
Finished Jun 25 06:58:43 PM PDT 24
Peak memory 225352 kb
Host smart-9a238434-fee4-4b91-a64d-55033b7d529f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262839028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.262839028
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3498578678
Short name T485
Test name
Test status
Simulation time 11160395 ps
CPU time 0.74 seconds
Started Jun 25 06:58:44 PM PDT 24
Finished Jun 25 06:58:46 PM PDT 24
Peak memory 206568 kb
Host smart-aa5ad510-3df4-4ad8-9b63-8338889df0f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498578678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3498578678
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1326265432
Short name T717
Test name
Test status
Simulation time 584575556 ps
CPU time 7.1 seconds
Started Jun 25 06:58:49 PM PDT 24
Finished Jun 25 06:58:57 PM PDT 24
Peak memory 225348 kb
Host smart-2a16dfb4-2b43-48bd-b20f-e8c5684d293e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326265432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1326265432
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1652814569
Short name T481
Test name
Test status
Simulation time 33187797 ps
CPU time 0.8 seconds
Started Jun 25 06:58:40 PM PDT 24
Finished Jun 25 06:58:42 PM PDT 24
Peak memory 206372 kb
Host smart-4e15e20b-e999-4cdb-9b67-78ee9bad07c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652814569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1652814569
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2736110702
Short name T715
Test name
Test status
Simulation time 31539004 ps
CPU time 0.79 seconds
Started Jun 25 06:58:49 PM PDT 24
Finished Jun 25 06:58:52 PM PDT 24
Peak memory 216780 kb
Host smart-d4fc31c9-c6b1-472f-b5b0-f0ae3873b6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736110702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2736110702
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1637456383
Short name T257
Test name
Test status
Simulation time 22181039564 ps
CPU time 152.97 seconds
Started Jun 25 06:58:47 PM PDT 24
Finished Jun 25 07:01:21 PM PDT 24
Peak memory 274048 kb
Host smart-d97bc2d2-0a57-498e-9f4a-b4237826b2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637456383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1637456383
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.484975341
Short name T416
Test name
Test status
Simulation time 5134371504 ps
CPU time 78.65 seconds
Started Jun 25 06:58:46 PM PDT 24
Finished Jun 25 07:00:05 PM PDT 24
Peak memory 250192 kb
Host smart-5b4b8dd1-624c-4618-9992-99c8febe7d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484975341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.484975341
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2599429565
Short name T324
Test name
Test status
Simulation time 223642676 ps
CPU time 5.44 seconds
Started Jun 25 06:58:47 PM PDT 24
Finished Jun 25 06:58:53 PM PDT 24
Peak memory 225424 kb
Host smart-1887a090-6da9-4033-936e-2ad83ffa562f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599429565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2599429565
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1288133779
Short name T492
Test name
Test status
Simulation time 388581782 ps
CPU time 6.68 seconds
Started Jun 25 06:58:46 PM PDT 24
Finished Jun 25 06:58:54 PM PDT 24
Peak memory 219612 kb
Host smart-d4fa1c7d-4e55-409e-8884-0e848ed39d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288133779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1288133779
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2716311232
Short name T592
Test name
Test status
Simulation time 3994438273 ps
CPU time 17.75 seconds
Started Jun 25 06:58:49 PM PDT 24
Finished Jun 25 06:59:07 PM PDT 24
Peak memory 241864 kb
Host smart-5c7293fc-c48e-46c1-b3e8-ec04e6134394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716311232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2716311232
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3906791158
Short name T690
Test name
Test status
Simulation time 23985527819 ps
CPU time 14.33 seconds
Started Jun 25 06:58:48 PM PDT 24
Finished Jun 25 06:59:04 PM PDT 24
Peak memory 233664 kb
Host smart-80dde2dc-6a00-45c9-a7a4-911de4cbbbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906791158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3906791158
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.844173364
Short name T856
Test name
Test status
Simulation time 95434754192 ps
CPU time 22.61 seconds
Started Jun 25 06:58:46 PM PDT 24
Finished Jun 25 06:59:10 PM PDT 24
Peak memory 250056 kb
Host smart-e563f488-fcf3-443d-9ae3-5a7ef7c1b1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844173364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.844173364
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3981738755
Short name T384
Test name
Test status
Simulation time 235956196 ps
CPU time 5.11 seconds
Started Jun 25 06:58:50 PM PDT 24
Finished Jun 25 06:58:57 PM PDT 24
Peak memory 223600 kb
Host smart-3811c4cb-668d-4d35-91cb-806dc08188db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3981738755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3981738755
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.693670497
Short name T134
Test name
Test status
Simulation time 160015221 ps
CPU time 1.14 seconds
Started Jun 25 06:58:51 PM PDT 24
Finished Jun 25 06:58:53 PM PDT 24
Peak memory 208404 kb
Host smart-1e21b71b-35a6-469f-bdd0-e402ac50f7f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693670497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.693670497
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3641097877
Short name T935
Test name
Test status
Simulation time 24297307241 ps
CPU time 33.18 seconds
Started Jun 25 06:58:51 PM PDT 24
Finished Jun 25 06:59:25 PM PDT 24
Peak memory 217232 kb
Host smart-774d38d3-ccdc-44f5-8c54-1de65878dbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641097877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3641097877
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.4126174688
Short name T315
Test name
Test status
Simulation time 7415179604 ps
CPU time 8.01 seconds
Started Jun 25 06:58:40 PM PDT 24
Finished Jun 25 06:58:50 PM PDT 24
Peak memory 217224 kb
Host smart-2caff39c-9505-458a-b52d-e5b385e9bd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126174688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.4126174688
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2376710111
Short name T867
Test name
Test status
Simulation time 437889771 ps
CPU time 5.44 seconds
Started Jun 25 06:58:51 PM PDT 24
Finished Jun 25 06:58:57 PM PDT 24
Peak memory 216700 kb
Host smart-c05a3d4f-ea75-4216-b3d6-f2e040b420be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376710111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2376710111
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3641751465
Short name T366
Test name
Test status
Simulation time 26454206 ps
CPU time 0.84 seconds
Started Jun 25 06:58:46 PM PDT 24
Finished Jun 25 06:58:48 PM PDT 24
Peak memory 206708 kb
Host smart-5039a783-5ee4-41ff-931e-9c7809a3c336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641751465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3641751465
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3695396812
Short name T156
Test name
Test status
Simulation time 286450648 ps
CPU time 2.57 seconds
Started Jun 25 06:58:47 PM PDT 24
Finished Jun 25 06:58:50 PM PDT 24
Peak memory 233604 kb
Host smart-7e6fb185-7dd7-4dda-9b64-b32efd39f83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695396812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3695396812
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1946039894
Short name T772
Test name
Test status
Simulation time 65373961 ps
CPU time 0.72 seconds
Started Jun 25 06:58:53 PM PDT 24
Finished Jun 25 06:58:55 PM PDT 24
Peak memory 206252 kb
Host smart-5a399795-07ab-4fc3-970d-7fec3e003bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946039894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1946039894
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2825802054
Short name T588
Test name
Test status
Simulation time 979965199 ps
CPU time 7.99 seconds
Started Jun 25 06:58:54 PM PDT 24
Finished Jun 25 06:59:03 PM PDT 24
Peak memory 233656 kb
Host smart-ddc3633b-8d68-4077-a5ca-5f32d1188069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825802054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2825802054
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3339986292
Short name T421
Test name
Test status
Simulation time 12813755 ps
CPU time 0.75 seconds
Started Jun 25 06:58:47 PM PDT 24
Finished Jun 25 06:58:49 PM PDT 24
Peak memory 206716 kb
Host smart-f5eeb09e-3c5d-47e4-8de7-af9e588a7f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339986292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3339986292
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1206277398
Short name T921
Test name
Test status
Simulation time 2616091286 ps
CPU time 16.79 seconds
Started Jun 25 06:58:52 PM PDT 24
Finished Jun 25 06:59:10 PM PDT 24
Peak memory 240560 kb
Host smart-0e6477b6-230e-4bda-b5bc-dbdbd6bfbbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206277398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1206277398
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.812755929
Short name T272
Test name
Test status
Simulation time 60747063657 ps
CPU time 562.69 seconds
Started Jun 25 06:58:53 PM PDT 24
Finished Jun 25 07:08:17 PM PDT 24
Peak memory 268872 kb
Host smart-d8f10e8d-c7e2-4015-8166-c70ecd4c831e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812755929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.812755929
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.4065135551
Short name T908
Test name
Test status
Simulation time 7611653025 ps
CPU time 66.01 seconds
Started Jun 25 06:58:53 PM PDT 24
Finished Jun 25 07:00:01 PM PDT 24
Peak memory 240068 kb
Host smart-3bd62968-ad49-4f34-9b30-44e26fbbcb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065135551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.4065135551
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2816289683
Short name T200
Test name
Test status
Simulation time 4016334901 ps
CPU time 59.31 seconds
Started Jun 25 06:58:51 PM PDT 24
Finished Jun 25 06:59:52 PM PDT 24
Peak memory 233744 kb
Host smart-db8bdf2a-dbb7-45dd-9856-d3147e0940aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816289683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2816289683
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1830720150
Short name T576
Test name
Test status
Simulation time 231189085 ps
CPU time 4.5 seconds
Started Jun 25 06:58:53 PM PDT 24
Finished Jun 25 06:58:58 PM PDT 24
Peak memory 233620 kb
Host smart-af4d3e86-1033-4fcf-8210-0df71824347a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830720150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1830720150
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.41897728
Short name T465
Test name
Test status
Simulation time 1520730458 ps
CPU time 13.66 seconds
Started Jun 25 06:58:54 PM PDT 24
Finished Jun 25 06:59:09 PM PDT 24
Peak memory 236048 kb
Host smart-25343917-573e-467f-900c-7f7e5e5f806b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41897728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.41897728
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.37231653
Short name T259
Test name
Test status
Simulation time 11768758844 ps
CPU time 11.03 seconds
Started Jun 25 06:58:53 PM PDT 24
Finished Jun 25 06:59:06 PM PDT 24
Peak memory 225684 kb
Host smart-b4aca415-0519-4616-b301-6bb0f9013335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37231653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.37231653
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.230190713
Short name T632
Test name
Test status
Simulation time 3304397948 ps
CPU time 10.86 seconds
Started Jun 25 06:58:52 PM PDT 24
Finished Jun 25 06:59:04 PM PDT 24
Peak memory 225488 kb
Host smart-f4708e5b-d95e-4bc2-9abc-932c1ab70a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230190713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.230190713
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3317043488
Short name T114
Test name
Test status
Simulation time 1238488349 ps
CPU time 13.55 seconds
Started Jun 25 06:58:55 PM PDT 24
Finished Jun 25 06:59:09 PM PDT 24
Peak memory 223532 kb
Host smart-14069ba1-1149-4691-b3bd-bb1384bf3249
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3317043488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3317043488
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3498118607
Short name T34
Test name
Test status
Simulation time 6342935615 ps
CPU time 66.62 seconds
Started Jun 25 06:58:55 PM PDT 24
Finished Jun 25 07:00:02 PM PDT 24
Peak memory 250212 kb
Host smart-9189b138-4388-443c-830d-22c967bcf793
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498118607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3498118607
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1782480563
Short name T675
Test name
Test status
Simulation time 3864700121 ps
CPU time 22.42 seconds
Started Jun 25 06:58:53 PM PDT 24
Finished Jun 25 06:59:16 PM PDT 24
Peak memory 217428 kb
Host smart-41f1e843-9a4b-48fe-b231-d0e086995df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782480563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1782480563
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3617032942
Short name T765
Test name
Test status
Simulation time 11424584906 ps
CPU time 7.56 seconds
Started Jun 25 06:58:54 PM PDT 24
Finished Jun 25 06:59:03 PM PDT 24
Peak memory 217204 kb
Host smart-a9a50d53-6c10-4f16-98db-08d5051014fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617032942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3617032942
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3406408108
Short name T330
Test name
Test status
Simulation time 119591935 ps
CPU time 0.73 seconds
Started Jun 25 06:58:54 PM PDT 24
Finished Jun 25 06:58:56 PM PDT 24
Peak memory 206728 kb
Host smart-92e87484-94aa-4327-a242-891787069aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406408108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3406408108
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1811351554
Short name T346
Test name
Test status
Simulation time 40609691 ps
CPU time 0.84 seconds
Started Jun 25 06:58:53 PM PDT 24
Finished Jun 25 06:58:55 PM PDT 24
Peak memory 206652 kb
Host smart-37dec45d-b23c-4f1c-b145-220727d6926b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811351554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1811351554
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.168872224
Short name T187
Test name
Test status
Simulation time 457791413 ps
CPU time 6.82 seconds
Started Jun 25 06:58:51 PM PDT 24
Finished Jun 25 06:58:59 PM PDT 24
Peak memory 233620 kb
Host smart-dc64002b-5368-4ff5-aad2-3586795ec186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168872224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.168872224
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.436715456
Short name T50
Test name
Test status
Simulation time 22784374 ps
CPU time 0.75 seconds
Started Jun 25 06:59:02 PM PDT 24
Finished Jun 25 06:59:04 PM PDT 24
Peak memory 205760 kb
Host smart-a618c494-ea41-461e-88d5-ae5e2e160ab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436715456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.436715456
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.819737077
Short name T264
Test name
Test status
Simulation time 157736037 ps
CPU time 2.37 seconds
Started Jun 25 06:59:00 PM PDT 24
Finished Jun 25 06:59:04 PM PDT 24
Peak memory 225432 kb
Host smart-cb25fbf5-0ba5-4c67-9bd5-92610072ca7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819737077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.819737077
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3765421419
Short name T605
Test name
Test status
Simulation time 51813534 ps
CPU time 0.79 seconds
Started Jun 25 06:58:52 PM PDT 24
Finished Jun 25 06:58:54 PM PDT 24
Peak memory 207408 kb
Host smart-4d90c039-254d-4986-82be-2691dd1e954a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765421419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3765421419
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.637125345
Short name T252
Test name
Test status
Simulation time 4181943529 ps
CPU time 50.34 seconds
Started Jun 25 06:59:02 PM PDT 24
Finished Jun 25 06:59:54 PM PDT 24
Peak memory 257896 kb
Host smart-3967c4aa-f341-4769-a385-976167f9fae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637125345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.637125345
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.699480052
Short name T23
Test name
Test status
Simulation time 67175117758 ps
CPU time 182.84 seconds
Started Jun 25 06:59:01 PM PDT 24
Finished Jun 25 07:02:05 PM PDT 24
Peak memory 255412 kb
Host smart-b70a5759-6fa4-45cc-98ce-356bab81b5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699480052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.699480052
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.211163388
Short name T718
Test name
Test status
Simulation time 17506429964 ps
CPU time 54.74 seconds
Started Jun 25 06:59:03 PM PDT 24
Finished Jun 25 06:59:59 PM PDT 24
Peak memory 241896 kb
Host smart-c715662d-dc08-430c-a261-61ac61fd13a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211163388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.211163388
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1307732658
Short name T946
Test name
Test status
Simulation time 205664428 ps
CPU time 5.8 seconds
Started Jun 25 06:59:03 PM PDT 24
Finished Jun 25 06:59:10 PM PDT 24
Peak memory 234668 kb
Host smart-cd1fead5-09ed-4195-af08-b168a1f4d97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307732658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1307732658
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1045899853
Short name T199
Test name
Test status
Simulation time 5903765592 ps
CPU time 12.43 seconds
Started Jun 25 06:58:59 PM PDT 24
Finished Jun 25 06:59:12 PM PDT 24
Peak memory 233744 kb
Host smart-f84c4cea-0762-4bea-ac1f-ae6a5c621d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045899853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1045899853
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2278219850
Short name T353
Test name
Test status
Simulation time 9735132853 ps
CPU time 20.32 seconds
Started Jun 25 06:59:00 PM PDT 24
Finished Jun 25 06:59:21 PM PDT 24
Peak memory 225508 kb
Host smart-499c46fe-de6f-4794-8ae5-e1336c07df39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278219850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2278219850
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.21513441
Short name T567
Test name
Test status
Simulation time 6999320647 ps
CPU time 23.13 seconds
Started Jun 25 06:59:02 PM PDT 24
Finished Jun 25 06:59:27 PM PDT 24
Peak memory 225508 kb
Host smart-0b2e9990-f3a9-41fe-82ab-b3bb9a44a1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21513441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.21513441
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.943250837
Short name T459
Test name
Test status
Simulation time 203013342 ps
CPU time 2.44 seconds
Started Jun 25 06:59:02 PM PDT 24
Finished Jun 25 06:59:06 PM PDT 24
Peak memory 225392 kb
Host smart-8f982bcc-b5f7-4b01-b9ed-8323233e6564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943250837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.943250837
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3028514363
Short name T40
Test name
Test status
Simulation time 842793722 ps
CPU time 10.63 seconds
Started Jun 25 06:59:02 PM PDT 24
Finished Jun 25 06:59:14 PM PDT 24
Peak memory 221344 kb
Host smart-6200bf81-4055-4dca-aa28-7ece36194383
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3028514363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3028514363
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.687356589
Short name T760
Test name
Test status
Simulation time 2757532458 ps
CPU time 10.99 seconds
Started Jun 25 06:59:01 PM PDT 24
Finished Jun 25 06:59:13 PM PDT 24
Peak memory 217172 kb
Host smart-809a7143-230c-4739-8b7f-2028e431305a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687356589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.687356589
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2859312802
Short name T563
Test name
Test status
Simulation time 2707243856 ps
CPU time 4.93 seconds
Started Jun 25 06:59:01 PM PDT 24
Finished Jun 25 06:59:07 PM PDT 24
Peak memory 217224 kb
Host smart-40e53062-5e27-4495-ae96-3bfdeaa93278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859312802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2859312802
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2928733810
Short name T611
Test name
Test status
Simulation time 423127334 ps
CPU time 0.94 seconds
Started Jun 25 06:59:02 PM PDT 24
Finished Jun 25 06:59:04 PM PDT 24
Peak memory 207760 kb
Host smart-53d349c7-3576-4a7d-8922-7262366e10ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928733810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2928733810
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2497785676
Short name T429
Test name
Test status
Simulation time 295379494 ps
CPU time 0.93 seconds
Started Jun 25 06:59:01 PM PDT 24
Finished Jun 25 06:59:03 PM PDT 24
Peak memory 206712 kb
Host smart-c6ccc72c-baf7-435f-9efa-dc890b142d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497785676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2497785676
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1004351737
Short name T208
Test name
Test status
Simulation time 35594319891 ps
CPU time 18.31 seconds
Started Jun 25 06:59:01 PM PDT 24
Finished Jun 25 06:59:20 PM PDT 24
Peak memory 225404 kb
Host smart-fa9c35b0-c8b7-449a-8553-2eccd16eb8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004351737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1004351737
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.588859736
Short name T598
Test name
Test status
Simulation time 13869334 ps
CPU time 0.74 seconds
Started Jun 25 06:59:08 PM PDT 24
Finished Jun 25 06:59:10 PM PDT 24
Peak memory 205772 kb
Host smart-f30fefd5-8db6-4e31-baa3-4beec443aa23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588859736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.588859736
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3253469086
Short name T230
Test name
Test status
Simulation time 720331388 ps
CPU time 6.51 seconds
Started Jun 25 06:59:09 PM PDT 24
Finished Jun 25 06:59:16 PM PDT 24
Peak memory 233592 kb
Host smart-7743bc4a-d10c-4cd0-8835-ca665bb708e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253469086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3253469086
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3905933654
Short name T732
Test name
Test status
Simulation time 17232203 ps
CPU time 0.8 seconds
Started Jun 25 06:59:01 PM PDT 24
Finished Jun 25 06:59:03 PM PDT 24
Peak memory 207408 kb
Host smart-4822264b-cbb5-45b3-a51c-cddf1155fc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905933654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3905933654
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2307403046
Short name T958
Test name
Test status
Simulation time 432220898 ps
CPU time 8.95 seconds
Started Jun 25 06:59:11 PM PDT 24
Finished Jun 25 06:59:20 PM PDT 24
Peak memory 225428 kb
Host smart-f73f85af-a47f-4f11-b7d7-3017576b3400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307403046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2307403046
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2404290191
Short name T895
Test name
Test status
Simulation time 53746745842 ps
CPU time 357.93 seconds
Started Jun 25 06:59:08 PM PDT 24
Finished Jun 25 07:05:07 PM PDT 24
Peak memory 266688 kb
Host smart-9087ea2b-26d5-4a92-85f3-86a7c6e8301c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404290191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2404290191
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3696866248
Short name T540
Test name
Test status
Simulation time 41240659000 ps
CPU time 116.94 seconds
Started Jun 25 06:59:08 PM PDT 24
Finished Jun 25 07:01:06 PM PDT 24
Peak memory 256252 kb
Host smart-65ce96c6-c9cc-4565-be5b-bd9d783f8ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696866248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3696866248
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3254710395
Short name T287
Test name
Test status
Simulation time 3449702127 ps
CPU time 17.13 seconds
Started Jun 25 06:59:10 PM PDT 24
Finished Jun 25 06:59:28 PM PDT 24
Peak memory 225532 kb
Host smart-6471e182-0c1c-4308-aebb-89a9dea84120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254710395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3254710395
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3070585380
Short name T305
Test name
Test status
Simulation time 272254426 ps
CPU time 2.36 seconds
Started Jun 25 06:59:09 PM PDT 24
Finished Jun 25 06:59:12 PM PDT 24
Peak memory 219276 kb
Host smart-b4f268bc-d681-4e7d-ac08-76fae198ba1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070585380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3070585380
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3501269553
Short name T874
Test name
Test status
Simulation time 3365271417 ps
CPU time 26.39 seconds
Started Jun 25 06:59:08 PM PDT 24
Finished Jun 25 06:59:35 PM PDT 24
Peak memory 233748 kb
Host smart-1e711b2b-f228-43c9-be66-b00faa43a64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501269553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3501269553
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2128491420
Short name T212
Test name
Test status
Simulation time 330955347 ps
CPU time 3.46 seconds
Started Jun 25 06:59:10 PM PDT 24
Finished Jun 25 06:59:15 PM PDT 24
Peak memory 225356 kb
Host smart-cfea8bb8-7eb7-4604-b9ce-5ebd5a3a4578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128491420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2128491420
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2848917665
Short name T219
Test name
Test status
Simulation time 6779463070 ps
CPU time 11.18 seconds
Started Jun 25 06:59:09 PM PDT 24
Finished Jun 25 06:59:22 PM PDT 24
Peak memory 233768 kb
Host smart-c66d0269-cc1a-42fc-8743-da4f61196e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848917665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2848917665
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3196561560
Short name T385
Test name
Test status
Simulation time 467144221 ps
CPU time 3.28 seconds
Started Jun 25 06:59:08 PM PDT 24
Finished Jun 25 06:59:12 PM PDT 24
Peak memory 220084 kb
Host smart-92fc7d83-7088-42ba-9122-116777937973
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3196561560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3196561560
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1225821324
Short name T129
Test name
Test status
Simulation time 324768073298 ps
CPU time 265.24 seconds
Started Jun 25 06:59:09 PM PDT 24
Finished Jun 25 07:03:35 PM PDT 24
Peak memory 252796 kb
Host smart-89471eff-59a0-45a8-8c28-d7adf280f893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225821324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1225821324
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2722278616
Short name T390
Test name
Test status
Simulation time 16597917274 ps
CPU time 16.19 seconds
Started Jun 25 06:59:00 PM PDT 24
Finished Jun 25 06:59:17 PM PDT 24
Peak memory 217228 kb
Host smart-20e5bf75-9a0f-494f-983a-787991218622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722278616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2722278616
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2132634806
Short name T364
Test name
Test status
Simulation time 2796059942 ps
CPU time 12.75 seconds
Started Jun 25 06:59:02 PM PDT 24
Finished Jun 25 06:59:17 PM PDT 24
Peak memory 217228 kb
Host smart-a7a50258-6b1f-462b-971e-1c923577033c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132634806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2132634806
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3040409971
Short name T775
Test name
Test status
Simulation time 182274002 ps
CPU time 1 seconds
Started Jun 25 06:59:01 PM PDT 24
Finished Jun 25 06:59:03 PM PDT 24
Peak memory 207804 kb
Host smart-6b5255fb-8ce5-4356-bcde-3d5fcc2fc839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040409971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3040409971
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.597391397
Short name T883
Test name
Test status
Simulation time 31339671 ps
CPU time 0.89 seconds
Started Jun 25 06:59:01 PM PDT 24
Finished Jun 25 06:59:03 PM PDT 24
Peak memory 206748 kb
Host smart-7e78133e-04de-41d1-beca-06ff71975ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597391397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.597391397
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.491052757
Short name T189
Test name
Test status
Simulation time 591836232 ps
CPU time 6.37 seconds
Started Jun 25 06:59:09 PM PDT 24
Finished Jun 25 06:59:16 PM PDT 24
Peak memory 240080 kb
Host smart-fafa97a5-c859-4e94-8b06-8ffcdc7a3da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491052757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.491052757
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1382334597
Short name T49
Test name
Test status
Simulation time 12598870 ps
CPU time 0.7 seconds
Started Jun 25 06:59:21 PM PDT 24
Finished Jun 25 06:59:22 PM PDT 24
Peak memory 206684 kb
Host smart-f8322b3a-d9e0-4c55-a8e5-e46c2fb10e5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382334597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1382334597
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2933180252
Short name T648
Test name
Test status
Simulation time 8016104109 ps
CPU time 12.48 seconds
Started Jun 25 06:59:14 PM PDT 24
Finished Jun 25 06:59:28 PM PDT 24
Peak memory 225496 kb
Host smart-b02e564f-f0f8-4a89-a37e-0b0fa2aff612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933180252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2933180252
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2913136119
Short name T445
Test name
Test status
Simulation time 14447780 ps
CPU time 0.77 seconds
Started Jun 25 06:59:07 PM PDT 24
Finished Jun 25 06:59:09 PM PDT 24
Peak memory 207748 kb
Host smart-23a0b052-9bab-4699-8d7c-fb9a8d3be763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913136119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2913136119
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1423842440
Short name T233
Test name
Test status
Simulation time 1110864617 ps
CPU time 9.12 seconds
Started Jun 25 06:59:16 PM PDT 24
Finished Jun 25 06:59:26 PM PDT 24
Peak memory 225376 kb
Host smart-a5beceb0-f844-453d-965c-c6a1e5e952d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423842440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1423842440
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.697150599
Short name T487
Test name
Test status
Simulation time 2737604390 ps
CPU time 60.88 seconds
Started Jun 25 06:59:13 PM PDT 24
Finished Jun 25 07:00:15 PM PDT 24
Peak memory 250184 kb
Host smart-5e209463-95d6-4f16-bef4-1a8bed22884a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697150599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.697150599
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3171987125
Short name T871
Test name
Test status
Simulation time 6486031095 ps
CPU time 12.48 seconds
Started Jun 25 06:59:14 PM PDT 24
Finished Jun 25 06:59:27 PM PDT 24
Peak memory 218704 kb
Host smart-77fabbbb-20b7-455e-a291-1c8e7809023a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171987125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3171987125
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1373381895
Short name T894
Test name
Test status
Simulation time 3010470001 ps
CPU time 12.32 seconds
Started Jun 25 06:59:21 PM PDT 24
Finished Jun 25 06:59:34 PM PDT 24
Peak memory 241900 kb
Host smart-c2da04ff-de62-4039-a7fd-c43d24ba4d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373381895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1373381895
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.394132388
Short name T9
Test name
Test status
Simulation time 572489770 ps
CPU time 4.5 seconds
Started Jun 25 06:59:17 PM PDT 24
Finished Jun 25 06:59:22 PM PDT 24
Peak memory 233640 kb
Host smart-a5619f3f-d714-4a6a-878d-dce44ed27f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394132388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.394132388
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.933038420
Short name T616
Test name
Test status
Simulation time 759972885 ps
CPU time 12.11 seconds
Started Jun 25 06:59:14 PM PDT 24
Finished Jun 25 06:59:27 PM PDT 24
Peak memory 240536 kb
Host smart-4378be92-5b79-4cf6-aa4c-64dfde1cf870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933038420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.933038420
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.336678438
Short name T203
Test name
Test status
Simulation time 19185507819 ps
CPU time 17.96 seconds
Started Jun 25 06:59:14 PM PDT 24
Finished Jun 25 06:59:33 PM PDT 24
Peak memory 233716 kb
Host smart-028eb77f-808a-4c40-8e5f-b283127e39e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336678438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.336678438
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3743430148
Short name T608
Test name
Test status
Simulation time 8051290020 ps
CPU time 15.86 seconds
Started Jun 25 06:59:14 PM PDT 24
Finished Jun 25 06:59:31 PM PDT 24
Peak memory 233704 kb
Host smart-8eac67d1-ac24-4b9c-a83d-1b6edb743955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743430148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3743430148
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.64487054
Short name T735
Test name
Test status
Simulation time 814703959 ps
CPU time 4.79 seconds
Started Jun 25 06:59:16 PM PDT 24
Finished Jun 25 06:59:21 PM PDT 24
Peak memory 223996 kb
Host smart-8bedbf41-3a0c-422e-879b-424f7c30c6ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=64487054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direc
t.64487054
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3852988171
Short name T522
Test name
Test status
Simulation time 20594147 ps
CPU time 0.74 seconds
Started Jun 25 06:59:09 PM PDT 24
Finished Jun 25 06:59:10 PM PDT 24
Peak memory 206528 kb
Host smart-2300d0fc-3405-4467-a73f-307478f6d1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852988171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3852988171
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.559023711
Short name T490
Test name
Test status
Simulation time 12722754543 ps
CPU time 9.77 seconds
Started Jun 25 06:59:09 PM PDT 24
Finished Jun 25 06:59:20 PM PDT 24
Peak memory 217120 kb
Host smart-57ec9453-1820-436a-9776-e9cf789aa1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559023711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.559023711
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3097275996
Short name T684
Test name
Test status
Simulation time 36660453 ps
CPU time 0.72 seconds
Started Jun 25 06:59:15 PM PDT 24
Finished Jun 25 06:59:16 PM PDT 24
Peak memory 206492 kb
Host smart-412ec367-358a-458e-880d-a2a8f340a8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097275996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3097275996
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1228639437
Short name T634
Test name
Test status
Simulation time 25851123 ps
CPU time 0.76 seconds
Started Jun 25 06:59:15 PM PDT 24
Finished Jun 25 06:59:16 PM PDT 24
Peak memory 206680 kb
Host smart-bd88d874-3e7f-4f11-9296-fc81503f6a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228639437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1228639437
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.206305192
Short name T941
Test name
Test status
Simulation time 12439537091 ps
CPU time 16.44 seconds
Started Jun 25 06:59:13 PM PDT 24
Finished Jun 25 06:59:30 PM PDT 24
Peak memory 225536 kb
Host smart-1ed9a503-3c46-46a4-8a42-f81c039b6d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206305192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.206305192
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3851098964
Short name T431
Test name
Test status
Simulation time 10803486 ps
CPU time 0.73 seconds
Started Jun 25 06:54:26 PM PDT 24
Finished Jun 25 06:54:27 PM PDT 24
Peak memory 205752 kb
Host smart-679f8d99-e31c-4601-a13b-4ae2991373c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851098964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
851098964
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3743822410
Short name T620
Test name
Test status
Simulation time 536823566 ps
CPU time 7.15 seconds
Started Jun 25 06:54:22 PM PDT 24
Finished Jun 25 06:54:31 PM PDT 24
Peak memory 224572 kb
Host smart-7c744837-ba63-4b76-bdf3-172de693ec34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743822410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3743822410
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.561469530
Short name T342
Test name
Test status
Simulation time 147405673 ps
CPU time 0.8 seconds
Started Jun 25 06:54:22 PM PDT 24
Finished Jun 25 06:54:24 PM PDT 24
Peak memory 207452 kb
Host smart-4793e18d-4a2e-44f3-8ba6-23de5d9b8399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561469530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.561469530
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.118598464
Short name T868
Test name
Test status
Simulation time 74279958735 ps
CPU time 110.28 seconds
Started Jun 25 06:54:27 PM PDT 24
Finished Jun 25 06:56:19 PM PDT 24
Peak memory 240536 kb
Host smart-ecbea74c-99ec-49ef-8db3-7567c1f49b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118598464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.118598464
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3151752842
Short name T143
Test name
Test status
Simulation time 4716355094 ps
CPU time 51.49 seconds
Started Jun 25 06:54:26 PM PDT 24
Finished Jun 25 06:55:19 PM PDT 24
Peak memory 255344 kb
Host smart-c4653e0e-0f45-4346-84e4-28e39d2faebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151752842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3151752842
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.4258732909
Short name T167
Test name
Test status
Simulation time 156190527653 ps
CPU time 666.23 seconds
Started Jun 25 06:54:26 PM PDT 24
Finished Jun 25 07:05:33 PM PDT 24
Peak memory 265968 kb
Host smart-4168f555-d719-4b2b-b194-18e5616ce02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258732909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.4258732909
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.4026457904
Short name T439
Test name
Test status
Simulation time 960398046 ps
CPU time 17.8 seconds
Started Jun 25 06:54:19 PM PDT 24
Finished Jun 25 06:54:38 PM PDT 24
Peak memory 249724 kb
Host smart-69756ce9-bea5-4005-a4b5-f91c22c2cf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026457904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.4026457904
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.998646984
Short name T74
Test name
Test status
Simulation time 72461067 ps
CPU time 3.22 seconds
Started Jun 25 06:54:20 PM PDT 24
Finished Jun 25 06:54:24 PM PDT 24
Peak memory 233580 kb
Host smart-83c17bac-cbff-4c8a-a71a-265721552ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998646984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.998646984
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1224433179
Short name T719
Test name
Test status
Simulation time 723697288 ps
CPU time 11.33 seconds
Started Jun 25 06:54:20 PM PDT 24
Finished Jun 25 06:54:32 PM PDT 24
Peak memory 225396 kb
Host smart-fb14c725-cd3b-412b-aba1-1bddacde85ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224433179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1224433179
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2871730317
Short name T754
Test name
Test status
Simulation time 3788560430 ps
CPU time 5.53 seconds
Started Jun 25 06:54:21 PM PDT 24
Finished Jun 25 06:54:28 PM PDT 24
Peak memory 225524 kb
Host smart-dacf8358-987a-4cc6-bd31-ebc5d98a158a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871730317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2871730317
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3029324230
Short name T571
Test name
Test status
Simulation time 878395939 ps
CPU time 4.3 seconds
Started Jun 25 06:54:19 PM PDT 24
Finished Jun 25 06:54:24 PM PDT 24
Peak memory 225440 kb
Host smart-582c3710-cc20-47ed-830a-54d875e899f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029324230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3029324230
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1981913636
Short name T546
Test name
Test status
Simulation time 1035593037 ps
CPU time 6.65 seconds
Started Jun 25 06:54:22 PM PDT 24
Finished Jun 25 06:54:29 PM PDT 24
Peak memory 224020 kb
Host smart-a94677c1-4b57-408b-becd-e66815f4353c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1981913636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1981913636
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.4230472466
Short name T227
Test name
Test status
Simulation time 26254212839 ps
CPU time 245.59 seconds
Started Jun 25 06:54:28 PM PDT 24
Finished Jun 25 06:58:35 PM PDT 24
Peak memory 255360 kb
Host smart-6dcfecf1-ad28-4911-9f95-c8224992ee0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230472466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.4230472466
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2137040534
Short name T67
Test name
Test status
Simulation time 4810589894 ps
CPU time 30.12 seconds
Started Jun 25 06:54:19 PM PDT 24
Finished Jun 25 06:54:50 PM PDT 24
Peak memory 217252 kb
Host smart-4ea8e877-a7aa-47d1-b278-774fa9506846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137040534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2137040534
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1808280151
Short name T789
Test name
Test status
Simulation time 607260637 ps
CPU time 2.22 seconds
Started Jun 25 06:54:22 PM PDT 24
Finished Jun 25 06:54:26 PM PDT 24
Peak memory 216320 kb
Host smart-e5e96a53-39c5-4d60-8f07-247d20f67023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808280151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1808280151
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2740746927
Short name T919
Test name
Test status
Simulation time 448145636 ps
CPU time 2.84 seconds
Started Jun 25 06:54:20 PM PDT 24
Finished Jun 25 06:54:24 PM PDT 24
Peak memory 217120 kb
Host smart-d5275971-3725-4639-8524-d4cc28be3d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740746927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2740746927
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3156303413
Short name T482
Test name
Test status
Simulation time 54884830 ps
CPU time 0.91 seconds
Started Jun 25 06:54:20 PM PDT 24
Finished Jun 25 06:54:22 PM PDT 24
Peak memory 206824 kb
Host smart-83bd9460-b7d0-4c91-a8aa-49d368ada4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156303413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3156303413
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.4152100682
Short name T803
Test name
Test status
Simulation time 16066993298 ps
CPU time 15.65 seconds
Started Jun 25 06:54:19 PM PDT 24
Finished Jun 25 06:54:36 PM PDT 24
Peak memory 225564 kb
Host smart-a771749e-a78e-45e6-aa25-b98c3e8ad83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152100682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.4152100682
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.387926201
Short name T939
Test name
Test status
Simulation time 14548012 ps
CPU time 0.77 seconds
Started Jun 25 06:54:34 PM PDT 24
Finished Jun 25 06:54:37 PM PDT 24
Peak memory 206336 kb
Host smart-508fe0d8-8213-4256-8cc6-f12f7b955955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387926201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.387926201
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1422859746
Short name T759
Test name
Test status
Simulation time 1306432008 ps
CPU time 2.89 seconds
Started Jun 25 06:54:34 PM PDT 24
Finished Jun 25 06:54:39 PM PDT 24
Peak memory 225524 kb
Host smart-07306194-9f80-4fb2-b787-4195281ece42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422859746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1422859746
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.469155092
Short name T725
Test name
Test status
Simulation time 99541496 ps
CPU time 0.77 seconds
Started Jun 25 06:54:27 PM PDT 24
Finished Jun 25 06:54:29 PM PDT 24
Peak memory 206692 kb
Host smart-6ebc6825-47b9-4ec0-8a7a-db96b75f95fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469155092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.469155092
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1585643488
Short name T500
Test name
Test status
Simulation time 19522203 ps
CPU time 0.78 seconds
Started Jun 25 06:54:35 PM PDT 24
Finished Jun 25 06:54:37 PM PDT 24
Peak memory 216784 kb
Host smart-1ed17ce1-55fe-4a8c-ad04-ec59ed501b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585643488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1585643488
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2492220381
Short name T936
Test name
Test status
Simulation time 17396408163 ps
CPU time 38.37 seconds
Started Jun 25 06:54:36 PM PDT 24
Finished Jun 25 06:55:15 PM PDT 24
Peak memory 239232 kb
Host smart-ed4aa2b5-3205-40f7-866c-6967d145cba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492220381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2492220381
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.169178718
Short name T667
Test name
Test status
Simulation time 1670065769 ps
CPU time 11.63 seconds
Started Jun 25 06:54:32 PM PDT 24
Finished Jun 25 06:54:45 PM PDT 24
Peak memory 240008 kb
Host smart-71456dfa-275d-4abe-8462-6d78f3e264d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169178718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.169178718
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2505834753
Short name T672
Test name
Test status
Simulation time 116168766 ps
CPU time 3.98 seconds
Started Jun 25 06:54:26 PM PDT 24
Finished Jun 25 06:54:31 PM PDT 24
Peak memory 225372 kb
Host smart-8726cddd-0dab-42a6-9ec1-ec00fb5a7555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505834753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2505834753
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2657814227
Short name T243
Test name
Test status
Simulation time 13836845097 ps
CPU time 48.11 seconds
Started Jun 25 06:54:28 PM PDT 24
Finished Jun 25 06:55:17 PM PDT 24
Peak memory 236856 kb
Host smart-66f119af-b98e-41a0-aa16-c846c129ddb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657814227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2657814227
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2598268416
Short name T172
Test name
Test status
Simulation time 1084846257 ps
CPU time 8.55 seconds
Started Jun 25 06:54:26 PM PDT 24
Finished Jun 25 06:54:36 PM PDT 24
Peak memory 233568 kb
Host smart-35f429b3-6692-4ad7-b6f7-5a78e932859a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598268416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2598268416
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3531544215
Short name T245
Test name
Test status
Simulation time 3859126149 ps
CPU time 15.94 seconds
Started Jun 25 06:54:26 PM PDT 24
Finished Jun 25 06:54:43 PM PDT 24
Peak memory 233744 kb
Host smart-50fe9f43-3ea3-452f-917d-6a35dce5dae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531544215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3531544215
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3059464122
Short name T449
Test name
Test status
Simulation time 492827347 ps
CPU time 4.3 seconds
Started Jun 25 06:54:37 PM PDT 24
Finished Jun 25 06:54:42 PM PDT 24
Peak memory 219860 kb
Host smart-a0081e66-2647-4501-ae1a-ae86011479fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3059464122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3059464122
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3442481454
Short name T751
Test name
Test status
Simulation time 1813593520 ps
CPU time 13.02 seconds
Started Jun 25 06:54:26 PM PDT 24
Finished Jun 25 06:54:39 PM PDT 24
Peak memory 217116 kb
Host smart-86eff4cf-fe1b-4699-b064-1906a1f24f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442481454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3442481454
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2674593372
Short name T850
Test name
Test status
Simulation time 886056004 ps
CPU time 6.18 seconds
Started Jun 25 06:54:27 PM PDT 24
Finished Jun 25 06:54:34 PM PDT 24
Peak memory 217012 kb
Host smart-dee2b394-195f-465e-b6e0-97baf3220d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674593372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2674593372
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.757926115
Short name T714
Test name
Test status
Simulation time 47178351 ps
CPU time 1.66 seconds
Started Jun 25 06:54:28 PM PDT 24
Finished Jun 25 06:54:31 PM PDT 24
Peak memory 217088 kb
Host smart-7aab1cdb-75b3-48c5-a283-67cdee05f89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757926115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.757926115
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2547309323
Short name T665
Test name
Test status
Simulation time 233716758 ps
CPU time 0.93 seconds
Started Jun 25 06:54:27 PM PDT 24
Finished Jun 25 06:54:29 PM PDT 24
Peak memory 206704 kb
Host smart-0a923db5-3c35-4b1f-b310-a55c326eed80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547309323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2547309323
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1160267986
Short name T262
Test name
Test status
Simulation time 1099317312 ps
CPU time 4 seconds
Started Jun 25 06:54:34 PM PDT 24
Finished Jun 25 06:54:40 PM PDT 24
Peak memory 231400 kb
Host smart-d9c72c40-7742-48ed-a235-782e246f20aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160267986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1160267986
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2808922580
Short name T623
Test name
Test status
Simulation time 10783977 ps
CPU time 0.75 seconds
Started Jun 25 06:54:43 PM PDT 24
Finished Jun 25 06:54:45 PM PDT 24
Peak memory 206040 kb
Host smart-a6c28c3b-ff3b-43f0-a1bf-be71303e6346
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808922580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
808922580
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.847835484
Short name T417
Test name
Test status
Simulation time 777174472 ps
CPU time 8.53 seconds
Started Jun 25 06:54:41 PM PDT 24
Finished Jun 25 06:54:51 PM PDT 24
Peak memory 225372 kb
Host smart-34ec8a09-01eb-4329-bb87-a1dfca072b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847835484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.847835484
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.534725789
Short name T846
Test name
Test status
Simulation time 22928202 ps
CPU time 0.82 seconds
Started Jun 25 06:54:35 PM PDT 24
Finished Jun 25 06:54:37 PM PDT 24
Peak memory 207736 kb
Host smart-257f1682-914f-4fc8-97d5-38f0b3a78dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534725789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.534725789
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1029472559
Short name T240
Test name
Test status
Simulation time 247961272031 ps
CPU time 431.79 seconds
Started Jun 25 06:54:42 PM PDT 24
Finished Jun 25 07:01:55 PM PDT 24
Peak memory 255936 kb
Host smart-4662f322-d74a-444e-9261-b4e5ea288125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029472559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1029472559
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.859866424
Short name T926
Test name
Test status
Simulation time 20176916699 ps
CPU time 150.22 seconds
Started Jun 25 06:54:40 PM PDT 24
Finished Jun 25 06:57:11 PM PDT 24
Peak memory 258568 kb
Host smart-65800c35-5408-4224-8c38-ef851970d6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859866424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.859866424
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1111442977
Short name T753
Test name
Test status
Simulation time 34374137741 ps
CPU time 95.94 seconds
Started Jun 25 06:54:41 PM PDT 24
Finished Jun 25 06:56:17 PM PDT 24
Peak memory 255580 kb
Host smart-cb9a61a3-6e44-41f4-a492-772fe3b5dc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111442977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1111442977
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1903498911
Short name T596
Test name
Test status
Simulation time 651676516 ps
CPU time 2.33 seconds
Started Jun 25 06:54:41 PM PDT 24
Finished Jun 25 06:54:45 PM PDT 24
Peak memory 225408 kb
Host smart-9f7c6086-8a7a-4af9-a65e-6b4eca267753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903498911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1903498911
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1974948110
Short name T891
Test name
Test status
Simulation time 408669218 ps
CPU time 3.99 seconds
Started Jun 25 06:54:41 PM PDT 24
Finished Jun 25 06:54:46 PM PDT 24
Peak memory 225380 kb
Host smart-cd381c7f-2b8f-4ced-b295-510b691511bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974948110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1974948110
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2609375480
Short name T644
Test name
Test status
Simulation time 39957783640 ps
CPU time 70.09 seconds
Started Jun 25 06:54:42 PM PDT 24
Finished Jun 25 06:55:54 PM PDT 24
Peak memory 233804 kb
Host smart-f2556dc4-1d7c-496e-a944-c46445f8462c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609375480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2609375480
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1212833814
Short name T499
Test name
Test status
Simulation time 1223884014 ps
CPU time 5.53 seconds
Started Jun 25 06:54:42 PM PDT 24
Finished Jun 25 06:54:48 PM PDT 24
Peak memory 233592 kb
Host smart-5fcacce9-3c60-4445-b8ee-b03110a0121d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212833814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1212833814
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2678867841
Short name T236
Test name
Test status
Simulation time 392920687 ps
CPU time 10.02 seconds
Started Jun 25 06:54:41 PM PDT 24
Finished Jun 25 06:54:52 PM PDT 24
Peak memory 240472 kb
Host smart-592e3a4a-82b6-4c2a-b5e6-da24ee64933f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678867841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2678867841
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1758698141
Short name T805
Test name
Test status
Simulation time 10811248130 ps
CPU time 19.57 seconds
Started Jun 25 06:54:42 PM PDT 24
Finished Jun 25 06:55:03 PM PDT 24
Peak memory 223240 kb
Host smart-fba11f7a-6896-4322-9beb-fbbdc767e5a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1758698141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1758698141
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3072812002
Short name T278
Test name
Test status
Simulation time 43476387720 ps
CPU time 118.58 seconds
Started Jun 25 06:54:41 PM PDT 24
Finished Jun 25 06:56:41 PM PDT 24
Peak memory 254756 kb
Host smart-ad456294-583f-4813-b128-41f8d11cf8fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072812002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3072812002
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.4204753082
Short name T957
Test name
Test status
Simulation time 18324410 ps
CPU time 0.72 seconds
Started Jun 25 06:54:35 PM PDT 24
Finished Jun 25 06:54:38 PM PDT 24
Peak memory 206564 kb
Host smart-9b4e6361-1ca4-44ae-a88b-edb25375b3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204753082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.4204753082
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1846171799
Short name T836
Test name
Test status
Simulation time 13569676567 ps
CPU time 22 seconds
Started Jun 25 06:54:36 PM PDT 24
Finished Jun 25 06:54:59 PM PDT 24
Peak memory 217196 kb
Host smart-c2a77271-1cf4-465d-b007-bea472068854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846171799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1846171799
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3829486123
Short name T480
Test name
Test status
Simulation time 85600335 ps
CPU time 0.97 seconds
Started Jun 25 06:54:40 PM PDT 24
Finished Jun 25 06:54:42 PM PDT 24
Peak memory 207780 kb
Host smart-b7699733-77b6-4173-8983-5ffb60a68f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829486123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3829486123
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1457892464
Short name T455
Test name
Test status
Simulation time 36537395 ps
CPU time 0.71 seconds
Started Jun 25 06:54:36 PM PDT 24
Finished Jun 25 06:54:38 PM PDT 24
Peak memory 206704 kb
Host smart-0b8b1dff-dbbd-40d6-b6ad-ef51a6098be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457892464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1457892464
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1011880127
Short name T234
Test name
Test status
Simulation time 739749027 ps
CPU time 3.57 seconds
Started Jun 25 06:54:40 PM PDT 24
Finished Jun 25 06:54:44 PM PDT 24
Peak memory 225432 kb
Host smart-4c8f2d13-a1a0-44e4-b380-583e92d8608b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011880127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1011880127
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1336221961
Short name T892
Test name
Test status
Simulation time 33433965 ps
CPU time 0.73 seconds
Started Jun 25 06:54:47 PM PDT 24
Finished Jun 25 06:54:49 PM PDT 24
Peak memory 206264 kb
Host smart-559ef84f-afe5-4037-a042-bd3f94959d36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336221961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
336221961
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2456136845
Short name T365
Test name
Test status
Simulation time 34200559 ps
CPU time 2.75 seconds
Started Jun 25 06:54:47 PM PDT 24
Finished Jun 25 06:54:51 PM PDT 24
Peak memory 233600 kb
Host smart-029906c4-1911-4bf1-adef-749d08558d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456136845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2456136845
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2873024490
Short name T606
Test name
Test status
Simulation time 14774662 ps
CPU time 0.76 seconds
Started Jun 25 06:54:41 PM PDT 24
Finished Jun 25 06:54:42 PM PDT 24
Peak memory 206376 kb
Host smart-ac2818fe-fd47-40bc-8837-88238e2e88e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873024490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2873024490
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1921486987
Short name T709
Test name
Test status
Simulation time 9398216236 ps
CPU time 80.5 seconds
Started Jun 25 06:54:49 PM PDT 24
Finished Jun 25 06:56:12 PM PDT 24
Peak memory 241920 kb
Host smart-de0406c5-327b-47c2-a317-4aafdabcccd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921486987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1921486987
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1786837593
Short name T609
Test name
Test status
Simulation time 40314809892 ps
CPU time 190.42 seconds
Started Jun 25 06:54:49 PM PDT 24
Finished Jun 25 06:58:02 PM PDT 24
Peak memory 252532 kb
Host smart-63d2bdac-33a9-4999-a14b-a2959acffbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786837593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1786837593
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.106133279
Short name T198
Test name
Test status
Simulation time 81398904319 ps
CPU time 199.82 seconds
Started Jun 25 06:54:48 PM PDT 24
Finished Jun 25 06:58:09 PM PDT 24
Peak memory 262040 kb
Host smart-4147ae85-0c63-40aa-8c30-7fd19786ed97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106133279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
106133279
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2427986305
Short name T443
Test name
Test status
Simulation time 1225621398 ps
CPU time 21.07 seconds
Started Jun 25 06:54:50 PM PDT 24
Finished Jun 25 06:55:14 PM PDT 24
Peak memory 225436 kb
Host smart-115d2af1-c891-47ff-9c41-763de50cf275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427986305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2427986305
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.862819456
Short name T207
Test name
Test status
Simulation time 210031568 ps
CPU time 3.16 seconds
Started Jun 25 06:54:42 PM PDT 24
Finished Jun 25 06:54:47 PM PDT 24
Peak memory 225376 kb
Host smart-0a704b6c-6868-48f8-9d29-586cff5254ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862819456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.862819456
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3268757316
Short name T599
Test name
Test status
Simulation time 32089623 ps
CPU time 2.49 seconds
Started Jun 25 06:54:49 PM PDT 24
Finished Jun 25 06:54:55 PM PDT 24
Peak memory 233384 kb
Host smart-21611a05-4d5b-418d-b7e2-4d8a3e2f49b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268757316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3268757316
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2954321538
Short name T468
Test name
Test status
Simulation time 182485898 ps
CPU time 2.68 seconds
Started Jun 25 06:54:40 PM PDT 24
Finished Jun 25 06:54:43 PM PDT 24
Peak memory 233624 kb
Host smart-8f6aab4a-404b-46b0-a5f1-966d920f2c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954321538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2954321538
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3786281586
Short name T953
Test name
Test status
Simulation time 230451318 ps
CPU time 4.27 seconds
Started Jun 25 06:54:48 PM PDT 24
Finished Jun 25 06:54:56 PM PDT 24
Peak memory 224056 kb
Host smart-9d70248d-8c2b-412e-9a4e-3e9c5604a6ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3786281586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3786281586
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1929776058
Short name T17
Test name
Test status
Simulation time 199399729 ps
CPU time 1.06 seconds
Started Jun 25 06:54:47 PM PDT 24
Finished Jun 25 06:54:50 PM PDT 24
Peak memory 208520 kb
Host smart-32f60200-f1b4-4ad7-a957-dfe0ebbd4c6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929776058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1929776058
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2036812843
Short name T896
Test name
Test status
Simulation time 2685051155 ps
CPU time 15.66 seconds
Started Jun 25 06:54:40 PM PDT 24
Finished Jun 25 06:54:56 PM PDT 24
Peak memory 217208 kb
Host smart-06f2f3c6-2169-417d-b9f1-b0e40d8ef353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036812843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2036812843
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2795959805
Short name T422
Test name
Test status
Simulation time 1223054123 ps
CPU time 7.46 seconds
Started Jun 25 06:54:41 PM PDT 24
Finished Jun 25 06:54:50 PM PDT 24
Peak memory 217064 kb
Host smart-5559d5c7-89bb-4e00-ab95-258eb1605d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795959805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2795959805
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.628156106
Short name T356
Test name
Test status
Simulation time 131768672 ps
CPU time 1.35 seconds
Started Jun 25 06:54:40 PM PDT 24
Finished Jun 25 06:54:42 PM PDT 24
Peak memory 208704 kb
Host smart-5be2c119-29e8-4454-8cbf-98d4b69dcf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628156106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.628156106
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.4093268982
Short name T707
Test name
Test status
Simulation time 14573167 ps
CPU time 0.74 seconds
Started Jun 25 06:54:43 PM PDT 24
Finished Jun 25 06:54:45 PM PDT 24
Peak memory 206716 kb
Host smart-ec9e405b-b21e-4a92-a6fb-aeb6dd4d9aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093268982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.4093268982
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3968151220
Short name T681
Test name
Test status
Simulation time 16237675838 ps
CPU time 10.5 seconds
Started Jun 25 06:54:49 PM PDT 24
Finished Jun 25 06:55:03 PM PDT 24
Peak memory 225624 kb
Host smart-1166d4b6-5dc2-4c2c-bf0c-ffbf30261e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968151220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3968151220
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1459581059
Short name T643
Test name
Test status
Simulation time 11656513 ps
CPU time 0.74 seconds
Started Jun 25 06:54:55 PM PDT 24
Finished Jun 25 06:54:57 PM PDT 24
Peak memory 205752 kb
Host smart-debd92f1-5407-4282-bd92-58939595f41e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459581059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
459581059
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.956192099
Short name T595
Test name
Test status
Simulation time 884084077 ps
CPU time 10.8 seconds
Started Jun 25 06:54:56 PM PDT 24
Finished Jun 25 06:55:08 PM PDT 24
Peak memory 233528 kb
Host smart-1bff201c-133d-4045-8a03-6ea8557c5a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956192099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.956192099
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2191561478
Short name T363
Test name
Test status
Simulation time 51936136 ps
CPU time 0.79 seconds
Started Jun 25 06:54:48 PM PDT 24
Finished Jun 25 06:54:51 PM PDT 24
Peak memory 207420 kb
Host smart-3c1e9580-eaad-4f7c-8411-7cb76bfb18c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191561478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2191561478
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3348386306
Short name T43
Test name
Test status
Simulation time 19374137133 ps
CPU time 35.33 seconds
Started Jun 25 06:54:57 PM PDT 24
Finished Jun 25 06:55:33 PM PDT 24
Peak memory 241792 kb
Host smart-e58d0f6a-d74f-4b86-a16f-4eb407070e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348386306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3348386306
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2639277195
Short name T495
Test name
Test status
Simulation time 8154172675 ps
CPU time 62.4 seconds
Started Jun 25 06:54:54 PM PDT 24
Finished Jun 25 06:55:58 PM PDT 24
Peak memory 251692 kb
Host smart-513f8a2e-0067-4c12-97b5-1a80627e9b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639277195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2639277195
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.583908215
Short name T174
Test name
Test status
Simulation time 13983935314 ps
CPU time 115.66 seconds
Started Jun 25 06:54:56 PM PDT 24
Finished Jun 25 06:56:53 PM PDT 24
Peak memory 258380 kb
Host smart-df15ff6f-51c9-4b7b-9d18-d9fe2922cd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583908215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
583908215
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3460288675
Short name T336
Test name
Test status
Simulation time 1179205893 ps
CPU time 4.2 seconds
Started Jun 25 06:54:55 PM PDT 24
Finished Jun 25 06:55:01 PM PDT 24
Peak memory 225436 kb
Host smart-03d123a9-07b0-4fa3-b654-e42ef40d4a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460288675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3460288675
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.958221240
Short name T470
Test name
Test status
Simulation time 215143516 ps
CPU time 3.76 seconds
Started Jun 25 06:54:53 PM PDT 24
Finished Jun 25 06:54:58 PM PDT 24
Peak memory 233604 kb
Host smart-d07b2ebd-f601-4457-b5fe-2f7d2621f4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958221240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.958221240
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1104837149
Short name T823
Test name
Test status
Simulation time 145571205 ps
CPU time 2.19 seconds
Started Jun 25 06:54:54 PM PDT 24
Finished Jun 25 06:54:58 PM PDT 24
Peak memory 223908 kb
Host smart-175eb230-c933-4d6c-8511-38a5a21fe8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104837149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1104837149
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3951210550
Short name T267
Test name
Test status
Simulation time 13055244272 ps
CPU time 20.95 seconds
Started Jun 25 06:54:55 PM PDT 24
Finished Jun 25 06:55:17 PM PDT 24
Peak memory 241588 kb
Host smart-00f0fbe4-67ab-4e93-b6fb-f695e86377ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951210550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3951210550
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2415791820
Short name T504
Test name
Test status
Simulation time 12723315677 ps
CPU time 16.21 seconds
Started Jun 25 06:54:55 PM PDT 24
Finished Jun 25 06:55:12 PM PDT 24
Peak memory 233668 kb
Host smart-81d3945d-3b6a-4f3d-88fd-80d8beefcfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415791820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2415791820
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2982750868
Short name T876
Test name
Test status
Simulation time 796970413 ps
CPU time 8.42 seconds
Started Jun 25 06:54:55 PM PDT 24
Finished Jun 25 06:55:05 PM PDT 24
Peak memory 224084 kb
Host smart-448f4f7f-f73a-4ce8-83c8-3c76819d1a33
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2982750868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2982750868
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1458659858
Short name T128
Test name
Test status
Simulation time 53422225312 ps
CPU time 122.72 seconds
Started Jun 25 06:54:56 PM PDT 24
Finished Jun 25 06:57:00 PM PDT 24
Peak memory 252188 kb
Host smart-e6c320b4-2c8e-449a-a31f-a93ce2fcf975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458659858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1458659858
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1448928980
Short name T808
Test name
Test status
Simulation time 1422683851 ps
CPU time 14.73 seconds
Started Jun 25 06:54:49 PM PDT 24
Finished Jun 25 06:55:07 PM PDT 24
Peak memory 217116 kb
Host smart-7475f332-03b7-4307-81db-2e2529e6a400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448928980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1448928980
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3549014603
Short name T807
Test name
Test status
Simulation time 5608193701 ps
CPU time 7.88 seconds
Started Jun 25 06:54:48 PM PDT 24
Finished Jun 25 06:54:59 PM PDT 24
Peak memory 217196 kb
Host smart-cd957913-0b04-401a-a79f-db7623eb45c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549014603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3549014603
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2639637307
Short name T310
Test name
Test status
Simulation time 38710972 ps
CPU time 1.3 seconds
Started Jun 25 06:54:52 PM PDT 24
Finished Jun 25 06:54:55 PM PDT 24
Peak memory 208804 kb
Host smart-8e5141f0-bd03-4cbb-826c-a4329dfdfb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639637307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2639637307
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.279753504
Short name T866
Test name
Test status
Simulation time 319192247 ps
CPU time 0.88 seconds
Started Jun 25 06:54:48 PM PDT 24
Finished Jun 25 06:54:52 PM PDT 24
Peak memory 206720 kb
Host smart-a64adb36-079b-4185-ba27-9903ea782e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279753504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.279753504
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3183321656
Short name T838
Test name
Test status
Simulation time 121011558 ps
CPU time 2.14 seconds
Started Jun 25 06:54:56 PM PDT 24
Finished Jun 25 06:54:59 PM PDT 24
Peak memory 225348 kb
Host smart-ff7a0ed1-1e1b-4ccc-8050-f07094d63705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183321656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3183321656
Directory /workspace/9.spi_device_upload/latest
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