Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3323192	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3779763

1

T1

1

T2

13087

T3

39

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3940978	1			T1	73		T2	24504		T3	546
values[0x0]	1579507	1			T2	425		T3	11		T4	1185
values[0x1]	1582470	1			T2	491		T3	23		T4	1231

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2355510	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4747445

1

T1

24

T2

15537

T3

217

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27589	1			T4	19		T5	456		T6	21
valid_sources[0x01]	26476	1			T1	1		T3	2		T4	36
valid_sources[0x02]	27136	1			T3	3		T4	32		T5	23
valid_sources[0x03]	28267	1			T4	11		T5	443		T6	32
valid_sources[0x04]	26463	1			T3	4		T4	7		T5	239
valid_sources[0x05]	24506	1			T3	2		T4	32		T5	256
valid_sources[0x06]	28236	1			T1	1		T3	2		T4	17
valid_sources[0x07]	27221	1			T4	20		T5	200		T6	31
valid_sources[0x08]	29020	1			T3	4		T4	22		T5	236
valid_sources[0x09]	29690	1			T1	1		T3	6		T4	16
valid_sources[0x0a]	24389	1			T4	24		T5	240		T6	17
valid_sources[0x0b]	28040	1			T3	3		T4	22		T5	329
valid_sources[0x0c]	22581	1			T3	1		T4	13		T5	267
valid_sources[0x0d]	43901	1			T1	2		T3	2		T4	25
valid_sources[0x0e]	28990	1			T1	1		T3	6		T4	31
valid_sources[0x0f]	25891	1			T3	2		T4	23		T5	165
valid_sources[0x10]	33392	1			T3	5		T4	24		T5	294
valid_sources[0x11]	27367	1			T3	1		T4	19		T5	47
valid_sources[0x12]	32724	1			T3	1		T4	22		T5	114
valid_sources[0x13]	26865	1			T3	5		T4	16		T5	244
valid_sources[0x14]	29630	1			T3	1		T4	23		T5	147
valid_sources[0x15]	25819	1			T4	22		T5	161		T6	31
valid_sources[0x16]	28185	1			T3	4		T4	17		T5	413
valid_sources[0x17]	25613	1			T3	2		T4	19		T5	77
valid_sources[0x18]	26829	1			T3	2		T4	16		T5	219
valid_sources[0x19]	28262	1			T1	1		T3	1		T4	25
valid_sources[0x1a]	24961	1			T3	3		T4	21		T5	99
valid_sources[0x1b]	25878	1			T1	1		T3	2		T4	38
valid_sources[0x1c]	29631	1			T1	1		T3	3		T4	20
valid_sources[0x1d]	27707	1			T3	1		T4	35		T5	186
valid_sources[0x1e]	25226	1			T1	1		T4	31		T5	151
valid_sources[0x1f]	25339	1			T4	25		T5	607		T6	31
valid_sources[0x20]	29470	1			T1	1		T3	3		T4	22
valid_sources[0x21]	24319	1			T3	1		T4	22		T5	111
valid_sources[0x22]	28765	1			T1	1		T3	3		T4	8
valid_sources[0x23]	26810	1			T3	6		T4	18		T5	506
valid_sources[0x24]	34063	1			T3	1		T4	16		T5	216
valid_sources[0x25]	26835	1			T3	4		T4	24		T5	364
valid_sources[0x26]	27614	1			T3	1		T4	9		T5	223
valid_sources[0x27]	26971	1			T3	3		T4	14		T5	124
valid_sources[0x28]	30210	1			T4	20		T5	131		T6	24
valid_sources[0x29]	25015	1			T4	26		T5	440		T6	31
valid_sources[0x2a]	29107	1			T3	2		T4	27		T5	201
valid_sources[0x2b]	25739	1			T4	23		T5	208		T6	31
valid_sources[0x2c]	26400	1			T3	4		T4	15		T5	137
valid_sources[0x2d]	25833	1			T4	22		T5	235		T6	20
valid_sources[0x2e]	25668	1			T3	1		T4	29		T5	233
valid_sources[0x2f]	29697	1			T3	1		T4	20		T5	427
valid_sources[0x30]	26140	1			T2	452		T4	30		T5	99
valid_sources[0x31]	26319	1			T1	1		T3	5		T4	36
valid_sources[0x32]	26773	1			T1	2		T4	20		T5	358
valid_sources[0x33]	26746	1			T3	1		T4	30		T5	252
valid_sources[0x34]	25365	1			T3	4		T4	28		T5	227
valid_sources[0x35]	25523	1			T1	1		T4	26		T5	123
valid_sources[0x36]	27578	1			T1	2		T3	2		T4	30
valid_sources[0x37]	29674	1			T3	4		T4	17		T5	319
valid_sources[0x38]	25381	1			T3	5		T4	16		T5	142
valid_sources[0x39]	26043	1			T3	1		T4	18		T5	324
valid_sources[0x3a]	26883	1			T3	2		T4	17		T5	309
valid_sources[0x3b]	25800	1			T1	2		T3	1		T4	15
valid_sources[0x3c]	26459	1			T3	5		T4	23		T5	160
valid_sources[0x3d]	40522	1			T4	21		T5	94		T6	32
valid_sources[0x3e]	28859	1			T3	3		T4	25		T5	74
valid_sources[0x3f]	26559	1			T4	34		T5	262		T6	32
valid_sources[0x40]	26490	1			T3	6		T4	27		T5	186
valid_sources[0x41]	26826	1			T3	2		T4	29		T5	348
valid_sources[0x42]	26064	1			T4	27		T5	232		T6	29
valid_sources[0x43]	25934	1			T3	10		T4	16		T5	29
valid_sources[0x44]	30995	1			T1	1		T3	1		T4	27
valid_sources[0x45]	28462	1			T3	1		T4	27		T5	227
valid_sources[0x46]	27895	1			T1	1		T4	20		T5	78
valid_sources[0x47]	32647	1			T4	26		T5	21		T6	26
valid_sources[0x48]	31737	1			T3	7		T4	13		T5	137
valid_sources[0x49]	29135	1			T1	1		T3	2		T4	15
valid_sources[0x4a]	28852	1			T4	21		T5	537		T6	20
valid_sources[0x4b]	25764	1			T1	1		T3	1		T4	33
valid_sources[0x4c]	26907	1			T1	1		T3	1		T4	12
valid_sources[0x4d]	27267	1			T3	1		T4	23		T5	177
valid_sources[0x4e]	51562	1			T1	1		T4	22		T5	62
valid_sources[0x4f]	29030	1			T4	32		T5	103		T6	25
valid_sources[0x50]	27688	1			T3	2		T4	15		T5	285
valid_sources[0x51]	25168	1			T3	1		T4	28		T5	237
valid_sources[0x52]	29795	1			T4	23		T5	430		T6	25
valid_sources[0x53]	28475	1			T4	23		T5	140		T6	28
valid_sources[0x54]	28337	1			T4	19		T5	136		T6	30
valid_sources[0x55]	26278	1			T3	1		T4	20		T5	149
valid_sources[0x56]	26763	1			T4	26		T5	223		T6	28
valid_sources[0x57]	26836	1			T1	1		T4	16		T5	228
valid_sources[0x58]	41469	1			T1	1		T3	4		T4	24
valid_sources[0x59]	27646	1			T1	3		T3	1		T4	17
valid_sources[0x5a]	31998	1			T3	1		T4	15		T5	200
valid_sources[0x5b]	27725	1			T3	8		T4	30		T5	164
valid_sources[0x5c]	23805	1			T3	2		T4	20		T5	134
valid_sources[0x5d]	27184	1			T3	2		T4	12		T5	427
valid_sources[0x5e]	26603	1			T3	1		T4	19		T5	276
valid_sources[0x5f]	29203	1			T3	3		T4	11		T5	336
valid_sources[0x60]	25929	1			T3	5		T4	29		T5	428
valid_sources[0x61]	27069	1			T3	1		T4	11		T5	189
valid_sources[0x62]	27247	1			T4	14		T5	208		T6	27
valid_sources[0x63]	29395	1			T3	2		T4	17		T5	271
valid_sources[0x64]	26655	1			T3	13		T4	23		T5	385
valid_sources[0x65]	26531	1			T1	1		T3	2		T4	27
valid_sources[0x66]	26448	1			T1	2		T3	3		T4	35
valid_sources[0x67]	25876	1			T3	1		T4	20		T5	227
valid_sources[0x68]	26809	1			T3	2		T4	25		T5	308
valid_sources[0x69]	39314	1			T2	10315		T4	24		T5	99
valid_sources[0x6a]	30069	1			T1	1		T3	2		T4	35
valid_sources[0x6b]	27059	1			T3	2		T4	19		T5	325
valid_sources[0x6c]	24087	1			T3	1		T4	19		T5	82
valid_sources[0x6d]	31006	1			T4	13		T5	106		T6	27
valid_sources[0x6e]	27184	1			T1	1		T3	1		T4	16
valid_sources[0x6f]	29168	1			T1	1		T3	4		T4	23
valid_sources[0x70]	24942	1			T3	2		T4	24		T5	222
valid_sources[0x71]	29554	1			T3	1		T4	13		T5	164
valid_sources[0x72]	28963	1			T3	8		T4	18		T5	147
valid_sources[0x73]	25371	1			T3	4		T4	18		T5	148
valid_sources[0x74]	25171	1			T1	1		T3	5		T4	25
valid_sources[0x75]	31554	1			T1	1		T4	19		T5	113
valid_sources[0x76]	25784	1			T1	1		T3	2		T4	23
valid_sources[0x77]	28464	1			T4	29		T5	179		T6	27
valid_sources[0x78]	26343	1			T3	2		T4	27		T5	101
valid_sources[0x79]	26760	1			T3	1		T4	13		T5	90
valid_sources[0x7a]	26753	1			T4	27		T5	456		T6	25
valid_sources[0x7b]	24689	1			T3	6		T4	16		T5	44
valid_sources[0x7c]	26944	1			T3	7		T4	29		T5	16
valid_sources[0x7d]	40146	1			T3	1		T4	23		T5	106
valid_sources[0x7e]	25226	1			T3	1		T4	21		T5	103
valid_sources[0x7f]	26152	1			T4	32		T5	167		T6	23
valid_sources[0x80]	27172	1			T3	8		T4	24		T5	295

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

930218

1

T1

1

T2

12181

T3

26

values[0x0]

all_enables

biggest_size

1435137

1

T2

425

T3

7

T4

929

values[0x1]

all_enables

biggest_size

1414408

1

T2

481

T3

6

T4

906