Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3341557

1

T1

72

T2

12333

T3

541

full_word

3780745

1

T1

1

T2

13087

T3

39

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7121892	1			T1	73		T2	25420		T3	580
auto[TlIntgErrCmd]	127	1			T93	9		T95	6		T96	3
auto[TlIntgErrData]	141	1			T93	12		T95	7		T96	2
auto[TlIntgErrBoth]	142	1			T93	9		T95	7		T96	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3943760

1

T1

73

T2

24504

T3

546

auto[1]

3178542

1

T2

916

T3

34

T4

2416

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3013153	1			T1	72		T2	12323		T3	520
auto[TlIntgErrNone]	partial	auto[1]	328016	1			T2	10		T3	21		T4	581
auto[TlIntgErrNone]	full_word	auto[0]	930416	1			T1	1		T2	12181		T3	26
auto[TlIntgErrNone]	full_word	auto[1]	2850307	1			T2	906		T3	13		T4	1835
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T93	4		T95	3		T96	1
auto[TlIntgErrCmd]	partial	auto[1]	76	1			T93	5		T95	2		T96	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T95	1		T160	1		T161	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T159	1		T162	1		T163	1
auto[TlIntgErrData]	partial	auto[0]	73	1			T93	5		T95	4		T96	2
auto[TlIntgErrData]	partial	auto[1]	61	1			T93	6		T95	3		T109	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T93	1		T109	1		T164	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T165	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	59	1			T93	2		T95	1		T96	4
auto[TlIntgErrBoth]	partial	auto[1]	74	1			T93	6		T95	5		T96	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T93	1		T109	1		T142	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T95	1		T109	1		T165	2