Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	388439100	2501865	0	0
DepthKnown_A	388439100	388310434	0	0
RvalidKnown_A	388439100	388310434	0	0
WreadyKnown_A	388439100	388310434	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	2501865	0	0
T2	687739	1663	0	0
T3	5933	0	0	0
T4	220295	0	0	0
T5	289489	6653	0	0
T6	170564	4991	0	0
T7	194548	0	0	0
T8	265700	10003	0	0
T9	474170	0	0	0
T10	6984	0	0	0
T11	5588	0	0	0
T12	0	832	0	0
T15	0	832	0	0
T17	0	14148	0	0
T18	0	832	0	0
T19	0	2175	0	0
T20	0	5822	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	388310434	0	0
T1	1838	1755	0	0
T2	687739	687648	0	0
T3	5933	5877	0	0
T4	220295	220214	0	0
T5	289489	289483	0	0
T6	170564	170554	0	0
T7	194548	194483	0	0
T8	265700	265691	0	0
T9	474170	474072	0	0
T10	6984	6919	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	388310434	0	0
T1	1838	1755	0	0
T2	687739	687648	0	0
T3	5933	5877	0	0
T4	220295	220214	0	0
T5	289489	289483	0	0
T6	170564	170554	0	0
T7	194548	194483	0	0
T8	265700	265691	0	0
T9	474170	474072	0	0
T10	6984	6919	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	388310434	0	0
T1	1838	1755	0	0
T2	687739	687648	0	0
T3	5933	5877	0	0
T4	220295	220214	0	0
T5	289489	289483	0	0
T6	170564	170554	0	0
T7	194548	194483	0	0
T8	265700	265691	0	0
T9	474170	474072	0	0
T10	6984	6919	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	388439100	2798472	0	0
DepthKnown_A	388439100	388310434	0	0
RvalidKnown_A	388439100	388310434	0	0
WreadyKnown_A	388439100	388310434	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	2798472	0	0
T2	687739	832	0	0
T3	5933	0	0	0
T4	220295	0	0	0
T5	289489	4160	0	0
T6	170564	4160	0	0
T7	194548	0	0	0
T8	265700	18658	0	0
T9	474170	0	0	0
T10	6984	0	0	0
T11	5588	0	0	0
T12	0	3690	0	0
T15	0	832	0	0
T17	0	38003	0	0
T18	0	832	0	0
T19	0	1089	0	0
T20	0	4160	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	388310434	0	0
T1	1838	1755	0	0
T2	687739	687648	0	0
T3	5933	5877	0	0
T4	220295	220214	0	0
T5	289489	289483	0	0
T6	170564	170554	0	0
T7	194548	194483	0	0
T8	265700	265691	0	0
T9	474170	474072	0	0
T10	6984	6919	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	388310434	0	0
T1	1838	1755	0	0
T2	687739	687648	0	0
T3	5933	5877	0	0
T4	220295	220214	0	0
T5	289489	289483	0	0
T6	170564	170554	0	0
T7	194548	194483	0	0
T8	265700	265691	0	0
T9	474170	474072	0	0
T10	6984	6919	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	388310434	0	0
T1	1838	1755	0	0
T2	687739	687648	0	0
T3	5933	5877	0	0
T4	220295	220214	0	0
T5	289489	289483	0	0
T6	170564	170554	0	0
T7	194548	194483	0	0
T8	265700	265691	0	0
T9	474170	474072	0	0
T10	6984	6919	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	388439100	173660	0	0
DepthKnown_A	388439100	388310434	0	0
RvalidKnown_A	388439100	388310434	0	0
WreadyKnown_A	388439100	388310434	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	173660	0	0
T3	5933	20	0	0
T4	220295	588	0	0
T5	289489	510	0	0
T6	170564	192	0	0
T7	194548	335	0	0
T8	265700	781	0	0
T9	474170	0	0	0
T10	6984	36	0	0
T11	5588	3	0	0
T12	252721	0	0	0
T17	0	1393	0	0
T42	0	628	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	388310434	0	0
T1	1838	1755	0	0
T2	687739	687648	0	0
T3	5933	5877	0	0
T4	220295	220214	0	0
T5	289489	289483	0	0
T6	170564	170554	0	0
T7	194548	194483	0	0
T8	265700	265691	0	0
T9	474170	474072	0	0
T10	6984	6919	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	388310434	0	0
T1	1838	1755	0	0
T2	687739	687648	0	0
T3	5933	5877	0	0
T4	220295	220214	0	0
T5	289489	289483	0	0
T6	170564	170554	0	0
T7	194548	194483	0	0
T8	265700	265691	0	0
T9	474170	474072	0	0
T10	6984	6919	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	388310434	0	0
T1	1838	1755	0	0
T2	687739	687648	0	0
T3	5933	5877	0	0
T4	220295	220214	0	0
T5	289489	289483	0	0
T6	170564	170554	0	0
T7	194548	194483	0	0
T8	265700	265691	0	0
T9	474170	474072	0	0
T10	6984	6919	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	388439100	412278	0	0
DepthKnown_A	388439100	388310434	0	0
RvalidKnown_A	388439100	388310434	0	0
WreadyKnown_A	388439100	388310434	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	412278	0	0
T3	5933	20	0	0
T4	220295	2647	0	0
T5	289489	510	0	0
T6	170564	192	0	0
T7	194548	335	0	0
T8	265700	3556	0	0
T9	474170	0	0	0
T10	6984	36	0	0
T11	5588	3	0	0
T12	252721	0	0	0
T17	0	6302	0	0
T42	0	628	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	388310434	0	0
T1	1838	1755	0	0
T2	687739	687648	0	0
T3	5933	5877	0	0
T4	220295	220214	0	0
T5	289489	289483	0	0
T6	170564	170554	0	0
T7	194548	194483	0	0
T8	265700	265691	0	0
T9	474170	474072	0	0
T10	6984	6919	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	388310434	0	0
T1	1838	1755	0	0
T2	687739	687648	0	0
T3	5933	5877	0	0
T4	220295	220214	0	0
T5	289489	289483	0	0
T6	170564	170554	0	0
T7	194548	194483	0	0
T8	265700	265691	0	0
T9	474170	474072	0	0
T10	6984	6919	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	388310434	0	0
T1	1838	1755	0	0
T2	687739	687648	0	0
T3	5933	5877	0	0
T4	220295	220214	0	0
T5	289489	289483	0	0
T6	170564	170554	0	0
T7	194548	194483	0	0
T8	265700	265691	0	0
T9	474170	474072	0	0
T10	6984	6919	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	388439100	5700249	0	0
DepthKnown_A	388439100	388310434	0	0
RvalidKnown_A	388439100	388310434	0	0
WreadyKnown_A	388439100	388310434	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	5700249	0	0
T1	1838	73	0	0
T2	687739	24588	0	0
T3	5933	560	0	0
T4	220295	5225	0	0
T5	289489	52759	0	0
T6	170564	2681	0	0
T7	194548	4451	0	0
T8	265700	39392	0	0
T9	474170	801	0	0
T10	6984	1621	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	388310434	0	0
T1	1838	1755	0	0
T2	687739	687648	0	0
T3	5933	5877	0	0
T4	220295	220214	0	0
T5	289489	289483	0	0
T6	170564	170554	0	0
T7	194548	194483	0	0
T8	265700	265691	0	0
T9	474170	474072	0	0
T10	6984	6919	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	388310434	0	0
T1	1838	1755	0	0
T2	687739	687648	0	0
T3	5933	5877	0	0
T4	220295	220214	0	0
T5	289489	289483	0	0
T6	170564	170554	0	0
T7	194548	194483	0	0
T8	265700	265691	0	0
T9	474170	474072	0	0
T10	6984	6919	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	388310434	0	0
T1	1838	1755	0	0
T2	687739	687648	0	0
T3	5933	5877	0	0
T4	220295	220214	0	0
T5	289489	289483	0	0
T6	170564	170554	0	0
T7	194548	194483	0	0
T8	265700	265691	0	0
T9	474170	474072	0	0
T10	6984	6919	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	388439100	12119737	0	0
DepthKnown_A	388439100	388310434	0	0
RvalidKnown_A	388439100	388310434	0	0
WreadyKnown_A	388439100	388310434	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	12119737	0	0
T1	1838	295	0	0
T2	687739	24588	0	0
T3	5933	560	0	0
T4	220295	22386	0	0
T5	289489	52479	0	0
T6	170564	5044	0	0
T7	194548	4423	0	0
T8	265700	159375	0	0
T9	474170	801	0	0
T10	6984	1621	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	388310434	0	0
T1	1838	1755	0	0
T2	687739	687648	0	0
T3	5933	5877	0	0
T4	220295	220214	0	0
T5	289489	289483	0	0
T6	170564	170554	0	0
T7	194548	194483	0	0
T8	265700	265691	0	0
T9	474170	474072	0	0
T10	6984	6919	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	388310434	0	0
T1	1838	1755	0	0
T2	687739	687648	0	0
T3	5933	5877	0	0
T4	220295	220214	0	0
T5	289489	289483	0	0
T6	170564	170554	0	0
T7	194548	194483	0	0
T8	265700	265691	0	0
T9	474170	474072	0	0
T10	6984	6919	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388439100	388310434	0	0
T1	1838	1755	0	0
T2	687739	687648	0	0
T3	5933	5877	0	0
T4	220295	220214	0	0
T5	289489	289483	0	0
T6	170564	170554	0	0
T7	194548	194483	0	0
T8	265700	265691	0	0
T9	474170	474072	0	0
T10	6984	6919	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0